[AArch64] Add ARMv8.3 combined pointer authentication load instructions
[deliverable/binutils-gdb.git] / gas / config / tc-aarch64.c
index e65daa090c5a4701cbec9146cfda623ba69e5f74..9b19d767730add8ec8067d19c064fc826f41c8f3 100644 (file)
@@ -6024,6 +6024,25 @@ parse_operands (char *str, const aarch64_opcode *opcode)
                                              /* skip_p */ 0);
          break;
 
+       case AARCH64_OPND_ADDR_SIMM10:
+         po_misc_or_fail (parse_address (&str, info));
+         if (info->addr.pcrel || info->addr.offset.is_reg
+             || !info->addr.preind || info->addr.postind)
+           {
+             set_syntax_error (_("invalid addressing mode"));
+             goto failure;
+           }
+         if (inst.reloc.type != BFD_RELOC_UNUSED)
+           {
+             set_syntax_error (_("relocation not allowed"));
+             goto failure;
+           }
+         assign_imm_if_const_or_fixup_later (&inst.reloc, info,
+                                             /* addr_off_p */ 1,
+                                             /* need_libopcodes_p */ 1,
+                                             /* skip_p */ 0);
+         break;
+
        case AARCH64_OPND_ADDR_UIMM12:
          po_misc_or_fail (parse_address (&str, info));
          if (info->addr.pcrel || info->addr.offset.is_reg
@@ -6481,6 +6500,7 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
     {
     case ldst_pos:
     case ldst_imm9:
+    case ldst_imm10:
     case ldst_unscaled:
     case ldst_unpriv:
       /* Loading/storing the base register is unpredictable if writeback.  */
@@ -7350,6 +7370,7 @@ fix_insn (fixS *fixP, uint32_t flags, offsetT value)
     case AARCH64_OPND_ADDR_SIMM7:
     case AARCH64_OPND_ADDR_SIMM9:
     case AARCH64_OPND_ADDR_SIMM9_2:
+    case AARCH64_OPND_ADDR_SIMM10:
     case AARCH64_OPND_ADDR_UIMM12:
       /* Immediate offset in an address.  */
       insn = get_aarch64_insn (buf);
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