/* tc-arc.c -- Assembler for the ARC
- Copyright (C) 1994-2017 Free Software Foundation, Inc.
+ Copyright (C) 1994-2019 Free Software Foundation, Inc.
Contributor: Claudiu Zissulescu <claziss@synopsys.com>
#include "as.h"
#include "subsegs.h"
-#include "struc-symbol.h"
#include "dwarf2dbg.h"
#include "dw2gencfi.h"
#include "safe-ctype.h"
#define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
&& (SUB_OPCODE (x) == 0x28))
-/* Equal to MAX_PRECISION in atof-ieee.c. */
-#define MAX_LITTLENUMS 6
-
#ifndef TARGET_WITH_CPU
#define TARGET_WITH_CPU "arc700"
#endif /* TARGET_WITH_CPU */
#define is_spfp_p(op) (((sc) == SPX))
#define is_dpfp_p(op) (((sc) == DPX))
#define is_fpuda_p(op) (((sc) == DPA))
-#define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
- || (op)->insn_class == JUMP))
+#define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
+ || (op)->insn_class == JUMP \
+ || (op)->insn_class == BRCC \
+ || (op)->insn_class == BBIT0 \
+ || (op)->insn_class == BBIT1 \
+ || (op)->insn_class == BI \
+ || (op)->insn_class == EI \
+ || (op)->insn_class == ENTER \
+ || (op)->insn_class == JLI \
+ || (op)->insn_class == LOOP \
+ || (op)->insn_class == LEAVE \
+ ))
#define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
#define is_nps400_p(op) (((sc) == NPS400))
#define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
{ #NAME, ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \
EF_ARC_CPU_ARCV2HS, EXTRA}
+#define ARC_CPU_TYPE_NONE \
+ { 0, 0, 0, 0, 0 }
/* A table of CPU names and opcode sets. */
static const struct cpu_type
}
cpu_types[] =
{
- ARC_CPU_TYPE_A7xx (arc700, 0x00),
- ARC_CPU_TYPE_A7xx (nps400, NPS400),
-
- ARC_CPU_TYPE_AV2EM (arcem, 0x00),
- ARC_CPU_TYPE_AV2EM (em, 0x00),
- ARC_CPU_TYPE_AV2EM (em4, CD),
- ARC_CPU_TYPE_AV2EM (em4_dmips, CD),
- ARC_CPU_TYPE_AV2EM (em4_fpus, CD),
- ARC_CPU_TYPE_AV2EM (em4_fpuda, CD | DPA),
- ARC_CPU_TYPE_AV2EM (quarkse_em, CD | SPX | DPX),
-
- ARC_CPU_TYPE_AV2HS (archs, CD),
- ARC_CPU_TYPE_AV2HS (hs, CD),
- ARC_CPU_TYPE_AV2HS (hs34, CD),
- ARC_CPU_TYPE_AV2HS (hs38, CD),
- ARC_CPU_TYPE_AV2HS (hs38_linux, CD),
-
- ARC_CPU_TYPE_A6xx (arc600, 0x00),
- ARC_CPU_TYPE_A6xx (arc600_norm, 0x00),
- ARC_CPU_TYPE_A6xx (arc600_mul64, 0x00),
- ARC_CPU_TYPE_A6xx (arc600_mul32x16, 0x00),
- ARC_CPU_TYPE_A6xx (arc601, 0x00),
- ARC_CPU_TYPE_A6xx (arc601_norm, 0x00),
- ARC_CPU_TYPE_A6xx (arc601_mul64, 0x00),
- ARC_CPU_TYPE_A6xx (arc601_mul32x16, 0x00),
- { 0, 0, 0, 0, 0 }
+ #include "elf/arc-cpu.def"
};
/* Information about the cpu/variant we're assembling for. */
static struct cpu_type selected_cpu = { 0, 0, 0, E_ARC_OSABI_CURRENT, 0 };
+/* TRUE if current assembly code uses RF16 only registers. */
+static bfd_boolean rf16_only = TRUE;
+
/* MPY option. */
static unsigned mpy_option = 0;
md_number_to_chars (buf, val, n);
break;
case 6:
- md_number_to_chars (buf, (val & 0xffff00000000) >> 32, 2);
+ md_number_to_chars (buf, (val & 0xffff00000000ull) >> 32, 2);
md_number_to_chars_midend (buf + 2, (val & 0xffffffff), 4);
break;
case 4:
md_number_to_chars (buf + 2, (val & 0xffff), 2);
break;
case 8:
- md_number_to_chars_midend (buf, (val & 0xffffffff00000000) >> 32, 4);
+ md_number_to_chars_midend (buf, (val & 0xffffffff00000000ull) >> 32, 4);
md_number_to_chars_midend (buf + 4, (val & 0xffffffff), 4);
break;
default:
case O_symbol:
{
const char *p;
+ char *tmpp, *pp;
const struct arc_aux_reg *auxr;
if (opcode->insn_class != AUXREG)
goto de_fault;
p = S_GET_NAME (tok[tokidx].X_add_symbol);
- auxr = hash_find (arc_aux_hash, p);
+ /* For compatibility reasons, an aux register can
+ be spelled with upper or lower case
+ letters. */
+ tmpp = strdup (p);
+ for (pp = tmpp; *pp; ++pp) *pp = TOLOWER (*pp);
+
+ auxr = hash_find (arc_aux_hash, tmpp);
if (auxr)
{
/* We modify the token array here, safe in the
tok[tokidx].X_add_number = auxr->address;
ARC_SET_FLAG (tok[tokidx].X_add_symbol, ARC_FLAG_AUX);
}
+ free (tmpp);
if (tok[tokidx].X_op != O_constant)
goto de_fault;
default:
break;
}
+
+ switch (tok[i].X_op)
+ {
+ case O_register:
+ if ((tok[i].X_add_number >= 4 && tok[i].X_add_number <= 9)
+ || (tok[i].X_add_number >= 16 && tok[i].X_add_number <= 25))
+ rf16_only = FALSE;
+ break;
+ default:
+ break;
+ }
}
}
break;
default:
if ((int) fixP->fx_r_type < 0)
- as_fatal (_("PC relative relocation not allowed for (internal) type %d"),
- fixP->fx_r_type);
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("PC relative relocation not allowed for (internal)"
+ " type %d"),
+ fixP->fx_r_type);
break;
}
}
int size, fix;
struct arc_relax_type *relax_arg = &fragP->tc_frag_data;
- fix = (fragP->fr_fix < 0 ? 0 : fragP->fr_fix);
+ fix = fragP->fr_fix;
dest = fragP->fr_literal + fix;
table_entry = TC_GENERIC_RELAX_TABLE + fragP->fr_subtype;
GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
if (((*name == '_')
&& (*(name+1) == 'G')
- && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0))
- || ((*name == '_')
- && (*(name+1) == 'D')
- && (strcmp (name, DYNAMIC_STRUCT_NAME) == 0)))
+ && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)))
{
if (!GOT_symbol)
{
{
case O_plt:
if (opcode->insn_class == JUMP)
- as_bad_where (frag_now->fr_file, frag_now->fr_line,
- _("Unable to use @plt relocation for insn %s"),
- opcode->name);
+ as_bad (_("Unable to use @plt relocation for insn %s"),
+ opcode->name);
needGOTSymbol = TRUE;
reloc = find_reloc ("plt", opcode->name,
pflags, nflg,
reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
if (arc_opcode_len (opcode) == 2
|| opcode->insn_class == JUMP)
- as_bad_where (frag_now->fr_file, frag_now->fr_line,
- _("Unable to use @pcl relocation for insn %s"),
- opcode->name);
+ as_bad (_("Unable to use @pcl relocation for insn %s"),
+ opcode->name);
}
else
{
/* Check if the current instruction is legally used. */
if (arc_last_insns[1].has_delay_slot
&& is_br_jmp_insn_p (arc_last_insns[0].opcode))
- as_bad_where (frag_now->fr_file, frag_now->fr_line,
- _("A jump/branch instruction in delay slot."));
+ as_bad (_("Insn %s has a jump/branch instruction %s in its delay slot."),
+ arc_last_insns[1].opcode->name,
+ arc_last_insns[0].opcode->name);
+ if (arc_last_insns[1].has_delay_slot
+ && arc_last_insns[0].has_limm)
+ as_bad (_("Insn %s has an instruction %s with limm in its delay slot."),
+ arc_last_insns[1].opcode->name,
+ arc_last_insns[0].opcode->name);
}
void
if (*r_type_p == BFD_RELOC_32
&& exp->X_op == O_subtract
&& exp->X_op_symbol != NULL
- && exp->X_op_symbol->bsym->section == now_seg)
+ && S_GET_SEGMENT (exp->X_op_symbol) == now_seg)
*r_type_p = BFD_RELOC_ARC_32_PCREL;
}
insn_name = xstrdup (p);
restore_line_pointer (c);
+ /* Convert to lower case. */
+ for (p = insn_name; *p; ++p)
+ *p = TOLOWER (*p);
+
/* 2nd: get major opcode. */
if (*input_line_pointer != ',')
{
/* Tag_ARC_ABI_tls. */
arc_set_attribute_int (Tag_ARC_ABI_tls, tls_option);
+
+ /* Tag_ARC_ATR_version. */
+ arc_set_attribute_int (Tag_ARC_ATR_version, 1);
+
+ /* Tag_ARC_ABI_rf16. */
+ if (attributes_set_explicitly[Tag_ARC_ABI_rf16]
+ && bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
+ Tag_ARC_ABI_rf16)
+ && !rf16_only)
+ {
+ as_warn (_("Overwrite explicitly set Tag_ARC_ABI_rf16 to full "
+ "register file"));
+ bfd_elf_add_proc_attr_int (stdoutput, Tag_ARC_ABI_rf16, 0);
+ }
}
/* Add the default contents for the .ARC.attributes section. */
T (Tag_ARC_ABI_double_size),
T (Tag_ARC_ISA_config),
T (Tag_ARC_ISA_apex),
- T (Tag_ARC_ISA_mpy_option)
+ T (Tag_ARC_ISA_mpy_option),
+ T (Tag_ARC_ATR_version)
#undef T
};
unsigned int i;
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