A series of fixes to addres problems detected by compiling the assembler with address...

[deliverable/binutils-gdb.git] / gas / config / tc-arc.c

diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index a56b2a5df1ac760801c0b5c9eb56d7d8746af541..c1d5ea3d47024d8b2da74be4e25e19ea8edbcd19 100644 (file)
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -1,5 +1,5 @@
 /* tc-arc.c -- Assembler for the ARC
-   Copyright (C) 1994-2017 Free Software Foundation, Inc.
+   Copyright (C) 1994-2019 Free Software Foundation, Inc.
 
    Contributor: Claudiu Zissulescu <claziss@synopsys.com>
 
@@ -22,7 +22,6 @@
 
 #include "as.h"
 #include "subsegs.h"
-#include "struc-symbol.h"
 #include "dwarf2dbg.h"
 #include "dw2gencfi.h"
 #include "safe-ctype.h"
@@ -49,9 +48,6 @@
 #define LP_INSN(x)      ((MAJOR_OPCODE (x) == 0x4) \
                          && (SUB_OPCODE (x) == 0x28))
 
-/* Equal to MAX_PRECISION in atof-ieee.c.  */
-#define MAX_LITTLENUMS 6
-
 #ifndef TARGET_WITH_CPU
 #define TARGET_WITH_CPU "arc700"
 #endif /* TARGET_WITH_CPU */
@@ -107,8 +103,18 @@ enum arc_rlx_types
 #define is_spfp_p(op)           (((sc) == SPX))
 #define is_dpfp_p(op)           (((sc) == DPX))
 #define is_fpuda_p(op)          (((sc) == DPA))
-#define is_br_jmp_insn_p(op)    (((op)->insn_class == BRANCH \
-                                 || (op)->insn_class == JUMP))
+#define is_br_jmp_insn_p(op)    (((op)->insn_class == BRANCH           \
+                                 || (op)->insn_class == JUMP           \
+                                 || (op)->insn_class == BRCC           \
+                                 || (op)->insn_class == BBIT0          \
+                                 || (op)->insn_class == BBIT1          \
+                                 || (op)->insn_class == BI             \
+                                 || (op)->insn_class == EI             \
+                                 || (op)->insn_class == ENTER          \
+                                 || (op)->insn_class == JLI            \
+                                 || (op)->insn_class == LOOP           \
+                                 || (op)->insn_class == LEAVE          \
+                                 ))
 #define is_kernel_insn_p(op)    (((op)->insn_class == KERNEL))
 #define is_nps400_p(op)         (((sc) == NPS400))
 
@@ -465,6 +471,9 @@ static const struct cpu_type
 /* Information about the cpu/variant we're assembling for.  */
 static struct cpu_type selected_cpu = { 0, 0, 0, E_ARC_OSABI_CURRENT, 0 };
 
+/* TRUE if current assembly code uses RF16 only registers.  */
+static bfd_boolean rf16_only = TRUE;
+
 /* MPY option.  */
 static unsigned mpy_option = 0;
 
@@ -786,7 +795,7 @@ md_number_to_chars_midend (char *buf, unsigned long long val, int n)
       md_number_to_chars (buf, val, n);
       break;
     case 6:
-      md_number_to_chars (buf, (val & 0xffff00000000) >> 32, 2);
+      md_number_to_chars (buf, (val & 0xffff00000000ull) >> 32, 2);
       md_number_to_chars_midend (buf + 2, (val & 0xffffffff), 4);
       break;
     case 4:
@@ -794,7 +803,7 @@ md_number_to_chars_midend (char *buf, unsigned long long val, int n)
       md_number_to_chars (buf + 2, (val & 0xffff), 2);
       break;
     case 8:
-      md_number_to_chars_midend (buf, (val & 0xffffffff00000000) >> 32, 4);
+      md_number_to_chars_midend (buf, (val & 0xffffffff00000000ull) >> 32, 4);
       md_number_to_chars_midend (buf + 4, (val & 0xffffffff), 4);
       break;
     default:
@@ -1872,13 +1881,20 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
                case O_symbol:
                  {
                    const char *p;
+                   char *tmpp, *pp;
                    const struct arc_aux_reg *auxr;
 
                    if (opcode->insn_class != AUXREG)
                      goto de_fault;
                    p = S_GET_NAME (tok[tokidx].X_add_symbol);
 
-                   auxr = hash_find (arc_aux_hash, p);
+                   /* For compatibility reasons, an aux register can
+                      be spelled with upper or lower case
+                      letters.  */
+                   tmpp = strdup (p);
+                   for (pp = tmpp; *pp; ++pp) *pp = TOLOWER (*pp);
+
+                   auxr = hash_find (arc_aux_hash, tmpp);
                    if (auxr)
                      {
                        /* We modify the token array here, safe in the
@@ -1889,6 +1905,7 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
                        tok[tokidx].X_add_number = auxr->address;
                        ARC_SET_FLAG (tok[tokidx].X_add_symbol, ARC_FLAG_AUX);
                      }
+                   free (tmpp);
 
                    if (tok[tokidx].X_op != O_constant)
                      goto de_fault;
@@ -2365,6 +2382,17 @@ autodetect_attributes (const struct arc_opcode *opcode,
        default:
          break;
        }
+
+      switch (tok[i].X_op)
+       {
+       case O_register:
+         if ((tok[i].X_add_number >= 4 && tok[i].X_add_number <= 9)
+             || (tok[i].X_add_number >= 16 && tok[i].X_add_number <= 25))
+           rf16_only = FALSE;
+         break;
+       default:
+         break;
+       }
     }
 }
 
@@ -3240,7 +3268,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
   int size, fix;
   struct arc_relax_type *relax_arg = &fragP->tc_frag_data;
 
-  fix = (fragP->fr_fix < 0 ? 0 : fragP->fr_fix);
+  fix = fragP->fr_fix;
   dest = fragP->fr_literal + fix;
   table_entry = TC_GENERIC_RELAX_TABLE + fragP->fr_subtype;
 
@@ -4107,6 +4135,11 @@ assemble_insn (const struct arc_opcode *opcode,
     as_bad (_("Insn %s has a jump/branch instruction %s in its delay slot."),
            arc_last_insns[1].opcode->name,
            arc_last_insns[0].opcode->name);
+  if (arc_last_insns[1].has_delay_slot
+      && arc_last_insns[0].has_limm)
+    as_bad (_("Insn %s has an instruction %s with limm in its delay slot."),
+           arc_last_insns[1].opcode->name,
+           arc_last_insns[0].opcode->name);
 }
 
 void
@@ -4174,7 +4207,7 @@ arc_check_reloc (expressionS *exp,
   if (*r_type_p == BFD_RELOC_32
       && exp->X_op == O_subtract
       && exp->X_op_symbol != NULL
-      && exp->X_op_symbol->bsym->section == now_seg)
+      && S_GET_SEGMENT (exp->X_op_symbol) == now_seg)
     *r_type_p = BFD_RELOC_ARC_32_PCREL;
 }
 
@@ -4354,6 +4387,10 @@ tokenize_extinsn (extInstruction_t *einsn)
   insn_name = xstrdup (p);
   restore_line_pointer (c);
 
+  /* Convert to lower case.  */
+  for (p = insn_name; *p; ++p)
+    *p = TOLOWER (*p);
+
   /* 2nd: get major opcode.  */
   if (*input_line_pointer != ',')
     {
@@ -4987,6 +5024,20 @@ arc_set_public_attributes (void)
 
   /* Tag_ARC_ABI_tls.  */
   arc_set_attribute_int (Tag_ARC_ABI_tls, tls_option);
+
+  /* Tag_ARC_ATR_version.  */
+  arc_set_attribute_int (Tag_ARC_ATR_version, 1);
+
+  /* Tag_ARC_ABI_rf16.  */
+  if (attributes_set_explicitly[Tag_ARC_ABI_rf16]
+      && bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
+                                  Tag_ARC_ABI_rf16)
+      && !rf16_only)
+    {
+      as_warn (_("Overwrite explicitly set Tag_ARC_ABI_rf16 to full "
+                "register file"));
+      bfd_elf_add_proc_attr_int (stdoutput, Tag_ARC_ABI_rf16, 0);
+    }
 }
 
 /* Add the default contents for the .ARC.attributes section.  */
@@ -5031,7 +5082,8 @@ int arc_convert_symbolic_attribute (const char *name)
   T (Tag_ARC_ABI_double_size),
   T (Tag_ARC_ISA_config),
   T (Tag_ARC_ISA_apex),
-  T (Tag_ARC_ISA_mpy_option)
+  T (Tag_ARC_ISA_mpy_option),
+  T (Tag_ARC_ATR_version)
 #undef T
     };
   unsigned int i;