/* tc-i386.h -- Header file for tc-i386.c
- Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
- 2001, 2002, 2003, 2004
- Free Software Foundation, Inc.
+ Copyright (C) 1989-2019 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
+ the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
#ifndef TC_I386
#define TC_I386 1
-#ifndef BFD_ASSEMBLER
-#error So, do you know what you are doing?
-#endif
+#include "opcodes/i386-opc.h"
-#ifdef ANSI_PROTOTYPES
struct fix;
-#endif
#define TARGET_BYTES_BIG_ENDIAN 0
-#define TARGET_ARCH bfd_arch_i386
+#define TARGET_ARCH (i386_arch ())
#define TARGET_MACH (i386_mach ())
+extern enum bfd_architecture i386_arch (void);
extern unsigned long i386_mach (void);
#ifdef TE_FreeBSD
#ifdef TE_FreeBSD
#define ELF_TARGET_FORMAT "elf32-i386-freebsd"
+#define ELF_TARGET_FORMAT64 "elf64-x86-64-freebsd"
#elif defined (TE_VXWORKS)
#define ELF_TARGET_FORMAT "elf32-i386-vxworks"
+#elif defined (TE_NACL)
+#define ELF_TARGET_FORMAT "elf32-i386-nacl"
+#define ELF_TARGET_FORMAT32 "elf32-x86-64-nacl"
+#define ELF_TARGET_FORMAT64 "elf64-x86-64-nacl"
+#elif defined TE_CLOUDABI
+#define ELF_TARGET_FORMAT64 "elf64-x86-64-cloudabi"
+#endif
+
+#ifdef TE_SOLARIS
+#define ELF_TARGET_FORMAT "elf32-i386-sol2"
+#define ELF_TARGET_FORMAT64 "elf64-x86-64-sol2"
#endif
#ifndef ELF_TARGET_FORMAT
#define ELF_TARGET_FORMAT "elf32-i386"
#endif
+#ifndef ELF_TARGET_FORMAT64
+#define ELF_TARGET_FORMAT64 "elf64-x86-64"
+#endif
+
+#ifndef ELF_TARGET_FORMAT32
+#define ELF_TARGET_FORMAT32 "elf32-x86-64"
+#endif
+
+#ifndef ELF_TARGET_L1OM_FORMAT
+#define ELF_TARGET_L1OM_FORMAT "elf64-l1om"
+#endif
+
+#ifndef ELF_TARGET_K1OM_FORMAT
+#define ELF_TARGET_K1OM_FORMAT "elf64-k1om"
+#endif
+
+#ifndef ELF_TARGET_IAMCU_FORMAT
+#define ELF_TARGET_IAMCU_FORMAT "elf32-iamcu"
+#endif
+
#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
- || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
-extern const char *i386_target_format PARAMS ((void));
+ || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
+ || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
+extern const char *i386_target_format (void);
#define TARGET_FORMAT i386_target_format ()
#else
-#ifdef OBJ_ELF
-#define TARGET_FORMAT ELF_TARGET_FORMAT
+#ifdef TE_GO32
+#define TARGET_FORMAT "coff-go32"
#endif
#ifdef OBJ_AOUT
#define TARGET_FORMAT AOUT_TARGET_FORMAT
#endif
#endif
-#if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF))
-#define md_end i386_elf_emit_arch_note
-extern void i386_elf_emit_arch_note PARAMS ((void));
-#endif
-
#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
+/* '$' may be used as immediate prefix. */
+#undef LOCAL_LABELS_DOLLAR
+#define LOCAL_LABELS_DOLLAR 0
+#undef LOCAL_LABELS_FB
#define LOCAL_LABELS_FB 1
extern const char extra_symbol_chars[];
#define tc_symbol_chars extra_symbol_chars
-#define MAX_OPERANDS 3 /* max operands per insn */
-#define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */
-#define MAX_MEMORY_OPERANDS 2 /* max memory refs per insn (string ops) */
-
-/* Prefixes will be emitted in the order defined below.
- WAIT_PREFIX must be the first prefix since FWAIT is really is an
- instruction, and so must come before any prefixes. */
-#define WAIT_PREFIX 0
-#define LOCKREP_PREFIX 1
-#define ADDR_PREFIX 2
-#define DATA_PREFIX 3
-#define SEG_PREFIX 4
-#define REX_PREFIX 5 /* must come last. */
-#define MAX_PREFIXES 6 /* max prefixes per opcode */
-
-/* we define the syntax here (modulo base,index,scale syntax) */
-#define REGISTER_PREFIX '%'
-#define IMMEDIATE_PREFIX '$'
-#define ABSOLUTE_PREFIX '*'
-
-#define TWO_BYTE_OPCODE_ESCAPE 0x0f
-#define NOP_OPCODE (char) 0x90
-
-/* register numbers */
-#define EBP_REG_NUM 5
-#define ESP_REG_NUM 4
-
-/* modrm_byte.regmem for twobyte escape */
-#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
-/* index_base_byte.index for no index register addressing */
-#define NO_INDEX_REGISTER ESP_REG_NUM
-/* index_base_byte.base for no base register addressing */
-#define NO_BASE_REGISTER EBP_REG_NUM
-#define NO_BASE_REGISTER_16 6
-
-/* these are the instruction mnemonic suffixes. */
-#define WORD_MNEM_SUFFIX 'w'
-#define BYTE_MNEM_SUFFIX 'b'
-#define SHORT_MNEM_SUFFIX 's'
-#define LONG_MNEM_SUFFIX 'l'
-#define QWORD_MNEM_SUFFIX 'q'
-/* Intel Syntax */
-#define LONG_DOUBLE_MNEM_SUFFIX 'x'
-
-/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
-#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
-#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
-
-#define END_OF_INSN '\0'
-
-typedef struct
-{
- /* instruction name sans width suffix ("mov" for movl insns) */
- char *name;
-
- /* how many operands */
- unsigned int operands;
-
- /* base_opcode is the fundamental opcode byte without optional
- prefix(es). */
- unsigned int base_opcode;
-
- /* extension_opcode is the 3 bit extension for group <n> insns.
- This field is also used to store the 8-bit opcode suffix for the
- AMD 3DNow! instructions.
- If this template has no extension opcode (the usual case) use None */
- unsigned int extension_opcode;
-#define None 0xffff /* If no extension_opcode is possible. */
-
- /* cpu feature flags */
- unsigned int cpu_flags;
-#define Cpu086 0x1 /* Any old cpu will do, 0 does the same */
-#define Cpu186 0x2 /* i186 or better required */
-#define Cpu286 0x4 /* i286 or better required */
-#define Cpu386 0x8 /* i386 or better required */
-#define Cpu486 0x10 /* i486 or better required */
-#define Cpu586 0x20 /* i585 or better required */
-#define Cpu686 0x40 /* i686 or better required */
-#define CpuP4 0x80 /* Pentium4 or better required */
-#define CpuK6 0x100 /* AMD K6 or better required*/
-#define CpuAthlon 0x200 /* AMD Athlon or better required*/
-#define CpuSledgehammer 0x400 /* Sledgehammer or better required */
-#define CpuMMX 0x800 /* MMX support required */
-#define CpuMMX2 0x1000 /* extended MMX support (with SSE or 3DNow!Ext) required */
-#define CpuSSE 0x2000 /* Streaming SIMD extensions required */
-#define CpuSSE2 0x4000 /* Streaming SIMD extensions 2 required */
-#define Cpu3dnow 0x8000 /* 3dnow! support required */
-#define Cpu3dnowA 0x10000 /* 3dnow!Extensions support required */
-#define CpuPNI 0x20000 /* Prescott New Instructions required */
-#define CpuPadLock 0x40000 /* VIA PadLock required */
-#define CpuSVME 0x80000 /* AMD Secure Virtual Machine Ext-s required */
-
- /* These flags are set by gas depending on the flag_code. */
-#define Cpu64 0x4000000 /* 64bit support required */
-#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */
-
- /* The default value for unknown CPUs - enable all features to avoid problems. */
-#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
- |CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI \
- |Cpu3dnow|Cpu3dnowA|CpuK6|CpuAthlon|CpuPadLock|CpuSVME)
-
- /* the bits in opcode_modifier are used to generate the final opcode from
- the base_opcode. These bits also are used to detect alternate forms of
- the same instruction */
- unsigned int opcode_modifier;
-
- /* opcode_modifier bits: */
-#define W 0x1 /* set if operands can be words or dwords
- encoded the canonical way */
-#define D 0x2 /* D = 0 if Reg --> Regmem;
- D = 1 if Regmem --> Reg: MUST BE 0x2 */
-#define Modrm 0x4
-#define FloatR 0x8 /* src/dest swap for floats: MUST BE 0x8 */
-#define ShortForm 0x10 /* register is in low 3 bits of opcode */
-#define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */
-#define Jump 0x40 /* special case for jump insns. */
-#define JumpDword 0x80 /* call and jump */
-#define JumpByte 0x100 /* loop and jecxz */
-#define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */
-#define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */
-#define Seg2ShortForm 0x800 /* encoding of load segment reg insns */
-#define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */
-#define Size16 0x2000 /* needs size prefix if in 32-bit mode */
-#define Size32 0x4000 /* needs size prefix if in 16-bit mode */
-#define Size64 0x8000 /* needs size prefix if in 16-bit mode */
-#define IgnoreSize 0x10000 /* instruction ignores operand size prefix */
-#define DefaultSize 0x20000 /* default insn size depends on mode */
-#define No_bSuf 0x40000 /* b suffix on instruction illegal */
-#define No_wSuf 0x80000 /* w suffix on instruction illegal */
-#define No_lSuf 0x100000 /* l suffix on instruction illegal */
-#define No_sSuf 0x200000 /* s suffix on instruction illegal */
-#define No_qSuf 0x400000 /* q suffix on instruction illegal */
-#define No_xSuf 0x800000 /* x suffix on instruction illegal */
-#define FWait 0x1000000 /* instruction needs FWAIT */
-#define IsString 0x2000000 /* quick test for string instructions */
-#define regKludge 0x4000000 /* fake an extra reg operand for clr, imul */
-#define IsPrefix 0x8000000 /* opcode is a prefix */
-#define ImmExt 0x10000000 /* instruction has extension in 8 bit imm */
-#define NoRex64 0x20000000 /* instruction don't need Rex64 prefix. */
-#define Rex64 0x40000000 /* instruction require Rex64 prefix. */
-#define Ugh 0x80000000 /* deprecated fp insn, gets a warning */
-
- /* operand_types[i] describes the type of operand i. This is made
- by OR'ing together all of the possible type masks. (e.g.
- 'operand_types[i] = Reg|Imm' specifies that operand i can be
- either a register or an immediate operand. */
- unsigned int operand_types[3];
-
- /* operand_types[i] bits */
- /* register */
-#define Reg8 0x1 /* 8 bit reg */
-#define Reg16 0x2 /* 16 bit reg */
-#define Reg32 0x4 /* 32 bit reg */
-#define Reg64 0x8 /* 64 bit reg */
- /* immediate */
-#define Imm8 0x10 /* 8 bit immediate */
-#define Imm8S 0x20 /* 8 bit immediate sign extended */
-#define Imm16 0x40 /* 16 bit immediate */
-#define Imm32 0x80 /* 32 bit immediate */
-#define Imm32S 0x100 /* 32 bit immediate sign extended */
-#define Imm64 0x200 /* 64 bit immediate */
-#define Imm1 0x400 /* 1 bit immediate */
- /* memory */
-#define BaseIndex 0x800
- /* Disp8,16,32 are used in different ways, depending on the
- instruction. For jumps, they specify the size of the PC relative
- displacement, for baseindex type instructions, they specify the
- size of the offset relative to the base register, and for memory
- offset instructions such as `mov 1234,%al' they specify the size of
- the offset relative to the segment base. */
-#define Disp8 0x1000 /* 8 bit displacement */
-#define Disp16 0x2000 /* 16 bit displacement */
-#define Disp32 0x4000 /* 32 bit displacement */
-#define Disp32S 0x8000 /* 32 bit signed displacement */
-#define Disp64 0x10000 /* 64 bit displacement */
- /* specials */
-#define InOutPortReg 0x20000 /* register to hold in/out port addr = dx */
-#define ShiftCount 0x40000 /* register to hold shift cound = cl */
-#define Control 0x80000 /* Control register */
-#define Debug 0x100000 /* Debug register */
-#define Test 0x200000 /* Test register */
-#define FloatReg 0x400000 /* Float register */
-#define FloatAcc 0x800000 /* Float stack top %st(0) */
-#define SReg2 0x1000000 /* 2 bit segment register */
-#define SReg3 0x2000000 /* 3 bit segment register */
-#define Acc 0x4000000 /* Accumulator %al or %ax or %eax */
-#define JumpAbsolute 0x8000000
-#define RegMMX 0x10000000 /* MMX register */
-#define RegXMM 0x20000000 /* XMM registers in PIII */
-#define EsSeg 0x40000000 /* String insn operand with fixed es segment */
-
- /* InvMem is for instructions with a modrm byte that only allow a
- general register encoding in the i.tm.mode and i.tm.regmem fields,
- eg. control reg moves. They really ought to support a memory form,
- but don't, so we add an InvMem flag to the register operand to
- indicate that it should be encoded in the i.tm.regmem field. */
-#define InvMem 0x80000000
-
-#define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
-#define WordReg (Reg16|Reg32|Reg64)
-#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
-#define Imm (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
-#define EncImm (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
-#define Disp (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
-#define AnyMem (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem) /* General memory */
- /* The following aliases are defined because the opcode table
- carefully specifies the allowed memory types for each instruction.
- At the moment we can only tell a memory reference size by the
- instruction suffix, so there's not much point in defining Mem8,
- Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
- the suffix directly to check memory operands. */
-#define LLongMem AnyMem /* 64 bits (or more) */
-#define LongMem AnyMem /* 32 bit memory ref */
-#define ShortMem AnyMem /* 16 bit memory ref */
-#define WordMem AnyMem /* 16 or 32 bit memory ref */
-#define ByteMem AnyMem /* 8 bit memory ref */
-}
-template;
-
-/*
- 'templates' is for grouping together 'template' structures for opcodes
- of the same name. This is only used for storing the insns in the grand
- ole hash table of insns.
- The templates themselves start at START and range up to (but not including)
- END.
- */
-typedef struct
-{
- const template *start;
- const template *end;
-}
-templates;
-
-/* these are for register name --> number & type hash lookup */
-typedef struct
-{
- char *reg_name;
- unsigned int reg_type;
- unsigned int reg_flags;
-#define RegRex 0x1 /* Extended register. */
-#define RegRex64 0x2 /* Extended 8 bit register. */
- unsigned int reg_num;
-}
-reg_entry;
-
-typedef struct
-{
- char *seg_name;
- unsigned int seg_prefix;
-}
-seg_entry;
-
-/* 386 operand encoding bytes: see 386 book for details of this. */
-typedef struct
-{
- unsigned int regmem; /* codes register or memory operand */
- unsigned int reg; /* codes register operand (or extended opcode) */
- unsigned int mode; /* how to interpret regmem & reg */
-}
-modrm_byte;
-
-/* x86-64 extension prefix. */
-typedef int rex_byte;
-#define REX_OPCODE 0x40
-
-/* Indicates 64 bit operand size. */
-#define REX_MODE64 8
-/* High extension to reg field of modrm byte. */
-#define REX_EXTX 4
-/* High extension to SIB index field. */
-#define REX_EXTY 2
-/* High extension to base field of modrm or SIB, or reg field of opcode. */
-#define REX_EXTZ 1
-
-/* 386 opcode byte to code indirect addressing. */
-typedef struct
-{
- unsigned base;
- unsigned index;
- unsigned scale;
-}
-sib_byte;
-
-/* x86 arch names and features */
-typedef struct
-{
- const char *name; /* arch name */
- unsigned int flags; /* cpu feature flags */
-}
-arch_entry;
+extern const char *i386_comment_chars;
+#define tc_comment_chars i386_comment_chars
/* The name of the global offset table generated by the compiler. Allow
this to be overridden if need be. */
#define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
#endif
-#ifndef LEX_AT
+#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && !defined (LEX_AT)
#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES)
-extern void x86_cons PARAMS ((expressionS *, int));
+#endif
+extern bfd_reloc_code_real_type x86_cons (expressionS *, int);
-#define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP)
+#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP, RELOC) \
+ x86_cons_fix_new(FRAG, OFF, LEN, EXP, RELOC)
extern void x86_cons_fix_new
- PARAMS ((fragS *, unsigned int, unsigned int, expressionS *));
-#endif
+(fragS *, unsigned int, unsigned int, expressionS *, bfd_reloc_code_real_type);
-#ifdef TE_PE
-#define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_pe_cons_fix_new(FRAG, OFF, LEN, EXP)
-extern void x86_pe_cons_fix_new
- PARAMS ((fragS *, unsigned int, unsigned int, expressionS *));
-#endif
+#define TC_ADDRESS_BYTES x86_address_bytes
+extern int x86_address_bytes (void);
#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */
#define NO_RELOC BFD_RELOC_NONE
-void i386_validate_fix PARAMS ((struct fix *));
+void i386_validate_fix (struct fix *);
#define TC_VALIDATE_FIX(FIX,SEGTYPE,SKIP) i386_validate_fix(FIX)
#define tc_fix_adjustable(X) tc_i386_fix_adjustable(X)
-extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
+extern int tc_i386_fix_adjustable (struct fix *);
/* Values passed to md_apply_fix don't include the symbol value. */
#define MD_APPLY_SYM_VALUE(FIX) 0
/* This expression evaluates to true if the relocation is for a local
object for which we still want to do the relocation at runtime.
False if we are willing to perform this relocation while building
- the .o file. GOTOFF does not need to be checked here because it is
- not pcrel. I am not sure if some of the others are ever used with
- pcrel, but it is easier to be safe than sorry. */
+ the .o file. GOTOFF and GOT32 do not need to be checked here because
+ they are not pcrel. .*/
-#define TC_FORCE_RELOCATION_LOCAL(FIX) \
- (!(FIX)->fx_pcrel \
- || (FIX)->fx_plt \
- || (FIX)->fx_r_type == BFD_RELOC_386_PLT32 \
- || (FIX)->fx_r_type == BFD_RELOC_386_GOT32 \
- || (FIX)->fx_r_type == BFD_RELOC_386_GOTPC \
- || TC_FORCE_RELOCATION (FIX))
+#define TC_FORCE_RELOCATION_LOCAL(FIX) \
+ (GENERIC_FORCE_RELOCATION_LOCAL (FIX) \
+ || (FIX)->fx_r_type == BFD_RELOC_386_PLT32 \
+ || (FIX)->fx_r_type == BFD_RELOC_386_GOTPC \
+ || (FIX)->fx_r_type == BFD_RELOC_X86_64_GOTPCREL \
+ || (FIX)->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX \
+ || (FIX)->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX)
-#define md_operand(x)
+extern int i386_parse_name (char *, expressionS *, char *);
+#define md_parse_name(s, e, m, c) i386_parse_name (s, e, c)
+
+extern operatorT i386_operator (const char *name, unsigned int operands, char *);
+#define md_operator i386_operator
+
+extern int i386_need_index_operator (void);
+#define md_need_index_operator i386_need_index_operator
+
+#define md_register_arithmetic 0
extern const struct relax_type md_relax_table[];
#define TC_GENERIC_RELAX_TABLE md_relax_table
goto around; \
}
-#define MAX_MEM_FOR_RS_ALIGN_CODE 15
-
-extern void i386_align_code PARAMS ((fragS *, int));
+#define MAX_MEM_FOR_RS_ALIGN_CODE (alignment ? ((1 << alignment) - 1) : 1)
-#define HANDLE_ALIGN(fragP) \
-if (fragP->fr_type == rs_align_code) \
- i386_align_code (fragP, (fragP->fr_next->fr_address \
- - fragP->fr_address \
- - fragP->fr_fix));
+extern void i386_cons_align (int);
+#define md_cons_align(nbytes) i386_cons_align (nbytes)
-void i386_print_statistics PARAMS ((FILE *));
+void i386_print_statistics (FILE *);
#define tc_print_statistics i386_print_statistics
+extern unsigned int i386_frag_max_var (fragS *);
+#define md_frag_max_var i386_frag_max_var
+
+extern long i386_generic_table_relax_frag (segT, fragS *, long);
+#define md_generic_table_relax_frag(segment, fragP, stretch) \
+ i386_generic_table_relax_frag (segment, fragP, stretch)
+
#define md_number_to_chars number_to_chars_littleendian
-#ifdef SCO_ELF
-#define tc_init_after_args() sco_id ()
-extern void sco_id PARAMS ((void));
-#endif
+enum processor_type
+{
+ PROCESSOR_UNKNOWN,
+ PROCESSOR_I386,
+ PROCESSOR_I486,
+ PROCESSOR_PENTIUM,
+ PROCESSOR_PENTIUMPRO,
+ PROCESSOR_PENTIUM4,
+ PROCESSOR_NOCONA,
+ PROCESSOR_CORE,
+ PROCESSOR_CORE2,
+ PROCESSOR_COREI7,
+ PROCESSOR_L1OM,
+ PROCESSOR_K1OM,
+ PROCESSOR_IAMCU,
+ PROCESSOR_K6,
+ PROCESSOR_ATHLON,
+ PROCESSOR_K8,
+ PROCESSOR_GENERIC32,
+ PROCESSOR_GENERIC64,
+ PROCESSOR_AMDFAM10,
+ PROCESSOR_BD,
+ PROCESSOR_ZNVER,
+ PROCESSOR_BT
+};
+
+extern enum processor_type cpu_arch_tune;
+extern enum processor_type cpu_arch_isa;
+extern i386_cpu_flags cpu_arch_isa_flags;
+
+struct i386_tc_frag_data
+{
+ union
+ {
+ fragS *padding_fragP;
+ fragS *branch_fragP;
+ } u;
+ addressT padding_address;
+ enum processor_type isa;
+ i386_cpu_flags isa_flags;
+ enum processor_type tune;
+ unsigned int max_bytes;
+ unsigned char length;
+ unsigned char last_length;
+ unsigned char max_prefix_length;
+ unsigned char prefix_length;
+ unsigned char default_prefix;
+ unsigned char cmp_size;
+ unsigned int classified : 1;
+ unsigned int branch_type : 3;
+};
+
+/* We need to emit the right NOP pattern in .align frags. This is
+ done after the text-to-bits assembly pass, so we need to mark it with
+ the isa/tune settings at the time the .align was assembled. */
+#define TC_FRAG_TYPE struct i386_tc_frag_data
+
+#define TC_FRAG_INIT(FRAGP, MAX_BYTES) \
+ do \
+ { \
+ (FRAGP)->tc_frag_data.u.padding_fragP = NULL; \
+ (FRAGP)->tc_frag_data.padding_address = 0; \
+ (FRAGP)->tc_frag_data.isa = cpu_arch_isa; \
+ (FRAGP)->tc_frag_data.isa_flags = cpu_arch_isa_flags; \
+ (FRAGP)->tc_frag_data.tune = cpu_arch_tune; \
+ (FRAGP)->tc_frag_data.max_bytes = (MAX_BYTES); \
+ (FRAGP)->tc_frag_data.length = 0; \
+ (FRAGP)->tc_frag_data.last_length = 0; \
+ (FRAGP)->tc_frag_data.max_prefix_length = 0; \
+ (FRAGP)->tc_frag_data.prefix_length = 0; \
+ (FRAGP)->tc_frag_data.default_prefix = 0; \
+ (FRAGP)->tc_frag_data.cmp_size = 0; \
+ (FRAGP)->tc_frag_data.classified = 0; \
+ (FRAGP)->tc_frag_data.branch_type = 0; \
+ } \
+ while (0)
+
+#define WORKING_DOT_WORD 1
+
+/* How to generate NOPs for .nop direct directive. */
+extern void i386_generate_nops (fragS *, char *, offsetT, int);
+#define md_generate_nops(frag, where, amount, control) \
+ i386_generate_nops ((frag), (where), (amount), (control))
+
+#define HANDLE_ALIGN(fragP) \
+if (fragP->fr_type == rs_align_code) \
+ { \
+ offsetT __count = (fragP->fr_next->fr_address \
+ - fragP->fr_address \
+ - fragP->fr_fix); \
+ if (__count > 0 \
+ && (unsigned int) __count <= fragP->tc_frag_data.max_bytes) \
+ md_generate_nops (fragP, fragP->fr_literal + fragP->fr_fix, \
+ __count, 0); \
+ }
/* We want .cfi_* pseudo-ops for generating unwind info. */
#define TARGET_USE_CFIPOP 1
extern int x86_cie_data_alignment;
#define DWARF2_CIE_DATA_ALIGNMENT x86_cie_data_alignment
-#define tc_regname_to_dw2regnum tc_x86_regname_to_dw2regnum
-extern int tc_x86_regname_to_dw2regnum PARAMS ((const char *regname));
+extern int x86_dwarf2_addr_size (void);
+#define DWARF2_ADDR_SIZE(bfd) x86_dwarf2_addr_size ()
+
+#define tc_parse_to_dw2regnum tc_x86_parse_to_dw2regnum
+extern void tc_x86_parse_to_dw2regnum (expressionS *);
#define tc_cfi_frame_initial_instructions tc_x86_frame_initial_instructions
-extern void tc_x86_frame_initial_instructions PARAMS ((void));
+extern void tc_x86_frame_initial_instructions (void);
#define md_elf_section_type(str,len) i386_elf_section_type (str, len)
-extern int i386_elf_section_type PARAMS ((const char *, size_t len));
+extern int i386_elf_section_type (const char *, size_t);
+
+#ifdef TE_SOLARIS
+#define md_fix_up_eh_frame(sec) i386_solaris_fix_up_eh_frame (sec)
+extern void i386_solaris_fix_up_eh_frame (segT);
+#endif
+
+/* Support for SHF_X86_64_LARGE */
+extern bfd_vma x86_64_section_word (char *, size_t);
+extern bfd_vma x86_64_section_letter (int, const char **);
+#define md_elf_section_letter(LETTER, PTR_MSG) x86_64_section_letter (LETTER, PTR_MSG)
+#define md_elf_section_word(STR, LEN) x86_64_section_word (STR, LEN)
+
+#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
+extern void x86_cleanup (void);
+#define md_cleanup() x86_cleanup ()
+#endif
#ifdef TE_PE
#endif /* TE_PE */
+/* X_add_symbol:X_op_symbol (Intel mode only) */
+#define O_full_ptr O_md2
+
+#ifdef OBJ_MACH_O
+
+#define TC_FORCE_RELOCATION(FIX) (obj_mach_o_force_reloc (FIX))
+
+#define TC_FORCE_RELOCATION_SUB_SAME(FIX,SEG) \
+ (obj_mach_o_force_reloc_sub_same (FIX, SEG))
+
+#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX,SEG) \
+ (obj_mach_o_force_reloc_sub_local (FIX, SEG))
+
+#define TC_VALIDATE_FIX_SUB(FIX, SEG) 1
+
+#endif /* OBJ_MACH_O */
+
#endif /* TC_I386 */
projects / deliverable / binutils-gdb.git / blobdiff