\input texinfo @c -*-Texinfo-*-
-@c Copyright (C) 1991-2018 Free Software Foundation, Inc.
+@c Copyright (C) 1991-2020 Free Software Foundation, Inc.
@c UPDATE!! On future updates--
@c (1) check for new machine-dep cmdline options in
@c md_parse_option definitions in config/tc-*.c
@ifset Blackfin
@set Blackfin
@end ifset
+@ifset BPF
+@set BPF
+@end ifset
@ifset H8/300
@set H8
@end ifset
This file documents the GNU Assembler "@value{AS}".
@c man begin COPYRIGHT
-Copyright @copyright{} 1991-2018 Free Software Foundation, Inc.
+Copyright @copyright{} 1991-2020 Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.3
@end tex
@vskip 0pt plus 1filll
-Copyright @copyright{} 1991-2018 Free Software Foundation, Inc.
+Copyright @copyright{} 1991-2020 Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.3
[@b{--debug-prefix-map} @var{old}=@var{new}]
[@b{--defsym} @var{sym}=@var{val}] [@b{-f}] [@b{-g}] [@b{--gstabs}]
[@b{--gstabs+}] [@b{--gdwarf-2}] [@b{--gdwarf-sections}]
+ [@b{--gdwarf-cie-version}=@var{VERSION}]
[@b{--help}] [@b{-I} @var{dir}] [@b{-J}]
[@b{-K}] [@b{-L}] [@b{--listing-lhs-width}=@var{NUM}]
[@b{--listing-lhs-width2}=@var{NUM}] [@b{--listing-rhs-width}=@var{NUM}]
[@b{-mno-fdpic}]
[@b{-mnopic}]
@end ifset
+@ifset BPF
+
+@emph{Target BPF options:}
+ [@b{-EL}] [@b{-EB}]
+@end ifset
@ifset CRIS
@emph{Target CRIS options:}
@c Deprecated -- deliberately not documented.
@c [@b{-h}] [@b{-H}]
@end ifset
+@ifset CSKY
+
+@emph{Target C-SKY options:}
+ [@b{-march=@var{arch}}] [@b{-mcpu=@var{cpu}}]
+ [@b{-EL}] [@b{-mlittle-endian}] [@b{-EB}] [@b{-mbig-endian}]
+ [@b{-fpic}] [@b{-pic}]
+ [@b{-mljump}] [@b{-mno-ljump}]
+ [@b{-force2bsr}] [@b{-mforce2bsr}] [@b{-no-force2bsr}] [@b{-mno-force2bsr}]
+ [@b{-jsri2bsr}] [@b{-mjsri2bsr}] [@b{-no-jsri2bsr }] [@b{-mno-jsri2bsr}]
+ [@b{-mnolrw }] [@b{-mno-lrw}]
+ [@b{-melrw}] [@b{-mno-elrw}]
+ [@b{-mlaf }] [@b{-mliterals-after-func}]
+ [@b{-mno-laf}] [@b{-mno-literals-after-func}]
+ [@b{-mlabr}] [@b{-mliterals-after-br}]
+ [@b{-mno-labr}] [@b{-mnoliterals-after-br}]
+ [@b{-mistack}] [@b{-mno-istack}]
+ [@b{-mhard-float}] [@b{-mmp}] [@b{-mcp}] [@b{-mcache}]
+ [@b{-msecurity}] [@b{-mtrust}]
+ [@b{-mdsp}] [@b{-medsp}] [@b{-mvdsp}]
+@end ifset
@ifset D10V
@emph{Target D10V options:}
[@b{-mcrc}] [@b{-mno-crc}]
[@b{-mginv}] [@b{-mno-ginv}]
[@b{-mloongson-mmi}] [@b{-mno-loongson-mmi}]
+ [@b{-mloongson-cam}] [@b{-mno-loongson-cam}]
+ [@b{-mloongson-ext}] [@b{-mno-loongson-ext}]
+ [@b{-mloongson-ext2}] [@b{-mno-loongson-ext2}]
[@b{-minsn32}] [@b{-mno-insn32}]
[@b{-mfix7000}] [@b{-mno-fix7000}]
[@b{-mfix-rm7000}] [@b{-mno-fix-rm7000}]
[@b{-mfix-vr4120}] [@b{-mno-fix-vr4120}]
[@b{-mfix-vr4130}] [@b{-mno-fix-vr4130}]
+ [@b{-mfix-r5900}] [@b{-mno-fix-r5900}]
[@b{-mdebug}] [@b{-no-mdebug}]
[@b{-mpdr}] [@b{-mno-pdr}]
@end ifset
[@b{-mfull-regs}] [@b{-m[no-]dx-regs}] [@b{-mpic}] [@b{-mno-relax}]
[@b{-mb2bb}]
@end ifset
+@ifset OPENRISC
+@c OpenRISC has no machine-dependent assembler options.
+@end ifset
@ifset PDP11
@emph{Target PDP11 options:}
@emph{Target PowerPC options:}
[@b{-a32}|@b{-a64}]
[@b{-mpwrx}|@b{-mpwr2}|@b{-mpwr}|@b{-m601}|@b{-mppc}|@b{-mppc32}|@b{-m603}|@b{-m604}|@b{-m403}|@b{-m405}|
- @b{-m440}|@b{-m464}|@b{-m476}|@b{-m7400}|@b{-m7410}|@b{-m7450}|@b{-m7455}|@b{-m750cl}|@b{-mppc64}|
- @b{-m620}|@b{-me500}|@b{-e500x2}|@b{-me500mc}|@b{-me500mc64}|@b{-me5500}|@b{-me6500}|@b{-mppc64bridge}|
- @b{-mbooke}|@b{-mpower4}|@b{-mpwr4}|@b{-mpower5}|@b{-mpwr5}|@b{-mpwr5x}|@b{-mpower6}|@b{-mpwr6}|
- @b{-mpower7}|@b{-mpwr7}|@b{-mpower8}|@b{-mpwr8}|@b{-mpower9}|@b{-mpwr9}@b{-ma2}|
+ @b{-m440}|@b{-m464}|@b{-m476}|@b{-m7400}|@b{-m7410}|@b{-m7450}|@b{-m7455}|@b{-m750cl}|@b{-mgekko}|
+ @b{-mbroadway}|@b{-mppc64}|@b{-m620}|@b{-me500}|@b{-e500x2}|@b{-me500mc}|@b{-me500mc64}|@b{-me5500}|
+ @b{-me6500}|@b{-mppc64bridge}|@b{-mbooke}|@b{-mpower4}|@b{-mpwr4}|@b{-mpower5}|@b{-mpwr5}|@b{-mpwr5x}|
+ @b{-mpower6}|@b{-mpwr6}|@b{-mpower7}|@b{-mpwr7}|@b{-mpower8}|@b{-mpwr8}|@b{-mpower9}|@b{-mpwr9}@b{-ma2}|
@b{-mcell}|@b{-mspe}|@b{-mspe2}|@b{-mtitan}|@b{-me300}|@b{-mcom}]
[@b{-many}] [@b{-maltivec}|@b{-mvsx}|@b{-mhtm}|@b{-mvle}]
[@b{-mregnames}|@b{-mno-regnames}]
@ifset Z80
@emph{Target Z80 options:}
- [@b{-z80}] [@b{-r800}]
+ [@b{-z80}]|[@b{-z180}]|[@b{-r800}]|[@b{-ez80}]|[@b{-ez80-adl}]
+ [@b{-strict}]|[@b{-full}]
+ [@b{-with-inst=@var{INST}[,...]}] [@b{-Wnins @var{INST}[,...]}]
+ [@b{-without-inst=@var{INST}[,...]}] [@b{-Fins @var{INST}[,...]}]
[@b{ -ignore-undocumented-instructions}] [@b{-Wnud}]
[@b{ -ignore-unportable-instructions}] [@b{-Wnup}]
[@b{ -warn-undocumented-instructions}] [@b{-Wud}]
then debug line section will still be called just @var{.debug_line} without any
suffix.
+@item --gdwarf-cie-version=@var{version}
+Control which version of DWARF Common Information Entries (CIEs) are produced.
+When this flag is not specificed the default is version 1, though some targets
+can modify this default. Other possible values for @var{version} are 3 or 4.
+
@ifset ELF
@item --size-check=error
@itemx --size-check=warning
@end ifset
+@ifset BPF
+
+@ifclear man
+@xref{BPF Options}, for the options available when @value{AS} is
+configured for the Linux kernel BPF processor family.
+@end ifclear
+
+@ifset man
+@c man begin OPTIONS
+The following options are available when @value{AS} is configured for
+the Linux kernel BPF processor family.
+@c man end
+@c man begin INCLUDE
+@include c-bpf.texi
+@c ended inside the included file
+@end ifset
+
+@end ifset
+
@c man begin OPTIONS
@ifset CRIS
See the info pages for documentation of the CRIS-specific options.
@end ifset
+@ifset CSKY
+
+@ifclear man
+@xref{C-SKY Options}, for the options available when @value{AS} is
+configured for the C-SKY processor family.
+@end ifclear
+
+@ifset man
+@c man begin OPTIONS
+The following options are available when @value{AS} is configured for
+the C-SKY processor family.
+@c man end
+@c man begin INCLUDE
+@include c-csky.texi
+@c ended inside the included file
+@end ifset
+
+@end ifset
+
@ifset D10V
The following options are available when @value{AS} is configured for
a D10V processor.
Cause nops to be inserted if a dmult or dmultu instruction is
followed by a load instruction.
+@item -mfix-r5900
+@itemx -mno-fix-r5900
+Do not attempt to schedule the preceding instruction into the delay slot
+of a branch instruction placed at the end of a short loop of six
+instructions or fewer and always schedule a @code{nop} instruction there
+instead. The short loop bug under certain conditions causes loops to
+execute only once or twice, due to a hardware bug in the R5900 chip.
+
@item -mdebug
@itemx -no-mdebug
Cause stabs-style debugging output to go into an ECOFF-style .mdebug
instructions.
@samp{-mno-loongson-mmi} turns off this option.
+@item -mloongson-cam
+@itemx -mno-loongson-cam
+Generate code for the Loongson Content Address Memory (CAM) instructions.
+This tells the assembler to accept Loongson CAM instructions.
+@samp{-mno-loongson-cam} turns off this option.
+
+@item -mloongson-ext
+@itemx -mno-loongson-ext
+Generate code for the Loongson EXTensions (EXT) instructions.
+This tells the assembler to accept Loongson EXT instructions.
+@samp{-mno-loongson-ext} turns off this option.
+
+@item -mloongson-ext2
+@itemx -mno-loongson-ext2
+Generate code for the Loongson EXTensions R2 (EXT2) instructions.
+This option implies @samp{-mloongson-ext}.
+This tells the assembler to accept Loongson EXT2 instructions.
+@samp{-mno-loongson-ext2} turns off this option.
+
@item -minsn32
@itemx -mno-insn32
Only use 32-bit instruction encodings when generating code for the
@samp{arch3}), @samp{g6}, @samp{z900} (or @samp{arch5}), @samp{z990} (or
@samp{arch6}), @samp{z9-109}, @samp{z9-ec} (or @samp{arch7}), @samp{z10} (or
@samp{arch8}), @samp{z196} (or @samp{arch9}), @samp{zEC12} (or @samp{arch10}),
-@samp{z13} (or @samp{arch11}), or @samp{z14} (or @samp{arch12}).
+@samp{z13} (or @samp{arch11}), @samp{z14} (or @samp{arch12}), or @samp{z15}
+(or @samp{arch13}).
@item -mregnames
@itemx -mno-regnames
Allow or disallow symbolic names for registers.
The following options are available when @value{AS} is configured for
a Z80 family processor.
@table @gcctabopt
+
@item -z80
Assemble for Z80 processor.
@item -r800
Assemble for R800 processor.
+@item -z180
+Assemble for Z180 processor.
+@item -ez80
+Assemble for eZ80 processor in Z80 memory mode by default.
+@item -ez80-adl
+Assemble for eZ80 processor in ADL memory mode by default.
+
+@item @code{-colonless}
+Accept colonless labels. All names at line begin are treated as labels.
+@item @code{-sdcc}
+Accept assembler code produces by SDCC.
+
+@item @code{-strict}
+Accept documented instructions only.
+@item @code{-full}
+Accept all known Z80 instructions.
+@item @code{-with-inst=INST[,...]}
+@itemx @code{-Wnins INST[,...]}
+Enable specified undocumented instruction(s).
+@item @code{-without-inst=INST[,...]}
+@itemx @code{-Fins INST[,...]}
+Disable specified undocumented instruction(s).
+
@item -ignore-undocumented-instructions
@itemx -Wnud
Assemble undocumented Z80 instructions that also work on R800 without warning.
@itemx -Fup
Treat undocumented Z80 instructions that do not work on R800 as errors.
@end table
+
+Folowing undocumented instructions may be enabled/disabled by
+@code{-with-inst}/@code{-without-inst}:
+@table @gcctabopt
+@item @code{idx-reg-halves}
+All operations with halves of index registers (IXL, IXH, IYL, IYH).
+@item @code{sli}
+SLI or SLL instruction.
+@item @code{op-ii-ld}
+Istructions like @code{<op> (<ii>+<d>),<r>}, where @code{<op>}
+is shift or bit manipulation instruction (RLC, SLA, SET, RES...).
+@item @code{in-f-c}
+Instruction @code{IN F,(C)}.
+@item @code{out-c-0}
+Instruction @code{OUT (C),0}
+@end table
@end ifset
@c man end
* ABORT (COFF):: @code{.ABORT}
@end ifset
-* Align:: @code{.align @var{abs-expr} , @var{abs-expr}}
+* Align:: @code{.align [@var{abs-expr}[, @var{abs-expr}[, @var{abs-expr}]]]}
* Altmacro:: @code{.altmacro}
* Ascii:: @code{.ascii "@var{string}"}@dots{}
* Asciz:: @code{.asciz "@var{string}"}@dots{}
-* Balign:: @code{.balign @var{abs-expr} , @var{abs-expr}}
+* Balign:: @code{.balign [@var{abs-expr}[, @var{abs-expr}]]}
* Bundle directives:: @code{.bundle_align_mode @var{abs-expr}}, etc
* Byte:: @code{.byte @var{expressions}}
* CFI directives:: @code{.cfi_startproc [simple]}, @code{.cfi_endproc}, etc.
* Octa:: @code{.octa @var{bignums}}
* Offset:: @code{.offset @var{loc}}
* Org:: @code{.org @var{new-lc}, @var{fill}}
-* P2align:: @code{.p2align @var{abs-expr}, @var{abs-expr}, @var{abs-expr}}
+* P2align:: @code{.p2align [@var{abs-expr}[, @var{abs-expr}[, @var{abs-expr}]]]}
@ifset ELF
* PopSection:: @code{.popsection}
* Previous:: @code{.previous}
@end ifset
@node Align
-@section @code{.align @var{abs-expr}, @var{abs-expr}, @var{abs-expr}}
+@section @code{.align [@var{abs-expr}[, @var{abs-expr}[, @var{abs-expr}]]]}
@cindex padding the location counter
@cindex @code{align} directive
Pad the location counter (in the current subsection) to a particular storage
boundary. The first expression (which must be absolute) is the alignment
-required, as described below.
+required, as described below. If this expression is omitted then a default
+value of 0 is used, effectively disabling alignment requirements.
The second expression (also absolute) gives the fill value to be stored in the
padding bytes. It (and the comma) may be omitted. If it is omitted, the
The way the required alignment is specified varies from system to system.
For the arc, hppa, i386 using ELF, iq2000, m68k, or1k,
-s390, sparc, tic4x, tic80 and xtensa, the first expression is the
+s390, sparc, tic4x and xtensa, the first expression is the
alignment request in bytes. For example @samp{.align 8} advances
the location counter until it is a multiple of 8. If the location counter
is already a multiple of 8, no change is needed. For the tic54x, the
strongarm, it is the
number of low-order zero bits the location counter must have after
advancement. For example @samp{.align 3} advances the location
-counter until it a multiple of 8. If the location counter is already a
+counter until it is a multiple of 8. If the location counter is already a
multiple of 8, no change is needed.
This inconsistency is due to the different behaviors of the various
a zero byte. The ``z'' in @samp{.asciz} stands for ``zero''.
@node Balign
-@section @code{.balign[wl] @var{abs-expr}, @var{abs-expr}, @var{abs-expr}}
+@section @code{.balign[wl] [@var{abs-expr}[, @var{abs-expr}[, @var{abs-expr}]]]}
@cindex padding the location counter given number of bytes
@cindex @code{balign} directive
storage boundary. The first expression (which must be absolute) is the
alignment request in bytes. For example @samp{.balign 8} advances
the location counter until it is a multiple of 8. If the location counter
-is already a multiple of 8, no change is needed.
+is already a multiple of 8, no change is needed. If the expression is omitted
+then a default value of 0 is used, effectively disabling alignment requirements.
The second expression (also absolute) gives the fill value to be stored in the
padding bytes. It (and the comma) may be omitted. If it is omitted, the
@var{fill} defaults to zero.
@node P2align
-@section @code{.p2align[wl] @var{abs-expr}, @var{abs-expr}, @var{abs-expr}}
+@section @code{.p2align[wl] [@var{abs-expr}[, @var{abs-expr}[, @var{abs-expr}]]]}
@cindex padding the location counter given a power of two
@cindex @code{p2align} directive
storage boundary. The first expression (which must be absolute) is the
number of low-order zero bits the location counter must have after
advancement. For example @samp{.p2align 3} advances the location
-counter until it a multiple of 8. If the location counter is already a
-multiple of 8, no change is needed.
+counter until it is a multiple of 8. If the location counter is already a
+multiple of 8, no change is needed. If the expression is omitted then a
+default value of 0 is used, effectively disabling alignment requirements.
The second expression (also absolute) gives the fill value to be stored in the
padding bytes. It (and the comma) may be omitted. If it is omitted, the
file is the last value stored into it.
@ifset Z80
-On Z80 @code{set} is a real instruction, use
+On Z80 @code{set} is a real instruction, use @code{.set} or
@samp{@var{symbol} defl @var{expression}} instead.
@end ifset
@end table
+Changing between incompatible types other than from/to STT_NOTYPE will
+result in a diagnostic. An intermediate change to STT_NOTYPE will silence
+this.
+
Note: Some targets support extra types in addition to those listed above.
@end ifset
@cindex filling memory with zero bytes
This directive emits @var{size} 0-valued bytes. @var{size} must be an absolute
expression. This directive is actually an alias for the @samp{.skip} directive
-so in can take an optional second argument of the value to store in the bytes
+so it can take an optional second argument of the value to store in the bytes
instead of zero. Using @samp{.zero} in this way would be confusing however.
@end ifclear
@end itemize
@end table
+@subsection MSP430 Attributes
+
+@table @r
+@item Tag_GNU_MSP430_Data_Region (4)
+The data region used by this object file. The value will be:
+
+@itemize @bullet
+@item
+0 for files not using the large memory model.
+@item
+1 for files which have been compiled with the condition that all
+data is in the lower memory region, i.e. below address 0x10000.
+@item
+2 for files which allow data to be placed in the full 20-bit memory range.
+@end itemize
+@end table
+
@node Defining New Object Attributes
@section Defining New Object Attributes
@ifset Blackfin
* Blackfin-Dependent:: Blackfin Dependent Features
@end ifset
+@ifset BPF
+* BPF-Dependent:: BPF Dependent Features
+@end ifset
@ifset CR16
* CR16-Dependent:: CR16 Dependent Features
@end ifset
@ifset CRIS
* CRIS-Dependent:: CRIS Dependent Features
@end ifset
+@ifset CSKY
+* C-SKY-Dependent:: C-SKY Dependent Features
+@end ifset
@ifset D10V
* D10V-Dependent:: D10V Dependent Features
@end ifset
* M68HC11-Dependent:: M68HC11 and 68HC12 Dependent Features
@end ifset
@ifset S12Z
-* S12Z-Dependent:: S12Z Dependent Features
+* S12Z-Dependent:: S12Z Dependent Features
@end ifset
@ifset METAG
* Meta-Dependent :: Meta Dependent Features
@ifset NS32K
* NS32K-Dependent:: NS32K Dependent Features
@end ifset
+@ifset OPENRISC
+* OpenRISC-Dependent:: OpenRISC 1000 Features
+@end ifset
@ifset PDP11
* PDP-11-Dependent:: PDP-11 Dependent Features
@end ifset
@include c-bfin.texi
@end ifset
+@ifset BPF
+@include c-bpf.texi
+@end ifset
+
@ifset CR16
@include c-cr16.texi
@end ifset
@include c-cris.texi
@end ifset
+@ifset CSKY
+@include c-csky.texi
+@end ifset
+
@ifset Renesas-all
@ifclear GENERIC
@node Machine Dependencies
@include c-ns32k.texi
@end ifset
+@ifset OPENRISC
+@include c-or1k.texi
+@end ifset
+
@ifset PDP11
@include c-pdp11.texi
@end ifset
projects / deliverable / binutils-gdb.git / blobdiff