-@c Copyright 2009, 2011
-@c Free Software Foundation, Inc.
+@c Copyright (C) 2009-2020 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@cindex s390 support
The s390 version of @code{@value{AS}} supports two architectures modes
-and seven chip levels. The architecture modes are the Enterprise System
+and eleven chip levels. The architecture modes are the Enterprise System
Architecture (ESA) and the newer z/Architecture mode. The chip levels
-are g5, g6, z900, z990, z9-109, z9-ec, z10, z196, and zEC12.
+are g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec
+(or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13
+(or arch11), z14 (or arch12), and z15 (or arch13).
@menu
* s390 Options:: Command-line Options.
@item -march=@var{CPU}
This option specifies the target processor. The following processor names
are recognized:
-@code{g5},
+@code{g5} (or @code{arch3}),
@code{g6},
-@code{z900},
-@code{z990},
+@code{z900} (or @code{arch5}),
+@code{z990} (or @code{arch6}),
@code{z9-109},
-@code{z9-ec},
-@code{z10} and
-@code{z196}.
-Assembling an instruction that is not supported on the target processor
-results in an error message. Do not specify @code{g5} or @code{g6}
-with @samp{-mzarch}.
+@code{z9-ec} (or @code{arch7}),
+@code{z10} (or @code{arch8}),
+@code{z196} (or @code{arch9}),
+@code{zEC12} (or @code{arch10}),
+@code{z13} (or @code{arch11}),
+@code{z14} (or @code{arch12}), and
+@code{z15} (or @code{arch13}).
+
+Assembling an instruction that is not supported on the target
+processor results in an error message.
+
+The processor names starting with @code{arch} refer to the edition
+number in the Principle of Operations manual. They can be used as
+alternate processor names and have been added for compatibility with
+the IBM XL compiler.
+
+@code{arch3}, @code{g5} and @code{g6} cannot be used with the
+@samp{-mzarch} option since the z/Architecture mode is not supported
+on these processor levels.
+
+There is no @code{arch4} option supported. @code{arch4} matches
+@code{-march=arch5 -mesa}.
@cindex @samp{-mregnames} option, s390
@item -mregnames
@end display
There are many exceptions to the scheme outlined in the above lists, in
-particular for the priviledged instructions. For non-priviledged
+particular for the privileged instructions. For non-privileged
instruction it works quite well, for example the instruction @samp{clgfr}
c: compare instruction, l: unsigned operands, g: 64-bit operands,
f: 32- to 64-bit extension, r: register operands. The instruction compares
base register and the displacement field Dn.
@item Dn(Ln,Bn)
the address for operand number n is formed from the content of general
-regiser Bn called the base register and the displacement field Dn.
+register Bn called the base register and the displacement field Dn.
The length of the operand n is specified by the field Ln.
@end table
dumped to the current location (@ref{s390 Literal Pool Entries}).
@cindex @code{.machine} directive, s390
-@item .machine string
-This directive allows you to change the machine for which code is
-generated. @code{string} may be any of the @code{-march=} selection
-options (without the -march=), @code{push}, or @code{pop}.
-@code{.machine push} saves the currently selected cpu, which may be
-restored with @code{.machine pop}. Be aware that the cpu string has
-to be put into double quotes in case it contains characters not
-appropriate for identifiers. So you have to write @code{"z9-109"}
-instead of just @code{z9-109}.
+@item .machine @var{STRING}[+@var{EXTENSION}]@dots{}
+
+This directive allows changing the machine for which code is
+generated. @code{string} may be any of the @code{-march=}
+selection options, or @code{push}, or @code{pop}. @code{.machine
+push} saves the currently selected cpu, which may be restored with
+@code{.machine pop}. Be aware that the cpu string has to be put
+into double quotes in case it contains characters not appropriate
+for identifiers. So you have to write @code{"z9-109"} instead of
+just @code{z9-109}. Extensions can be specified after the cpu
+name, separated by plus characters. Valid extensions are:
+@code{htm},
+@code{nohtm},
+@code{vx},
+@code{novx}.
+They extend the basic instruction set with features from a higher
+cpu level, or remove support for a feature from the given cpu
+level.
+
+Example: @code{z13+nohtm} allows all instructions of the z13 cpu
+except instructions from the HTM facility.
@cindex @code{.machinemode} directive, s390
@item .machinemode string
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