/* Native-dependent code for GNU/Linux AArch64.
- Copyright (C) 2011-2018 Free Software Foundation, Inc.
+ Copyright (C) 2011-2020 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GDB.
#include "aarch64-tdep.h"
#include "aarch64-linux-tdep.h"
#include "aarch32-linux-nat.h"
+#include "aarch32-tdep.h"
+#include "arch/arm.h"
#include "nat/aarch64-linux.h"
#include "nat/aarch64-linux-hw-point.h"
+#include "nat/aarch64-sve-linux-ptrace.h"
#include "elf/external.h"
#include "elf/common.h"
#include <asm/ptrace.h>
#include "gregset.h"
+#include "linux-tdep.h"
/* Defines ps_err_e, struct ps_prochandle. */
#include "gdb_proc_service.h"
+#include "arch-utils.h"
#ifndef TRAP_HWBKPT
#define TRAP_HWBKPT 0x0004
/* Override the GNU/Linux inferior startup hook. */
void post_startup_inferior (ptid_t) override;
+ /* Override the GNU/Linux post attach hook. */
+ void post_attach (int pid) override;
+
/* These three defer to common nat/ code. */
void low_new_thread (struct lwp_info *lp) override
{ aarch64_linux_new_thread (lp); }
/* Add our siginfo layout converter. */
bool low_siginfo_fixup (siginfo_t *ptrace, gdb_byte *inf, int direction)
override;
+
+ struct gdbarch *thread_architecture (ptid_t) override;
};
static aarch64_linux_nat_target the_aarch64_linux_nat_target;
and arm. */
gdb_static_assert (sizeof (regs) >= 18 * 4);
- tid = ptid_get_lwp (regcache->ptid ());
+ tid = regcache->ptid ().lwp ();
iovec.iov_base = ®s;
if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
/* Make sure REGS can hold all registers contents on both aarch64
and arm. */
gdb_static_assert (sizeof (regs) >= 18 * 4);
- tid = ptid_get_lwp (regcache->ptid ());
+ tid = regcache->ptid ().lwp ();
iovec.iov_base = ®s;
if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
/* Make sure REGS can hold all VFP registers contents on both aarch64
and arm. */
- gdb_static_assert (sizeof regs >= VFP_REGS_SIZE);
+ gdb_static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE);
- tid = ptid_get_lwp (regcache->ptid ());
+ tid = regcache->ptid ().lwp ();
iovec.iov_base = ®s;
if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
{
- iovec.iov_len = VFP_REGS_SIZE;
+ iovec.iov_len = ARM_VFP3_REGS_SIZE;
ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
if (ret < 0)
/* Make sure REGS can hold all VFP registers contents on both aarch64
and arm. */
- gdb_static_assert (sizeof regs >= VFP_REGS_SIZE);
- tid = ptid_get_lwp (regcache->ptid ());
+ gdb_static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE);
+ tid = regcache->ptid ().lwp ();
iovec.iov_base = ®s;
if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
{
- iovec.iov_len = VFP_REGS_SIZE;
+ iovec.iov_len = ARM_VFP3_REGS_SIZE;
ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
if (ret < 0)
}
}
+/* Fill GDB's register array with the sve register values
+ from the current thread. */
+
+static void
+fetch_sveregs_from_thread (struct regcache *regcache)
+{
+ std::unique_ptr<gdb_byte[]> base
+ = aarch64_sve_get_sveregs (regcache->ptid ().lwp ());
+ aarch64_sve_regs_copy_to_reg_buf (regcache, base.get ());
+}
+
+/* Store to the current thread the valid sve register
+ values in the GDB's register array. */
+
+static void
+store_sveregs_to_thread (struct regcache *regcache)
+{
+ int ret;
+ struct iovec iovec;
+ int tid = regcache->ptid ().lwp ();
+
+ /* First store vector length to the thread. This is done first to ensure the
+ ptrace buffers read from the kernel are the correct size. */
+ if (!aarch64_sve_set_vq (tid, regcache))
+ perror_with_name (_("Unable to set VG register."));
+
+ /* Obtain a dump of SVE registers from ptrace. */
+ std::unique_ptr<gdb_byte[]> base = aarch64_sve_get_sveregs (tid);
+
+ /* Overwrite with regcache state. */
+ aarch64_sve_regs_copy_from_reg_buf (regcache, base.get ());
+
+ /* Write back to the kernel. */
+ iovec.iov_base = base.get ();
+ iovec.iov_len = ((struct user_sve_header *) base.get ())->size;
+ ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_SVE, &iovec);
+
+ if (ret < 0)
+ perror_with_name (_("Unable to store sve registers"));
+}
+
+/* Fill GDB's register array with the pointer authentication mask values from
+ the current thread. */
+
+static void
+fetch_pauth_masks_from_thread (struct regcache *regcache)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ());
+ int ret;
+ struct iovec iovec;
+ uint64_t pauth_regset[2] = {0, 0};
+ int tid = regcache->ptid ().lwp ();
+
+ iovec.iov_base = &pauth_regset;
+ iovec.iov_len = sizeof (pauth_regset);
+
+ ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_PAC_MASK, &iovec);
+ if (ret != 0)
+ perror_with_name (_("unable to fetch pauth registers."));
+
+ regcache->raw_supply (AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base),
+ &pauth_regset[0]);
+ regcache->raw_supply (AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base),
+ &pauth_regset[1]);
+}
+
/* Implement the "fetch_registers" target_ops method. */
void
aarch64_linux_nat_target::fetch_registers (struct regcache *regcache,
int regno)
{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ());
+
if (regno == -1)
{
fetch_gregs_from_thread (regcache);
- fetch_fpregs_from_thread (regcache);
+ if (tdep->has_sve ())
+ fetch_sveregs_from_thread (regcache);
+ else
+ fetch_fpregs_from_thread (regcache);
+
+ if (tdep->has_pauth ())
+ fetch_pauth_masks_from_thread (regcache);
}
else if (regno < AARCH64_V0_REGNUM)
fetch_gregs_from_thread (regcache);
+ else if (tdep->has_sve ())
+ fetch_sveregs_from_thread (regcache);
else
fetch_fpregs_from_thread (regcache);
+
+ if (tdep->has_pauth ())
+ {
+ if (regno == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base)
+ || regno == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base))
+ fetch_pauth_masks_from_thread (regcache);
+ }
}
/* Implement the "store_registers" target_ops method. */
aarch64_linux_nat_target::store_registers (struct regcache *regcache,
int regno)
{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ());
+
if (regno == -1)
{
store_gregs_to_thread (regcache);
- store_fpregs_to_thread (regcache);
+ if (tdep->has_sve ())
+ store_sveregs_to_thread (regcache);
+ else
+ store_fpregs_to_thread (regcache);
}
else if (regno < AARCH64_V0_REGNUM)
store_gregs_to_thread (regcache);
+ else if (tdep->has_sve ())
+ store_sveregs_to_thread (regcache);
else
store_fpregs_to_thread (regcache);
}
new process so that all breakpoints and watchpoints can be
removed together. */
- parent_pid = ptid_get_pid (parent->ptid);
+ parent_pid = parent->ptid.pid ();
parent_state = aarch64_get_debug_reg_state (parent_pid);
child_state = aarch64_get_debug_reg_state (child_pid);
*child_state = *parent_state;
void
aarch64_linux_nat_target::post_startup_inferior (ptid_t ptid)
{
- low_forget_process (ptid_get_pid (ptid));
- aarch64_linux_get_debug_reg_capacity (ptid_get_pid (ptid));
+ low_forget_process (ptid.pid ());
+ aarch64_linux_get_debug_reg_capacity (ptid.pid ());
linux_nat_target::post_startup_inferior (ptid);
}
-extern struct target_desc *tdesc_arm_with_neon;
+/* Implement the "post_attach" target_ops method. */
+
+void
+aarch64_linux_nat_target::post_attach (int pid)
+{
+ low_forget_process (pid);
+ /* Set the hardware debug register capacity. If
+ aarch64_linux_get_debug_reg_capacity is not called
+ (as it is in aarch64_linux_child_post_startup_inferior) then
+ software watchpoints will be used instead of hardware
+ watchpoints when attaching to a target. */
+ aarch64_linux_get_debug_reg_capacity (pid);
+ linux_nat_target::post_attach (pid);
+}
/* Implement the "read_description" target_ops method. */
aarch64_linux_nat_target::read_description ()
{
int ret, tid;
- gdb_byte regbuf[VFP_REGS_SIZE];
+ gdb_byte regbuf[ARM_VFP3_REGS_SIZE];
struct iovec iovec;
- tid = ptid_get_lwp (inferior_ptid);
+ tid = inferior_ptid.lwp ();
iovec.iov_base = regbuf;
- iovec.iov_len = VFP_REGS_SIZE;
+ iovec.iov_len = ARM_VFP3_REGS_SIZE;
ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
if (ret == 0)
- return tdesc_arm_with_neon;
- else
- /* SVE not yet supported. */
- return aarch64_read_description (0);
+ return aarch32_read_description ();
+
+ CORE_ADDR hwcap = linux_get_hwcap (this);
+
+ return aarch64_read_description (aarch64_sve_get_vq (tid),
+ hwcap & AARCH64_HWCAP_PACA);
}
/* Convert a native/host siginfo object, into/from the siginfo in the
int len;
const enum target_hw_bp_type type = hw_execute;
struct aarch64_debug_reg_state *state
- = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
+ = aarch64_get_debug_reg_state (inferior_ptid.pid ());
gdbarch_breakpoint_from_pc (gdbarch, &addr, &len);
int len = 4;
const enum target_hw_bp_type type = hw_execute;
struct aarch64_debug_reg_state *state
- = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
+ = aarch64_get_debug_reg_state (inferior_ptid.pid ());
gdbarch_breakpoint_from_pc (gdbarch, &addr, &len);
{
int ret;
struct aarch64_debug_reg_state *state
- = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
+ = aarch64_get_debug_reg_state (inferior_ptid.pid ());
if (show_debug_regs)
fprintf_unfiltered (gdb_stdlog,
{
int ret;
struct aarch64_debug_reg_state *state
- = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
+ = aarch64_get_debug_reg_state (inferior_ptid.pid ());
if (show_debug_regs)
fprintf_unfiltered (gdb_stdlog,
aarch64_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p)
{
siginfo_t siginfo;
- int i, tid;
+ int i;
struct aarch64_debug_reg_state *state;
if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
return false;
/* Check if the address matches any watched address. */
- state = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid));
+ state = aarch64_get_debug_reg_state (inferior_ptid.pid ());
for (i = aarch64_num_wp_regs - 1; i >= 0; --i)
{
const unsigned int offset
return 1;
}
+/* Implement the "thread_architecture" target_ops method. */
+
+struct gdbarch *
+aarch64_linux_nat_target::thread_architecture (ptid_t ptid)
+{
+ /* Return the gdbarch for the current thread. If the vector length has
+ changed since the last time this was called, then do a further lookup. */
+
+ uint64_t vq = aarch64_sve_get_vq (ptid.lwp ());
+
+ /* Find the current gdbarch the same way as process_stratum_target. Only
+ return it if the current vector length matches the one in the tdep. */
+ inferior *inf = find_inferior_ptid (this, ptid);
+ gdb_assert (inf != NULL);
+ if (vq == gdbarch_tdep (inf->gdbarch)->vq)
+ return inf->gdbarch;
+
+ /* We reach here if the vector length for the thread is different from its
+ value at process start. Lookup gdbarch via info (potentially creating a
+ new one), stashing the vector length inside id. Use -1 for when SVE
+ unavailable, to distinguish from an unset value of 0. */
+ struct gdbarch_info info;
+ gdbarch_info_init (&info);
+ info.bfd_arch_info = bfd_lookup_arch (bfd_arch_aarch64, bfd_mach_aarch64);
+ info.id = (int *) (vq == 0 ? -1 : vq);
+ return gdbarch_find_by_info (info);
+}
+
/* Define AArch64 maintenance commands. */
static void
projects / deliverable / binutils-gdb.git / blobdiff