Make queue_and_load_dwo_tu receive a dwarf2_cu

[deliverable/binutils-gdb.git] / gdb / amd64-nat.c

diff --git a/gdb/amd64-nat.c b/gdb/amd64-nat.c
index c641e89d0082c00d90fb54c7867f753f93fd03e8..fb3f52234812a7c82c175c7ee7c8eb9fa93eb3f0 100644 (file)
--- a/gdb/amd64-nat.c
+++ b/gdb/amd64-nat.c
@@ -1,6 +1,6 @@
 /* Native-dependent code for AMD64.
 
-   Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc.
+   Copyright (C) 2003-2020 Free Software Foundation, Inc.
 
    This file is part of GDB.
 
@@ -21,22 +21,20 @@
 #include "gdbarch.h"
 #include "regcache.h"
 
-#include "gdb_assert.h"
-#include "gdb_string.h"
-
 #include "i386-tdep.h"
 #include "amd64-tdep.h"
+#include "amd64-nat.h"
 
 /* The following bits of code help with implementing debugging 32-bit
    code natively on AMD64.  The idea is to define two mappings between
    the register number as used by GDB and the register set used by the
    host to represent the general-purpose registers; one for 32-bit
    code and one for 64-bit code.  The mappings are specified by the
-   follwing variables and consist of an array of offsets within the
+   following variables and consist of an array of offsets within the
    register set indexed by register number, and the number of
    registers supported by the mapping.  We don't need mappings for the
    floating-point and SSE registers, since the difference between
-   64-bit and 32-bit variants are negligable.  The difference in the
+   64-bit and 32-bit variants are negligible.  The difference in the
    number of SSE registers is already handled by the target code.  */
 
 /* General-purpose register mapping for native 32-bit code.  */
@@ -51,35 +49,35 @@ int amd64_native_gregset64_num_regs = AMD64_NUM_GREGS;
    general-purpose register set.  */
 
 static int
-amd64_native_gregset_reg_offset (int regnum)
+amd64_native_gregset_reg_offset (struct gdbarch *gdbarch, int regnum)
 {
   int *reg_offset = amd64_native_gregset64_reg_offset;
   int num_regs = amd64_native_gregset64_num_regs;
 
   gdb_assert (regnum >= 0);
 
-  if (gdbarch_ptr_bit (current_gdbarch) == 32)
+  if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
     {
       reg_offset = amd64_native_gregset32_reg_offset;
       num_regs = amd64_native_gregset32_num_regs;
     }
 
-  if (num_regs > gdbarch_num_regs (current_gdbarch))
-    num_regs = gdbarch_num_regs (current_gdbarch);
+  if (num_regs > gdbarch_num_regs (gdbarch))
+    num_regs = gdbarch_num_regs (gdbarch);
 
-  if (regnum < num_regs && regnum < gdbarch_num_regs (current_gdbarch))
-    return reg_offset[regnum];
+  if (regnum >= num_regs)
+    return -1;
 
-  return -1;
+  return reg_offset[regnum];
 }
 
 /* Return whether the native general-purpose register set supplies
    register REGNUM.  */
 
 int
-amd64_native_gregset_supplies_p (int regnum)
+amd64_native_gregset_supplies_p (struct gdbarch *gdbarch, int regnum)
 {
-  return (amd64_native_gregset_reg_offset (regnum) != -1);
+  return (amd64_native_gregset_reg_offset (gdbarch, regnum) != -1);
 }
 
 
@@ -90,25 +88,25 @@ void
 amd64_supply_native_gregset (struct regcache *regcache,
                             const void *gregs, int regnum)
 {
-  const char *regs = gregs;
-  struct gdbarch *gdbarch = get_regcache_arch (regcache);
+  const char *regs = (const char *) gregs;
+  struct gdbarch *gdbarch = regcache->arch ();
   int num_regs = amd64_native_gregset64_num_regs;
   int i;
 
-  if (gdbarch_ptr_bit (gdbarch) == 32)
+  if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
     num_regs = amd64_native_gregset32_num_regs;
 
-  if (num_regs > gdbarch_num_regs (current_gdbarch))
-    num_regs = gdbarch_num_regs (current_gdbarch);
+  if (num_regs > gdbarch_num_regs (gdbarch))
+    num_regs = gdbarch_num_regs (gdbarch);
 
   for (i = 0; i < num_regs; i++)
     {
       if (regnum == -1 || regnum == i)
        {
-         int offset = amd64_native_gregset_reg_offset (i);
+         int offset = amd64_native_gregset_reg_offset (gdbarch, i);
 
          if (offset != -1)
-           regcache_raw_supply (regcache, i, regs + offset);
+           regcache->raw_supply (i, regs + offset);
        }
     }
 }
@@ -121,12 +119,12 @@ void
 amd64_collect_native_gregset (const struct regcache *regcache,
                              void *gregs, int regnum)
 {
-  char *regs = gregs;
-  struct gdbarch *gdbarch = get_regcache_arch (regcache);
+  char *regs = (char *) gregs;
+  struct gdbarch *gdbarch = regcache->arch ();
   int num_regs = amd64_native_gregset64_num_regs;
   int i;
 
-  if (gdbarch_ptr_bit (gdbarch) == 32)
+  if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
     {
       num_regs = amd64_native_gregset32_num_regs;
 
@@ -135,27 +133,27 @@ amd64_collect_native_gregset (const struct regcache *regcache,
       for (i = 0; i <= I386_EIP_REGNUM; i++)
        {
          if (regnum == -1 || regnum == i)
-           memset (regs + amd64_native_gregset_reg_offset (i), 0, 8);
+           memset (regs + amd64_native_gregset_reg_offset (gdbarch, i), 0, 8);
        }
       /* Ditto for %cs, %ss, %ds, %es, %fs, and %gs.  */
       for (i = I386_CS_REGNUM; i <= I386_GS_REGNUM; i++)
        {
          if (regnum == -1 || regnum == i)
-           memset (regs + amd64_native_gregset_reg_offset (i), 0, 8);
+           memset (regs + amd64_native_gregset_reg_offset (gdbarch, i), 0, 8);
        }
     }
 
-  if (num_regs > gdbarch_num_regs (current_gdbarch))
-    num_regs = gdbarch_num_regs (current_gdbarch);
+  if (num_regs > gdbarch_num_regs (gdbarch))
+    num_regs = gdbarch_num_regs (gdbarch);
 
   for (i = 0; i < num_regs; i++)
     {
       if (regnum == -1 || regnum == i)
        {
-         int offset = amd64_native_gregset_reg_offset (i);
+         int offset = amd64_native_gregset_reg_offset (gdbarch, i);
 
          if (offset != -1)
-           regcache_raw_collect (regcache, i, regs + offset);
+           regcache->raw_collect (i, regs + offset);
        }
     }
 }