Fix -Wmisleading-indentation warning in top.c

[deliverable/binutils-gdb.git] / gdb / arc-tdep.h

diff --git a/gdb/arc-tdep.h b/gdb/arc-tdep.h
index ea34b9e8610c66fd9f421462061ab8dbb761478e..02f34dc1e6d0bbb21b260bdcb68f1c6b9d7b5945 100644 (file)
--- a/gdb/arc-tdep.h
+++ b/gdb/arc-tdep.h
@@ -1,6 +1,6 @@
-/* Target dependent code for ARC arhitecture, for GDB.
+/* Target dependent code for ARC architecture, for GDB.
 
-   Copyright 2005-2016 Free Software Foundation, Inc.
+   Copyright 2005-2019 Free Software Foundation, Inc.
    Contributed by Synopsys Inc.
 
    This file is part of GDB.
@@ -24,6 +24,12 @@
 /* Need disassemble_info.  */
 #include "dis-asm.h"
 
+/* To simplify GDB code this enum assumes that internal regnums should be same
+   as architectural register numbers, i.e. PCL regnum is 63.  This allows to
+   use internal GDB regnums as architectural numbers when dealing with
+   instruction encodings, for example when analyzing what are the registers
+   saved in function prologue.  */
+
 enum arc_regnum
   {
     /* Core registers.  */
@@ -49,6 +55,16 @@ enum arc_regnum
     ARC_BLINK_REGNUM,
     /* Zero-delay loop counter.  */
     ARC_LP_COUNT_REGNUM = 60,
+    /* Reserved register number.  There should never be a register with such
+       number, this name is needed only for a sanity check in
+      arc_cannot_(fetch|store)_register.  */
+    ARC_RESERVED_REGNUM,
+    /* Long-immediate value.  This is not a physical register - if instruction
+       has register 62 as an operand, then this operand is a literal value
+       stored in the instruction memory right after the instruction itself.
+       This value is required in this enumeration as an architectural number
+       for instruction analysis.  */
+    ARC_LIMM_REGNUM,
     /* Program counter, aligned to 4-bytes, read-only.  */
     ARC_PCL_REGNUM,
     ARC_LAST_CORE_REGNUM = ARC_PCL_REGNUM,
@@ -81,6 +97,9 @@ extern int arc_debug;
 
 struct gdbarch_tdep
 {
+  /* Offset to PC value in jump buffer.  If this is negative, longjmp
+     support will be disabled.  */
+  int jb_pc;
 };
 
 /* Utility functions used by other ARC-specific modules.  */
@@ -104,4 +123,44 @@ arc_mach_is_arcv2 (struct gdbarch *gdbarch)
   return gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_arc_arcv2;
 }
 
+/* ARC EM and ARC HS are unique BFD arches, however they share the same machine
+   number as "ARCv2".  */
+
+static inline bool
+arc_arch_is_hs (const struct bfd_arch_info* arch)
+{
+  return startswith (arch->printable_name, "HS");
+}
+
+static inline bool
+arc_arch_is_em (const struct bfd_arch_info* arch)
+{
+  return startswith (arch->printable_name, "EM");
+}
+
+/* Function to access ARC disassembler.  Underlying opcodes disassembler will
+   print an instruction into stream specified in the INFO, so if it is
+   undesired, then this stream should be set to some invisible stream, but it
+   can't be set to an actual NULL value - that would cause a crash.  */
+int arc_delayed_print_insn (bfd_vma addr, struct disassemble_info *info);
+
+/* Return properly initialized disassemble_info for ARC disassembler - it will
+   not print disassembled instructions to stderr.  */
+
+struct disassemble_info arc_disassemble_info (struct gdbarch *gdbarch);
+
+/* Get branch/jump target address for the INSN.  Note that this function
+   returns branch target and doesn't evaluate if this branch is taken or not.
+   For the indirect jumps value depends in register state, hence can change.
+   It is an error to call this function for a non-branch instruction.  */
+
+CORE_ADDR arc_insn_get_branch_target (const struct arc_instruction &insn);
+
+/* Get address of next instruction after INSN, assuming linear execution (no
+   taken branches).  If instruction has a delay slot, then returned value will
+   point at the instruction in delay slot.  That is - "address of instruction +
+   instruction length with LIMM".  */
+
+CORE_ADDR arc_insn_get_linear_next_pc (const struct arc_instruction &insn);
+
 #endif /* ARC_TDEP_H */