/* Common target dependent code for GDB on ARM systems.
- Copyright (C) 2002-2015 Free Software Foundation, Inc.
+ Copyright (C) 2002-2019 Free Software Foundation, Inc.
This file is part of GDB.
#define ARM_TDEP_H
/* Forward declarations. */
-struct gdbarch;
struct regset;
struct address_space;
+struct get_next_pcs;
+struct arm_get_next_pcs;
+struct gdb_get_next_pcs;
-#include "arch/arm.h"
+/* Set to true if the 32-bit mode is in use. */
-/* Size of integer registers. */
-#define INT_REGISTER_SIZE 4
+extern bool arm_apcs_32;
-/* Say how long FP registers are. Used for documentation purposes and
- code readability in this header. IEEE extended doubles are 80
- bits. DWORD aligned they use 96 bits. */
-#define FP_REGISTER_SIZE 12
+#include "gdbarch.h"
+#include "arch/arm.h"
+#include "infrun.h"
-/* Say how long VFP double precision registers are. Used for documentation
- purposes and code readability. These are fixed at 64 bits. */
-#define VFP_REGISTER_SIZE 8
+#include <vector>
/* Number of machine registers. The only define actually required
is gdbarch_num_regs. The other definitions are used for documentation
#define NUM_GREGS 16 /* Number of general purpose registers. */
-/* Instruction condition field values. */
-#define INST_EQ 0x0
-#define INST_NE 0x1
-#define INST_CS 0x2
-#define INST_CC 0x3
-#define INST_MI 0x4
-#define INST_PL 0x5
-#define INST_VS 0x6
-#define INST_VC 0x7
-#define INST_HI 0x8
-#define INST_LS 0x9
-#define INST_GE 0xa
-#define INST_LT 0xb
-#define INST_GT 0xc
-#define INST_LE 0xd
-#define INST_AL 0xe
-#define INST_NV 0xf
-
-#define FLAG_N 0x80000000
-#define FLAG_Z 0x40000000
-#define FLAG_C 0x20000000
-#define FLAG_V 0x10000000
-
-#define CPSR_T 0x20
-
-#define XPSR_T 0x01000000
/* Type of floating-point code in use by inferior. There are really 3 models
that are traditionally supported (plus the endianness issue), but gcc can
struct type *neon_double_type;
struct type *neon_quad_type;
- /* Return the expected next PC if FRAME is stopped at a syscall
- instruction. */
- CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
-
/* syscall record. */
int (*arm_syscall_record) (struct regcache *regcache, unsigned long svc_number);
};
/* The maximum number of modified instructions generated for one single-stepped
instruction, including the breakpoint (usually at the end of the instruction
sequence) and any scratch words, etc. */
-#define DISPLACED_MODIFIED_INSNS 8
+#define ARM_DISPLACED_MODIFIED_INSNS 8
-struct displaced_step_closure
+struct arm_displaced_step_closure : public displaced_step_closure
{
ULONGEST tmp[DISPLACED_TEMPS];
int rd;
/* If non-NULL, override generic SVC handling (e.g. for a particular
OS). */
int (*copy_svc_os) (struct gdbarch *gdbarch, struct regcache *regs,
- struct displaced_step_closure *dsc);
+ arm_displaced_step_closure *dsc);
} svc;
} u;
- ARM instruction occupies one slot,
- Thumb 16 bit instruction occupies one slot,
- Thumb 32-bit instruction occupies *two* slots, one part for each. */
- unsigned long modinsn[DISPLACED_MODIFIED_INSNS];
+ unsigned long modinsn[ARM_DISPLACED_MODIFIED_INSNS];
int numinsns;
CORE_ADDR insn_addr;
CORE_ADDR scratch_base;
void (*cleanup) (struct gdbarch *, struct regcache *,
- struct displaced_step_closure *);
+ arm_displaced_step_closure *);
};
/* Values for the WRITE_PC argument to displaced_write_reg. If the register
extern void
arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
CORE_ADDR to, struct regcache *regs,
- struct displaced_step_closure *dsc);
+ arm_displaced_step_closure *dsc);
extern void
arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
- CORE_ADDR to, struct displaced_step_closure *dsc);
+ CORE_ADDR to, arm_displaced_step_closure *dsc);
extern ULONGEST
- displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc,
+ displaced_read_reg (struct regcache *regs, arm_displaced_step_closure *dsc,
int regno);
extern void
displaced_write_reg (struct regcache *regs,
- struct displaced_step_closure *dsc, int regno,
+ arm_displaced_step_closure *dsc, int regno,
ULONGEST val, enum pc_write_style write_pc);
CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR);
-CORE_ADDR arm_get_next_pc (struct frame_info *, CORE_ADDR);
-void arm_insert_single_step_breakpoint (struct gdbarch *,
- struct address_space *, CORE_ADDR);
-int arm_deal_with_atomic_sequence (struct frame_info *);
-int arm_software_single_step (struct frame_info *);
+
+ULONGEST arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr,
+ int len,
+ int byte_order);
+
+CORE_ADDR arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self,
+ CORE_ADDR val);
+
+int arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self);
+
+std::vector<CORE_ADDR> arm_software_single_step (struct regcache *);
+int arm_is_thumb (struct regcache *regcache);
int arm_frame_is_thumb (struct frame_info *frame);
-extern struct displaced_step_closure *
- arm_displaced_step_copy_insn (struct gdbarch *, CORE_ADDR, CORE_ADDR,
- struct regcache *);
extern void arm_displaced_step_fixup (struct gdbarch *,
struct displaced_step_closure *,
CORE_ADDR, CORE_ADDR, struct regcache *);
extern int arm_process_record (struct gdbarch *gdbarch,
struct regcache *regcache, CORE_ADDR addr);
-/* Functions exported from armbsd-tdep.h. */
+/* Functions exported from arm-bsd-tdep.h. */
/* Return the appropriate register set for the core section identified
by SECT_NAME and SECT_SIZE. */
void *cb_data,
const struct regcache *regcache);
-/* Target descriptions. */
-extern struct target_desc *tdesc_arm_with_m;
-extern struct target_desc *tdesc_arm_with_iwmmxt;
-extern struct target_desc *tdesc_arm_with_vfpv2;
-extern struct target_desc *tdesc_arm_with_vfpv3;
-extern struct target_desc *tdesc_arm_with_neon;
+/* Get the correct Arm target description with given FP hardware type. */
+const target_desc *arm_read_description (arm_fp_type fp_type);
+
+/* Get the correct Arm M-Profile target description with given hardware
+ type. */
+const target_desc *arm_read_mprofile_description (arm_m_profile_type m_type);
#endif /* arm-tdep.h */
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