/* Functions specific to running gdb native on IA-64 running
GNU/Linux.
- Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
- 2009 Free Software Foundation, Inc.
+ Copyright (C) 1999-2020 Free Software Foundation, Inc.
This file is part of GDB.
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "defs.h"
-#include "gdb_string.h"
#include "inferior.h"
#include "target.h"
#include "gdbcore.h"
#include "linux-nat.h"
#include <signal.h>
-#include <sys/ptrace.h>
-#include "gdb_wait.h"
+#include "nat/gdb_ptrace.h"
+#include "gdbsupport/gdb_wait.h"
#ifdef HAVE_SYS_REG_H
#include <sys/reg.h>
#endif
#include <asm/ptrace_offsets.h>
#include <sys/procfs.h>
-/* Prototypes for supply_gregset etc. */
+/* Prototypes for supply_gregset etc. */
#include "gregset.h"
+#include "inf-ptrace.h"
+
+class ia64_linux_nat_target final : public linux_nat_target
+{
+public:
+ /* Add our register access methods. */
+ void fetch_registers (struct regcache *, int) override;
+ void store_registers (struct regcache *, int) override;
+
+ enum target_xfer_status xfer_partial (enum target_object object,
+ const char *annex,
+ gdb_byte *readbuf,
+ const gdb_byte *writebuf,
+ ULONGEST offset, ULONGEST len,
+ ULONGEST *xfered_len) override;
+
+ /* Override watchpoint routines. */
+
+ /* The IA-64 architecture can step over a watch point (without
+ triggering it again) if the "dd" (data debug fault disable) bit
+ in the processor status word is set.
+
+ This PSR bit is set in
+ ia64_linux_nat_target::stopped_by_watchpoint when the code there
+ has determined that a hardware watchpoint has indeed been hit.
+ The CPU will then be able to execute one instruction without
+ triggering a watchpoint. */
+ bool have_steppable_watchpoint () override { return true; }
+
+ int can_use_hw_breakpoint (enum bptype, int, int) override;
+ bool stopped_by_watchpoint () override;
+ bool stopped_data_address (CORE_ADDR *) override;
+ int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
+ struct expression *) override;
+ int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
+ struct expression *) override;
+ /* Override linux_nat_target low methods. */
+ void low_new_thread (struct lwp_info *lp) override;
+ bool low_status_is_event (int status) override;
+
+ void enable_watchpoints_in_psr (ptid_t ptid);
+};
+
+static ia64_linux_nat_target the_ia64_linux_nat_target;
+
/* These must match the order of the register names.
Some sort of lookup table is needed because the offsets associated
static int u_offsets[] =
{
/* general registers */
- -1, /* gr0 not available; i.e, it's always zero */
+ -1, /* gr0 not available; i.e, it's always zero. */
PT_R1,
PT_R2,
PT_R3,
PT_R29,
PT_R30,
PT_R31,
- /* gr32 through gr127 not directly available via the ptrace interface */
+ /* gr32 through gr127 not directly available via the ptrace interface. */
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
/* Floating point registers */
- -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0) */
+ -1, -1, /* f0 and f1 not available (f0 is +0.0 and f1 is +1.0). */
PT_F2,
PT_F3,
PT_F4,
PT_F125,
PT_F126,
PT_F127,
- /* predicate registers - we don't fetch these individually */
+ /* Predicate registers - we don't fetch these individually. */
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
PT_B5,
PT_B6,
PT_B7,
- /* virtual frame pointer and virtual return address pointer */
+ /* Virtual frame pointer and virtual return address pointer. */
-1, -1,
/* other registers */
PT_PR,
PT_CR_IIP, /* ip */
PT_CR_IPSR, /* psr */
PT_CFM, /* cfm */
- /* kernel registers not visible via ptrace interface (?) */
+ /* kernel registers not visible via ptrace interface (?) */
-1, -1, -1, -1, -1, -1, -1, -1,
/* hole */
-1, -1, -1, -1, -1, -1, -1, -1,
PT_AR_BSPSTORE,
PT_AR_RNAT,
-1,
- -1, /* Not available: FCR, IA32 floating control register */
+ -1, /* Not available: FCR, IA32 floating control register. */
-1, -1,
-1, /* Not available: EFLAG */
-1, /* Not available: CSD */
-1, -1, -1, -1, -1, -1, -1, -1, -1,
PT_AR_PFS,
PT_AR_LC,
- -1, /* Not available: EC, the Epilog Count register */
+ PT_AR_EC,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
-1,
/* nat bits - not fetched directly; instead we obtain these bits from
- either rnat or unat or from memory. */
+ either rnat or unat or from memory. */
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1, -1,
for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
{
- regcache_raw_supply (regcache, regi, regp + (regi - IA64_GR0_REGNUM));
+ regcache->raw_supply (regi, regp + (regi - IA64_GR0_REGNUM));
}
/* FIXME: NAT collection bits are at index 32; gotta deal with these
- somehow... */
+ somehow... */
- regcache_raw_supply (regcache, IA64_PR_REGNUM, regp + 33);
+ regcache->raw_supply (IA64_PR_REGNUM, regp + 33);
for (regi = IA64_BR0_REGNUM; regi <= IA64_BR7_REGNUM; regi++)
{
- regcache_raw_supply (regcache, regi,
- regp + 34 + (regi - IA64_BR0_REGNUM));
+ regcache->raw_supply (regi, regp + 34 + (regi - IA64_BR0_REGNUM));
}
- regcache_raw_supply (regcache, IA64_IP_REGNUM, regp + 42);
- regcache_raw_supply (regcache, IA64_CFM_REGNUM, regp + 43);
- regcache_raw_supply (regcache, IA64_PSR_REGNUM, regp + 44);
- regcache_raw_supply (regcache, IA64_RSC_REGNUM, regp + 45);
- regcache_raw_supply (regcache, IA64_BSP_REGNUM, regp + 46);
- regcache_raw_supply (regcache, IA64_BSPSTORE_REGNUM, regp + 47);
- regcache_raw_supply (regcache, IA64_RNAT_REGNUM, regp + 48);
- regcache_raw_supply (regcache, IA64_CCV_REGNUM, regp + 49);
- regcache_raw_supply (regcache, IA64_UNAT_REGNUM, regp + 50);
- regcache_raw_supply (regcache, IA64_FPSR_REGNUM, regp + 51);
- regcache_raw_supply (regcache, IA64_PFS_REGNUM, regp + 52);
- regcache_raw_supply (regcache, IA64_LC_REGNUM, regp + 53);
- regcache_raw_supply (regcache, IA64_EC_REGNUM, regp + 54);
+ regcache->raw_supply (IA64_IP_REGNUM, regp + 42);
+ regcache->raw_supply (IA64_CFM_REGNUM, regp + 43);
+ regcache->raw_supply (IA64_PSR_REGNUM, regp + 44);
+ regcache->raw_supply (IA64_RSC_REGNUM, regp + 45);
+ regcache->raw_supply (IA64_BSP_REGNUM, regp + 46);
+ regcache->raw_supply (IA64_BSPSTORE_REGNUM, regp + 47);
+ regcache->raw_supply (IA64_RNAT_REGNUM, regp + 48);
+ regcache->raw_supply (IA64_CCV_REGNUM, regp + 49);
+ regcache->raw_supply (IA64_UNAT_REGNUM, regp + 50);
+ regcache->raw_supply (IA64_FPSR_REGNUM, regp + 51);
+ regcache->raw_supply (IA64_PFS_REGNUM, regp + 52);
+ regcache->raw_supply (IA64_LC_REGNUM, regp + 53);
+ regcache->raw_supply (IA64_EC_REGNUM, regp + 54);
}
void
#define COPY_REG(_idx_,_regi_) \
if ((regno == -1) || regno == _regi_) \
- regcache_raw_collect (regcache, _regi_, regp + _idx_)
+ regcache->raw_collect (_regi_, regp + _idx_)
for (regi = IA64_GR0_REGNUM; regi <= IA64_GR31_REGNUM; regi++)
{
COPY_REG (regi - IA64_GR0_REGNUM, regi);
}
- /* FIXME: NAT collection bits at index 32? */
+ /* FIXME: NAT collection bits at index 32? */
COPY_REG (33, IA64_PR_REGNUM);
/* Given a pointer to a floating point register set in /proc format
(fpregset_t *), unpack the register contents and supply them as gdb's
- idea of the current floating point register values. */
+ idea of the current floating point register values. */
void
supply_fpregset (struct regcache *regcache, const fpregset_t *fpregsetp)
{
int regi;
const char *from;
+ const gdb_byte f_zero[16] = { 0 };
+ const gdb_byte f_one[16] =
+ { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 };
- for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
+ /* Kernel generated cores have fr1==0 instead of 1.0. Older GDBs
+ did the same. So ignore whatever might be recorded in fpregset_t
+ for fr0/fr1 and always supply their expected values. */
+
+ /* fr0 is always read as zero. */
+ regcache->raw_supply (IA64_FR0_REGNUM, f_zero);
+ /* fr1 is always read as one (1.0). */
+ regcache->raw_supply (IA64_FR1_REGNUM, f_one);
+
+ for (regi = IA64_FR2_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
{
from = (const char *) &((*fpregsetp)[regi - IA64_FR0_REGNUM]);
- regcache_raw_supply (regcache, regi, from);
+ regcache->raw_supply (regi, from);
}
}
/* Given a pointer to a floating point register set in /proc format
(fpregset_t *), update the register specified by REGNO from gdb's idea
of the current floating point register set. If REGNO is -1, update
- them all. */
+ them all. */
void
fill_fpregset (const struct regcache *regcache,
for (regi = IA64_FR0_REGNUM; regi <= IA64_FR127_REGNUM; regi++)
{
if ((regno == -1) || (regno == regi))
- regcache_raw_collect (regcache, regi,
- &((*fpregsetp)[regi - IA64_FR0_REGNUM]));
+ regcache->raw_collect (regi, &((*fpregsetp)[regi - IA64_FR0_REGNUM]));
}
}
#define IA64_PSR_DB (1UL << 24)
#define IA64_PSR_DD (1UL << 39)
-static void
-enable_watchpoints_in_psr (ptid_t ptid)
+void
+ia64_linux_nat_target::enable_watchpoints_in_psr (ptid_t ptid)
{
- struct regcache *regcache = get_thread_regcache (ptid);
+ struct regcache *regcache = get_thread_regcache (this, ptid);
ULONGEST psr;
regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
if (!(psr & IA64_PSR_DB))
{
psr |= IA64_PSR_DB; /* Set the db bit - this enables hardware
- watchpoints and breakpoints. */
+ watchpoints and breakpoints. */
regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
}
}
{
int tid;
- tid = TIDGET (ptid);
+ tid = ptid.lwp ();
if (tid == 0)
- tid = PIDGET (ptid);
+ tid = ptid.pid ();
(void) ptrace (PT_WRITE_U, tid, (PTRACE_TYPE_ARG3) (PT_DBR + 8 * idx), val);
}
static void
-store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr, long *dbr_mask)
+store_debug_register_pair (ptid_t ptid, int idx, long *dbr_addr,
+ long *dbr_mask)
{
if (dbr_addr)
store_debug_register (ptid, 2 * idx, *dbr_addr);
return onecount <= 1;
}
-static int
-ia64_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw)
+int
+ia64_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len,
+ enum target_hw_bp_type type,
+ struct expression *cond)
{
struct lwp_info *lp;
- ptid_t ptid;
int idx;
long dbr_addr, dbr_mask;
int max_watchpoints = 4;
dbr_mask = debug_registers[idx * 2 + 1];
if ((dbr_mask & (0x3UL << 62)) == 0)
{
- /* Exit loop if both r and w bits clear */
+ /* Exit loop if both r and w bits clear. */
break;
}
}
dbr_addr = (long) addr;
dbr_mask = (~(len - 1) & 0x00ffffffffffffffL); /* construct mask to match */
dbr_mask |= 0x0800000000000000L; /* Only match privilege level 3 */
- switch (rw)
+ switch (type)
{
case hw_write:
dbr_mask |= (1L << 62); /* Set w bit */
debug_registers[2 * idx] = dbr_addr;
debug_registers[2 * idx + 1] = dbr_mask;
- ALL_LWPS (lp, ptid)
+ ALL_LWPS (lp)
{
- store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
- enable_watchpoints_in_psr (ptid);
+ store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask);
+ enable_watchpoints_in_psr (lp->ptid);
}
return 0;
}
-static int
-ia64_linux_remove_watchpoint (CORE_ADDR addr, int len, int type)
+int
+ia64_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len,
+ enum target_hw_bp_type type,
+ struct expression *cond)
{
int idx;
long dbr_addr, dbr_mask;
if ((dbr_mask & (0x3UL << 62)) && addr == (CORE_ADDR) dbr_addr)
{
struct lwp_info *lp;
- ptid_t ptid;
debug_registers[2 * idx] = 0;
debug_registers[2 * idx + 1] = 0;
dbr_addr = 0;
dbr_mask = 0;
- ALL_LWPS (lp, ptid)
- store_debug_register_pair (ptid, idx, &dbr_addr, &dbr_mask);
+ ALL_LWPS (lp)
+ store_debug_register_pair (lp->ptid, idx, &dbr_addr, &dbr_mask);
return 0;
}
return -1;
}
-static void
-ia64_linux_new_thread (ptid_t ptid)
+void
+ia64_linux_nat_target::low_new_thread (struct lwp_info *lp)
{
int i, any;
{
if (debug_registers[i] != 0)
any = 1;
- store_debug_register (ptid, i, debug_registers[i]);
+ store_debug_register (lp->ptid, i, debug_registers[i]);
}
if (any)
- enable_watchpoints_in_psr (ptid);
+ enable_watchpoints_in_psr (lp->ptid);
}
-static int
-ia64_linux_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p)
+bool
+ia64_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p)
{
CORE_ADDR psr;
- struct siginfo *siginfo_p;
+ siginfo_t siginfo;
struct regcache *regcache = get_current_regcache ();
- siginfo_p = linux_nat_get_siginfo (inferior_ptid);
+ if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
+ return false;
- if (siginfo_p->si_signo != SIGTRAP
- || (siginfo_p->si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
- return 0;
+ if (siginfo.si_signo != SIGTRAP
+ || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
+ return false;
regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr);
psr |= IA64_PSR_DD; /* Set the dd bit - this will disable the watchpoint
- for the next instruction */
+ for the next instruction. */
regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr);
- *addr_p = (CORE_ADDR)siginfo_p->si_addr;
- return 1;
+ *addr_p = (CORE_ADDR) siginfo.si_addr;
+ return true;
}
-static int
-ia64_linux_stopped_by_watchpoint (void)
+bool
+ia64_linux_nat_target::stopped_by_watchpoint ()
{
CORE_ADDR addr;
- return ia64_linux_stopped_data_address (¤t_target, &addr);
+ return stopped_data_address (&addr);
}
-static int
-ia64_linux_can_use_hw_breakpoint (int type, int cnt, int othertype)
+int
+ia64_linux_nat_target::can_use_hw_breakpoint (enum bptype type,
+ int cnt, int othertype)
{
return 1;
}
static void
ia64_linux_fetch_register (struct regcache *regcache, int regnum)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
CORE_ADDR addr;
size_t size;
PTRACE_TYPE_RET *buf;
- int pid, i;
+ pid_t pid;
+ int i;
+
+ /* r0 cannot be fetched but is always zero. */
+ if (regnum == IA64_GR0_REGNUM)
+ {
+ const gdb_byte zero[8] = { 0 };
+
+ gdb_assert (sizeof (zero) == register_size (gdbarch, regnum));
+ regcache->raw_supply (regnum, zero);
+ return;
+ }
+
+ /* fr0 cannot be fetched but is always zero. */
+ if (regnum == IA64_FR0_REGNUM)
+ {
+ const gdb_byte f_zero[16] = { 0 };
+
+ gdb_assert (sizeof (f_zero) == register_size (gdbarch, regnum));
+ regcache->raw_supply (regnum, f_zero);
+ return;
+ }
+
+ /* fr1 cannot be fetched but is always one (1.0). */
+ if (regnum == IA64_FR1_REGNUM)
+ {
+ const gdb_byte f_one[16] =
+ { 0, 0, 0, 0, 0, 0, 0, 0x80, 0xff, 0xff, 0, 0, 0, 0, 0, 0 };
+
+ gdb_assert (sizeof (f_one) == register_size (gdbarch, regnum));
+ regcache->raw_supply (regnum, f_one);
+ return;
+ }
if (ia64_cannot_fetch_register (gdbarch, regnum))
{
- regcache_raw_supply (regcache, regnum, NULL);
+ regcache->raw_supply (regnum, NULL);
return;
}
- /* Cater for systems like GNU/Linux, that implement threads as
- separate processes. */
- pid = ptid_get_lwp (inferior_ptid);
- if (pid == 0)
- pid = ptid_get_pid (inferior_ptid);
+ pid = get_ptrace_pid (regcache->ptid ());
/* This isn't really an address, but ptrace thinks of it as one. */
addr = ia64_register_addr (gdbarch, regnum);
size = register_size (gdbarch, regnum);
gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
- buf = alloca (size);
+ buf = (PTRACE_TYPE_RET *) alloca (size);
/* Read the register contents from the inferior a chunk at a time. */
for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
addr += sizeof (PTRACE_TYPE_RET);
}
- regcache_raw_supply (regcache, regnum, buf);
+ regcache->raw_supply (regnum, buf);
}
/* Fetch register REGNUM from the inferior. If REGNUM is -1, do this
for all registers. */
-static void
-ia64_linux_fetch_registers (struct regcache *regcache, int regnum)
+void
+ia64_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum)
{
if (regnum == -1)
for (regnum = 0;
- regnum < gdbarch_num_regs (get_regcache_arch (regcache));
+ regnum < gdbarch_num_regs (regcache->arch ());
regnum++)
ia64_linux_fetch_register (regcache, regnum);
else
static void
ia64_linux_store_register (const struct regcache *regcache, int regnum)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
CORE_ADDR addr;
size_t size;
PTRACE_TYPE_RET *buf;
- int pid, i;
+ pid_t pid;
+ int i;
if (ia64_cannot_store_register (gdbarch, regnum))
return;
- /* Cater for systems like GNU/Linux, that implement threads as
- separate processes. */
- pid = ptid_get_lwp (inferior_ptid);
- if (pid == 0)
- pid = ptid_get_pid (inferior_ptid);
+ pid = get_ptrace_pid (regcache->ptid ());
/* This isn't really an address, but ptrace thinks of it as one. */
addr = ia64_register_addr (gdbarch, regnum);
size = register_size (gdbarch, regnum);
gdb_assert ((size % sizeof (PTRACE_TYPE_RET)) == 0);
- buf = alloca (size);
+ buf = (PTRACE_TYPE_RET *) alloca (size);
/* Write the register contents into the inferior a chunk at a time. */
- regcache_raw_collect (regcache, regnum, buf);
+ regcache->raw_collect (regnum, buf);
for (i = 0; i < size / sizeof (PTRACE_TYPE_RET); i++)
{
errno = 0;
/* Store register REGNUM back into the inferior. If REGNUM is -1, do
this for all registers. */
-static void
-ia64_linux_store_registers (struct regcache *regcache, int regnum)
+void
+ia64_linux_nat_target::store_registers (struct regcache *regcache, int regnum)
{
if (regnum == -1)
for (regnum = 0;
- regnum < gdbarch_num_regs (get_regcache_arch (regcache));
+ regnum < gdbarch_num_regs (regcache->arch ());
regnum++)
ia64_linux_store_register (regcache, regnum);
else
ia64_linux_store_register (regcache, regnum);
}
+/* Implement the xfer_partial target_ops method. */
-static LONGEST (*super_xfer_partial) (struct target_ops *, enum target_object,
- const char *, gdb_byte *, const gdb_byte *,
- ULONGEST, LONGEST);
-
-static LONGEST
-ia64_linux_xfer_partial (struct target_ops *ops,
- enum target_object object,
- const char *annex,
- gdb_byte *readbuf, const gdb_byte *writebuf,
- ULONGEST offset, LONGEST len)
+enum target_xfer_status
+ia64_linux_nat_target::xfer_partial (enum target_object object,
+ const char *annex,
+ gdb_byte *readbuf, const gdb_byte *writebuf,
+ ULONGEST offset, ULONGEST len,
+ ULONGEST *xfered_len)
{
- if (object == TARGET_OBJECT_UNWIND_TABLE && writebuf == NULL && offset == 0)
- return syscall (__NR_getunwind, readbuf, len);
+ if (object == TARGET_OBJECT_UNWIND_TABLE && readbuf != NULL)
+ {
+ static long gate_table_size;
+ gdb_byte *tmp_buf;
+ long res;
+
+ /* Probe for the table size once. */
+ if (gate_table_size == 0)
+ gate_table_size = syscall (__NR_getunwind, NULL, 0);
+ if (gate_table_size < 0)
+ return TARGET_XFER_E_IO;
+
+ if (offset >= gate_table_size)
+ return TARGET_XFER_EOF;
+
+ tmp_buf = (gdb_byte *) alloca (gate_table_size);
+ res = syscall (__NR_getunwind, tmp_buf, gate_table_size);
+ if (res < 0)
+ return TARGET_XFER_E_IO;
+ gdb_assert (res == gate_table_size);
+
+ if (offset + len > gate_table_size)
+ len = gate_table_size - offset;
+
+ memcpy (readbuf, tmp_buf + offset, len);
+ *xfered_len = len;
+ return TARGET_XFER_OK;
+ }
- return super_xfer_partial (ops, object, annex, readbuf, writebuf,
- offset, len);
+ return linux_nat_target::xfer_partial (object, annex, readbuf, writebuf,
+ offset, len, xfered_len);
}
-void _initialize_ia64_linux_nat (void);
+/* For break.b instruction ia64 CPU forgets the immediate value and generates
+ SIGILL with ILL_ILLOPC instead of more common SIGTRAP with TRAP_BRKPT.
+ ia64 does not use gdbarch_decr_pc_after_break so we do not have to make any
+ difference for the signals here. */
-void
-_initialize_ia64_linux_nat (void)
+bool
+ia64_linux_nat_target::low_status_is_event (int status)
{
- struct target_ops *t;
-
- /* Fill in the generic GNU/Linux methods. */
- t = linux_target ();
-
- /* Override the default fetch/store register routines. */
- t->to_fetch_registers = ia64_linux_fetch_registers;
- t->to_store_registers = ia64_linux_store_registers;
-
- /* Override the default to_xfer_partial. */
- super_xfer_partial = t->to_xfer_partial;
- t->to_xfer_partial = ia64_linux_xfer_partial;
-
- /* Override watchpoint routines. */
-
- /* The IA-64 architecture can step over a watch point (without triggering
- it again) if the "dd" (data debug fault disable) bit in the processor
- status word is set.
-
- This PSR bit is set in ia64_linux_stopped_by_watchpoint when the
- code there has determined that a hardware watchpoint has indeed
- been hit. The CPU will then be able to execute one instruction
- without triggering a watchpoint. */
-
- t->to_have_steppable_watchpoint = 1;
- t->to_can_use_hw_breakpoint = ia64_linux_can_use_hw_breakpoint;
- t->to_stopped_by_watchpoint = ia64_linux_stopped_by_watchpoint;
- t->to_stopped_data_address = ia64_linux_stopped_data_address;
- t->to_insert_watchpoint = ia64_linux_insert_watchpoint;
- t->to_remove_watchpoint = ia64_linux_remove_watchpoint;
+ return WIFSTOPPED (status) && (WSTOPSIG (status) == SIGTRAP
+ || WSTOPSIG (status) == SIGILL);
+}
+void _initialize_ia64_linux_nat ();
+void
+_initialize_ia64_linux_nat ()
+{
/* Register the target. */
- linux_nat_add_target (t);
- linux_nat_set_new_thread (t, ia64_linux_new_thread);
+ linux_target = &the_ia64_linux_nat_target;
+ add_inf_child_target (&the_ia64_linux_nat_target);
}
projects / deliverable / binutils-gdb.git / blobdiff