Regenerate pot files.

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index d247bac90bdc240ee6f90b429db840407048d384..1280eaf9444ce2ceea17227cb3ad82bc6546e84b 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,81 @@
+2016-12-23  Tristan Gingold  <gingold@adacore.com>
+
+       * po/opcodes.pot: Regenerate.
+
+2016-12-21  Andrew Waterman  <andrew@sifive.com>
+
+       * riscv-opc.c (riscv_opcodes): Reorder jal and call entries.
+
+2016-12-20  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than
+       ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry.
+       (print_insn_mips16): Check opcode entries for validity against
+       the ISA level and ASE set selected.
+
+2016-12-20  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
+       `insn' together, with `extend' as the high-order 16 bits.
+       (match_kind): New enum.
+       (print_insn_mips16): Rework for 32-bit instruction matching.
+       Do not dump EXTEND prefixes here.
+       * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
+       Recode `match' and `mask' fields as 32-bit in absolute "jal" and
+       "jalx" entries.
+
+2016-12-20  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
+       than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu"
+       INSN_MACRO entries.
+
+2016-12-20  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * mips16-opc.c (mips16_opcodes): Set membership to I3 rather
+       than I1 for the SP-relative "sd"/$ra entry (SDRASP minor
+       opcode).
+
+2016-12-20  Andrew Waterman  <andrew@sifive.com>
+
+       * riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to
+       "*.aqrl".
+
+2016-12-20  Andrew Waterman  <andrew@sifive.com>
+
+       * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as
+       INSN_ALIAS.
+
+2016-12-20  Andrew Waterman  <andrew@sifive.com>
+
+       * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)"
+       format.
+
+2016-12-20  Andrew Waterman  <andrew@sifive.com>
+
+       * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
+       XLEN when none is provided.
+
+2016-12-20  Andrew Waterman  <andrew@sifive.com>
+
+       * riscv-opc.c: Formatting fixes.
+
+2016-12-20  Alan Modra  <amodra@gmail.com>
+
+       * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files.
+       * Makefile.in: Regenerate.
+       * po/POTFILES.in: Regenerate.
+
+2016-12-19  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]:
+       Only examine ELF file structures here.
+
+2016-12-19  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call
+       `bfd_mips_elf_get_abiflags' here.
+
 2016-12-16  Nick Clifton  <nickc@redhat.com>
 
        * arm-dis.c (print_insn_thumb32): Fix compile time warning