RISC-V: Support the ISA-dependent CSR checking.

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e5aa59d03a619d795601fe5c1c063ebafa9b10c8..73091b9e61d16bef786188b8c2238cbc5bfaa591 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
+
+       * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
+       changed.
+
 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 
        * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed