Update copyright years

[deliverable/binutils-gdb.git] / opcodes / aarch64-dis.c

diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 84b7b0a3eb837d3fc28c77ba317e2397d832cacb..477edb618193668981400c6e589f92a11c8269bd 100644 (file)
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -1,5 +1,5 @@
 /* aarch64-dis.c -- AArch64 disassembler.
-   Copyright 2009, 2010, 2011, 2012  Free Software Foundation, Inc.
+   Copyright (C) 2009-2014 Free Software Foundation, Inc.
    Contributed by ARM Ltd.
 
    This file is part of the GNU opcodes library.
@@ -24,12 +24,7 @@
 #include "libiberty.h"
 #include "opintl.h"
 #include "aarch64-dis.h"
-
-#if !defined(EMBEDDED_ENV)
-#define SYMTAB_AVAILABLE 1
 #include "elf-bfd.h"
-#include "elf/aarch64.h"
-#endif
 
 #define ERR_OK   0
 #define ERR_UND -1
@@ -125,7 +120,7 @@ parse_aarch64_dis_options (const char *options)
    N.B. the fields are required to be in such an order than the most signficant
    field for VALUE comes the first, e.g. the <index> in
     SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
-   is encoded in H:L:M in some cases, the the fields H:L:M should be passed in
+   is encoded in H:L:M in some cases, the fields H:L:M should be passed in
    the order of H, L, M.  */
 
 static inline aarch64_insn
@@ -642,6 +637,7 @@ aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
        {
        case 4: gen_sub_field (FLD_cmode, 1, 2, &field); break; /* per word */
        case 2: gen_sub_field (FLD_cmode, 1, 1, &field); break; /* per half */
+       case 1: gen_sub_field (FLD_cmode, 1, 0, &field); break; /* per byte */
        default: assert (0); return 0;
        }
       /* 00: 0; 01: 8; 10:16; 11:24.  */
@@ -1477,6 +1473,20 @@ convert_extr_to_ror (aarch64_inst *inst)
   return 0;
 }
 
+/* UXTL<Q> <Vd>.<Ta>, <Vn>.<Tb>
+     is equivalent to:
+   USHLL<Q> <Vd>.<Ta>, <Vn>.<Tb>, #0.  */
+static int
+convert_shll_to_xtl (aarch64_inst *inst)
+{
+  if (inst->operands[2].imm.value == 0)
+    {
+      inst->operands[2].type = AARCH64_OPND_NIL;
+      return 1;
+    }
+  return 0;
+}
+
 /* Convert
      UBFM <Xd>, <Xn>, #<shift>, #63.
    to
@@ -1591,12 +1601,14 @@ convert_ubfm_to_lsl (aarch64_inst *inst)
 
 /* CINC <Wd>, <Wn>, <cond>
      is equivalent to:
-   CSINC <Wd>, <Wn>, <Wn>, invert(<cond>).  */
+   CSINC <Wd>, <Wn>, <Wn>, invert(<cond>)
+     where <cond> is not AL or NV.  */
 
 static int
 convert_from_csel (aarch64_inst *inst)
 {
-  if (inst->operands[1].reg.regno == inst->operands[2].reg.regno)
+  if (inst->operands[1].reg.regno == inst->operands[2].reg.regno
+      && (inst->operands[3].cond->value & 0xe) != 0xe)
     {
       copy_operand_info (inst, 2, 3);
       inst->operands[2].cond = get_inverted_cond (inst->operands[3].cond);
@@ -1608,13 +1620,15 @@ convert_from_csel (aarch64_inst *inst)
 
 /* CSET <Wd>, <cond>
      is equivalent to:
-   CSINC <Wd>, WZR, WZR, invert(<cond>).  */
+   CSINC <Wd>, WZR, WZR, invert(<cond>)
+     where <cond> is not AL or NV.  */
 
 static int
 convert_csinc_to_cset (aarch64_inst *inst)
 {
   if (inst->operands[1].reg.regno == 0x1f
-      && inst->operands[2].reg.regno == 0x1f)
+      && inst->operands[2].reg.regno == 0x1f
+      && (inst->operands[3].cond->value & 0xe) != 0xe)
     {
       copy_operand_info (inst, 1, 3);
       inst->operands[1].cond = get_inverted_cond (inst->operands[3].cond);
@@ -1730,6 +1744,11 @@ convert_to_alias (aarch64_inst *inst, const aarch64_opcode *alias)
       return convert_movebitmask_to_mov (inst);
     case OP_ROR_IMM:
       return convert_extr_to_ror (inst);
+    case OP_SXTL:
+    case OP_SXTL2:
+    case OP_UXTL:
+    case OP_UXTL2:
+      return convert_shll_to_xtl (inst);
     default:
       return 0;
     }