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[deliverable/binutils-gdb.git] / opcodes / aarch64-opc.c

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 5be0d0f14181f063d69ff0b9aac8bfc0ca74a434..61547b403df47a3d23361019799b00e285290969 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -294,6 +294,9 @@ const aarch64_field fields[] =
     {  0,  5 }, /* SVE_Zt: SVE vector register, bits [4,0].  */
     {  5,  1 }, /* SVE_i1: single-bit immediate.  */
     { 22,  1 }, /* SVE_i3h: high bit of 3-bit immediate.  */
+    { 11,  1 }, /* SVE_i3l: low bit of 3-bit immediate.  */
+    { 19,  2 }, /* SVE_i3h2: two high bits of 3bit immediate, bits [20,19].  */
+    { 20,  1 }, /* SVE_i2h: high bit of 2bit immediate, bits.  */
     { 16,  3 }, /* SVE_imm3: 3-bit immediate field.  */
     { 16,  4 }, /* SVE_imm4: 4-bit immediate field.  */
     {  5,  5 }, /* SVE_imm5: 5-bit immediate field.  */
@@ -309,7 +312,10 @@ const aarch64_field fields[] =
     {  0,  4 }, /* SVE_prfop: prefetch operation for SVE PRF[BHWD].  */
     { 16,  1 }, /* SVE_rot1: 1-bit rotation amount.  */
     { 10,  2 }, /* SVE_rot2: 2-bit rotation amount.  */
+    { 10,  1 }, /* SVE_rot3: 1-bit rotation amount at bit 10.  */
     { 22,  1 }, /* SVE_sz: 1-bit element size select.  */
+    { 17,  2 }, /* SVE_size: 2-bit element size, bits [18,17].  */
+    { 30,  1 }, /* SVE_sz2: 1-bit element size select.  */
     { 16,  4 }, /* SVE_tsz: triangular size select.  */
     { 22,  2 }, /* SVE_tszh: triangular size select high, bits [23,22].  */
     {  8,  2 }, /* SVE_tszl_8: triangular size select low, bits [9,8].  */
@@ -706,6 +712,7 @@ struct operand_qualifier_data aarch64_opnd_qualifiers[] =
   {8, 1, 0x3, "d", OQK_OPD_VARIANT},
   {16, 1, 0x4, "q", OQK_OPD_VARIANT},
   {4, 1, 0x0, "4b", OQK_OPD_VARIANT},
+  {4, 1, 0x0, "2h", OQK_OPD_VARIANT},
 
   {1, 4, 0x0, "4b", OQK_OPD_VARIANT},
   {1, 8, 0x0, "8b", OQK_OPD_VARIANT},
@@ -1513,6 +1520,8 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
        {
        case AARCH64_OPND_SVE_Zm3_INDEX:
        case AARCH64_OPND_SVE_Zm3_22_INDEX:
+       case AARCH64_OPND_SVE_Zm3_11_INDEX:
+       case AARCH64_OPND_SVE_Zm4_11_INDEX:
        case AARCH64_OPND_SVE_Zm4_INDEX:
          size = get_operand_fields_width (get_operand_from_code (type));
          shift = get_operand_specific_data (&aarch64_operands[type]);
@@ -1890,10 +1899,22 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
          break;
 
        case AARCH64_OPND_SVE_ADDR_RI_S4x16:
+       case AARCH64_OPND_SVE_ADDR_RI_S4x32:
          min_value = -8;
          max_value = 7;
          goto sve_imm_offset;
 
+       case AARCH64_OPND_SVE_ADDR_ZX:
+         /* Everything is already ensured by parse_operands or
+            aarch64_ext_sve_addr_rr_lsl (because this is a very specific
+            argument type).  */
+         assert (opnd->addr.offset.is_reg);
+         assert (opnd->addr.preind);
+         assert ((aarch64_operands[type].flags & OPD_F_NO_ZR) == 0);
+         assert (opnd->shifter.kind == AARCH64_MOD_LSL);
+         assert (opnd->shifter.operator_present == 0);
+         break;
+
        case AARCH64_OPND_SVE_ADDR_R:
        case AARCH64_OPND_SVE_ADDR_RR:
        case AARCH64_OPND_SVE_ADDR_RR_LSL1:
@@ -2231,6 +2252,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
 
        case AARCH64_OPND_IMM_ROT3:
        case AARCH64_OPND_SVE_IMM_ROT1:
+       case AARCH64_OPND_SVE_IMM_ROT3:
          if (opnd->imm.value != 90 && opnd->imm.value != 270)
            {
              set_other_error (mismatch_detail, idx,
@@ -2511,6 +2533,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
 
        case AARCH64_OPND_SVE_SHLIMM_PRED:
        case AARCH64_OPND_SVE_SHLIMM_UNPRED:
+       case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
          size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
          if (!value_in_range_p (opnd->imm.value, 0, 8 * size - 1))
            {
@@ -2522,10 +2545,12 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
 
        case AARCH64_OPND_SVE_SHRIMM_PRED:
        case AARCH64_OPND_SVE_SHRIMM_UNPRED:
-         size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
+       case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
+         num = (type == AARCH64_OPND_SVE_SHRIMM_UNPRED_22) ? 2 : 1;
+         size = aarch64_get_qualifier_esize (opnds[idx - num].qualifier);
          if (!value_in_range_p (opnd->imm.value, 1, 8 * size))
            {
-             set_imm_out_of_range_error (mismatch_detail, idx, 1, 8 * size);
+             set_imm_out_of_range_error (mismatch_detail, idx, 1, 8*size);
              return 0;
            }
          break;
@@ -3037,7 +3062,12 @@ print_immediate_offset_address (char *buf, size_t size,
   if (opnd->addr.writeback)
     {
       if (opnd->addr.preind)
-       snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm);
+        {
+         if (opnd->type == AARCH64_OPND_ADDR_SIMM10 && !opnd->addr.offset.imm)
+            snprintf (buf, size, "[%s]!", base);
+          else
+           snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm);
+        }
       else
        snprintf (buf, size, "[%s], #%d", base, opnd->addr.offset.imm);
     }
@@ -3300,6 +3330,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
 
     case AARCH64_OPND_SVE_Zm3_INDEX:
     case AARCH64_OPND_SVE_Zm3_22_INDEX:
+    case AARCH64_OPND_SVE_Zm3_11_INDEX:
+    case AARCH64_OPND_SVE_Zm4_11_INDEX:
     case AARCH64_OPND_SVE_Zm4_INDEX:
     case AARCH64_OPND_SVE_Zn_INDEX:
       snprintf (buf, size, "z%d.%s[%" PRIi64 "]", opnd->reglane.regno,
@@ -3331,8 +3363,10 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
     case AARCH64_OPND_SIMM5:
     case AARCH64_OPND_SVE_SHLIMM_PRED:
     case AARCH64_OPND_SVE_SHLIMM_UNPRED:
+    case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
     case AARCH64_OPND_SVE_SHRIMM_PRED:
     case AARCH64_OPND_SVE_SHRIMM_UNPRED:
+    case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
     case AARCH64_OPND_SVE_SIMM5:
     case AARCH64_OPND_SVE_SIMM5B:
     case AARCH64_OPND_SVE_SIMM6:
@@ -3346,6 +3380,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
     case AARCH64_OPND_IMM_ROT3:
     case AARCH64_OPND_SVE_IMM_ROT1:
     case AARCH64_OPND_SVE_IMM_ROT2:
+    case AARCH64_OPND_SVE_IMM_ROT3:
       snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
       break;
 
@@ -3575,6 +3610,13 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
         get_offset_int_reg_name (opnd));
       break;
 
+    case AARCH64_OPND_SVE_ADDR_ZX:
+      print_register_offset_address
+       (buf, size, opnd,
+        get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
+        get_64bit_int_reg_name (opnd->addr.offset.regno, 0));
+      break;
+
     case AARCH64_OPND_SVE_ADDR_RZ:
     case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
     case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
@@ -3600,6 +3642,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
     case AARCH64_OPND_ADDR_SIMM13:
     case AARCH64_OPND_ADDR_OFFSET:
     case AARCH64_OPND_SVE_ADDR_RI_S4x16:
+    case AARCH64_OPND_SVE_ADDR_RI_S4x32:
     case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
     case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
     case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
@@ -3928,13 +3971,14 @@ const aarch64_sys_reg aarch64_sys_regs [] =
   { "rndr",            CPENC(3,3,C2,C4,0), F_ARCHEXT | F_REG_READ }, /* RO */
   { "rndrrs",          CPENC(3,3,C2,C4,1), F_ARCHEXT | F_REG_READ }, /* RO */
   { "tco",             CPENC(3,3,C4,C2,7), F_ARCHEXT },
-  { "tfsre0_el1",      CPENC(3,0,C6,C6,1), F_ARCHEXT },
-  { "tfsr_el1",                CPENC(3,0,C6,C5,0), F_ARCHEXT },
-  { "tfsr_el2",                CPENC(3,4,C6,C5,0), F_ARCHEXT },
-  { "tfsr_el3",                CPENC(3,6,C6,C6,0), F_ARCHEXT },
-  { "tfsr_el12",       CPENC(3,5,C6,C6,0), F_ARCHEXT },
+  { "tfsre0_el1",      CPENC(3,0,C5,C6,1), F_ARCHEXT },
+  { "tfsr_el1",                CPENC(3,0,C5,C6,0), F_ARCHEXT },
+  { "tfsr_el2",                CPENC(3,4,C5,C6,0), F_ARCHEXT },
+  { "tfsr_el3",                CPENC(3,6,C5,C6,0), F_ARCHEXT },
+  { "tfsr_el12",       CPENC(3,5,C5,C6,0), F_ARCHEXT },
   { "rgsr_el1",                CPENC(3,0,C1,C0,5), F_ARCHEXT },
   { "gcr_el1",         CPENC(3,0,C1,C0,6), F_ARCHEXT },
+  { "gmid_el1",                CPENC(3,1,C0,C0,4), F_ARCHEXT | F_REG_READ }, /* RO */
   { "tpidr_el0",        CPENC(3,3,C13,C0,2),   0 },
   { "tpidrro_el0",      CPENC(3,3,C13,C0,3),   0 }, /* RW */
   { "tpidr_el1",        CPENC(3,0,C13,C0,4),   0 },
@@ -4400,13 +4444,14 @@ aarch64_sys_reg_supported_p (const aarch64_feature_set features,
 
   /* System Registers in ARMv8.5-A with AARCH64_FEATURE_MEMTAG.  */
   if ((reg->value == CPENC (3, 3, C4, C2, 7)
-       || reg->value == CPENC (3, 0, C6, C6, 1)
-       || reg->value == CPENC (3, 0, C6, C5, 0)
-       || reg->value == CPENC (3, 4, C6, C5, 0)
-       || reg->value == CPENC (3, 6, C6, C6, 0)
-       || reg->value == CPENC (3, 5, C6, C6, 0)
+       || reg->value == CPENC (3, 0, C5, C6, 1)
+       || reg->value == CPENC (3, 0, C5, C6, 0)
+       || reg->value == CPENC (3, 4, C5, C6, 0)
+       || reg->value == CPENC (3, 6, C5, C6, 0)
+       || reg->value == CPENC (3, 5, C5, C6, 0)
        || reg->value == CPENC (3, 0, C1, C0, 5)
-       || reg->value == CPENC (3, 0, C1, C0, 6))
+       || reg->value == CPENC (3, 0, C1, C0, 6)
+       || reg->value == CPENC (3, 1, C0, C0, 4))
       && !(AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG)))
     return FALSE;
 
@@ -4867,7 +4912,9 @@ verify_constraints (const struct aarch64_inst *inst,
        {
          /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
             instruction for better error messages.  */
-         if (!opcode->avariant || !(*opcode->avariant & AARCH64_FEATURE_SVE))
+         if (!opcode->avariant
+             || !(*opcode->avariant &
+                  (AARCH64_FEATURE_SVE | AARCH64_FEATURE_SVE2)))
            {
              mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
              mismatch_detail->error = _("SVE instruction expected after "
@@ -4928,11 +4975,6 @@ verify_constraints (const struct aarch64_inst *inst,
                  case AARCH64_OPND_Vm:
                  case AARCH64_OPND_Sn:
                  case AARCH64_OPND_Sm:
-                 case AARCH64_OPND_Rn:
-                 case AARCH64_OPND_Rm:
-                 case AARCH64_OPND_Rn_SP:
-                 case AARCH64_OPND_Rt_SP:
-                 case AARCH64_OPND_Rm_SP:
                    if (inst_op.reg.regno == blk_dest.reg.regno)
                      {
                        num_op_used++;