/* Instruction printing code for the ARC.
- Copyright (C) 1994-2016 Free Software Foundation, Inc.
+ Copyright (C) 1994-2020 Free Software Foundation, Inc.
Contributed by Claudiu Zissulescu (claziss@synopsys.com)
const unsigned char *opidx;
};
+/* A private data used by ARC decoder. */
+struct arc_disassemble_info
+{
+ /* The current disassembled arc opcode. */
+ const struct arc_opcode *opcode;
+
+ /* Instruction length w/o limm field. */
+ unsigned insn_len;
+
+ /* TRUE if we have limm. */
+ bfd_boolean limm_p;
+
+ /* LIMM value, if exists. */
+ unsigned limm;
+
+ /* Condition code, if exists. */
+ unsigned condition_code;
+
+ /* Writeback mode. */
+ unsigned writeback_mode;
+
+ /* Number of operands. */
+ unsigned operands_count;
+
+ struct arc_insn_operand operands[MAX_INSN_ARGS];
+};
+
/* Globals variables. */
static const char * const regnames[64] =
disassembling. */
static linkclass decodelist = NULL;
+/* ISA mask value enforced via disassembler info options. ARC_OPCODE_NONE
+ value means that no CPU is enforced. */
+
+static unsigned enforced_isa_mask = ARC_OPCODE_NONE;
+
+/* True if we want to print using only hex numbers. */
+static bfd_boolean print_hex = FALSE;
+
/* Macros section. */
#ifdef DEBUG
(info->endian == BFD_ENDIAN_LITTLE ? bfd_getm32 (bfd_getl32 (buf)) \
: bfd_getb32 (buf))
-#define BITS(word,s,e) (((word) << (sizeof (word) * 8 - 1 - e)) >> \
- (s + (sizeof (word) * 8 - 1 - e)))
+#define BITS(word,s,e) (((word) >> (s)) & ((1ull << ((e) - (s)) << 1) - 1))
#define OPCODE_32BIT_INSN(word) (BITS ((word), 27, 31))
/* Functions implementation. */
+/* Initialize private data. */
+static bfd_boolean
+init_arc_disasm_info (struct disassemble_info *info)
+{
+ struct arc_disassemble_info *arc_infop
+ = calloc (sizeof (*arc_infop), 1);
+
+ if (arc_infop == NULL)
+ return FALSE;
+
+ info->private_data = arc_infop;
+ return TRUE;
+}
+
/* Add a new element to the decode list. */
static void
/* Check opcode for major 0x06, return if it is not in. */
if (arc_opcode_len (opcode) == 4
- && OPCODE_32BIT_INSN (opcode->opcode) != 0x06)
+ && (OPCODE_32BIT_INSN (opcode->opcode) != 0x06
+ /* Can be an APEX extensions. */
+ && OPCODE_32BIT_INSN (opcode->opcode) != 0x07))
return FALSE;
/* or not a known truble class. */
{
case FLOAT:
case DSP:
+ case ARITH:
+ case MPY:
break;
default:
return FALSE;
if (operand->extract)
value = (*operand->extract) (insn, &invalid);
else
- value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
+ value = (insn >> operand->shift) & ((1ull << operand->bits) - 1);
/* Check for LIMM indicator. If it is there, then make sure
we pick the right format. */
continue;
}
+ /* Check for the implicit flags. */
+ if (cl_flags->flag_class & F_CLASS_IMPLICIT)
+ continue;
+
for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
{
const struct arc_flag_operand *flg_operand =
bfd_boolean needs_limm;
const extInstruction_t *einsn, *i;
unsigned limm = 0;
+ struct arc_disassemble_info *arc_infop = info->private_data;
/* First, try the extension instructions. */
if (*insn_len == 4)
}
*opcode_result = opcode;
+
+ /* Update private data. */
+ arc_infop->opcode = opcode;
+ arc_infop->limm = (needs_limm) ? limm : 0;
+ arc_infop->limm_p = needs_limm;
+
return TRUE;
}
{
const unsigned char *flgidx;
unsigned int value;
+ struct arc_disassemble_info *arc_infop = info->private_data;
/* Now extract and print the flags. */
for (flgidx = opcode->flags; *flgidx; flgidx++)
const struct arc_flag_operand *flg_operand =
&arc_flag_operands[*flgopridx];
+ /* Implicit flags are only used for the insn decoder. */
+ if (cl_flags->flag_class & F_CLASS_IMPLICIT)
+ {
+ if (cl_flags->flag_class & F_CLASS_COND)
+ arc_infop->condition_code = flg_operand->code;
+ else if (cl_flags->flag_class & F_CLASS_WB)
+ arc_infop->writeback_mode = flg_operand->code;
+ else if (cl_flags->flag_class & F_CLASS_ZZ)
+ info->data_size = flg_operand->code;
+ continue;
+ }
+
if (!flg_operand->favail)
continue;
info->insn_type = dis_condjsr;
else if (info->insn_type == dis_branch)
info->insn_type = dis_condbranch;
+ arc_infop->condition_code = flg_operand->code;
}
+ /* Check for the write back modes. */
+ if (cl_flags->flag_class & F_CLASS_WB)
+ arc_infop->writeback_mode = flg_operand->code;
+
(*info->fprintf_func) (info->stream, "%s", flg_operand->name);
}
}
break;
default:
- abort ();
+ return 0;
}
}
/* Helper for parsing the options. */
static void
-parse_option (char *option)
+parse_option (const char *option)
{
- if (CONST_STRNEQ (option, "dsp"))
+ if (disassembler_options_cmp (option, "dsp") == 0)
add_to_decodelist (DSP, NONE);
- else if (CONST_STRNEQ (option, "spfp"))
+ else if (disassembler_options_cmp (option, "spfp") == 0)
add_to_decodelist (FLOAT, SPX);
- else if (CONST_STRNEQ (option, "dpfp"))
+ else if (disassembler_options_cmp (option, "dpfp") == 0)
add_to_decodelist (FLOAT, DPX);
- else if (CONST_STRNEQ (option, "quarkse_em"))
+ else if (disassembler_options_cmp (option, "quarkse_em") == 0)
{
add_to_decodelist (FLOAT, DPX);
add_to_decodelist (FLOAT, SPX);
- add_to_decodelist (FLOAT, QUARKSE);
+ add_to_decodelist (FLOAT, QUARKSE1);
+ add_to_decodelist (FLOAT, QUARKSE2);
}
- else if (CONST_STRNEQ (option, "fpuda"))
+ else if (disassembler_options_cmp (option, "fpuda") == 0)
add_to_decodelist (FLOAT, DPA);
- else if (CONST_STRNEQ (option, "fpus"))
+ else if (disassembler_options_cmp (option, "nps400") == 0)
+ {
+ add_to_decodelist (ACL, NPS400);
+ add_to_decodelist (ARITH, NPS400);
+ add_to_decodelist (BITOP, NPS400);
+ add_to_decodelist (BMU, NPS400);
+ add_to_decodelist (CONTROL, NPS400);
+ add_to_decodelist (DMA, NPS400);
+ add_to_decodelist (DPI, NPS400);
+ add_to_decodelist (MEMORY, NPS400);
+ add_to_decodelist (MISC, NPS400);
+ add_to_decodelist (NET, NPS400);
+ add_to_decodelist (PMU, NPS400);
+ add_to_decodelist (PROTOCOL_DECODE, NPS400);
+ add_to_decodelist (ULTRAIP, NPS400);
+ }
+
+ else if (disassembler_options_cmp (option, "fpus") == 0)
{
add_to_decodelist (FLOAT, SP);
add_to_decodelist (FLOAT, CVT);
}
- else if (CONST_STRNEQ (option, "fpud"))
+ else if (disassembler_options_cmp (option, "fpud") == 0)
{
add_to_decodelist (FLOAT, DP);
add_to_decodelist (FLOAT, CVT);
}
+ else if (CONST_STRNEQ (option, "hex"))
+ print_hex = TRUE;
else
- fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
+ /* xgettext:c-format */
+ opcodes_error_handler (_("unrecognised disassembler option: %s"), option);
}
-/* Go over the options list and parse it. */
+#define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
+ { #NAME, ARC_OPCODE_ARC600, "ARC600" }
+#define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
+ { #NAME, ARC_OPCODE_ARC700, "ARC700" }
+#define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
+ { #NAME, ARC_OPCODE_ARCv2EM, "ARC EM" }
+#define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
+ { #NAME, ARC_OPCODE_ARCv2HS, "ARC HS" }
+#define ARC_CPU_TYPE_NONE \
+ { 0, 0, 0 }
+
+/* A table of CPU names and opcode sets. */
+static const struct cpu_type
+{
+ const char *name;
+ unsigned flags;
+ const char *isa;
+}
+ cpu_types[] =
+{
+ #include "elf/arc-cpu.def"
+};
-static void
-parse_disassembler_options (char *options)
+/* Helper for parsing the CPU options. Accept any of the ARC architectures
+ values. OPTION should be a value passed to cpu=. */
+
+static unsigned
+parse_cpu_option (const char *option)
{
- if (options == NULL)
- return;
+ int i;
- while (*options)
+ for (i = 0; cpu_types[i].name; ++i)
{
- /* Skip empty options. */
- if (*options == ',')
+ if (!disassembler_options_cmp (cpu_types[i].name, option))
{
- ++ options;
- continue;
+ return cpu_types[i].flags;
}
+ }
- parse_option (options);
+ /* xgettext:c-format */
+ opcodes_error_handler (_("unrecognised disassembler CPU option: %s"), option);
+ return ARC_OPCODE_NONE;
+}
- while (*options != ',' && *options != '\0')
- ++ options;
+/* Go over the options list and parse it. */
+
+static void
+parse_disassembler_options (const char *options)
+{
+ const char *option;
+
+ if (options == NULL)
+ return;
+
+ /* Disassembler might be reused for difference CPU's, and cpu option set for
+ the first one shouldn't be applied to second (which might not have
+ explicit cpu in its options. Therefore it is required to reset enforced
+ CPU when new options are being parsed. */
+ enforced_isa_mask = ARC_OPCODE_NONE;
+
+ FOR_EACH_DISASSEMBLER_OPTION (option, options)
+ {
+ /* A CPU option? Cannot use STRING_COMMA_LEN because strncmp is also a
+ preprocessor macro. */
+ if (strncmp (option, "cpu=", 4) == 0)
+ /* Strip leading `cpu=`. */
+ enforced_isa_mask = parse_cpu_option (option + 4);
+ else
+ parse_option (option);
}
}
switch (opcode->insn_class)
{
case BRANCH:
+ case BBIT0:
+ case BBIT1:
+ case BI:
+ case BIH:
+ case BRCC:
+ case EI:
+ case JLI:
case JUMP:
+ case LOOP:
if (!strncmp (opcode->name, "bl", 2)
|| !strncmp (opcode->name, "jl", 2))
{
insn_type = dis_branch;
}
break;
+ case LOAD:
+ case STORE:
case MEMORY:
- insn_type = dis_dref; /* FIXME! DB indicates mov as memory! */
+ case ENTER:
+ case PUSH:
+ case POP:
+ insn_type = dis_dref;
+ break;
+ case LEAVE:
+ insn_type = dis_branch;
break;
default:
insn_type = dis_nonbranch;
int status;
unsigned int insn_len;
unsigned long long insn = 0;
- unsigned isa_mask;
+ unsigned isa_mask = ARC_OPCODE_NONE;
const struct arc_opcode *opcode;
bfd_boolean need_comma;
bfd_boolean open_braket;
int size;
const struct arc_operand *operand;
- int value;
+ int value, vpcl;
struct arc_operand_iterator iter;
- Elf_Internal_Ehdr *header = NULL;
+ struct arc_disassemble_info *arc_infop;
+ bfd_boolean rpcl = FALSE, rset = FALSE;
if (info->disassembler_options)
{
info->disassembler_options = NULL;
}
+ if (info->private_data == NULL && !init_arc_disasm_info (info))
+ return -1;
+
memset (&iter, 0, sizeof (iter));
highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0);
lowbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1);
- if (info->section && info->section->owner)
- header = elf_elfheader (info->section->owner);
-
- switch (info->mach)
+ /* Figure out CPU type, unless it was enforced via disassembler options. */
+ if (enforced_isa_mask == ARC_OPCODE_NONE)
{
- case bfd_mach_arc_arc700:
- isa_mask = ARC_OPCODE_ARC700;
- break;
+ Elf_Internal_Ehdr *header = NULL;
- case bfd_mach_arc_arc600:
- isa_mask = ARC_OPCODE_ARC600;
- break;
+ if (info->section && info->section->owner)
+ header = elf_elfheader (info->section->owner);
- case bfd_mach_arc_arcv2:
- default:
- isa_mask = ARC_OPCODE_ARCv2EM;
- /* TODO: Perhaps remove defitinion of header since it is only used at
- this location. */
- if (header != NULL
- && (header->e_flags & EF_ARC_MACH_MSK) == EF_ARC_CPU_ARCV2HS)
+ switch (info->mach)
{
- isa_mask = ARC_OPCODE_ARCv2HS;
- /* FPU instructions are not extensions for HS. */
- add_to_decodelist (FLOAT, SP);
- add_to_decodelist (FLOAT, DP);
- add_to_decodelist (FLOAT, CVT);
+ case bfd_mach_arc_arc700:
+ isa_mask = ARC_OPCODE_ARC700;
+ break;
+
+ case bfd_mach_arc_arc600:
+ isa_mask = ARC_OPCODE_ARC600;
+ break;
+
+ case bfd_mach_arc_arcv2:
+ default:
+ isa_mask = ARC_OPCODE_ARCv2EM;
+ /* TODO: Perhaps remove definition of header since it is only used at
+ this location. */
+ if (header != NULL
+ && (header->e_flags & EF_ARC_MACH_MSK) == EF_ARC_CPU_ARCV2HS)
+ isa_mask = ARC_OPCODE_ARCv2HS;
+ break;
}
- break;
+ }
+ else
+ isa_mask = enforced_isa_mask;
+
+ if (isa_mask == ARC_OPCODE_ARCv2HS)
+ {
+ /* FPU instructions are not extensions for HS. */
+ add_to_decodelist (FLOAT, SP);
+ add_to_decodelist (FLOAT, DP);
+ add_to_decodelist (FLOAT, CVT);
}
/* This variable may be set by the instruction decoder. It suggests
the number of bytes objdump should display on a single line. If
the instruction decoder sets this, it should always set it to
the same value in order to get reasonable looking output. */
-
info->bytes_per_line = 8;
/* In the next lines, we set two info variables control the way
8 and bytes_per_chunk is 4, the output will look like this:
00: 00000000 00000000
with the chunks displayed according to "display_endian". */
-
if (info->section
&& !(info->section->flags & SEC_CODE))
{
/* Read the insn into a host word. */
status = (*info->read_memory_func) (memaddr, buffer, size, info);
+
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
(*info->fprintf_func) (info->stream, ".word\t0x%08lx", data);
break;
default:
- abort ();
+ return -1;
}
return size;
}
insn_len = arc_insn_length (buffer[highbyte], buffer[lowbyte], info);
pr_debug ("instruction length = %d bytes\n", insn_len);
+ if (insn_len == 0)
+ return -1;
+
+ arc_infop = info->private_data;
+ arc_infop->insn_len = insn_len;
switch (insn_len)
{
default:
/* There is no instruction whose length is not 2, 4, 6, or 8. */
- abort ();
+ return -1;
}
pr_debug ("instruction value = %llx\n", insn);
/* Set some defaults for the insn info. */
info->insn_info_valid = 1;
info->branch_delay_insns = 0;
- info->data_size = 0;
+ info->data_size = 4;
info->insn_type = dis_nonbranch;
info->target = 0;
info->target2 = 0;
switch (insn_len)
{
case 2:
- (*info->fprintf_func) (info->stream, ".long %#04llx",
+ (*info->fprintf_func) (info->stream, ".shor\t%#04llx",
insn & 0xffff);
break;
+
case 4:
- (*info->fprintf_func) (info->stream, ".long %#08llx",
+ (*info->fprintf_func) (info->stream, ".word\t%#08llx",
insn & 0xffffffff);
break;
+
case 6:
- (*info->fprintf_func) (info->stream, ".long %#08llx",
+ (*info->fprintf_func) (info->stream, ".long\t%#08llx",
insn & 0xffffffff);
- (*info->fprintf_func) (info->stream, ".long %#04llx",
+ (*info->fprintf_func) (info->stream, ".long\t%#04llx",
(insn >> 32) & 0xffff);
break;
+
case 8:
- (*info->fprintf_func) (info->stream, ".long %#08llx",
+ (*info->fprintf_func) (info->stream, ".long\t%#08llx",
insn & 0xffffffff);
- (*info->fprintf_func) (info->stream, ".long %#08llx",
+ (*info->fprintf_func) (info->stream, ".long\t%#08llx",
insn >> 32);
break;
+
default:
- abort ();
+ return -1;
}
info->insn_type = dis_noninsn;
need_comma = FALSE;
open_braket = FALSE;
+ arc_infop->operands_count = 0;
/* Now extract and print the operands. */
operand = NULL;
+ vpcl = 0;
while (operand_iterator_next (&iter, &operand, &value))
{
if (open_braket && (operand->flags & ARC_OPERAND_BRAKET))
if ((operand->flags & ARC_OPERAND_IGNORE)
&& (operand->flags & ARC_OPERAND_IR)
- && value == -1)
+ && value == -1)
continue;
if (operand->flags & ARC_OPERAND_COLON)
- {
- (*info->fprintf_func) (info->stream, ":");
- continue;
- }
+ {
+ (*info->fprintf_func) (info->stream, ":");
+ continue;
+ }
if (need_comma)
(*info->fprintf_func) (info->stream, ",");
need_comma = TRUE;
+ if (operand->flags & ARC_OPERAND_PCREL)
+ {
+ rpcl = TRUE;
+ vpcl = value;
+ rset = TRUE;
+
+ info->target = (bfd_vma) (memaddr & ~3) + value;
+ }
+ else if (!(operand->flags & ARC_OPERAND_IR))
+ {
+ vpcl = value;
+ rset = TRUE;
+ }
+
/* Print the operand as directed by the flags. */
if (operand->flags & ARC_OPERAND_IR)
{
rname = regnames[value + 1];
(*info->fprintf_func) (info->stream, "%s", rname);
}
+ if (value == 63)
+ rpcl = TRUE;
+ else
+ rpcl = FALSE;
}
else if (operand->flags & ARC_OPERAND_LIMM)
{
info->target = (bfd_vma) value;
}
}
- else if (operand->flags & ARC_OPERAND_PCREL)
- {
- /* PCL relative. */
- if (info->flags & INSN_HAS_RELOC)
- memaddr = 0;
- (*info->print_address_func) ((memaddr & ~3) + value, info);
-
- info->target = (bfd_vma) (memaddr & ~3) + value;
- }
else if (operand->flags & ARC_OPERAND_SIGNED)
{
const char *rname = get_auxreg (opcode, value, isa_mask);
if (rname && open_braket)
(*info->fprintf_func) (info->stream, "%s", rname);
else
- (*info->fprintf_func) (info->stream, "%d", value);
+ {
+ if (print_hex)
+ (*info->fprintf_func) (info->stream, "%#x", value);
+ else
+ (*info->fprintf_func) (info->stream, "%d", value);
+ }
}
else if (operand->flags & ARC_OPERAND_ADDRTYPE)
- {
- const char *addrtype = get_addrtype (value);
- (*info->fprintf_func) (info->stream, "%s", addrtype);
- /* A colon follow an address type. */
- need_comma = FALSE;
- }
+ {
+ const char *addrtype = get_addrtype (value);
+ (*info->fprintf_func) (info->stream, "%s", addrtype);
+ /* A colon follow an address type. */
+ need_comma = FALSE;
+ }
else
{
if (operand->flags & ARC_OPERAND_TRUNCATE
&& !(operand->flags & ARC_OPERAND_ALIGNED32)
&& !(operand->flags & ARC_OPERAND_ALIGNED16)
- && value > 0 && value <= 14)
- (*info->fprintf_func) (info->stream, "r13-%s",
- regnames[13 + value - 1]);
+ && value >= 0 && value <= 14)
+ {
+ /* Leave/Enter mnemonics. */
+ switch (value)
+ {
+ case 0:
+ need_comma = FALSE;
+ break;
+ case 1:
+ (*info->fprintf_func) (info->stream, "r13");
+ break;
+ default:
+ (*info->fprintf_func) (info->stream, "r13-%s",
+ regnames[13 + value - 1]);
+ break;
+ }
+ rpcl = FALSE;
+ rset = FALSE;
+ }
else
{
const char *rname = get_auxreg (opcode, value, isa_mask);
(*info->fprintf_func) (info->stream, "%#x", value);
}
}
+
+ if (operand->flags & ARC_OPERAND_LIMM)
+ {
+ arc_infop->operands[arc_infop->operands_count].kind
+ = ARC_OPERAND_KIND_LIMM;
+ /* It is not important to have exactly the LIMM indicator
+ here. */
+ arc_infop->operands[arc_infop->operands_count].value = 63;
+ }
+ else
+ {
+ arc_infop->operands[arc_infop->operands_count].value = value;
+ arc_infop->operands[arc_infop->operands_count].kind
+ = (operand->flags & ARC_OPERAND_IR
+ ? ARC_OPERAND_KIND_REG
+ : ARC_OPERAND_KIND_SHIMM);
+ }
+ arc_infop->operands_count ++;
+ }
+
+ /* Pretty print extra info for pc-relative operands. */
+ if (rpcl && rset)
+ {
+ if (info->flags & INSN_HAS_RELOC)
+ /* If the instruction has a reloc associated with it, then the
+ offset field in the instruction will actually be the addend
+ for the reloc. (We are using REL type relocs). In such
+ cases, we can ignore the pc when computing addresses, since
+ the addend is not currently pc-relative. */
+ memaddr = 0;
+
+ (*info->fprintf_func) (info->stream, "\t;");
+ (*info->print_address_func) ((memaddr & ~3) + vpcl, info);
}
return insn_len;
return print_insn_arc;
}
-/* Disassemble ARC instructions. Used by debugger. */
-
-struct arcDisState
-arcAnalyzeInstr (bfd_vma memaddr,
- struct disassemble_info *info)
-{
- struct arcDisState ret;
- memset (&ret, 0, sizeof (struct arcDisState));
-
- ret.instructionLen = print_insn_arc (memaddr, info);
-
-#if 0
- ret.words[0] = insn[0];
- ret.words[1] = insn[1];
- ret._this = &ret;
- ret.coreRegName = _coreRegName;
- ret.auxRegName = _auxRegName;
- ret.condCodeName = _condCodeName;
- ret.instName = _instName;
-#endif
-
- return ret;
-}
-
void
print_arc_disassembler_options (FILE *stream)
{
+ int i;
+
fprintf (stream, _("\n\
The following ARC specific disassembler options are supported for use \n\
with -M switch (multiple options should be separated by commas):\n"));
+ /* cpu=... options. */
+ for (i = 0; cpu_types[i].name; ++i)
+ {
+ /* As of now all value CPU values are less than 16 characters. */
+ fprintf (stream, " cpu=%-16s\tEnforce %s ISA.\n",
+ cpu_types[i].name, cpu_types[i].isa);
+ }
+
fprintf (stream, _("\
dsp Recognize DSP instructions.\n"));
fprintf (stream, _("\
fpus Recognize single precision FPU instructions.\n"));
fprintf (stream, _("\
fpud Recognize double precision FPU instructions.\n"));
+ fprintf (stream, _("\
+ nps400 Recognize NPS400 instructions.\n"));
+ fprintf (stream, _("\
+ hex Use only hexadecimal number to print immediates.\n"));
}
+void arc_insn_decode (bfd_vma addr,
+ struct disassemble_info *info,
+ disassembler_ftype disasm_func,
+ struct arc_instruction *insn)
+{
+ const struct arc_opcode *opcode;
+ struct arc_disassemble_info *arc_infop;
+
+ /* Ensure that insn would be in the reset state. */
+ memset (insn, 0, sizeof (struct arc_instruction));
+
+ /* There was an error when disassembling, for example memory read error. */
+ if (disasm_func (addr, info) < 0)
+ {
+ insn->valid = FALSE;
+ return;
+ }
+
+ assert (info->private_data != NULL);
+ arc_infop = info->private_data;
+
+ insn->length = arc_infop->insn_len;;
+ insn->address = addr;
+
+ /* Quick exit if memory at this address is not an instruction. */
+ if (info->insn_type == dis_noninsn)
+ {
+ insn->valid = FALSE;
+ return;
+ }
+
+ insn->valid = TRUE;
+
+ opcode = (const struct arc_opcode *) arc_infop->opcode;
+ insn->insn_class = opcode->insn_class;
+ insn->limm_value = arc_infop->limm;
+ insn->limm_p = arc_infop->limm_p;
+
+ insn->is_control_flow = (info->insn_type == dis_branch
+ || info->insn_type == dis_condbranch
+ || info->insn_type == dis_jsr
+ || info->insn_type == dis_condjsr);
+
+ insn->has_delay_slot = info->branch_delay_insns;
+ insn->writeback_mode
+ = (enum arc_ldst_writeback_mode) arc_infop->writeback_mode;
+ insn->data_size_mode = info->data_size;
+ insn->condition_code = arc_infop->condition_code;
+ memcpy (insn->operands, arc_infop->operands,
+ sizeof (struct arc_insn_operand) * MAX_INSN_ARGS);
+ insn->operands_count = arc_infop->operands_count;
+}
/* Local variables:
eval: (c-set-style "gnu")
projects / deliverable / binutils-gdb.git / blobdiff