[ARC] Update instruction type and delay slot info.

[deliverable/binutils-gdb.git] / opcodes / arc-tbl.h

diff --git a/opcodes/arc-tbl.h b/opcodes/arc-tbl.h
index c325be68727adf0271624eb2717a52ca65c2f4fc..7bda40a9c4e5f2edce2ea1c76f6e95cfd6e78187 100644 (file)
--- a/opcodes/arc-tbl.h
+++ b/opcodes/arc-tbl.h
@@ -1397,76 +1397,76 @@
 { "b", 0x00000000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM21_A16_5 }, { C_D, C_CC }},
 
 /* bbit0<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01110.  */
-{ "bbit0", 0x0801000E, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+{ "bbit0", 0x0801000E, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }},
 
 /* bbit0<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y110.  */
-{ "bbit0", 0x08010006, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
+{ "bbit0", 0x08010006, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
 
 /* bbit0<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11110.  */
-{ "bbit0", 0x0801001E, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+{ "bbit0", 0x0801001E, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
 
 /* bbit0<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y110.  */
-{ "bbit0", 0x08010016, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
+{ "bbit0", 0x08010016, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
 
 /* bbit0 b,limm,s9 00001bbbsssssss1SBBB111110001110.  */
-{ "bbit0", 0x08010F8E, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+{ "bbit0", 0x08010F8E, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
 
 /* bbit0 limm,c,s9 00001110sssssss1S111CCCCCC001110.  */
-{ "bbit0", 0x0E01700E, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+{ "bbit0", 0x0E01700E, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
 
 /* bbit0<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y110.  */
-{ "bbit0", 0x08010F86, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
+{ "bbit0", 0x08010F86, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
 
 /* bbit0<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y110.  */
-{ "bbit0", 0x0E017006, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
+{ "bbit0", 0x0E017006, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
 
 /* bbit0 limm,u6,s9 00001110sssssss1S111uuuuuu011110.  */
-{ "bbit0", 0x0E01701E, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+{ "bbit0", 0x0E01701E, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
 
 /* bbit0<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y110.  */
-{ "bbit0", 0x0E017016, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
+{ "bbit0", 0x0E017016, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
 
 /* bbit0 limm,limm,s9 00001110sssssss1S111111110001110.  */
-{ "bbit0", 0x0E017F8E, 0xFF017FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 }},
+{ "bbit0", 0x0E017F8E, 0xFF017FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 }},
 
 /* bbit0<.T> limm,limm,s9 00001110sssssss1S11111111000Y110.  */
-{ "bbit0", 0x0E017F86, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
+{ "bbit0", 0x0E017F86, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
 
 /* bbit1<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN01111.  */
-{ "bbit1", 0x0801000F, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+{ "bbit1", 0x0801000F, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }},
 
 /* bbit1<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y111.  */
-{ "bbit1", 0x08010007, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
+{ "bbit1", 0x08010007, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
 
 /* bbit1<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN11111.  */
-{ "bbit1", 0x0801001F, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+{ "bbit1", 0x0801001F, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
 
 /* bbit1<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y111.  */
-{ "bbit1", 0x08010017, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
+{ "bbit1", 0x08010017, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
 
 /* bbit1 b,limm,s9 00001bbbsssssss1SBBB111110001111.  */
-{ "bbit1", 0x08010F8F, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+{ "bbit1", 0x08010F8F, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
 
 /* bbit1 limm,c,s9 00001110sssssss1S111CCCCCC001111.  */
-{ "bbit1", 0x0E01700F, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+{ "bbit1", 0x0E01700F, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
 
 /* bbit1<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y111.  */
-{ "bbit1", 0x08010F87, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
+{ "bbit1", 0x08010F87, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
 
 /* bbit1<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y111.  */
-{ "bbit1", 0x0E017007, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
+{ "bbit1", 0x0E017007, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
 
 /* bbit1 limm,u6,s9 00001110sssssss1S111uuuuuu011111.  */
-{ "bbit1", 0x0E01701F, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+{ "bbit1", 0x0E01701F, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
 
 /* bbit1<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y111.  */
-{ "bbit1", 0x0E017017, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
+{ "bbit1", 0x0E017017, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
 
 /* bbit1 limm,limm,s9 00001110sssssss1S111111110001111.  */
-{ "bbit1", 0x0E017F8F, 0xFF017FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 }},
+{ "bbit1", 0x0E017F8F, 0xFF017FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { 0 }},
 
 /* bbit1<.T> limm,limm,s9 00001110sssssss1S11111111000Y111.  */
-{ "bbit1", 0x0E017F87, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
+{ "bbit1", 0x0E017F87, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
 
 /* bclr<.f> a,b,c 00100bbb00010000FBBBCCCCCCAAAAAA.  */
 { "bclr", 0x20100000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
@@ -1532,19 +1532,19 @@
 { "bclr_s", 0x0000B8A0, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
 
 /* beq_s s10 1111001sssssssss.  */
-{ "beq_s", 0x0000F200, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM10_A16_7_S }, { 0 }},
+{ "beq_s", 0x0000F200, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM10_A16_7_S }, { 0 }},
 
 /* bge_s s7 1111011001ssssss.  */
-{ "bge_s", 0x0000F640, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM7_A16_10_S }, { 0 }},
+{ "bge_s", 0x0000F640, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { 0 }},
 
 /* bgt_s s7 1111011000ssssss.  */
-{ "bgt_s", 0x0000F600, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM7_A16_10_S }, { 0 }},
+{ "bgt_s", 0x0000F600, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { 0 }},
 
 /* bhi_s s7 1111011100ssssss.  */
-{ "bhi_s", 0x0000F700, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM7_A16_10_S }, { 0 }},
+{ "bhi_s", 0x0000F700, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { 0 }},
 
 /* bhs_s s7 1111011101ssssss.  */
-{ "bhs_s", 0x0000F740, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM7_A16_10_S }, { 0 }},
+{ "bhs_s", 0x0000F740, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { 0 }},
 
 /* bi c 00100RRR001001000RRRCCCCCCRRRRRR.  */
 { "bi", 0x20240000, 0xF8FF8000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, CD1, { BRAKET, RC, BRAKETdup }, { 0 }},
@@ -1628,16 +1628,16 @@
 { "bl", 0x08000000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM21_A32_5 }, { C_CC, C_D }},
 
 /* ble_s s7 1111011011ssssss.  */
-{ "ble_s", 0x0000F6C0, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM7_A16_10_S }, { 0 }},
+{ "ble_s", 0x0000F6C0, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { 0 }},
 
 /* blo_s s7 1111011110ssssss.  */
-{ "blo_s", 0x0000F780, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM7_A16_10_S }, { 0 }},
+{ "blo_s", 0x0000F780, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { 0 }},
 
 /* bls_s s7 1111011111ssssss.  */
-{ "bls_s", 0x0000F7C0, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM7_A16_10_S }, { 0 }},
+{ "bls_s", 0x0000F7C0, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { 0 }},
 
 /* blt_s s7 1111011010ssssss.  */
-{ "blt_s", 0x0000F680, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM7_A16_10_S }, { 0 }},
+{ "blt_s", 0x0000F680, 0x0000FFC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM7_A16_10_S }, { 0 }},
 
 /* bl_s s13 11111sssssssssss.  */
 { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM13_A32_5_S }, { 0 }},
@@ -1766,109 +1766,109 @@
 { "bmsk_s", 0x0000B8C0, 0x0000F8E0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RB_Sdup, UIMM5_11_S }, { 0 }},
 
 /* bne_s s10 1111010sssssssss.  */
-{ "bne_s", 0x0000F400, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { SIMM10_A16_7_S }, { 0 }},
+{ "bne_s", 0x0000F400, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { SIMM10_A16_7_S }, { 0 }},
 
 /* breq<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00000.  */
-{ "breq", 0x08010000, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+{ "breq", 0x08010000, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }},
 
 /* breq<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y000.  */
-{ "breq", 0x08010000, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
+{ "breq", 0x08010000, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
 
 /* breq<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10000.  */
-{ "breq", 0x08010010, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+{ "breq", 0x08010010, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
 
 /* breq<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y000.  */
-{ "breq", 0x08010010, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
+{ "breq", 0x08010010, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
 
 /* breq b,limm,s9 00001bbbsssssss1SBBB111110000000.  */
-{ "breq", 0x08010F80, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+{ "breq", 0x08010F80, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
 
 /* breq limm,c,s9 00001110sssssss1S111CCCCCC000000.  */
-{ "breq", 0x0E017000, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+{ "breq", 0x0E017000, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
 
 /* breq<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y000.  */
-{ "breq", 0x08010F80, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
+{ "breq", 0x08010F80, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
 
 /* breq<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y000.  */
-{ "breq", 0x0E017000, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
+{ "breq", 0x0E017000, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
 
 /* breq limm,u6,s9 00001110sssssss1S111uuuuuu010000.  */
-{ "breq", 0x0E017010, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+{ "breq", 0x0E017010, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
 
 /* breq<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y000.  */
-{ "breq", 0x0E017010, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
+{ "breq", 0x0E017010, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
 
 /* breq<.T> limm,limm,s9 00001110sssssss1S11111111000Y000.  */
-{ "breq", 0x0E017F80, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
+{ "breq", 0x0E017F80, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
 
 /* breq_s b,0,s8 11101bbb0sssssss.  */
-{ "breq_s", 0x0000E800, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB_S, ZB_S, SIMM8_A16_9_S }, { 0 }},
+{ "breq_s", 0x0000E800, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB_S, ZB_S, SIMM8_A16_9_S }, { 0 }},
 
 /* brge<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00011.  */
-{ "brge", 0x08010003, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+{ "brge", 0x08010003, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }},
 
 /* brge<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y011.  */
-{ "brge", 0x08010003, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
+{ "brge", 0x08010003, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
 
 /* brge<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10011.  */
-{ "brge", 0x08010013, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+{ "brge", 0x08010013, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
 
 /* brge<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y011.  */
-{ "brge", 0x08010013, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
+{ "brge", 0x08010013, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
 
 /* brge b,limm,s9 00001bbbsssssss1SBBB111110000011.  */
-{ "brge", 0x08010F83, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+{ "brge", 0x08010F83, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
 
 /* brge limm,c,s9 00001110sssssss1S111CCCCCC000011.  */
-{ "brge", 0x0E017003, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+{ "brge", 0x0E017003, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
 
 /* brge<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y011.  */
-{ "brge", 0x08010F83, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
+{ "brge", 0x08010F83, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
 
 /* brge<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y011.  */
-{ "brge", 0x0E017003, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
+{ "brge", 0x0E017003, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
 
 /* brge limm,u6,s9 00001110sssssss1S111uuuuuu010011.  */
-{ "brge", 0x0E017013, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+{ "brge", 0x0E017013, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
 
 /* brge<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y011.  */
-{ "brge", 0x0E017013, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
+{ "brge", 0x0E017013, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
 
 /* brge<.T> limm,limm,s9 00001110sssssss1S11111111000Y011.  */
-{ "brge", 0x0E017F83, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
+{ "brge", 0x0E017F83, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
 
 /* brhs<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00101.  */
-{ "brhs", 0x08010005, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+{ "brhs", 0x08010005, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }},
 
 /* brhs<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y101.  */
-{ "brhs", 0x08010005, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
+{ "brhs", 0x08010005, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
 
 /* brhs<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10101.  */
-{ "brhs", 0x08010015, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+{ "brhs", 0x08010015, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
 
 /* brhs<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y101.  */
-{ "brhs", 0x08010015, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
+{ "brhs", 0x08010015, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
 
 /* brhs b,limm,s9 00001bbbsssssss1SBBB111110000101.  */
-{ "brhs", 0x08010F85, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+{ "brhs", 0x08010F85, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
 
 /* brhs limm,c,s9 00001110sssssss1S111CCCCCC000101.  */
-{ "brhs", 0x0E017005, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+{ "brhs", 0x0E017005, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
 
 /* brhs<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y101.  */
-{ "brhs", 0x08010F85, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
+{ "brhs", 0x08010F85, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
 
 /* brhs<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y101.  */
-{ "brhs", 0x0E017005, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
+{ "brhs", 0x0E017005, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
 
 /* brhs limm,u6,s9 00001110sssssss1S111uuuuuu010101.  */
-{ "brhs", 0x0E017015, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+{ "brhs", 0x0E017015, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
 
 /* brhs<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y101.  */
-{ "brhs", 0x0E017015, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
+{ "brhs", 0x0E017015, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
 
 /* brhs<.T> limm,limm,s9 00001110sssssss1S11111111000Y101.  */
-{ "brhs", 0x0E017F85, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
+{ "brhs", 0x0E017F85, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
 
 /* brk  00100101011011110000000000111111.  */
 { "brk", 0x256F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
@@ -1877,106 +1877,106 @@
 { "brk_s", 0x00007FFF, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
 
 /* brlo<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00100.  */
-{ "brlo", 0x08010004, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+{ "brlo", 0x08010004, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }},
 
 /* brlo<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y100.  */
-{ "brlo", 0x08010004, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
+{ "brlo", 0x08010004, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
 
 /* brlo<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10100.  */
-{ "brlo", 0x08010014, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+{ "brlo", 0x08010014, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
 
 /* brlo<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y100.  */
-{ "brlo", 0x08010014, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
+{ "brlo", 0x08010014, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
 
 /* brlo b,limm,s9 00001bbbsssssss1SBBB111110000100.  */
-{ "brlo", 0x08010F84, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+{ "brlo", 0x08010F84, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
 
 /* brlo limm,c,s9 00001110sssssss1S111CCCCCC000100.  */
-{ "brlo", 0x0E017004, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+{ "brlo", 0x0E017004, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
 
 /* brlo<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y100.  */
-{ "brlo", 0x08010F84, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
+{ "brlo", 0x08010F84, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
 
 /* brlo<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y100.  */
-{ "brlo", 0x0E017004, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
+{ "brlo", 0x0E017004, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
 
 /* brlo limm,u6,s9 00001110sssssss1S111uuuuuu010100.  */
-{ "brlo", 0x0E017014, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+{ "brlo", 0x0E017014, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
 
 /* brlo<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y100.  */
-{ "brlo", 0x0E017014, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
+{ "brlo", 0x0E017014, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
 
 /* brlo<.T> limm,limm,s9 00001110sssssss1S11111111000Y100.  */
-{ "brlo", 0x0E017F84, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
+{ "brlo", 0x0E017F84, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
 
 /* brlt<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00010.  */
-{ "brlt", 0x08010002, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+{ "brlt", 0x08010002, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }},
 
 /* brlt<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y010.  */
-{ "brlt", 0x08010002, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
+{ "brlt", 0x08010002, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
 
 /* brlt<.d> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN10010.  */
-{ "brlt", 0x08010012, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+{ "brlt", 0x08010012, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
 
 /* brlt<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y010.  */
-{ "brlt", 0x08010012, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
+{ "brlt", 0x08010012, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
 
 /* brlt b,limm,s9 00001bbbsssssss1SBBB111110000010.  */
-{ "brlt", 0x08010F82, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+{ "brlt", 0x08010F82, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
 
 /* brlt limm,c,s9 00001110sssssss1S111CCCCCC000010.  */
-{ "brlt", 0x0E017002, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+{ "brlt", 0x0E017002, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
 
 /* brlt<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y010.  */
-{ "brlt", 0x08010F82, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
+{ "brlt", 0x08010F82, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
 
 /* brlt<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y010.  */
-{ "brlt", 0x0E017002, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
+{ "brlt", 0x0E017002, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
 
 /* brlt limm,u6,s9 00001110sssssss1S111uuuuuu010010.  */
-{ "brlt", 0x0E017012, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+{ "brlt", 0x0E017012, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
 
 /* brlt<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y010.  */
-{ "brlt", 0x0E017012, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
+{ "brlt", 0x0E017012, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
 
 /* brlt<.T> limm,limm,s9 00001110sssssss1S11111111000Y010.  */
-{ "brlt", 0x0E017F82, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
+{ "brlt", 0x0E017F82, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
 
 /* brne<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00001.  */
-{ "brne", 0x08010001, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
+{ "brne", 0x08010001, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D }},
 
 /* brne<.d><.T> b,c,s9 00001bbbsssssss1SBBBCCCCCCN0Y001.  */
-{ "brne", 0x08010001, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
+{ "brne", 0x08010001, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, RC, SIMM9_A16_8 }, { C_D, C_T }},
 
 /* brne<.d> b,u6,s9 00001bbbsssssss1SBBBUUUUUUN10001.  */
-{ "brne", 0x08010011, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
+{ "brne", 0x08010011, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D }},
 
 /* brne<.d><.T> b,u6,s9 00001bbbsssssss1SBBBuuuuuuN1Y001.  */
-{ "brne", 0x08010011, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
+{ "brne", 0x08010011, 0xF8010017, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, UIMM6_8, SIMM9_A16_8 }, { C_D, C_T }},
 
 /* brne b,limm,s9 00001bbbsssssss1SBBB111110000001.  */
-{ "brne", 0x08010F81, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
+{ "brne", 0x08010F81, 0xF8010FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { 0 }},
 
 /* brne limm,c,s9 00001110sssssss1S111CCCCCC000001.  */
-{ "brne", 0x0E017001, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
+{ "brne", 0x0E017001, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { 0 }},
 
 /* brne<.T> b,limm,s9 00001bbbsssssss1SBBB11111000Y001.  */
-{ "brne", 0x08010F81, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
+{ "brne", 0x08010F81, 0xF8010FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB, LIMM, SIMM9_A16_8 }, { C_T }},
 
 /* brne<.T> limm,c,s9 00001110sssssss1S111CCCCCC00Y001.  */
-{ "brne", 0x0E017001, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
+{ "brne", 0x0E017001, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, RC, SIMM9_A16_8 }, { C_T }},
 
 /* brne limm,u6,s9 00001110sssssss1S111uuuuuu010001.  */
-{ "brne", 0x0E017011, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
+{ "brne", 0x0E017011, 0xFF01703F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { 0 }},
 
 /* brne<.T> limm,u6,s9 00001110sssssss1S111uuuuuu01Y001.  */
-{ "brne", 0x0E017011, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
+{ "brne", 0x0E017011, 0xFF017037, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, UIMM6_8, SIMM9_A16_8 }, { C_T }},
 
 /* brne<.T> limm,limm,s9 00001110sssssss1S11111111000Y001.  */
-{ "brne", 0x0E017F81, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
+{ "brne", 0x0E017F81, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
 
 /* brne_s b,0,s8 11101bbb1sssssss.  */
-{ "brne_s", 0x0000E880, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { RB_S, ZB_S, SIMM8_A16_9_S }, { 0 }},
+{ "brne_s", 0x0000E880, 0x0000F880, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, COND, { RB_S, ZB_S, SIMM8_A16_9_S }, { 0 }},
 
 /* bset<.f> a,b,c 00100bbb00001111FBBBCCCCCCAAAAAA.  */
 { "bset", 0x200F0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RA, RB, RC }, { C_F }},
@@ -7965,10 +7965,10 @@
 { "j", 0x20E00F80, 0xF8FF0FE0, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { LIMM }, { C_CC }},
 
 /* jeq_s BLINK 0111110011100000.  */
-{ "jeq_s", 0x00007CE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, BLINK_S, BRAKETdup }, { 0 }},
+{ "jeq_s", 0x00007CE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, COND, { BRAKET, BLINK_S, BRAKETdup }, { 0 }},
 
 /* jeq_s BLINK 0111110011100000.  */
-{ "jeq_s", 0x00007CE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, BLINK_S, BRAKETdup }, { 0 }},
+{ "jeq_s", 0x00007CE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, COND, { BRAKET, BLINK_S, BRAKETdup }, { 0 }},
 
 /* jl c 00100RRR001000100RRRCCCCCCRRRRRR.  */
 { "jl", 0x20220000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { 0 }},
@@ -8058,10 +8058,10 @@
 { "jl_s", 0x00007860, 0x0000F8FF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { C_DHARD }},
 
 /* jne_s BLINK 0111110111100000.  */
-{ "jne_s", 0x00007DE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, BLINK_S, BRAKETdup }, { 0 }},
+{ "jne_s", 0x00007DE0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, COND, { BRAKET, BLINK_S, BRAKETdup }, { 0 }},
 
 /* jne_s BLINK 0111110111100000.  */
-{ "jne_s", 0x00007DE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, NONE, { BRAKET, BLINK_S, BRAKETdup }, { 0 }},
+{ "jne_s", 0x00007DE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, COND, { BRAKET, BLINK_S, BRAKETdup }, { 0 }},
 
 /* j_s b 01111bbb00000000.  */
 { "j_s", 0x00007800, 0x0000F8FF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RB_S, BRAKETdup }, { 0 }},