+/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
/* CPU data for frv.
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996-2005 Free Software Foundation, Inc.
+Copyright (C) 1996-2021 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
{ "dbmr31", 2089, {0, {{{0, 0}}}}, 0, 0 },
{ "dbmr32", 2090, {0, {{{0, 0}}}}, 0, 0 },
{ "dbmr33", 2091, {0, {{{0, 0}}}}, 0, 0 },
- { "cpcfr", 2092, {0, {{{0, 0}}}}, 0, 0 },
- { "cpcr", 2093, {0, {{{0, 0}}}}, 0, 0 },
- { "cpsr", 2094, {0, {{{0, 0}}}}, 0, 0 },
- { "cpesr0", 2096, {0, {{{0, 0}}}}, 0, 0 },
- { "cpesr1", 2097, {0, {{{0, 0}}}}, 0, 0 },
- { "cpemr0", 2098, {0, {{{0, 0}}}}, 0, 0 },
- { "cpemr1", 2099, {0, {{{0, 0}}}}, 0, 0 },
- { "ihsr8", 3848, {0, {{{0, 0}}}}, 0, 0 }
+ { "cpcfr", 2304, {0, {{{0, 0}}}}, 0, 0 },
+ { "cpcr", 2305, {0, {{{0, 0}}}}, 0, 0 },
+ { "cpsr", 2306, {0, {{{0, 0}}}}, 0, 0 },
+ { "cptr", 2307, {0, {{{0, 0}}}}, 0, 0 },
+ { "cphsr0", 2308, {0, {{{0, 0}}}}, 0, 0 },
+ { "cphsr1", 2309, {0, {{{0, 0}}}}, 0, 0 },
+ { "cpesr0", 2320, {0, {{{0, 0}}}}, 0, 0 },
+ { "cpesr1", 2321, {0, {{{0, 0}}}}, 0, 0 },
+ { "cpemr0", 2322, {0, {{{0, 0}}}}, 0, 0 },
+ { "cpemr1", 2323, {0, {{{0, 0}}}}, 0, 0 },
+ { "iperr0", 2324, {0, {{{0, 0}}}}, 0, 0 },
+ { "iperr1", 2325, {0, {{{0, 0}}}}, 0, 0 },
+ { "ipjsr", 2326, {0, {{{0, 0}}}}, 0, 0 },
+ { "ipjrr", 2327, {0, {{{0, 0}}}}, 0, 0 },
+ { "ipcsr0", 2336, {0, {{{0, 0}}}}, 0, 0 },
+ { "ipcsr1", 2337, {0, {{{0, 0}}}}, 0, 0 },
+ { "ipcwer0", 2338, {0, {{{0, 0}}}}, 0, 0 },
+ { "ipcwer1", 2339, {0, {{{0, 0}}}}, 0, 0 },
+ { "ipcwr", 2340, {0, {{{0, 0}}}}, 0, 0 },
+ { "mbhsr", 2352, {0, {{{0, 0}}}}, 0, 0 },
+ { "mbssr", 2353, {0, {{{0, 0}}}}, 0, 0 },
+ { "mbrsr", 2354, {0, {{{0, 0}}}}, 0, 0 },
+ { "mbsdr", 2355, {0, {{{0, 0}}}}, 0, 0 },
+ { "mbrdr", 2356, {0, {{{0, 0}}}}, 0, 0 },
+ { "mbsmr", 2357, {0, {{{0, 0}}}}, 0, 0 },
+ { "mbstr0", 2359, {0, {{{0, 0}}}}, 0, 0 },
+ { "mbstr1", 2360, {0, {{{0, 0}}}}, 0, 0 },
+ { "slpr", 2368, {0, {{{0, 0}}}}, 0, 0 },
+ { "sldr", 2369, {0, {{{0, 0}}}}, 0, 0 },
+ { "slhsr", 2370, {0, {{{0, 0}}}}, 0, 0 },
+ { "sltr", 2371, {0, {{{0, 0}}}}, 0, 0 },
+ { "slwr", 2372, {0, {{{0, 0}}}}, 0, 0 },
+ { "ihsr8", 3848, {0, {{{0, 0}}}}, 0, 0 },
+ { "ihsr9", 3849, {0, {{{0, 0}}}}, 0, 0 },
+ { "ihsr10", 3850, {0, {{{0, 0}}}}, 0, 0 }
};
CGEN_KEYWORD frv_cgen_opval_spr_names =
{
& frv_cgen_opval_spr_names_entries[0],
- 1022,
+ 1049,
0, 0, 0, 0, ""
};
/* The hardware table. */
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_HW_##a)
-#else
-#define A(a) (1 << CGEN_HW_/**/a)
-#endif
const CGEN_HW_ENTRY frv_cgen_hw_table[] =
{
/* The instruction field table. */
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_IFLD_##a)
-#else
-#define A(a) (1 << CGEN_IFLD_/**/a)
-#endif
const CGEN_IFLD frv_cgen_ifld_table[] =
{
/* The operand table. */
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_OPERAND_##a)
-#else
-#define A(a) (1 << CGEN_OPERAND_/**/a)
-#endif
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define OPERAND(op) FRV_OPERAND_##op
-#else
-#define OPERAND(op) FRV_OPERAND_/**/op
-#endif
const CGEN_OPERAND frv_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", FRV_OPERAND_PC, HW_H_PC, 0, 0,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_NIL] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* pack: packing bit */
{ "pack", FRV_OPERAND_PACK, HW_H_PACK, 31, 1,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_PACK] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_PACK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* GRi: source register 1 */
{ "GRi", FRV_OPERAND_GRI, HW_H_GR, 17, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRI] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* GRj: source register 2 */
{ "GRj", FRV_OPERAND_GRJ, HW_H_GR, 5, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRJ] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* GRk: destination register */
{ "GRk", FRV_OPERAND_GRK, HW_H_GR, 30, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* GRkhi: destination register */
{ "GRkhi", FRV_OPERAND_GRKHI, HW_H_GR_HI, 30, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* GRklo: destination register */
{ "GRklo", FRV_OPERAND_GRKLO, HW_H_GR_LO, 30, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* GRdoublek: destination register */
{ "GRdoublek", FRV_OPERAND_GRDOUBLEK, HW_H_GR_DOUBLE, 30, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ACC40Si: signed accumulator */
{ "ACC40Si", FRV_OPERAND_ACC40SI, HW_H_ACC40S, 17, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SI] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ACC40Ui: unsigned accumulator */
{ "ACC40Ui", FRV_OPERAND_ACC40UI, HW_H_ACC40U, 17, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UI] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ACC40Sk: target accumulator */
{ "ACC40Sk", FRV_OPERAND_ACC40SK, HW_H_ACC40S, 30, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SK] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ACC40Uk: target accumulator */
{ "ACC40Uk", FRV_OPERAND_ACC40UK, HW_H_ACC40U, 30, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UK] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ACCGi: source register */
{ "ACCGi", FRV_OPERAND_ACCGI, HW_H_ACCG, 17, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGI] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ACCGk: target register */
{ "ACCGk", FRV_OPERAND_ACCGK, HW_H_ACCG, 30, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGK] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CPRi: source register */
{ "CPRi", FRV_OPERAND_CPRI, HW_H_CPR, 17, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRI] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRI] } },
{ 0, { { { (1<<MACH_FRV), 0 } } } } },
/* CPRj: source register */
{ "CPRj", FRV_OPERAND_CPRJ, HW_H_CPR, 5, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRJ] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRJ] } },
{ 0, { { { (1<<MACH_FRV), 0 } } } } },
/* CPRk: destination register */
{ "CPRk", FRV_OPERAND_CPRK, HW_H_CPR, 30, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } },
{ 0, { { { (1<<MACH_FRV), 0 } } } } },
/* CPRdoublek: destination register */
{ "CPRdoublek", FRV_OPERAND_CPRDOUBLEK, HW_H_CPR_DOUBLE, 30, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } },
{ 0, { { { (1<<MACH_FRV), 0 } } } } },
/* FRinti: source register 1 */
{ "FRinti", FRV_OPERAND_FRINTI, HW_H_FR_INT, 17, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRintj: source register 2 */
{ "FRintj", FRV_OPERAND_FRINTJ, HW_H_FR_INT, 5, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRintk: target register */
{ "FRintk", FRV_OPERAND_FRINTK, HW_H_FR_INT, 30, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRi: source register 1 */
{ "FRi", FRV_OPERAND_FRI, HW_H_FR, 17, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRj: source register 2 */
{ "FRj", FRV_OPERAND_FRJ, HW_H_FR, 5, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRk: destination register */
{ "FRk", FRV_OPERAND_FRK, HW_H_FR, 30, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRkhi: destination register */
{ "FRkhi", FRV_OPERAND_FRKHI, HW_H_FR_HI, 30, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRklo: destination register */
{ "FRklo", FRV_OPERAND_FRKLO, HW_H_FR_LO, 30, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRdoublei: source register 1 */
{ "FRdoublei", FRV_OPERAND_FRDOUBLEI, HW_H_FR_DOUBLE, 17, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRdoublej: source register 2 */
{ "FRdoublej", FRV_OPERAND_FRDOUBLEJ, HW_H_FR_DOUBLE, 5, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRdoublek: target register */
{ "FRdoublek", FRV_OPERAND_FRDOUBLEK, HW_H_FR_DOUBLE, 30, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CRi: source register 1 */
{ "CRi", FRV_OPERAND_CRI, HW_H_CCCR, 14, 3,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRI] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CRj: source register 2 */
{ "CRj", FRV_OPERAND_CRJ, HW_H_CCCR, 2, 3,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CRj_int: destination register */
{ "CRj_int", FRV_OPERAND_CRJ_INT, HW_H_CCCR, 26, 2,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_INT] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_INT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CRj_float: destination register */
{ "CRj_float", FRV_OPERAND_CRJ_FLOAT, HW_H_CCCR, 26, 2,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_FLOAT] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_FLOAT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CRk: destination register */
{ "CRk", FRV_OPERAND_CRK, HW_H_CCCR, 27, 3,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRK] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* CCi: condition register */
{ "CCi", FRV_OPERAND_CCI, HW_H_CCCR, 11, 3,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCI] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ICCi_1: condition register */
{ "ICCi_1", FRV_OPERAND_ICCI_1, HW_H_ICCR, 11, 2,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_1] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ICCi_2: condition register */
{ "ICCi_2", FRV_OPERAND_ICCI_2, HW_H_ICCR, 26, 2,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_2] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* ICCi_3: condition register */
{ "ICCi_3", FRV_OPERAND_ICCI_3, HW_H_ICCR, 1, 2,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_3] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_3] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FCCi_1: condition register */
{ "FCCi_1", FRV_OPERAND_FCCI_1, HW_H_FCCR, 11, 2,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_1] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FCCi_2: condition register */
{ "FCCi_2", FRV_OPERAND_FCCI_2, HW_H_FCCR, 26, 2,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_2] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FCCi_3: condition register */
{ "FCCi_3", FRV_OPERAND_FCCI_3, HW_H_FCCR, 1, 2,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_3] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_3] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FCCk: condition register */
{ "FCCk", FRV_OPERAND_FCCK, HW_H_FCCR, 26, 2,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCK] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* eir: exception insn reg */
{ "eir", FRV_OPERAND_EIR, HW_H_UINT, 17, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_EIR] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_EIR] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* s10: 10 bit signed immediate */
{ "s10", FRV_OPERAND_S10, HW_H_SINT, 9, 10,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S10] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S10] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* u16: 16 bit unsigned immediate */
{ "u16", FRV_OPERAND_U16, HW_H_UINT, 15, 16,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* s16: 16 bit signed immediate */
{ "s16", FRV_OPERAND_S16, HW_H_SINT, 15, 16,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* s6: 6 bit signed immediate */
{ "s6", FRV_OPERAND_S6, HW_H_SINT, 5, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* s6_1: 6 bit signed immediate */
{ "s6_1", FRV_OPERAND_S6_1, HW_H_SINT, 11, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6_1] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6_1] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* u6: 6 bit unsigned immediate */
{ "u6", FRV_OPERAND_U6, HW_H_UINT, 5, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U6] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U6] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* s5: 5 bit signed immediate */
{ "s5", FRV_OPERAND_S5, HW_H_SINT, 4, 5,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S5] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S5] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* cond: conditional arithmetic */
{ "cond", FRV_OPERAND_COND, HW_H_UINT, 8, 1,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_COND] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_COND] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* ccond: lr branch condition */
{ "ccond", FRV_OPERAND_CCOND, HW_H_UINT, 12, 1,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCOND] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCOND] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* hint: 2 bit branch predictor */
{ "hint", FRV_OPERAND_HINT, HW_H_UINT, 17, 2,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* hint_taken: 2 bit branch predictor */
{ "hint_taken", FRV_OPERAND_HINT_TAKEN, HW_H_HINT_TAKEN, 17, 2,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* hint_not_taken: 2 bit branch predictor */
{ "hint_not_taken", FRV_OPERAND_HINT_NOT_TAKEN, HW_H_HINT_NOT_TAKEN, 17, 2,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* LI: link indicator */
{ "LI", FRV_OPERAND_LI, HW_H_UINT, 25, 1,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LI] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* lock: cache lock indicator */
{ "lock", FRV_OPERAND_LOCK, HW_H_UINT, 25, 1,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LOCK] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LOCK] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* debug: debug mode indicator */
{ "debug", FRV_OPERAND_DEBUG, HW_H_UINT, 25, 1,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_DEBUG] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_DEBUG] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* ae: all entries indicator */
{ "ae", FRV_OPERAND_AE, HW_H_UINT, 25, 1,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_AE] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_AE] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* label16: 18 bit pc relative address */
{ "label16", FRV_OPERAND_LABEL16, HW_H_IADDR, 15, 16,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LABEL16] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LABEL16] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* LRAE: Load Real Address E flag */
{ "LRAE", FRV_OPERAND_LRAE, HW_H_UINT, 5, 1,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAE] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAE] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* LRAD: Load Real Address D flag */
{ "LRAD", FRV_OPERAND_LRAD, HW_H_UINT, 4, 1,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAD] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAD] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* LRAS: Load Real Address S flag */
{ "LRAS", FRV_OPERAND_LRAS, HW_H_UINT, 3, 1,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAS] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAS] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* TLBPRopx: TLB Probe operation number */
{ "TLBPRopx", FRV_OPERAND_TLBPROPX, HW_H_UINT, 28, 3,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_TLBPROPX] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_TLBPROPX] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* TLBPRL: TLB Probe L flag */
{ "TLBPRL", FRV_OPERAND_TLBPRL, HW_H_UINT, 25, 1,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_TLBPRL] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_TLBPRL] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* A0: A==0 operand of mclracc */
{ "A0", FRV_OPERAND_A0, HW_H_UINT, 17, 1,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* A1: A==1 operand of mclracc */
{ "A1", FRV_OPERAND_A1, HW_H_UINT, 17, 1,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRintieven: (even) source register 1 */
{ "FRintieven", FRV_OPERAND_FRINTIEVEN, HW_H_FR_INT, 17, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRintjeven: (even) source register 2 */
{ "FRintjeven", FRV_OPERAND_FRINTJEVEN, HW_H_FR_INT, 5, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* FRintkeven: (even) target register */
{ "FRintkeven", FRV_OPERAND_FRINTKEVEN, HW_H_FR_INT, 30, 6,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* d12: 12 bit signed immediate */
{ "d12", FRV_OPERAND_D12, HW_H_SINT, 11, 12,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* s12: 12 bit signed immediate */
{ "s12", FRV_OPERAND_S12, HW_H_SINT, 11, 12,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } },
{ 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } } },
/* u12: 12 bit signed immediate */
{ "u12", FRV_OPERAND_U12, HW_H_SINT, 5, 12,
- { 2, { (const PTR) &FRV_F_U12_MULTI_IFIELD[0] } },
+ { 2, { (const PTR) &FRV_F_U12_MULTI_IFIELD[0] } },
{ 0|A(HASH_PREFIX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* spr: special purpose register */
{ "spr", FRV_OPERAND_SPR, HW_H_SPR, 17, 12,
- { 2, { (const PTR) &FRV_F_SPR_MULTI_IFIELD[0] } },
+ { 2, { (const PTR) &FRV_F_SPR_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* ulo16: 16 bit unsigned immediate, for #lo() */
{ "ulo16", FRV_OPERAND_ULO16, HW_H_UINT, 15, 16,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* slo16: 16 bit unsigned immediate, for #lo() */
{ "slo16", FRV_OPERAND_SLO16, HW_H_SINT, 15, 16,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* uhi16: 16 bit unsigned immediate, for #hi() */
{ "uhi16", FRV_OPERAND_UHI16, HW_H_UINT, 15, 16,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* label24: 26 bit pc relative address */
{ "label24", FRV_OPERAND_LABEL24, HW_H_IADDR, 17, 24,
- { 2, { (const PTR) &FRV_F_LABEL24_MULTI_IFIELD[0] } },
+ { 2, { (const PTR) &FRV_F_LABEL24_MULTI_IFIELD[0] } },
{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* psr_esr: PSR.ESR bit */
{ "psr_esr", FRV_OPERAND_PSR_ESR, HW_H_PSR_ESR, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* psr_s: PSR.S bit */
{ "psr_s", FRV_OPERAND_PSR_S, HW_H_PSR_S, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* psr_ps: PSR.PS bit */
{ "psr_ps", FRV_OPERAND_PSR_PS, HW_H_PSR_PS, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* psr_et: PSR.ET bit */
{ "psr_et", FRV_OPERAND_PSR_ET, HW_H_PSR_ET, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bpsr_bs: BPSR.BS bit */
{ "bpsr_bs", FRV_OPERAND_BPSR_BS, HW_H_BPSR_BS, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* bpsr_bet: BPSR.BET bit */
{ "bpsr_bet", FRV_OPERAND_BPSR_BET, HW_H_BPSR_BET, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* tbr_tba: TBR.TBA */
{ "tbr_tba", FRV_OPERAND_TBR_TBA, HW_H_TBR_TBA, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* tbr_tt: TBR.TT */
{ "tbr_tt", FRV_OPERAND_TBR_TT, HW_H_TBR_TT, 0, 0,
- { 0, { (const PTR) 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* ldann: ld annotation */
{ "ldann", FRV_OPERAND_LDANN, HW_H_RELOC_ANN, 0, 0,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* lddann: ldd annotation */
{ "lddann", FRV_OPERAND_LDDANN, HW_H_RELOC_ANN, 0, 0,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* callann: call annotation */
{ "callann", FRV_OPERAND_CALLANN, HW_H_RELOC_ANN, 0, 0,
- { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } },
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_RELOC_ANN] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
/* The instruction table. */
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_INSN_##a)
-#else
-#define A(a) (1 << CGEN_INSN_/**/a)
-#endif
static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
{
{
}
+#ifndef opcodes_error_handler
+#define opcodes_error_handler(...) \
+ fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr)
+#endif
+
static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
static void build_hw_table (CGEN_CPU_TABLE *);
static void build_ifield_table (CGEN_CPU_TABLE *);
return table;
++table;
}
- abort ();
+ return NULL;
}
/* Subroutine of frv_cgen_cpu_open to build the hardware table. */
{
if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
{
- fprintf (stderr, "frv_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
- cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
+ opcodes_error_handler
+ (/* xgettext:c-format */
+ _("internal error: frv_cgen_rebuild_tables: "
+ "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"),
+ cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
abort ();
}
CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
CGEN_CPU_OPEN_ENDIAN: specify endian choice
+ CGEN_CPU_OPEN_INSN_ENDIAN: specify instruction endian choice
CGEN_CPU_OPEN_END: terminates arguments
??? Simultaneous multiple isas might not make sense, but it's not (yet)
- precluded.
-
- ??? We only support ISO C stdargs here, not K&R.
- Laziness, plus experiment to see if anything requires K&R - eventually
- K&R will no longer be supported - e.g. GDB is currently trying this. */
+ precluded. */
CGEN_CPU_DESC
frv_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
CGEN_BITSET *isas = 0; /* 0 = "unspecified" */
unsigned int machs = 0; /* 0 = "unspecified" */
enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
+ enum cgen_endian insn_endian = CGEN_ENDIAN_UNKNOWN;
va_list ap;
if (! init_p)
const CGEN_MACH *mach =
lookup_mach_via_bfd_name (frv_cgen_mach_table, name);
- machs |= 1 << mach->num;
+ if (mach != NULL)
+ machs |= 1 << mach->num;
break;
}
case CGEN_CPU_OPEN_ENDIAN :
endian = va_arg (ap, enum cgen_endian);
break;
+ case CGEN_CPU_OPEN_INSN_ENDIAN :
+ insn_endian = va_arg (ap, enum cgen_endian);
+ break;
default :
- fprintf (stderr, "frv_cgen_cpu_open: unsupported argument `%d'\n",
- arg_type);
+ opcodes_error_handler
+ (/* xgettext:c-format */
+ _("internal error: frv_cgen_cpu_open: "
+ "unsupported argument `%d'"),
+ arg_type);
abort (); /* ??? return NULL? */
}
arg_type = va_arg (ap, enum cgen_cpu_open_arg);
if (endian == CGEN_ENDIAN_UNKNOWN)
{
/* ??? If target has only one, could have a default. */
- fprintf (stderr, "frv_cgen_cpu_open: no endianness specified\n");
+ opcodes_error_handler
+ (/* xgettext:c-format */
+ _("internal error: frv_cgen_cpu_open: no endianness specified"));
abort ();
}
cd->isas = cgen_bitset_copy (isas);
cd->machs = machs;
cd->endian = endian;
- /* FIXME: for the sparc case we can determine insn-endianness statically.
- The worry here is where both data and insn endian can be independently
- chosen, in which case this function will need another argument.
- Actually, will want to allow for more arguments in the future anyway. */
- cd->insn_endian = endian;
+ cd->insn_endian
+ = (insn_endian == CGEN_ENDIAN_UNKNOWN ? endian : insn_endian);
/* Table (re)builder. */
cd->rebuild_tables = frv_cgen_rebuild_tables;
/* Default to not allowing signed overflow. */
cd->signed_overflow_ok_p = 0;
-
+
return (CGEN_CPU_DESC) cd;
}
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
- }
-
- if (cd->macro_insn_table.init_entries)
- free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
-
- if (cd->insn_table.init_entries)
- free ((CGEN_INSN *) cd->insn_table.init_entries);
-
- if (cd->hw_table.entries)
- free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
-
- if (cd->operand_table.entries)
- free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
+ }
+ free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+ free ((CGEN_INSN *) cd->insn_table.init_entries);
+ free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
+ free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
free (cd);
}
projects / deliverable / binutils-gdb.git / blobdiff