#include "opintl.h"
#include "opcode/i386.h"
#include "libiberty.h"
+#include "safe-ctype.h"
#include <setjmp.h>
static void OP_XS (int, int);
static void OP_M (int, int);
static void OP_VEX (int, int);
+static void OP_VexW (int, int);
static void OP_EX_Vex (int, int);
-static void OP_EX_VexW (int, int);
-static void OP_EX_VexImmW (int, int);
static void OP_XMM_Vex (int, int);
-static void OP_XMM_VexW (int, int);
static void OP_Rounding (int, int);
static void OP_REG_VexI4 (int, int);
+static void OP_VexI4 (int, int);
static void PCLMUL_Fixup (int, int);
static void VCMP_Fixup (int, int);
static void VPCMP_Fixup (int, int);
static void PCMPESTR_Fixup (int, int);
static void OP_LWPCB_E (int, int);
static void OP_LWP_E (int, int);
-static void OP_Vex_2src_1 (int, int);
-static void OP_Vex_2src_2 (int, int);
static void MOVBE_Fixup (int, int);
static void MOVSXD_Fixup (int, int);
static int rex;
/* Bits of REX we've already used. */
static int rex_used;
-/* REX bits in original REX prefix ignored. */
-static int rex_ignored;
/* Mark parts used in the REX prefix. When we are testing for
empty prefix (for 8bit register REX extension), just mask it
out. Otherwise test for REX bit is excuse for existence of REX
#define EXw { OP_EX, w_mode }
#define EXwScalar { OP_EX, w_scalar_mode }
#define EXd { OP_EX, d_mode }
-#define EXdScalar { OP_EX, d_scalar_mode }
#define EXdS { OP_EX, d_swap_mode }
#define EXq { OP_EX, q_mode }
-#define EXqScalar { OP_EX, q_scalar_mode }
-#define EXqScalarS { OP_EX, q_scalar_swap_mode }
#define EXqS { OP_EX, q_swap_mode }
#define EXx { OP_EX, x_mode }
#define EXxS { OP_EX, x_swap_mode }
#define CMP { CMP_Fixup, 0 }
#define XMM0 { XMM_Fixup, 0 }
#define FXSAVE { FXSAVE_Fixup, 0 }
-#define Vex_2src_1 { OP_Vex_2src_1, 0 }
-#define Vex_2src_2 { OP_Vex_2src_2, 0 }
#define Vex { OP_VEX, vex_mode }
+#define VexW { OP_VexW, vex_mode }
#define VexScalar { OP_VEX, vex_scalar_mode }
#define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
#define Vex128 { OP_VEX, vex128_mode }
#define VexGdq { OP_VEX, dq_mode }
#define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
#define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
-#define EXVexW { OP_EX_VexW, x_mode }
-#define EXdVexW { OP_EX_VexW, d_mode }
-#define EXqVexW { OP_EX_VexW, q_mode }
-#define EXVexImmW { OP_EX_VexImmW, x_mode }
#define XMVexScalar { OP_XMM_Vex, scalar_mode }
-#define XMVexW { OP_XMM_VexW, 0 }
#define XMVexI4 { OP_REG_VexI4, x_mode }
+#define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
+#define VexI4 { OP_VexI4, 0 }
#define PCLMUL { PCLMUL_Fixup, 0 }
#define VCMP { VCMP_Fixup, 0 }
#define VPCMP { VPCMP_Fixup, 0 }
b_scalar_mode,
/* like w_mode, ignore vector length. */
w_scalar_mode,
- /* like d_mode, ignore vector length. */
- d_scalar_mode,
/* like d_swap_mode, ignore vector length. */
d_scalar_swap_mode,
- /* like q_mode, ignore vector length. */
- q_scalar_mode,
/* like q_swap_mode, ignore vector length. */
q_scalar_swap_mode,
/* like vex_mode, ignore vector length. */
MOD_0F01_REG_5,
MOD_0F01_REG_7,
MOD_0F12_PREFIX_0,
+ MOD_0F12_PREFIX_2,
MOD_0F13,
MOD_0F16_PREFIX_0,
+ MOD_0F16_PREFIX_2,
MOD_0F17,
MOD_0F18_REG_0,
MOD_0F18_REG_1,
MOD_0F2B_PREFIX_1,
MOD_0F2B_PREFIX_2,
MOD_0F2B_PREFIX_3,
- MOD_0F51,
+ MOD_0F50,
MOD_0F71_REG_2,
MOD_0F71_REG_4,
MOD_0F71_REG_6,
MOD_C4_32BIT,
MOD_C5_32BIT,
MOD_VEX_0F12_PREFIX_0,
+ MOD_VEX_0F12_PREFIX_2,
MOD_VEX_0F13,
MOD_VEX_0F16_PREFIX_0,
+ MOD_VEX_0F16_PREFIX_2,
MOD_VEX_0F17,
MOD_VEX_0F2B,
MOD_VEX_W_0_0F41_P_0_LEN_1,
MOD_VEX_W_1_0F3A33_P_2_LEN_0,
MOD_EVEX_0F12_PREFIX_0,
+ MOD_EVEX_0F12_PREFIX_2,
+ MOD_EVEX_0F13,
MOD_EVEX_0F16_PREFIX_0,
+ MOD_EVEX_0F16_PREFIX_2,
+ MOD_EVEX_0F17,
+ MOD_EVEX_0F2B,
+ MOD_EVEX_0F381A_P_2_W_0,
+ MOD_EVEX_0F381A_P_2_W_1,
+ MOD_EVEX_0F381B_P_2_W_0,
+ MOD_EVEX_0F381B_P_2_W_1,
+ MOD_EVEX_0F385A_P_2_W_0,
+ MOD_EVEX_0F385A_P_2_W_1,
+ MOD_EVEX_0F385B_P_2_W_0,
+ MOD_EVEX_0F385B_P_2_W_1,
MOD_EVEX_0F38C6_REG_1,
MOD_EVEX_0F38C6_REG_2,
MOD_EVEX_0F38C6_REG_5,
enum
{
PREFIX_90 = 0,
+ PREFIX_0F01_REG_3_RM_1,
PREFIX_0F01_REG_5_MOD_0,
PREFIX_0F01_REG_5_MOD_3_RM_0,
+ PREFIX_0F01_REG_5_MOD_3_RM_1,
PREFIX_0F01_REG_5_MOD_3_RM_2,
PREFIX_0F01_REG_7_MOD_3_RM_2,
PREFIX_0F01_REG_7_MOD_3_RM_3,
PREFIX_EVEX_0F10,
PREFIX_EVEX_0F11,
PREFIX_EVEX_0F12,
- PREFIX_EVEX_0F13,
- PREFIX_EVEX_0F14,
- PREFIX_EVEX_0F15,
PREFIX_EVEX_0F16,
- PREFIX_EVEX_0F17,
- PREFIX_EVEX_0F28,
- PREFIX_EVEX_0F29,
PREFIX_EVEX_0F2A,
- PREFIX_EVEX_0F2B,
PREFIX_EVEX_0F2C,
PREFIX_EVEX_0F2D,
PREFIX_EVEX_0F2E,
PREFIX_EVEX_0F2F,
PREFIX_EVEX_0F51,
- PREFIX_EVEX_0F54,
- PREFIX_EVEX_0F55,
- PREFIX_EVEX_0F56,
- PREFIX_EVEX_0F57,
PREFIX_EVEX_0F58,
PREFIX_EVEX_0F59,
PREFIX_EVEX_0F5A,
PREFIX_EVEX_0F5D,
PREFIX_EVEX_0F5E,
PREFIX_EVEX_0F5F,
- PREFIX_EVEX_0F60,
- PREFIX_EVEX_0F61,
- PREFIX_EVEX_0F62,
- PREFIX_EVEX_0F63,
PREFIX_EVEX_0F64,
PREFIX_EVEX_0F65,
PREFIX_EVEX_0F66,
- PREFIX_EVEX_0F67,
- PREFIX_EVEX_0F68,
- PREFIX_EVEX_0F69,
- PREFIX_EVEX_0F6A,
- PREFIX_EVEX_0F6B,
- PREFIX_EVEX_0F6C,
- PREFIX_EVEX_0F6D,
PREFIX_EVEX_0F6E,
PREFIX_EVEX_0F6F,
PREFIX_EVEX_0F70,
PREFIX_EVEX_0FC2,
PREFIX_EVEX_0FC4,
PREFIX_EVEX_0FC5,
- PREFIX_EVEX_0FC6,
- PREFIX_EVEX_0FD1,
- PREFIX_EVEX_0FD2,
- PREFIX_EVEX_0FD3,
- PREFIX_EVEX_0FD4,
- PREFIX_EVEX_0FD5,
PREFIX_EVEX_0FD6,
- PREFIX_EVEX_0FD8,
- PREFIX_EVEX_0FD9,
- PREFIX_EVEX_0FDA,
PREFIX_EVEX_0FDB,
- PREFIX_EVEX_0FDC,
- PREFIX_EVEX_0FDD,
- PREFIX_EVEX_0FDE,
PREFIX_EVEX_0FDF,
- PREFIX_EVEX_0FE0,
- PREFIX_EVEX_0FE1,
PREFIX_EVEX_0FE2,
- PREFIX_EVEX_0FE3,
- PREFIX_EVEX_0FE4,
- PREFIX_EVEX_0FE5,
PREFIX_EVEX_0FE6,
PREFIX_EVEX_0FE7,
- PREFIX_EVEX_0FE8,
- PREFIX_EVEX_0FE9,
- PREFIX_EVEX_0FEA,
PREFIX_EVEX_0FEB,
- PREFIX_EVEX_0FEC,
- PREFIX_EVEX_0FED,
- PREFIX_EVEX_0FEE,
PREFIX_EVEX_0FEF,
- PREFIX_EVEX_0FF1,
- PREFIX_EVEX_0FF2,
- PREFIX_EVEX_0FF3,
- PREFIX_EVEX_0FF4,
- PREFIX_EVEX_0FF5,
- PREFIX_EVEX_0FF6,
- PREFIX_EVEX_0FF8,
- PREFIX_EVEX_0FF9,
- PREFIX_EVEX_0FFA,
- PREFIX_EVEX_0FFB,
- PREFIX_EVEX_0FFC,
- PREFIX_EVEX_0FFD,
- PREFIX_EVEX_0FFE,
- PREFIX_EVEX_0F3800,
- PREFIX_EVEX_0F3804,
- PREFIX_EVEX_0F380B,
- PREFIX_EVEX_0F380C,
PREFIX_EVEX_0F380D,
PREFIX_EVEX_0F3810,
PREFIX_EVEX_0F3811,
PREFIX_EVEX_0F3814,
PREFIX_EVEX_0F3815,
PREFIX_EVEX_0F3816,
- PREFIX_EVEX_0F3818,
PREFIX_EVEX_0F3819,
PREFIX_EVEX_0F381A,
PREFIX_EVEX_0F381B,
- PREFIX_EVEX_0F381C,
- PREFIX_EVEX_0F381D,
PREFIX_EVEX_0F381E,
PREFIX_EVEX_0F381F,
PREFIX_EVEX_0F3820,
PREFIX_EVEX_0F3828,
PREFIX_EVEX_0F3829,
PREFIX_EVEX_0F382A,
- PREFIX_EVEX_0F382B,
PREFIX_EVEX_0F382C,
PREFIX_EVEX_0F382D,
PREFIX_EVEX_0F3830,
PREFIX_EVEX_0F3839,
PREFIX_EVEX_0F383A,
PREFIX_EVEX_0F383B,
- PREFIX_EVEX_0F383C,
PREFIX_EVEX_0F383D,
- PREFIX_EVEX_0F383E,
PREFIX_EVEX_0F383F,
PREFIX_EVEX_0F3840,
PREFIX_EVEX_0F3842,
PREFIX_EVEX_0F3853,
PREFIX_EVEX_0F3854,
PREFIX_EVEX_0F3855,
- PREFIX_EVEX_0F3858,
PREFIX_EVEX_0F3859,
PREFIX_EVEX_0F385A,
PREFIX_EVEX_0F385B,
PREFIX_EVEX_0F3875,
PREFIX_EVEX_0F3876,
PREFIX_EVEX_0F3877,
- PREFIX_EVEX_0F3878,
- PREFIX_EVEX_0F3879,
PREFIX_EVEX_0F387A,
PREFIX_EVEX_0F387B,
PREFIX_EVEX_0F387C,
PREFIX_EVEX_0F3891,
PREFIX_EVEX_0F3892,
PREFIX_EVEX_0F3893,
- PREFIX_EVEX_0F3896,
- PREFIX_EVEX_0F3897,
- PREFIX_EVEX_0F3898,
- PREFIX_EVEX_0F3899,
PREFIX_EVEX_0F389A,
PREFIX_EVEX_0F389B,
- PREFIX_EVEX_0F389C,
- PREFIX_EVEX_0F389D,
- PREFIX_EVEX_0F389E,
- PREFIX_EVEX_0F389F,
PREFIX_EVEX_0F38A0,
PREFIX_EVEX_0F38A1,
PREFIX_EVEX_0F38A2,
PREFIX_EVEX_0F38A3,
- PREFIX_EVEX_0F38A6,
- PREFIX_EVEX_0F38A7,
- PREFIX_EVEX_0F38A8,
- PREFIX_EVEX_0F38A9,
PREFIX_EVEX_0F38AA,
PREFIX_EVEX_0F38AB,
- PREFIX_EVEX_0F38AC,
- PREFIX_EVEX_0F38AD,
- PREFIX_EVEX_0F38AE,
- PREFIX_EVEX_0F38AF,
PREFIX_EVEX_0F38B4,
PREFIX_EVEX_0F38B5,
- PREFIX_EVEX_0F38B6,
- PREFIX_EVEX_0F38B7,
- PREFIX_EVEX_0F38B8,
- PREFIX_EVEX_0F38B9,
- PREFIX_EVEX_0F38BA,
- PREFIX_EVEX_0F38BB,
- PREFIX_EVEX_0F38BC,
- PREFIX_EVEX_0F38BD,
- PREFIX_EVEX_0F38BE,
- PREFIX_EVEX_0F38BF,
PREFIX_EVEX_0F38C4,
PREFIX_EVEX_0F38C6_REG_1,
PREFIX_EVEX_0F38C6_REG_2,
PREFIX_EVEX_0F38CB,
PREFIX_EVEX_0F38CC,
PREFIX_EVEX_0F38CD,
- PREFIX_EVEX_0F38CF,
- PREFIX_EVEX_0F38DC,
- PREFIX_EVEX_0F38DD,
- PREFIX_EVEX_0F38DE,
- PREFIX_EVEX_0F38DF,
PREFIX_EVEX_0F3A00,
PREFIX_EVEX_0F3A01,
PREFIX_EVEX_0F3A03,
- PREFIX_EVEX_0F3A04,
PREFIX_EVEX_0F3A05,
PREFIX_EVEX_0F3A08,
PREFIX_EVEX_0F3A09,
PREFIX_EVEX_0F3A0A,
PREFIX_EVEX_0F3A0B,
- PREFIX_EVEX_0F3A0F,
PREFIX_EVEX_0F3A14,
PREFIX_EVEX_0F3A15,
PREFIX_EVEX_0F3A16,
PREFIX_EVEX_0F3A19,
PREFIX_EVEX_0F3A1A,
PREFIX_EVEX_0F3A1B,
- PREFIX_EVEX_0F3A1D,
PREFIX_EVEX_0F3A1E,
PREFIX_EVEX_0F3A1F,
PREFIX_EVEX_0F3A20,
PREFIX_EVEX_0F3A3F,
PREFIX_EVEX_0F3A42,
PREFIX_EVEX_0F3A43,
- PREFIX_EVEX_0F3A44,
PREFIX_EVEX_0F3A50,
PREFIX_EVEX_0F3A51,
PREFIX_EVEX_0F3A54,
PREFIX_EVEX_0F3A71,
PREFIX_EVEX_0F3A72,
PREFIX_EVEX_0F3A73,
- PREFIX_EVEX_0F3ACE,
- PREFIX_EVEX_0F3ACF
};
enum
{
X86_64_06 = 0,
X86_64_07,
- X86_64_0D,
+ X86_64_0E,
X86_64_16,
X86_64_17,
X86_64_1E,
{
VEX_LEN_0F12_P_0_M_0 = 0,
VEX_LEN_0F12_P_0_M_1,
- VEX_LEN_0F12_P_2,
+#define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
VEX_LEN_0F13_M_0,
VEX_LEN_0F16_P_0_M_0,
VEX_LEN_0F16_P_0_M_1,
- VEX_LEN_0F16_P_2,
+#define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
VEX_LEN_0F17_M_0,
VEX_LEN_0F41_P_0,
VEX_LEN_0F41_P_2,
VEX_LEN_0F3A61_P_2,
VEX_LEN_0F3A62_P_2,
VEX_LEN_0F3A63_P_2,
- VEX_LEN_0F3A6A_P_2,
- VEX_LEN_0F3A6B_P_2,
- VEX_LEN_0F3A6E_P_2,
- VEX_LEN_0F3A6F_P_2,
- VEX_LEN_0F3A7A_P_2,
- VEX_LEN_0F3A7B_P_2,
- VEX_LEN_0F3A7E_P_2,
- VEX_LEN_0F3A7F_P_2,
VEX_LEN_0F3ADF_P_2,
VEX_LEN_0F3AF0_P_3,
VEX_LEN_0FXOP_08_CC,
VEX_LEN_0FXOP_08_ED,
VEX_LEN_0FXOP_08_EE,
VEX_LEN_0FXOP_08_EF,
- VEX_LEN_0FXOP_09_80,
- VEX_LEN_0FXOP_09_81
+ VEX_LEN_0FXOP_09_82_W_0,
+ VEX_LEN_0FXOP_09_83_W_0,
};
enum
EVEX_LEN_0F6E_P_2 = 0,
EVEX_LEN_0F7E_P_1,
EVEX_LEN_0F7E_P_2,
+ EVEX_LEN_0FC4_P_2,
+ EVEX_LEN_0FC5_P_2,
EVEX_LEN_0FD6_P_2,
+ EVEX_LEN_0F3816_P_2,
EVEX_LEN_0F3819_P_2_W_0,
EVEX_LEN_0F3819_P_2_W_1,
- EVEX_LEN_0F381A_P_2_W_0,
- EVEX_LEN_0F381A_P_2_W_1,
- EVEX_LEN_0F381B_P_2_W_0,
- EVEX_LEN_0F381B_P_2_W_1,
- EVEX_LEN_0F385A_P_2_W_0,
- EVEX_LEN_0F385A_P_2_W_1,
- EVEX_LEN_0F385B_P_2_W_0,
- EVEX_LEN_0F385B_P_2_W_1,
+ EVEX_LEN_0F381A_P_2_W_0_M_0,
+ EVEX_LEN_0F381A_P_2_W_1_M_0,
+ EVEX_LEN_0F381B_P_2_W_0_M_0,
+ EVEX_LEN_0F381B_P_2_W_1_M_0,
+ EVEX_LEN_0F3836_P_2,
+ EVEX_LEN_0F385A_P_2_W_0_M_0,
+ EVEX_LEN_0F385A_P_2_W_1_M_0,
+ EVEX_LEN_0F385B_P_2_W_0_M_0,
+ EVEX_LEN_0F385B_P_2_W_1_M_0,
EVEX_LEN_0F38C6_REG_1_PREFIX_2,
EVEX_LEN_0F38C6_REG_2_PREFIX_2,
EVEX_LEN_0F38C6_REG_5_PREFIX_2,
EVEX_LEN_0F38C7_R_5_P_2_W_1,
EVEX_LEN_0F38C7_R_6_P_2_W_0,
EVEX_LEN_0F38C7_R_6_P_2_W_1,
+ EVEX_LEN_0F3A00_P_2_W_1,
+ EVEX_LEN_0F3A01_P_2_W_1,
+ EVEX_LEN_0F3A14_P_2,
+ EVEX_LEN_0F3A15_P_2,
+ EVEX_LEN_0F3A16_P_2,
+ EVEX_LEN_0F3A17_P_2,
EVEX_LEN_0F3A18_P_2_W_0,
EVEX_LEN_0F3A18_P_2_W_1,
EVEX_LEN_0F3A19_P_2_W_0,
EVEX_LEN_0F3A1A_P_2_W_1,
EVEX_LEN_0F3A1B_P_2_W_0,
EVEX_LEN_0F3A1B_P_2_W_1,
+ EVEX_LEN_0F3A20_P_2,
+ EVEX_LEN_0F3A21_P_2_W_0,
+ EVEX_LEN_0F3A22_P_2,
EVEX_LEN_0F3A23_P_2_W_0,
EVEX_LEN_0F3A23_P_2_W_1,
EVEX_LEN_0F3A38_P_2_W_0,
VEX_W_0F380D_P_2,
VEX_W_0F380E_P_2,
VEX_W_0F380F_P_2,
+ VEX_W_0F3813_P_2,
VEX_W_0F3816_P_2,
VEX_W_0F3818_P_2,
VEX_W_0F3819_P_2,
VEX_W_0F3A06_P_2,
VEX_W_0F3A18_P_2,
VEX_W_0F3A19_P_2,
+ VEX_W_0F3A1D_P_2,
VEX_W_0F3A30_P_2_LEN_0,
VEX_W_0F3A31_P_2_LEN_0,
VEX_W_0F3A32_P_2_LEN_0,
VEX_W_0F3A38_P_2,
VEX_W_0F3A39_P_2,
VEX_W_0F3A46_P_2,
- VEX_W_0F3A48_P_2,
- VEX_W_0F3A49_P_2,
VEX_W_0F3A4A_P_2,
VEX_W_0F3A4B_P_2,
VEX_W_0F3A4C_P_2,
VEX_W_0F3ACE_P_2,
VEX_W_0F3ACF_P_2,
- EVEX_W_0F10_P_0,
+ VEX_W_0FXOP_09_80,
+ VEX_W_0FXOP_09_81,
+ VEX_W_0FXOP_09_82,
+ VEX_W_0FXOP_09_83,
+
EVEX_W_0F10_P_1,
- EVEX_W_0F10_P_2,
EVEX_W_0F10_P_3,
- EVEX_W_0F11_P_0,
EVEX_W_0F11_P_1,
- EVEX_W_0F11_P_2,
EVEX_W_0F11_P_3,
- EVEX_W_0F12_P_0_M_0,
EVEX_W_0F12_P_0_M_1,
EVEX_W_0F12_P_1,
- EVEX_W_0F12_P_2,
EVEX_W_0F12_P_3,
- EVEX_W_0F13_P_0,
- EVEX_W_0F13_P_2,
- EVEX_W_0F14_P_0,
- EVEX_W_0F14_P_2,
- EVEX_W_0F15_P_0,
- EVEX_W_0F15_P_2,
- EVEX_W_0F16_P_0_M_0,
EVEX_W_0F16_P_0_M_1,
EVEX_W_0F16_P_1,
- EVEX_W_0F16_P_2,
- EVEX_W_0F17_P_0,
- EVEX_W_0F17_P_2,
- EVEX_W_0F28_P_0,
- EVEX_W_0F28_P_2,
- EVEX_W_0F29_P_0,
- EVEX_W_0F29_P_2,
EVEX_W_0F2A_P_3,
- EVEX_W_0F2B_P_0,
- EVEX_W_0F2B_P_2,
- EVEX_W_0F2E_P_0,
- EVEX_W_0F2E_P_2,
- EVEX_W_0F2F_P_0,
- EVEX_W_0F2F_P_2,
- EVEX_W_0F51_P_0,
EVEX_W_0F51_P_1,
- EVEX_W_0F51_P_2,
EVEX_W_0F51_P_3,
- EVEX_W_0F54_P_0,
- EVEX_W_0F54_P_2,
- EVEX_W_0F55_P_0,
- EVEX_W_0F55_P_2,
- EVEX_W_0F56_P_0,
- EVEX_W_0F56_P_2,
- EVEX_W_0F57_P_0,
- EVEX_W_0F57_P_2,
- EVEX_W_0F58_P_0,
EVEX_W_0F58_P_1,
- EVEX_W_0F58_P_2,
EVEX_W_0F58_P_3,
- EVEX_W_0F59_P_0,
EVEX_W_0F59_P_1,
- EVEX_W_0F59_P_2,
EVEX_W_0F59_P_3,
EVEX_W_0F5A_P_0,
EVEX_W_0F5A_P_1,
EVEX_W_0F5B_P_0,
EVEX_W_0F5B_P_1,
EVEX_W_0F5B_P_2,
- EVEX_W_0F5C_P_0,
EVEX_W_0F5C_P_1,
- EVEX_W_0F5C_P_2,
EVEX_W_0F5C_P_3,
- EVEX_W_0F5D_P_0,
EVEX_W_0F5D_P_1,
- EVEX_W_0F5D_P_2,
EVEX_W_0F5D_P_3,
- EVEX_W_0F5E_P_0,
EVEX_W_0F5E_P_1,
- EVEX_W_0F5E_P_2,
EVEX_W_0F5E_P_3,
- EVEX_W_0F5F_P_0,
EVEX_W_0F5F_P_1,
- EVEX_W_0F5F_P_2,
EVEX_W_0F5F_P_3,
- EVEX_W_0F62_P_2,
+ EVEX_W_0F62,
EVEX_W_0F66_P_2,
- EVEX_W_0F6A_P_2,
- EVEX_W_0F6B_P_2,
- EVEX_W_0F6C_P_2,
- EVEX_W_0F6D_P_2,
+ EVEX_W_0F6A,
+ EVEX_W_0F6B,
+ EVEX_W_0F6C,
+ EVEX_W_0F6D,
EVEX_W_0F6F_P_1,
EVEX_W_0F6F_P_2,
EVEX_W_0F6F_P_3,
EVEX_W_0F7F_P_1,
EVEX_W_0F7F_P_2,
EVEX_W_0F7F_P_3,
- EVEX_W_0FC2_P_0,
EVEX_W_0FC2_P_1,
- EVEX_W_0FC2_P_2,
EVEX_W_0FC2_P_3,
- EVEX_W_0FC6_P_0,
- EVEX_W_0FC6_P_2,
- EVEX_W_0FD2_P_2,
- EVEX_W_0FD3_P_2,
- EVEX_W_0FD4_P_2,
+ EVEX_W_0FD2,
+ EVEX_W_0FD3,
+ EVEX_W_0FD4,
EVEX_W_0FD6_P_2,
EVEX_W_0FE6_P_1,
EVEX_W_0FE6_P_2,
EVEX_W_0FE6_P_3,
EVEX_W_0FE7_P_2,
- EVEX_W_0FF2_P_2,
- EVEX_W_0FF3_P_2,
- EVEX_W_0FF4_P_2,
- EVEX_W_0FFA_P_2,
- EVEX_W_0FFB_P_2,
- EVEX_W_0FFE_P_2,
- EVEX_W_0F380C_P_2,
+ EVEX_W_0FF2,
+ EVEX_W_0FF3,
+ EVEX_W_0FF4,
+ EVEX_W_0FFA,
+ EVEX_W_0FFB,
+ EVEX_W_0FFE,
EVEX_W_0F380D_P_2,
EVEX_W_0F3810_P_1,
EVEX_W_0F3810_P_2,
EVEX_W_0F3813_P_2,
EVEX_W_0F3814_P_1,
EVEX_W_0F3815_P_1,
- EVEX_W_0F3818_P_2,
EVEX_W_0F3819_P_2,
EVEX_W_0F381A_P_2,
EVEX_W_0F381B_P_2,
EVEX_W_0F3824_P_1,
EVEX_W_0F3825_P_1,
EVEX_W_0F3825_P_2,
- EVEX_W_0F3826_P_1,
- EVEX_W_0F3826_P_2,
- EVEX_W_0F3828_P_1,
EVEX_W_0F3828_P_2,
- EVEX_W_0F3829_P_1,
EVEX_W_0F3829_P_2,
EVEX_W_0F382A_P_1,
EVEX_W_0F382A_P_2,
- EVEX_W_0F382B_P_2,
+ EVEX_W_0F382B,
EVEX_W_0F3830_P_1,
EVEX_W_0F3831_P_1,
EVEX_W_0F3832_P_1,
EVEX_W_0F3835_P_1,
EVEX_W_0F3835_P_2,
EVEX_W_0F3837_P_2,
- EVEX_W_0F3838_P_1,
- EVEX_W_0F3839_P_1,
EVEX_W_0F383A_P_1,
- EVEX_W_0F3840_P_2,
EVEX_W_0F3852_P_1,
- EVEX_W_0F3854_P_2,
- EVEX_W_0F3855_P_2,
- EVEX_W_0F3858_P_2,
EVEX_W_0F3859_P_2,
EVEX_W_0F385A_P_2,
EVEX_W_0F385B_P_2,
EVEX_W_0F3862_P_2,
EVEX_W_0F3863_P_2,
- EVEX_W_0F3866_P_2,
- EVEX_W_0F3868_P_3,
EVEX_W_0F3870_P_2,
- EVEX_W_0F3871_P_2,
EVEX_W_0F3872_P_1,
EVEX_W_0F3872_P_2,
EVEX_W_0F3872_P_3,
- EVEX_W_0F3873_P_2,
- EVEX_W_0F3875_P_2,
- EVEX_W_0F3878_P_2,
- EVEX_W_0F3879_P_2,
EVEX_W_0F387A_P_2,
EVEX_W_0F387B_P_2,
- EVEX_W_0F387D_P_2,
EVEX_W_0F3883_P_2,
- EVEX_W_0F388D_P_2,
EVEX_W_0F3891_P_2,
EVEX_W_0F3893_P_2,
EVEX_W_0F38A1_P_2,
EVEX_W_0F3A00_P_2,
EVEX_W_0F3A01_P_2,
- EVEX_W_0F3A04_P_2,
EVEX_W_0F3A05_P_2,
EVEX_W_0F3A08_P_2,
EVEX_W_0F3A09_P_2,
EVEX_W_0F3A19_P_2,
EVEX_W_0F3A1A_P_2,
EVEX_W_0F3A1B_P_2,
- EVEX_W_0F3A1D_P_2,
EVEX_W_0F3A21_P_2,
EVEX_W_0F3A23_P_2,
EVEX_W_0F3A38_P_2,
EVEX_W_0F3A39_P_2,
EVEX_W_0F3A3A_P_2,
EVEX_W_0F3A3B_P_2,
- EVEX_W_0F3A3E_P_2,
- EVEX_W_0F3A3F_P_2,
EVEX_W_0F3A42_P_2,
EVEX_W_0F3A43_P_2,
- EVEX_W_0F3A50_P_2,
- EVEX_W_0F3A51_P_2,
- EVEX_W_0F3A56_P_2,
- EVEX_W_0F3A57_P_2,
- EVEX_W_0F3A66_P_2,
- EVEX_W_0F3A67_P_2,
EVEX_W_0F3A70_P_2,
- EVEX_W_0F3A71_P_2,
EVEX_W_0F3A72_P_2,
- EVEX_W_0F3A73_P_2,
- EVEX_W_0F3ACE_P_2,
- EVEX_W_0F3ACF_P_2
};
typedef void (*op_rtn) (int bytemode, int sizeflag);
'F' => print 'w' or 'l' depending on address size prefix (loop insns)
'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
'H' => print ",pt" or ",pn" branch hint
- 'I' => honor following macro letter even in Intel mode (implemented only
- for some of the macro letters)
- 'J' => print 'l'
+ 'I' unused.
+ 'J' unused.
'K' => print 'd' or 'q' if rex prefix is present.
'L' => print 'l' if suffix_always is true
'M' => print 'r' if intel_mnemonic is false.
"XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
register operands and no broadcast.
"XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
- "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
- or suffix_always is true
+ "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory
+ operand or no operand at all in 64bit mode, or if suffix_always
+ is true.
"LB" => print "abs" in 64bit mode and behave as 'B' otherwise
"LS" => print "abs" in 64bit mode and behave as 'S' otherwise
"LV" => print "abs" for 64bit operand and behave as 'S' otherwise
"LW" => print 'd', 'q' depending on the VEX.W bit
+ "BW" => print 'b' or 'w' depending on the EVEX.W bit
"LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
an operand size prefix, or suffix_always is true. print
'q' if rex prefix is present.
{ "orS", { Gv, EvS }, 0 },
{ "orB", { AL, Ib }, 0 },
{ "orS", { eAX, Iv }, 0 },
- { X86_64_TABLE (X86_64_0D) },
+ { X86_64_TABLE (X86_64_0E) },
{ Bad_Opcode }, /* 0x0f extended opcode escape */
/* 10 */
{ "adcB", { Ebh1, Gb }, 0 },
/* c8 */
{ "enterT", { Iw, Ib }, 0 },
{ "leaveT", { XX }, 0 },
- { "Jret{|f}P", { Iw }, 0 },
- { "Jret{|f}P", { XX }, 0 },
+ { "{l|}ret{|f}P", { Iw }, 0 },
+ { "{l|}ret{|f}P", { XX }, 0 },
{ "int3", { XX }, 0 },
{ "int", { Ib }, 0 },
{ X86_64_TABLE (X86_64_CE) },
{ Bad_Opcode },
{ "syscall", { XX }, 0 },
{ "clts", { XX }, 0 },
- { "sysret%LP", { XX }, 0 },
+ { "sysret%LQ", { XX }, 0 },
/* 08 */
{ "invd", { XX }, 0 },
{ PREFIX_TABLE (PREFIX_0F09) },
{ "cmovleS", { Gv, Ev }, 0 },
{ "cmovgS", { Gv, Ev }, 0 },
/* 50 */
- { MOD_TABLE (MOD_0F51) },
+ { MOD_TABLE (MOD_0F50) },
{ PREFIX_TABLE (PREFIX_0F51) },
{ PREFIX_TABLE (PREFIX_0F52) },
{ PREFIX_TABLE (PREFIX_0F53) },
vex;
static unsigned char need_vex;
static unsigned char need_vex_reg;
-static unsigned char vex_w_done;
struct op
{
{ NULL, { { NULL, 0 } }, PREFIX_IGNORED }
},
+ /* PREFIX_0F01_REG_3_RM_1 */
+ {
+ { "vmmcall", { Skip_MODRM }, 0 },
+ { "vmgexit", { Skip_MODRM }, 0 },
+ { Bad_Opcode },
+ { "vmgexit", { Skip_MODRM }, 0 },
+ },
+
/* PREFIX_0F01_REG_5_MOD_0 */
{
{ Bad_Opcode },
/* PREFIX_0F01_REG_5_MOD_3_RM_0 */
{
- { Bad_Opcode },
+ { "serialize", { Skip_MODRM }, PREFIX_OPCODE },
{ "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
+ { Bad_Opcode },
+ { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE },
},
/* PREFIX_0F01_REG_5_MOD_3_RM_2 */
{
{ MOD_TABLE (MOD_0F12_PREFIX_0) },
{ "movsldup", { XM, EXx }, PREFIX_OPCODE },
- { "movlpd", { XM, EXq }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_0F12_PREFIX_2) },
{ "movddup", { XM, EXq }, PREFIX_OPCODE },
},
{
{ MOD_TABLE (MOD_0F16_PREFIX_0) },
{ "movshdup", { XM, EXx }, PREFIX_OPCODE },
- { "movhpd", { XM, EXq }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_0F16_PREFIX_2) },
},
/* PREFIX_0F1A */
/* PREFIX_VEX_0F10 */
{
{ "vmovups", { XM, EXx }, 0 },
- { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
+ { "vmovss", { XMVexScalar, VexScalar, EXxmm_md }, 0 },
{ "vmovupd", { XM, EXx }, 0 },
- { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
+ { "vmovsd", { XMVexScalar, VexScalar, EXxmm_mq }, 0 },
},
/* PREFIX_VEX_0F11 */
{
{ MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
{ "vmovsldup", { XM, EXx }, 0 },
- { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
+ { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
{ "vmovddup", { XM, EXymmq }, 0 },
},
{
{ MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
{ "vmovshdup", { XM, EXx }, 0 },
- { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
+ { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
},
/* PREFIX_VEX_0F2A */
/* PREFIX_VEX_0F2C */
{
{ Bad_Opcode },
- { "vcvttss2si", { Gdq, EXdScalar }, 0 },
+ { "vcvttss2si", { Gdq, EXxmm_md }, 0 },
{ Bad_Opcode },
- { "vcvttsd2si", { Gdq, EXqScalar }, 0 },
+ { "vcvttsd2si", { Gdq, EXxmm_mq }, 0 },
},
/* PREFIX_VEX_0F2D */
{
{ Bad_Opcode },
- { "vcvtss2si", { Gdq, EXdScalar }, 0 },
+ { "vcvtss2si", { Gdq, EXxmm_md }, 0 },
{ Bad_Opcode },
- { "vcvtsd2si", { Gdq, EXqScalar }, 0 },
+ { "vcvtsd2si", { Gdq, EXxmm_mq }, 0 },
},
/* PREFIX_VEX_0F2E */
{
- { "vucomiss", { XMScalar, EXdScalar }, 0 },
+ { "vucomiss", { XMScalar, EXxmm_md }, 0 },
{ Bad_Opcode },
- { "vucomisd", { XMScalar, EXqScalar }, 0 },
+ { "vucomisd", { XMScalar, EXxmm_mq }, 0 },
},
/* PREFIX_VEX_0F2F */
{
- { "vcomiss", { XMScalar, EXdScalar }, 0 },
+ { "vcomiss", { XMScalar, EXxmm_md }, 0 },
{ Bad_Opcode },
- { "vcomisd", { XMScalar, EXqScalar }, 0 },
+ { "vcomisd", { XMScalar, EXxmm_mq }, 0 },
},
/* PREFIX_VEX_0F41 */
/* PREFIX_VEX_0F51 */
{
{ "vsqrtps", { XM, EXx }, 0 },
- { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { "vsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
{ "vsqrtpd", { XM, EXx }, 0 },
- { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
},
/* PREFIX_VEX_0F52 */
{
{ "vrsqrtps", { XM, EXx }, 0 },
- { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { "vrsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
},
/* PREFIX_VEX_0F53 */
{
{ "vrcpps", { XM, EXx }, 0 },
- { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { "vrcpss", { XMScalar, VexScalar, EXxmm_md }, 0 },
},
/* PREFIX_VEX_0F58 */
{
{ "vaddps", { XM, Vex, EXx }, 0 },
- { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { "vaddss", { XMScalar, VexScalar, EXxmm_md }, 0 },
{ "vaddpd", { XM, Vex, EXx }, 0 },
- { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ { "vaddsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
},
/* PREFIX_VEX_0F59 */
{
{ "vmulps", { XM, Vex, EXx }, 0 },
- { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { "vmulss", { XMScalar, VexScalar, EXxmm_md }, 0 },
{ "vmulpd", { XM, Vex, EXx }, 0 },
- { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ { "vmulsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
},
/* PREFIX_VEX_0F5A */
{
{ "vcvtps2pd", { XM, EXxmmq }, 0 },
- { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md }, 0 },
{ "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
- { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
+ { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq }, 0 },
},
/* PREFIX_VEX_0F5B */
/* PREFIX_VEX_0F5C */
{
{ "vsubps", { XM, Vex, EXx }, 0 },
- { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { "vsubss", { XMScalar, VexScalar, EXxmm_md }, 0 },
{ "vsubpd", { XM, Vex, EXx }, 0 },
- { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ { "vsubsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
},
/* PREFIX_VEX_0F5D */
{
{ "vminps", { XM, Vex, EXx }, 0 },
- { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { "vminss", { XMScalar, VexScalar, EXxmm_md }, 0 },
{ "vminpd", { XM, Vex, EXx }, 0 },
- { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ { "vminsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
},
/* PREFIX_VEX_0F5E */
{
{ "vdivps", { XM, Vex, EXx }, 0 },
- { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { "vdivss", { XMScalar, VexScalar, EXxmm_md }, 0 },
{ "vdivpd", { XM, Vex, EXx }, 0 },
- { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ { "vdivsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
},
/* PREFIX_VEX_0F5F */
{
{ "vmaxps", { XM, Vex, EXx }, 0 },
- { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { "vmaxss", { XMScalar, VexScalar, EXxmm_md }, 0 },
{ "vmaxpd", { XM, Vex, EXx }, 0 },
- { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
},
/* PREFIX_VEX_0F60 */
/* PREFIX_VEX_0FC2 */
{
{ "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
- { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
+ { "vcmpss", { XMScalar, VexScalar, EXxmm_md, VCMP }, 0 },
{ "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
- { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
+ { "vcmpsd", { XMScalar, VexScalar, EXxmm_mq, VCMP }, 0 },
},
/* PREFIX_VEX_0FC4 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vcvtph2ps", { XM, EXxmmq }, 0 },
+ { VEX_W_TABLE (VEX_W_0F3813_P_2) },
},
/* PREFIX_VEX_0F3816 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
+ { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F3897 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
+ { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F3898 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
+ { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F3899 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F389A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
+ { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F389D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F389E */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
+ { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F389F */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38A6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
+ { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
{ Bad_Opcode },
},
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
+ { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38A8 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
+ { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38A9 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38AA */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
+ { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38AD */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38AE */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
+ { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38AF */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38B6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
+ { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38B7 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
+ { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38B8 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
+ { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38B9 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38BA */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
+ { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38BB */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38BC */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
+ { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38BD */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38BE */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
+ { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38BF */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
+ { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
},
/* PREFIX_VEX_0F38CF */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
+ { "vroundss", { XMScalar, VexScalar, EXxmm_md, Ib }, 0 },
},
/* PREFIX_VEX_0F3A0B */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
+ { "vroundsd", { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 },
},
/* PREFIX_VEX_0F3A0C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
+ { VEX_W_TABLE (VEX_W_0F3A1D_P_2) },
},
/* PREFIX_VEX_0F3A20 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
+ { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, 0 },
},
/* PREFIX_VEX_0F3A49 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
+ { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, 0 },
},
/* PREFIX_VEX_0F3A4A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
},
/* PREFIX_VEX_0F3A5D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
},
/* PREFIX_VEX_0F3A5E */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
},
/* PREFIX_VEX_0F3A5F */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
},
/* PREFIX_VEX_0F3A60 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
},
/* PREFIX_VEX_0F3A69 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
},
/* PREFIX_VEX_0F3A6A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
+ { "vfmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
},
/* PREFIX_VEX_0F3A6B */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
+ { "vfmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
},
/* PREFIX_VEX_0F3A6C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
},
/* PREFIX_VEX_0F3A6D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
},
/* PREFIX_VEX_0F3A6E */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
+ { "vfmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
},
/* PREFIX_VEX_0F3A6F */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
+ { "vfmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
},
/* PREFIX_VEX_0F3A78 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
},
/* PREFIX_VEX_0F3A79 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
},
/* PREFIX_VEX_0F3A7A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
+ { "vfnmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
},
/* PREFIX_VEX_0F3A7B */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
+ { "vfnmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
},
/* PREFIX_VEX_0F3A7C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
{ Bad_Opcode },
},
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
},
/* PREFIX_VEX_0F3A7E */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
+ { "vfnmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
},
/* PREFIX_VEX_0F3A7F */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
+ { "vfnmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
},
/* PREFIX_VEX_0F3ACE */
{ "popP", { es }, 0 },
},
- /* X86_64_0D */
+ /* X86_64_0E */
{
{ "pushP", { cs }, 0 },
},
/* X86_64_9A */
{
- { "Jcall{T|}", { Ap }, 0 },
+ { "{l|}call{T|}", { Ap }, 0 },
},
/* X86_64_C2 */
/* X86_64_EA */
{
- { "Jjmp{T|}", { Ap }, 0 },
+ { "{l|}jmp{T|}", { Ap }, 0 },
},
/* X86_64_0F01_REG_0 */
{
- { "sgdt{Q|IQ}", { M }, 0 },
+ { "sgdt{Q|Q}", { M }, 0 },
{ "sgdt", { M }, 0 },
},
/* X86_64_0F01_REG_1 */
{
- { "sidt{Q|IQ}", { M }, 0 },
+ { "sidt{Q|Q}", { M }, 0 },
{ "sidt", { M }, 0 },
},
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 },
+ { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
+ { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 },
/* 88 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 },
+ { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
/* 90 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 },
+ { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 },
+ { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 },
/* 98 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 },
+ { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
/* a0 */
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 },
+ { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
{ Bad_Opcode },
/* a8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 },
{ Bad_Opcode },
/* b8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* c0 */
- { "vprotb", { XM, Vex_2src_1, Ib }, 0 },
- { "vprotw", { XM, Vex_2src_1, Ib }, 0 },
- { "vprotd", { XM, Vex_2src_1, Ib }, 0 },
- { "vprotq", { XM, Vex_2src_1, Ib }, 0 },
+ { "vprotb", { XM, EXx, Ib }, 0 },
+ { "vprotw", { XM, EXx, Ib }, 0 },
+ { "vprotd", { XM, EXx, Ib }, 0 },
+ { "vprotq", { XM, EXx, Ib }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 80 */
- { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
- { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
- { "vfrczss", { XM, EXd }, 0 },
- { "vfrczsd", { XM, EXq }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 90 */
- { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vprotb", { XM, EXx, VexW }, 0 },
+ { "vprotw", { XM, EXx, VexW }, 0 },
+ { "vprotd", { XM, EXx, VexW }, 0 },
+ { "vprotq", { XM, EXx, VexW }, 0 },
+ { "vpshlb", { XM, EXx, VexW }, 0 },
+ { "vpshlw", { XM, EXx, VexW }, 0 },
+ { "vpshld", { XM, EXx, VexW }, 0 },
+ { "vpshlq", { XM, EXx, VexW }, 0 },
/* 98 */
- { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vpshab", { XM, EXx, VexW }, 0 },
+ { "vpshaw", { XM, EXx, VexW }, 0 },
+ { "vpshad", { XM, EXx, VexW }, 0 },
+ { "vpshaq", { XM, EXx, VexW }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_VEX_0F11) },
{ PREFIX_TABLE (PREFIX_VEX_0F12) },
{ MOD_TABLE (MOD_VEX_0F13) },
- { "vunpcklpX", { XM, Vex, EXx }, 0 },
- { "vunpckhpX", { XM, Vex, EXx }, 0 },
+ { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
+ { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
{ PREFIX_TABLE (PREFIX_VEX_0F16) },
{ MOD_TABLE (MOD_VEX_0F17) },
/* 18 */
{ Bad_Opcode },
{ Bad_Opcode },
/* 28 */
- { "vmovapX", { XM, EXx }, 0 },
- { "vmovapX", { EXxS, XM }, 0 },
+ { "vmovapX", { XM, EXx }, PREFIX_OPCODE },
+ { "vmovapX", { EXxS, XM }, PREFIX_OPCODE },
{ PREFIX_TABLE (PREFIX_VEX_0F2A) },
{ MOD_TABLE (MOD_VEX_0F2B) },
{ PREFIX_TABLE (PREFIX_VEX_0F2C) },
{ PREFIX_TABLE (PREFIX_VEX_0F51) },
{ PREFIX_TABLE (PREFIX_VEX_0F52) },
{ PREFIX_TABLE (PREFIX_VEX_0F53) },
- { "vandpX", { XM, Vex, EXx }, 0 },
- { "vandnpX", { XM, Vex, EXx }, 0 },
- { "vorpX", { XM, Vex, EXx }, 0 },
- { "vxorpX", { XM, Vex, EXx }, 0 },
+ { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
+ { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
+ { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
+ { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
/* 58 */
{ PREFIX_TABLE (PREFIX_VEX_0F58) },
{ PREFIX_TABLE (PREFIX_VEX_0F59) },
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_VEX_0FC4) },
{ PREFIX_TABLE (PREFIX_VEX_0FC5) },
- { "vshufpX", { XM, Vex, EXx, Ib }, 0 },
+ { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
{ Bad_Opcode },
/* c8 */
{ Bad_Opcode },
#include "i386-dis-evex.h"
static const struct dis386 vex_len_table[][2] = {
- /* VEX_LEN_0F12_P_0_M_0 */
+ /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
{
- { "vmovlps", { XM, Vex128, EXq }, 0 },
+ { "vmovlpX", { XM, Vex128, EXq }, 0 },
},
/* VEX_LEN_0F12_P_0_M_1 */
{ "vmovhlps", { XM, Vex128, EXq }, 0 },
},
- /* VEX_LEN_0F12_P_2 */
- {
- { "vmovlpd", { XM, Vex128, EXq }, 0 },
- },
-
/* VEX_LEN_0F13_M_0 */
{
- { "vmovlpX", { EXq, XM }, 0 },
+ { "vmovlpX", { EXq, XM }, PREFIX_OPCODE },
},
- /* VEX_LEN_0F16_P_0_M_0 */
+ /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
{
- { "vmovhps", { XM, Vex128, EXq }, 0 },
+ { "vmovhpX", { XM, Vex128, EXq }, 0 },
},
/* VEX_LEN_0F16_P_0_M_1 */
{ "vmovlhps", { XM, Vex128, EXq }, 0 },
},
- /* VEX_LEN_0F16_P_2 */
- {
- { "vmovhpd", { XM, Vex128, EXq }, 0 },
- },
-
/* VEX_LEN_0F17_M_0 */
{
- { "vmovhpX", { EXq, XM }, 0 },
+ { "vmovhpX", { EXq, XM }, PREFIX_OPCODE },
},
/* VEX_LEN_0F41_P_0 */
/* VEX_LEN_0F7E_P_1 */
{
- { "vmovq", { XMScalar, EXqScalar }, 0 },
+ { "vmovq", { XMScalar, EXxmm_mq }, 0 },
},
/* VEX_LEN_0F7E_P_2 */
/* VEX_LEN_0FD6_P_2 */
{
- { "vmovq", { EXqScalarS, XMScalar }, 0 },
+ { "vmovq", { EXqVexScalarS, XMScalar }, 0 },
},
/* VEX_LEN_0FF7_P_2 */
{ "vpcmpistri", { XM, EXx, Ib }, 0 },
},
- /* VEX_LEN_0F3A6A_P_2 */
- {
- { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
- },
-
- /* VEX_LEN_0F3A6B_P_2 */
- {
- { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
- },
-
- /* VEX_LEN_0F3A6E_P_2 */
- {
- { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
- },
-
- /* VEX_LEN_0F3A6F_P_2 */
- {
- { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
- },
-
- /* VEX_LEN_0F3A7A_P_2 */
- {
- { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
- },
-
- /* VEX_LEN_0F3A7B_P_2 */
- {
- { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
- },
-
- /* VEX_LEN_0F3A7E_P_2 */
- {
- { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
- },
-
- /* VEX_LEN_0F3A7F_P_2 */
- {
- { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
- },
-
/* VEX_LEN_0F3ADF_P_2 */
{
{ "vaeskeygenassist", { XM, EXx, Ib }, 0 },
{ "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 },
},
- /* VEX_LEN_0FXOP_09_80 */
+ /* VEX_LEN_0FXOP_09_82_W_0 */
{
- { "vfrczps", { XM, EXxmm }, 0 },
- { "vfrczps", { XM, EXymmq }, 0 },
+ { "vfrczss", { XM, EXd }, 0 },
},
- /* VEX_LEN_0FXOP_09_81 */
+ /* VEX_LEN_0FXOP_09_83_W_0 */
{
- { "vfrczpd", { XM, EXxmm }, 0 },
- { "vfrczpd", { XM, EXymmq }, 0 },
+ { "vfrczsd", { XM, EXq }, 0 },
},
};
/* VEX_W_0F380F_P_2 */
{ "vtestpd", { XM, EXx }, 0 },
},
+ {
+ /* VEX_W_0F3813_P_2 */
+ { "vcvtph2ps", { XM, EXxmmq }, 0 },
+ },
{
/* VEX_W_0F3816_P_2 */
{ "vpermps", { XM, Vex, EXx }, 0 },
/* VEX_W_0F3A19_P_2 */
{ "vextractf128", { EXxmm, XM, Ib }, 0 },
},
+ {
+ /* VEX_W_0F3A1D_P_2 */
+ { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, 0 },
+ },
{
/* VEX_W_0F3A30_P_2_LEN_0 */
{ MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
/* VEX_W_0F3A46_P_2 */
{ "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
},
- {
- /* VEX_W_0F3A48_P_2 */
- { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
- { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
- },
- {
- /* VEX_W_0F3A49_P_2 */
- { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
- { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
- },
{
/* VEX_W_0F3A4A_P_2 */
{ "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 },
{ Bad_Opcode },
{ "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 },
},
+ /* VEX_W_0FXOP_09_80 */
+ {
+ { "vfrczps", { XM, EXx }, 0 },
+ },
+ /* VEX_W_0FXOP_09_81 */
+ {
+ { "vfrczpd", { XM, EXx }, 0 },
+ },
+ /* VEX_W_0FXOP_09_82 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
+ },
+ /* VEX_W_0FXOP_09_83 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
+ },
#include "i386-dis-evex-w.h"
};
},
{
/* MOD_FF_REG_3 */
- { "Jcall^", { indirEp }, 0 },
+ { "{l|}call^", { indirEp }, 0 },
},
{
/* MOD_FF_REG_5 */
- { "Jjmp^", { indirEp }, 0 },
+ { "{l|}jmp^", { indirEp }, 0 },
},
{
/* MOD_0F01_REG_0 */
},
{
/* MOD_0F12_PREFIX_0 */
- { "movlps", { XM, EXq }, PREFIX_OPCODE },
- { "movhlps", { XM, EXq }, PREFIX_OPCODE },
+ { "movlpX", { XM, EXq }, 0 },
+ { "movhlps", { XM, EXq }, 0 },
+ },
+ {
+ /* MOD_0F12_PREFIX_2 */
+ { "movlpX", { XM, EXq }, 0 },
},
{
/* MOD_0F13 */
},
{
/* MOD_0F16_PREFIX_0 */
- { "movhps", { XM, EXq }, 0 },
+ { "movhpX", { XM, EXq }, 0 },
{ "movlhps", { XM, EXq }, 0 },
},
+ {
+ /* MOD_0F16_PREFIX_2 */
+ { "movhpX", { XM, EXq }, 0 },
+ },
{
/* MOD_0F17 */
{ "movhpX", { EXq, XM }, PREFIX_OPCODE },
{"movntsd", { Mq, XM }, PREFIX_OPCODE },
},
{
- /* MOD_0F51 */
+ /* MOD_0F50 */
{ Bad_Opcode },
{ "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
},
{ VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
{ VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
},
+ {
+ /* MOD_VEX_0F12_PREFIX_2 */
+ { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
+ },
{
/* MOD_VEX_0F13 */
{ VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
{ VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
{ VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
},
+ {
+ /* MOD_VEX_0F16_PREFIX_2 */
+ { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
+ },
{
/* MOD_VEX_0F17 */
{ VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
},
{
/* MOD_VEX_0F2B */
- { "vmovntpX", { Mx, XM }, 0 },
+ { "vmovntpX", { Mx, XM }, PREFIX_OPCODE },
},
{
/* MOD_VEX_W_0_0F41_P_0_LEN_1 */
{
/* MOD_VEX_0F50 */
{ Bad_Opcode },
- { "vmovmskpX", { Gdq, XS }, 0 },
+ { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE },
},
{
/* MOD_VEX_0F71_REG_2 */
{
/* RM_0F01_REG_3 */
{ "vmrun", { Skip_MODRM }, 0 },
- { "vmmcall", { Skip_MODRM }, 0 },
+ { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
{ "vmload", { Skip_MODRM }, 0 },
{ "vmsave", { Skip_MODRM }, 0 },
{ "stgi", { Skip_MODRM }, 0 },
{
/* RM_0F01_REG_5_MOD_3 */
{ PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
{ PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
{ Bad_Opcode },
{ Bad_Opcode },
{
int newrex, i, length;
rex = 0;
- rex_ignored = 0;
prefixes = 0;
used_prefixes = 0;
rex_used = 0;
case USE_XOP_8F_TABLE:
FETCH_DATA (info, codep + 3);
- /* All bits in the REX prefix are ignored. */
- rex_ignored = rex;
rex = ~(*codep >> 5) & 0x7;
/* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
modrm.mod = (*codep >> 6) & 3;
modrm.reg = (*codep >> 3) & 7;
modrm.rm = *codep & 7;
+
+ /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
+ having to decode the bits for every otherwise valid encoding. */
+ if (vex.prefix)
+ return &bad_opcode;
break;
case USE_VEX_C4_TABLE:
/* VEX prefix. */
FETCH_DATA (info, codep + 3);
- /* All bits in the REX prefix are ignored. */
- rex_ignored = rex;
rex = ~(*codep >> 5) & 0x7;
switch ((*codep & 0x1f))
{
case USE_VEX_C5_TABLE:
/* VEX prefix. */
FETCH_DATA (info, codep + 2);
- /* All bits in the REX prefix are ignored. */
- rex_ignored = rex;
rex = (*codep & 0x80) ? 0 : REX_R;
/* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
/* EVEX prefix. */
vex.evex = 1;
FETCH_DATA (info, codep + 4);
- /* All bits in the REX prefix are ignored. */
- rex_ignored = rex;
/* The first byte after 0x62. */
rex = ~(*codep >> 5) & 0x7;
vex.r = *codep & 0x10;
else if (CONST_STRNEQ (p, "x86-64"))
{
address_mode = mode_64bit;
- priv.orig_sizeflag = AFLAG | DFLAG;
+ priv.orig_sizeflag |= AFLAG | DFLAG;
}
else if (CONST_STRNEQ (p, "i386"))
{
address_mode = mode_32bit;
- priv.orig_sizeflag = AFLAG | DFLAG;
+ priv.orig_sizeflag |= AFLAG | DFLAG;
}
else if (CONST_STRNEQ (p, "i8086"))
{
address_mode = mode_16bit;
- priv.orig_sizeflag = 0;
+ priv.orig_sizeflag &= ~(AFLAG | DFLAG);
}
else if (CONST_STRNEQ (p, "intel"))
{
need_vex = 0;
need_vex_reg = 0;
- vex_w_done = 0;
memset (&vex, 0, sizeof (vex));
if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
}
/* Check if the REX prefix is used. */
- if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
+ if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
all_prefixes[last_rex_prefix] = 0;
/* Check if the SEG prefix is used. */
/* Check if the DATA prefix is used. */
if ((prefixes & PREFIX_DATA) != 0
- && (used_prefixes & PREFIX_DATA) != 0)
+ && (used_prefixes & PREFIX_DATA) != 0
+ && !need_vex)
all_prefixes[last_data_prefix] = 0;
/* Print the extra prefixes. */
PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
separately. */
if (dp->prefix_requirement == PREFIX_OPCODE
- && dp != &bad_opcode
- && (((prefixes
- & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
+ && (((need_vex
+ ? vex.prefix == REPE_PREFIX_OPCODE
+ || vex.prefix == REPNE_PREFIX_OPCODE
+ : (prefixes
+ & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
&& (used_prefixes
& (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
- || ((((prefixes
- & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
- == PREFIX_DATA)
- && (used_prefixes & PREFIX_DATA) == 0))))
+ || (((need_vex
+ ? vex.prefix == DATA_PREFIX_OPCODE
+ : ((prefixes
+ & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
+ == PREFIX_DATA))
+ && (used_prefixes & PREFIX_DATA) == 0))
+ || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA))))
{
(*info->fprintf_func) (info->stream, "(bad)");
return end_codep - priv.the_buffer;
"(bad)",
"fst{s|}",
"fstp{s|}",
- "fldenvIC",
+ "fldenv{C|C}",
"fldcw",
- "fNstenvIC",
+ "fNstenv{C|C}",
"fNstcw",
/* da */
"fiadd{l|}",
"fist{l|}",
"fistp{l|}",
"(bad)",
- "fld{t||t|}",
+ "fld{t|}",
"(bad)",
- "fstp{t||t|}",
+ "fstp{t|}",
/* dc */
"fadd{l|}",
"fmul{l|}",
"fisttp{ll|}",
"fst{l||}",
"fstp{l|}",
- "frstorIC",
+ "frstor{C|C}",
"(bad)",
- "fNsaveIC",
+ "fNsave{C|C}",
"fNstsw",
/* de */
"fiadd{s|}",
const char *p;
int alt = 0;
int cond = 1;
- unsigned int l = 0, len = 1;
+ unsigned int l = 0, len = 0;
char last[4];
-#define SAVE_LAST(c) \
- if (l < len && l < sizeof (last)) \
- last[l++] = c; \
- else \
- abort ();
-
for (p = in_template; *p; p++)
{
+ if (len > l)
+ {
+ if (l >= sizeof (last) || !ISUPPER (*p))
+ abort ();
+ last[l++] = *p;
+ continue;
+ }
switch (*p)
{
default:
while (*++p != '|')
if (*p == '}' || *p == '\0')
abort ();
+ alt = 1;
}
- /* Fall through. */
- case 'I':
- alt = 1;
- continue;
+ break;
case '|':
while (*++p != '}')
{
}
break;
case '}':
+ alt = 0;
break;
case 'A':
if (intel_syntax)
*obufp++ = 'b';
break;
case 'B':
- if (l == 0 && len == 1)
+ if (l == 0)
{
-case_B:
+ case_B:
if (intel_syntax)
break;
if (sizeflag & SUFFIX_ALWAYS)
*obufp++ = 'b';
}
- else
+ else if (l == 1 && last[0] == 'L')
{
- if (l != 1
- || len != 2
- || last[0] != 'L')
- {
- SAVE_LAST (*p);
- break;
- }
-
if (address_mode == mode_64bit
&& !(prefixes & PREFIX_ADDR))
{
goto case_B;
}
+ else
+ abort ();
break;
case 'C':
if (intel_syntax && !alt)
*obufp++ = 'n';
}
break;
- case 'J':
- if (intel_syntax)
- break;
- *obufp++ = 'l';
- break;
case 'K':
USED_REX (REX_W);
if (rex & REX_W)
*obufp++ = 'd';
break;
case 'Z':
- if (l != 0 || len != 1)
+ if (l != 0)
{
- if (l != 1 || len != 2 || last[0] != 'X')
- {
- SAVE_LAST (*p);
- break;
- }
+ if (l != 1 || last[0] != 'X')
+ abort ();
if (!need_vex || !vex.evex)
abort ();
if (intel_syntax
/* Fall through. */
goto case_L;
case 'L':
- if (l != 0 || len != 1)
- {
- SAVE_LAST (*p);
- break;
- }
-case_L:
+ if (l != 0)
+ abort ();
+ case_L:
if (intel_syntax)
break;
if (sizeflag & SUFFIX_ALWAYS)
/* Fall through. */
goto case_P;
case 'P':
- if (l == 0 && len == 1)
+ if (l == 0)
{
-case_P:
+ case_P:
if (intel_syntax)
{
if ((rex & REX_W) == 0
}
}
}
- else
+ else if (l == 1 && last[0] == 'L')
{
- if (l != 1 || len != 2 || last[0] != 'L')
- {
- SAVE_LAST (*p);
- break;
- }
-
if ((prefixes & PREFIX_DATA)
|| (rex & REX_W)
|| (sizeflag & SUFFIX_ALWAYS))
}
}
}
+ else
+ abort ();
break;
case 'U':
if (intel_syntax)
/* Fall through. */
goto case_Q;
case 'Q':
- if (l == 0 && len == 1)
+ if (l == 0)
{
-case_Q:
+ case_Q:
if (intel_syntax && !alt)
break;
USED_REX (REX_W);
}
}
}
- else
+ else if (l == 1 && last[0] == 'L')
{
- if (l != 1 || len != 2 || last[0] != 'L')
- {
- SAVE_LAST (*p);
- break;
- }
- if (intel_syntax
+ if ((intel_syntax && need_modrm)
|| (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
break;
if ((rex & REX_W))
USED_REX (REX_W);
*obufp++ = 'q';
}
- else
- *obufp++ = 'l';
+ else if((address_mode == mode_64bit && need_modrm)
+ || (sizeflag & SUFFIX_ALWAYS))
+ *obufp++ = intel_syntax? 'd' : 'l';
}
+ else
+ abort ();
break;
case 'R':
USED_REX (REX_W);
used_prefixes |= (prefixes & PREFIX_DATA);
break;
case 'V':
- if (l == 0 && len == 1)
+ if (l == 0)
{
if (intel_syntax)
break;
break;
}
}
- else
+ else if (l == 1 && last[0] == 'L')
{
- if (l != 1
- || len != 2
- || last[0] != 'L')
- {
- SAVE_LAST (*p);
- break;
- }
-
if (rex & REX_W)
{
*obufp++ = 'a';
*obufp++ = 's';
}
}
+ else
+ abort ();
/* Fall through. */
goto case_S;
case 'S':
- if (l == 0 && len == 1)
+ if (l == 0)
{
-case_S:
+ case_S:
if (intel_syntax)
break;
if (sizeflag & SUFFIX_ALWAYS)
}
}
}
- else
+ else if (l == 1 && last[0] == 'L')
{
- if (l != 1
- || len != 2
- || last[0] != 'L')
- {
- SAVE_LAST (*p);
- break;
- }
-
if (address_mode == mode_64bit
&& !(prefixes & PREFIX_ADDR))
{
goto case_S;
}
+ else
+ abort ();
break;
case 'X':
- if (l != 0 || len != 1)
- {
- SAVE_LAST (*p);
- break;
- }
- if (need_vex && vex.prefix)
+ if (l != 0)
+ abort ();
+ if (need_vex
+ ? vex.prefix == DATA_PREFIX_OPCODE
+ : prefixes & PREFIX_DATA)
{
- if (vex.prefix == DATA_PREFIX_OPCODE)
- *obufp++ = 'd';
- else
- *obufp++ = 's';
+ *obufp++ = 'd';
+ used_prefixes |= PREFIX_DATA;
}
else
- {
- if (prefixes & PREFIX_DATA)
- *obufp++ = 'd';
- else
- *obufp++ = 's';
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
+ *obufp++ = 's';
break;
case 'Y':
- if (l == 0 && len == 1)
- abort ();
- else
+ if (l == 1 && last[0] == 'X')
{
- if (l != 1 || len != 2 || last[0] != 'X')
- {
- SAVE_LAST (*p);
- break;
- }
if (!need_vex)
abort ();
if (intel_syntax
abort ();
}
}
+ else
+ abort ();
break;
case 'W':
- if (l == 0 && len == 1)
+ if (l == 0)
{
/* operand size flag for cwtl, cbtw */
USED_REX (REX_W);
if (!(rex & REX_W))
used_prefixes |= (prefixes & PREFIX_DATA);
}
- else
+ else if (l == 1)
{
- if (l != 1
- || len != 2
- || (last[0] != 'X'
- && last[0] != 'L'))
- {
- SAVE_LAST (*p);
- break;
- }
if (!need_vex)
abort ();
if (last[0] == 'X')
*obufp++ = vex.w ? 'd': 's';
- else
+ else if (last[0] == 'L')
*obufp++ = vex.w ? 'q': 'd';
+ else if (last[0] == 'B')
+ *obufp++ = vex.w ? 'w': 'b';
+ else
+ abort ();
}
+ else
+ abort ();
break;
case '^':
if (intel_syntax)
}
break;
}
- alt = 0;
+
+ if (len == l)
+ len = l = 0;
}
*obufp = 0;
mnemonicendp = obufp;
used_prefixes |= (prefixes & PREFIX_DATA);
break;
case d_mode:
- case d_scalar_mode:
case d_scalar_swap_mode:
case d_swap_mode:
case dqd_mode:
oappend ("DWORD PTR ");
break;
case q_mode:
- case q_scalar_mode:
case q_scalar_swap_mode:
case q_swap_mode:
oappend ("QWORD PTR ");
break;
case xmm_mq_mode:
case q_mode:
- case q_scalar_mode:
case q_swap_mode:
case q_scalar_swap_mode:
shift = 3;
case dqd_mode:
case xmm_md_mode:
case d_mode:
- case d_scalar_mode:
case d_swap_mode:
case d_scalar_swap_mode:
shift = 2;
}
if ((havebase || haveindex || needindex || needaddr32 || riprel)
- && (bytemode != v_bnd_mode)
- && (bytemode != v_bndmk_mode)
- && (bytemode != bnd_mode)
- && (bytemode != bnd_swap_mode))
+ && (address_mode != mode_64bit
+ || ((bytemode != v_bnd_mode)
+ && (bytemode != v_bndmk_mode)
+ && (bytemode != bnd_mode)
+ && (bytemode != bnd_swap_mode))))
used_prefixes |= PREFIX_ADDR;
if (havedisp || (intel_syntax && riprel))
}
}
}
+ else if (bytemode == v_bnd_mode
+ || bytemode == v_bndmk_mode
+ || bytemode == bnd_mode
+ || bytemode == bnd_swap_mode)
+ {
+ oappend ("(bad)");
+ return;
+ }
else
{
/* 16 bit address mode */
&& bytemode != xmmq_mode
&& bytemode != evex_half_bcst_xmmq_mode
&& bytemode != ymm_mode
- && bytemode != d_scalar_mode
&& bytemode != d_scalar_swap_mode
- && bytemode != q_scalar_mode
&& bytemode != q_scalar_swap_mode
&& bytemode != vex_scalar_w_dq_mode)
{
mnemonicendp = p;
*p = '\0';
-skip:
+ skip:
if (modrm.mod == 3)
{
int add;
oappend (names[reg]);
}
-/* Get the VEX immediate byte without moving codep. */
-
-static unsigned char
-get_vex_imm8 (int sizeflag, int opnum)
-{
- int bytes_before_imm = 0;
-
- if (modrm.mod != 3)
- {
- /* There are SIB/displacement bytes. */
- if ((sizeflag & AFLAG) || address_mode == mode_64bit)
- {
- /* 32/64 bit address mode */
- int base = modrm.rm;
-
- /* Check SIB byte. */
- if (base == 4)
- {
- FETCH_DATA (the_info, codep + 1);
- base = *codep & 7;
- /* When decoding the third source, don't increase
- bytes_before_imm as this has already been incremented
- by one in OP_E_memory while decoding the second
- source operand. */
- if (opnum == 0)
- bytes_before_imm++;
- }
-
- /* Don't increase bytes_before_imm when decoding the third source,
- it has already been incremented by OP_E_memory while decoding
- the second source operand. */
- if (opnum == 0)
- {
- switch (modrm.mod)
- {
- case 0:
- /* When modrm.rm == 5 or modrm.rm == 4 and base in
- SIB == 5, there is a 4 byte displacement. */
- if (base != 5)
- /* No displacement. */
- break;
- /* Fall through. */
- case 2:
- /* 4 byte displacement. */
- bytes_before_imm += 4;
- break;
- case 1:
- /* 1 byte displacement. */
- bytes_before_imm++;
- break;
- }
- }
- }
- else
- {
- /* 16 bit address mode */
- /* Don't increase bytes_before_imm when decoding the third source,
- it has already been incremented by OP_E_memory while decoding
- the second source operand. */
- if (opnum == 0)
- {
- switch (modrm.mod)
- {
- case 0:
- /* When modrm.rm == 6, there is a 2 byte displacement. */
- if (modrm.rm != 6)
- /* No displacement. */
- break;
- /* Fall through. */
- case 2:
- /* 2 byte displacement. */
- bytes_before_imm += 2;
- break;
- case 1:
- /* 1 byte displacement: when decoding the third source,
- don't increase bytes_before_imm as this has already
- been incremented by one in OP_E_memory while decoding
- the second source operand. */
- if (opnum == 0)
- bytes_before_imm++;
-
- break;
- }
- }
- }
- }
-
- FETCH_DATA (the_info, codep + bytes_before_imm + 1);
- return codep [bytes_before_imm];
-}
-
-static void
-OP_EX_VexReg (int bytemode, int sizeflag, int reg)
-{
- const char **names;
-
- if (reg == -1 && modrm.mod != 3)
- {
- OP_E_memory (bytemode, sizeflag);
- return;
- }
- else
- {
- if (reg == -1)
- {
- reg = modrm.rm;
- USED_REX (REX_B);
- if (rex & REX_B)
- reg += 8;
- }
- if (address_mode != mode_64bit)
- reg &= 7;
- }
-
- switch (vex.length)
- {
- case 128:
- names = names_xmm;
- break;
- case 256:
- names = names_ymm;
- break;
- default:
- abort ();
- }
- oappend (names[reg]);
-}
-
static void
-OP_EX_VexImmW (int bytemode, int sizeflag)
+OP_VexW (int bytemode, int sizeflag)
{
- int reg = -1;
- static unsigned char vex_imm8;
-
- if (vex_w_done == 0)
- {
- vex_w_done = 1;
-
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
-
- vex_imm8 = get_vex_imm8 (sizeflag, 0);
-
- if (vex.w)
- reg = vex_imm8 >> 4;
-
- OP_EX_VexReg (bytemode, sizeflag, reg);
- }
- else if (vex_w_done == 1)
- {
- vex_w_done = 2;
-
- if (!vex.w)
- reg = vex_imm8 >> 4;
-
- OP_EX_VexReg (bytemode, sizeflag, reg);
- }
- else
- {
- /* Output the imm8 directly. */
- scratchbuf[0] = '$';
- print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
- oappend_maybe_intel (scratchbuf);
- scratchbuf[0] = '\0';
- codep++;
- }
-}
-
-static void
-OP_Vex_2src (int bytemode, int sizeflag)
-{
- if (modrm.mod == 3)
- {
- int reg = modrm.rm;
- USED_REX (REX_B);
- if (rex & REX_B)
- reg += 8;
- oappend (names_xmm[reg]);
- }
- else
- {
- if (intel_syntax
- && (bytemode == v_mode || bytemode == v_swap_mode))
- {
- bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- OP_E (bytemode, sizeflag);
- }
-}
-
-static void
-OP_Vex_2src_1 (int bytemode, int sizeflag)
-{
- if (modrm.mod == 3)
- {
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
- }
+ OP_VEX (bytemode, sizeflag);
if (vex.w)
{
- unsigned int reg = vex.register_specifier;
- vex.register_specifier = 0;
-
- if (address_mode != mode_64bit)
- reg &= 7;
- oappend (names_xmm[reg]);
+ /* Swap 2nd and 3rd operands. */
+ strcpy (scratchbuf, op_out[2]);
+ strcpy (op_out[2], op_out[1]);
+ strcpy (op_out[1], scratchbuf);
}
- else
- OP_Vex_2src (bytemode, sizeflag);
-}
-
-static void
-OP_Vex_2src_2 (int bytemode, int sizeflag)
-{
- if (vex.w)
- OP_Vex_2src (bytemode, sizeflag);
- else
- {
- unsigned int reg = vex.register_specifier;
- vex.register_specifier = 0;
-
- if (address_mode != mode_64bit)
- reg &= 7;
- oappend (names_xmm[reg]);
- }
-}
-
-static void
-OP_EX_VexW (int bytemode, int sizeflag)
-{
- int reg = -1;
-
- if (!vex_w_done)
- {
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
-
- if (vex.w)
- reg = get_vex_imm8 (sizeflag, 0) >> 4;
- }
- else
- {
- if (!vex.w)
- reg = get_vex_imm8 (sizeflag, 1) >> 4;
- }
-
- OP_EX_VexReg (bytemode, sizeflag, reg);
-
- if (vex_w_done)
- codep++;
- vex_w_done = 1;
}
static void
OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
{
int reg;
- const char **names;
+ const char **names = names_xmm;
FETCH_DATA (the_info, codep + 1);
reg = *codep++;
- if (bytemode != x_mode)
+ if (bytemode != x_mode && bytemode != scalar_mode)
abort ();
reg >>= 4;
if (address_mode != mode_64bit)
reg &= 7;
- switch (vex.length)
+ if (bytemode == x_mode && vex.length == 256)
+ names = names_ymm;
+
+ oappend (names[reg]);
+
+ if (vex.w)
{
- case 128:
- names = names_xmm;
- break;
- case 256:
- names = names_ymm;
- break;
- default:
- abort ();
+ /* Swap 3rd and 4th operands. */
+ strcpy (scratchbuf, op_out[3]);
+ strcpy (op_out[3], op_out[2]);
+ strcpy (op_out[2], scratchbuf);
}
- oappend (names[reg]);
}
static void
-OP_XMM_VexW (int bytemode, int sizeflag)
+OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
+ int sizeflag ATTRIBUTE_UNUSED)
{
- /* Turn off the REX.W bit since it is used for swapping operands
- now. */
- rex &= ~REX_W;
- OP_XMM (bytemode, sizeflag);
+ scratchbuf[0] = '$';
+ print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
+ oappend_maybe_intel (scratchbuf);
}
static void
mnemonicendp = p;
*p = '\0';
-skip:
+ skip:
OP_M (bytemode, sizeflag);
}
break;
}
-skip:
+ skip:
mnemonicendp = p;
*p = '\0';
OP_E (bytemode, sizeflag);
static void
OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
{
- if (!vex.evex
- || (bytemode != evex_rounding_mode
- && bytemode != evex_rounding_64_mode
- && bytemode != evex_sae_mode))
- abort ();
if (modrm.mod == 3 && vex.b)
switch (bytemode)
{
oappend ("{sae}");
break;
default:
+ abort ();
break;
}
}
projects / deliverable / binutils-gdb.git / blobdiff