/* Print i386 instructions for GDB, the GNU debugger.
- Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
- 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
- Free Software Foundation, Inc.
+ Copyright (C) 1988-2016 Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
static void OP_EX_VexImmW (int, int);
static void OP_XMM_Vex (int, int);
static void OP_XMM_VexW (int, int);
+static void OP_Rounding (int, int);
static void OP_REG_VexI4 (int, int);
static void PCLMUL_Fixup (int, int);
static void VEXI4_Fixup (int, int);
static void VZERO_Fixup (int, int);
static void VCMP_Fixup (int, int);
+static void VPCMP_Fixup (int, int);
static void OP_0f07 (int, int);
static void OP_Monitor (int, int);
static void OP_Mwait (int, int);
+static void OP_Mwaitx (int, int);
static void NOP_Fixup1 (int, int);
static void NOP_Fixup2 (int, int);
static void OP_3DNowSuffix (int, int);
static void CMP_Fixup (int, int);
static void BadOp (void);
static void REP_Fixup (int, int);
+static void BND_Fixup (int, int);
+static void HLE_Fixup1 (int, int);
+static void HLE_Fixup2 (int, int);
+static void HLE_Fixup3 (int, int);
static void CMPXCHG8B_Fixup (int, int);
static void XMM_Fixup (int, int);
static void CRC32_Fixup (int, int);
static void MOVBE_Fixup (int, int);
+static void OP_Mask (int, int);
+
struct dis_private {
/* Points to first byte not fetched. */
bfd_byte *max_fetched;
bfd_byte the_buffer[MAX_MNEM_SIZE];
bfd_vma insn_start;
int orig_sizeflag;
- jmp_buf bailout;
+ OPCODES_SIGJMP_BUF bailout;
};
enum address_mode
STATUS. */
if (priv->max_fetched == priv->the_buffer)
(*info->memory_error_func) (status, start, info);
- longjmp (priv->bailout, 1);
+ OPCODES_SIGLONGJMP (priv->bailout, 1);
}
else
priv->max_fetched = addr;
return 1;
}
+/* Possible values for prefix requirement. */
+#define PREFIX_IGNORED_SHIFT 16
+#define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
+#define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
+#define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
+#define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
+#define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
+
+/* Opcode prefixes. */
+#define PREFIX_OPCODE (PREFIX_REPZ \
+ | PREFIX_REPNZ \
+ | PREFIX_DATA)
+
+/* Prefixes ignored. */
+#define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
+ | PREFIX_IGNORED_REPNZ \
+ | PREFIX_IGNORED_DATA)
+
#define XX { NULL, 0 }
-#define Bad_Opcode NULL, { { NULL, 0 } }
+#define Bad_Opcode NULL, { { NULL, 0 } }, 0
#define Eb { OP_E, b_mode }
+#define Ebnd { OP_E, bnd_mode }
#define EbS { OP_E, b_swap_mode }
#define Ev { OP_E, v_mode }
+#define Ev_bnd { OP_E, v_bnd_mode }
#define EvS { OP_E, v_swap_mode }
#define Ed { OP_E, d_mode }
#define Edq { OP_E, dq_mode }
#define Edqw { OP_E, dqw_mode }
+#define EdqwS { OP_E, dqw_swap_mode }
#define Edqb { OP_E, dqb_mode }
+#define Edb { OP_E, db_mode }
+#define Edw { OP_E, dw_mode }
#define Edqd { OP_E, dqd_mode }
#define Eq { OP_E, q_mode }
-#define indirEv { OP_indirE, stack_v_mode }
+#define indirEv { OP_indirE, indir_v_mode }
#define indirEp { OP_indirE, f_mode }
#define stackEv { OP_E, stack_v_mode }
#define Em { OP_E, m_mode }
#define Mx { OP_M, x_mode }
#define Mxmm { OP_M, xmm_mode }
#define Gb { OP_G, b_mode }
+#define Gbnd { OP_G, bnd_mode }
#define Gv { OP_G, v_mode }
#define Gd { OP_G, d_mode }
#define Gdq { OP_G, dq_mode }
#define Gm { OP_G, m_mode }
#define Gw { OP_G, w_mode }
#define Rd { OP_R, d_mode }
+#define Rdq { OP_R, dq_mode }
#define Rm { OP_R, m_mode }
#define Ib { OP_I, b_mode }
#define sIb { OP_sI, b_mode } /* sign extened byte */
+#define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
#define Iv { OP_I, v_mode }
-#define sIv { OP_sI, v_mode }
+#define sIv { OP_sI, v_mode }
#define Iq { OP_I, q_mode }
#define Iv64 { OP_I64, v_mode }
#define Iw { OP_I, w_mode }
#define MX { OP_MMX, 0 }
#define XM { OP_XMM, 0 }
#define XMScalar { OP_XMM, scalar_mode }
+#define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
#define XMM { OP_XMM, xmm_mode }
+#define XMxmmq { OP_XMM, xmmq_mode }
#define EM { OP_EM, v_mode }
#define EMS { OP_EM, v_swap_mode }
#define EMd { OP_EM, d_mode }
#define EXd { OP_EX, d_mode }
#define EXdScalar { OP_EX, d_scalar_mode }
#define EXdS { OP_EX, d_swap_mode }
+#define EXdScalarS { OP_EX, d_scalar_swap_mode }
#define EXq { OP_EX, q_mode }
#define EXqScalar { OP_EX, q_scalar_mode }
#define EXqScalarS { OP_EX, q_scalar_swap_mode }
#define EXx { OP_EX, x_mode }
#define EXxS { OP_EX, x_swap_mode }
#define EXxmm { OP_EX, xmm_mode }
+#define EXymm { OP_EX, ymm_mode }
#define EXxmmq { OP_EX, xmmq_mode }
+#define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
+#define EXxmm_mb { OP_EX, xmm_mb_mode }
+#define EXxmm_mw { OP_EX, xmm_mw_mode }
+#define EXxmm_md { OP_EX, xmm_md_mode }
+#define EXxmm_mq { OP_EX, xmm_mq_mode }
+#define EXxmm_mdq { OP_EX, xmm_mdq_mode }
+#define EXxmmdw { OP_EX, xmmdw_mode }
+#define EXxmmqd { OP_EX, xmmqd_mode }
#define EXymmq { OP_EX, ymmq_mode }
#define EXVexWdq { OP_EX, vex_w_dq_mode }
#define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
+#define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
+#define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
#define MS { OP_MS, v_mode }
#define XS { OP_XS, v_mode }
#define EMCq { OP_EMC, q_mode }
#define Vex { OP_VEX, vex_mode }
#define VexScalar { OP_VEX, vex_scalar_mode }
+#define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
#define Vex128 { OP_VEX, vex128_mode }
#define Vex256 { OP_VEX, vex256_mode }
#define VexGdq { OP_VEX, dq_mode }
#define PCLMUL { PCLMUL_Fixup, 0 }
#define VZERO { VZERO_Fixup, 0 }
#define VCMP { VCMP_Fixup, 0 }
+#define VPCMP { VPCMP_Fixup, 0 }
+
+#define EXxEVexR { OP_Rounding, evex_rounding_mode }
+#define EXxEVexS { OP_Rounding, evex_sae_mode }
+
+#define XMask { OP_Mask, mask_mode }
+#define MaskG { OP_G, mask_mode }
+#define MaskE { OP_E, mask_mode }
+#define MaskBDE { OP_E, mask_bd_mode }
+#define MaskR { OP_R, mask_mode }
+#define MaskVex { OP_VEX, mask_mode }
+
+#define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
+#define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
+#define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
+#define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
/* Used handle "rep" prefix for string instructions. */
#define Xbr { REP_Fixup, eSI_reg }
#define ALr { REP_Fixup, al_reg }
#define eAXr { REP_Fixup, eAX_reg }
+/* Used handle HLE prefix for lockable instructions. */
+#define Ebh1 { HLE_Fixup1, b_mode }
+#define Evh1 { HLE_Fixup1, v_mode }
+#define Ebh2 { HLE_Fixup2, b_mode }
+#define Evh2 { HLE_Fixup2, v_mode }
+#define Ebh3 { HLE_Fixup3, b_mode }
+#define Evh3 { HLE_Fixup3, v_mode }
+
+#define BND { BND_Fixup, 0 }
+
#define cond_jump_flag { NULL, cond_jump_mode }
#define loop_jcxz_flag { NULL, loop_jcxz_mode }
b_mode = 1,
/* byte operand with operand swapped */
b_swap_mode,
+ /* byte operand, sign extend like 'T' suffix */
+ b_T_mode,
/* operand size depends on prefixes */
v_mode,
/* operand size depends on prefixes with operand swapped */
q_swap_mode,
/* ten-byte operand */
t_mode,
- /* 16-byte XMM or 32-byte YMM operand */
+ /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
+ broadcast enabled. */
x_mode,
- /* 16-byte XMM or 32-byte YMM operand with operand swapped */
+ /* Similar to x_mode, but with different EVEX mem shifts. */
+ evex_x_gscat_mode,
+ /* Similar to x_mode, but with disabled broadcast. */
+ evex_x_nobcst_mode,
+ /* Similar to x_mode, but with operands swapped and disabled broadcast
+ in EVEX. */
x_swap_mode,
/* 16-byte XMM operand */
xmm_mode,
- /* 16-byte XMM or quad word operand */
+ /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
+ memory operand (depending on vector length). Broadcast isn't
+ allowed. */
xmmq_mode,
- /* 32-byte YMM or quad word operand */
+ /* Same as xmmq_mode, but broadcast is allowed. */
+ evex_half_bcst_xmmq_mode,
+ /* XMM register or byte memory operand */
+ xmm_mb_mode,
+ /* XMM register or word memory operand */
+ xmm_mw_mode,
+ /* XMM register or double word memory operand */
+ xmm_md_mode,
+ /* XMM register or quad word memory operand */
+ xmm_mq_mode,
+ /* XMM register or double/quad word memory operand, depending on
+ VEX.W. */
+ xmm_mdq_mode,
+ /* 16-byte XMM, word, double word or quad word operand. */
+ xmmdw_mode,
+ /* 16-byte XMM, double word, quad word operand or xmm word operand. */
+ xmmqd_mode,
+ /* 32-byte YMM operand */
+ ymm_mode,
+ /* quad word, ymmword or zmmword memory operand. */
ymmq_mode,
+ /* 32-byte YMM or 16-byte word operand */
+ ymmxmm_mode,
/* d_mode in 32bit, q_mode in 64bit mode. */
m_mode,
/* pair of v_mode operands */
a_mode,
cond_jump_mode,
loop_jcxz_mode,
+ v_bnd_mode,
/* operand size depends on REX prefixes. */
dq_mode,
/* registers like dq_mode, memory like w_mode. */
dqw_mode,
+ dqw_swap_mode,
+ bnd_mode,
/* 4- or 6-byte pointer operand */
f_mode,
const_1_mode,
+ /* v_mode for indirect branch opcodes. */
+ indir_v_mode,
/* v_mode for stack-related opcodes. */
stack_v_mode,
/* non-quad operand size depends on prefixes */
o_mode,
/* registers like dq_mode, memory like b_mode. */
dqb_mode,
+ /* registers like d_mode, memory like b_mode. */
+ db_mode,
+ /* registers like d_mode, memory like w_mode. */
+ dw_mode,
/* registers like dq_mode, memory like d_mode. */
dqd_mode,
/* normal vex mode */
/* operand size depends on the VEX.W bit. */
vex_w_dq_mode,
+ /* Similar to vex_w_dq_mode, with VSIB dword indices. */
+ vex_vsib_d_w_dq_mode,
+ /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
+ vex_vsib_d_w_d_mode,
+ /* Similar to vex_w_dq_mode, with VSIB qword indices. */
+ vex_vsib_q_w_dq_mode,
+ /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
+ vex_vsib_q_w_d_mode,
+
/* scalar, ignore vector length. */
scalar_mode,
/* like d_mode, ignore vector length. */
/* like vex_w_dq_mode, ignore vector length. */
vex_scalar_w_dq_mode,
+ /* Static rounding. */
+ evex_rounding_mode,
+ /* Supress all exceptions. */
+ evex_sae_mode,
+
+ /* Mask register operand. */
+ mask_mode,
+ /* Mask register operand. */
+ mask_bd_mode,
+
es_reg,
cs_reg,
ss_reg,
USE_VEX_C4_TABLE,
USE_VEX_C5_TABLE,
USE_VEX_LEN_TABLE,
- USE_VEX_W_TABLE
+ USE_VEX_W_TABLE,
+ USE_EVEX_TABLE
};
-#define FLOAT NULL, { { NULL, FLOATCODE } }
+#define FLOAT NULL, { { NULL, FLOATCODE } }, 0
-#define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
+#define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
+#define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
#define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
#define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
#define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
#define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
#define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
#define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
+#define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
#define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
#define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
#define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
#define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
#define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
+#define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
enum
{
REG_VEX_0F72,
REG_VEX_0F73,
REG_VEX_0FAE,
+ REG_VEX_0F38F3,
REG_XOP_LWPCB,
- REG_XOP_LWP
+ REG_XOP_LWP,
+ REG_XOP_TBM_01,
+ REG_XOP_TBM_02,
+
+ REG_EVEX_0F71,
+ REG_EVEX_0F72,
+ REG_EVEX_0F73,
+ REG_EVEX_0F38C6,
+ REG_EVEX_0F38C7
};
enum
{
MOD_8D = 0,
+ MOD_C6_REG_7,
+ MOD_C7_REG_7,
+ MOD_FF_REG_3,
+ MOD_FF_REG_5,
MOD_0F01_REG_0,
MOD_0F01_REG_1,
MOD_0F01_REG_2,
MOD_0F01_REG_3,
+ MOD_0F01_REG_5,
MOD_0F01_REG_7,
MOD_0F12_PREFIX_0,
MOD_0F13,
MOD_0F18_REG_1,
MOD_0F18_REG_2,
MOD_0F18_REG_3,
- MOD_0F20,
- MOD_0F21,
- MOD_0F22,
- MOD_0F23,
+ MOD_0F18_REG_4,
+ MOD_0F18_REG_5,
+ MOD_0F18_REG_6,
+ MOD_0F18_REG_7,
+ MOD_0F1A_PREFIX_0,
+ MOD_0F1B_PREFIX_0,
+ MOD_0F1B_PREFIX_1,
MOD_0F24,
MOD_0F26,
MOD_0F2B_PREFIX_0,
MOD_0FB2,
MOD_0FB4,
MOD_0FB5,
+ MOD_0FC3,
+ MOD_0FC7_REG_3,
+ MOD_0FC7_REG_4,
+ MOD_0FC7_REG_5,
MOD_0FC7_REG_6,
MOD_0FC7_REG_7,
MOD_0FD7,
MOD_VEX_0F16_PREFIX_0,
MOD_VEX_0F17,
MOD_VEX_0F2B,
+ MOD_VEX_W_0_0F41_P_0_LEN_1,
+ MOD_VEX_W_1_0F41_P_0_LEN_1,
+ MOD_VEX_W_0_0F41_P_2_LEN_1,
+ MOD_VEX_W_1_0F41_P_2_LEN_1,
+ MOD_VEX_W_0_0F42_P_0_LEN_1,
+ MOD_VEX_W_1_0F42_P_0_LEN_1,
+ MOD_VEX_W_0_0F42_P_2_LEN_1,
+ MOD_VEX_W_1_0F42_P_2_LEN_1,
+ MOD_VEX_W_0_0F44_P_0_LEN_1,
+ MOD_VEX_W_1_0F44_P_0_LEN_1,
+ MOD_VEX_W_0_0F44_P_2_LEN_1,
+ MOD_VEX_W_1_0F44_P_2_LEN_1,
+ MOD_VEX_W_0_0F45_P_0_LEN_1,
+ MOD_VEX_W_1_0F45_P_0_LEN_1,
+ MOD_VEX_W_0_0F45_P_2_LEN_1,
+ MOD_VEX_W_1_0F45_P_2_LEN_1,
+ MOD_VEX_W_0_0F46_P_0_LEN_1,
+ MOD_VEX_W_1_0F46_P_0_LEN_1,
+ MOD_VEX_W_0_0F46_P_2_LEN_1,
+ MOD_VEX_W_1_0F46_P_2_LEN_1,
+ MOD_VEX_W_0_0F47_P_0_LEN_1,
+ MOD_VEX_W_1_0F47_P_0_LEN_1,
+ MOD_VEX_W_0_0F47_P_2_LEN_1,
+ MOD_VEX_W_1_0F47_P_2_LEN_1,
+ MOD_VEX_W_0_0F4A_P_0_LEN_1,
+ MOD_VEX_W_1_0F4A_P_0_LEN_1,
+ MOD_VEX_W_0_0F4A_P_2_LEN_1,
+ MOD_VEX_W_1_0F4A_P_2_LEN_1,
+ MOD_VEX_W_0_0F4B_P_0_LEN_1,
+ MOD_VEX_W_1_0F4B_P_0_LEN_1,
+ MOD_VEX_W_0_0F4B_P_2_LEN_1,
MOD_VEX_0F50,
MOD_VEX_0F71_REG_2,
MOD_VEX_0F71_REG_4,
MOD_VEX_0F73_REG_3,
MOD_VEX_0F73_REG_6,
MOD_VEX_0F73_REG_7,
+ MOD_VEX_W_0_0F91_P_0_LEN_0,
+ MOD_VEX_W_1_0F91_P_0_LEN_0,
+ MOD_VEX_W_0_0F91_P_2_LEN_0,
+ MOD_VEX_W_1_0F91_P_2_LEN_0,
+ MOD_VEX_W_0_0F92_P_0_LEN_0,
+ MOD_VEX_W_0_0F92_P_2_LEN_0,
+ MOD_VEX_W_0_0F92_P_3_LEN_0,
+ MOD_VEX_W_1_0F92_P_3_LEN_0,
+ MOD_VEX_W_0_0F93_P_0_LEN_0,
+ MOD_VEX_W_0_0F93_P_2_LEN_0,
+ MOD_VEX_W_0_0F93_P_3_LEN_0,
+ MOD_VEX_W_1_0F93_P_3_LEN_0,
+ MOD_VEX_W_0_0F98_P_0_LEN_0,
+ MOD_VEX_W_1_0F98_P_0_LEN_0,
+ MOD_VEX_W_0_0F98_P_2_LEN_0,
+ MOD_VEX_W_1_0F98_P_2_LEN_0,
+ MOD_VEX_W_0_0F99_P_0_LEN_0,
+ MOD_VEX_W_1_0F99_P_0_LEN_0,
+ MOD_VEX_W_0_0F99_P_2_LEN_0,
+ MOD_VEX_W_1_0F99_P_2_LEN_0,
MOD_VEX_0FAE_REG_2,
MOD_VEX_0FAE_REG_3,
MOD_VEX_0FD7_PREFIX_2,
MOD_VEX_0FE7_PREFIX_2,
MOD_VEX_0FF0_PREFIX_3,
- MOD_VEX_0F3818_PREFIX_2,
- MOD_VEX_0F3819_PREFIX_2,
MOD_VEX_0F381A_PREFIX_2,
MOD_VEX_0F382A_PREFIX_2,
MOD_VEX_0F382C_PREFIX_2,
MOD_VEX_0F382D_PREFIX_2,
MOD_VEX_0F382E_PREFIX_2,
- MOD_VEX_0F382F_PREFIX_2
+ MOD_VEX_0F382F_PREFIX_2,
+ MOD_VEX_0F385A_PREFIX_2,
+ MOD_VEX_0F388C_PREFIX_2,
+ MOD_VEX_0F388E_PREFIX_2,
+ MOD_VEX_W_0_0F3A30_P_2_LEN_0,
+ MOD_VEX_W_1_0F3A30_P_2_LEN_0,
+ MOD_VEX_W_0_0F3A31_P_2_LEN_0,
+ MOD_VEX_W_1_0F3A31_P_2_LEN_0,
+ MOD_VEX_W_0_0F3A32_P_2_LEN_0,
+ MOD_VEX_W_1_0F3A32_P_2_LEN_0,
+ MOD_VEX_W_0_0F3A33_P_2_LEN_0,
+ MOD_VEX_W_1_0F3A33_P_2_LEN_0,
+
+ MOD_EVEX_0F10_PREFIX_1,
+ MOD_EVEX_0F10_PREFIX_3,
+ MOD_EVEX_0F11_PREFIX_1,
+ MOD_EVEX_0F11_PREFIX_3,
+ MOD_EVEX_0F12_PREFIX_0,
+ MOD_EVEX_0F16_PREFIX_0,
+ MOD_EVEX_0F38C6_REG_1,
+ MOD_EVEX_0F38C6_REG_2,
+ MOD_EVEX_0F38C6_REG_5,
+ MOD_EVEX_0F38C6_REG_6,
+ MOD_EVEX_0F38C7_REG_1,
+ MOD_EVEX_0F38C7_REG_2,
+ MOD_EVEX_0F38C7_REG_5,
+ MOD_EVEX_0F38C7_REG_6
};
enum
{
- RM_0F01_REG_0 = 0,
+ RM_C6_REG_7 = 0,
+ RM_C7_REG_7,
+ RM_0F01_REG_0,
RM_0F01_REG_1,
RM_0F01_REG_2,
RM_0F01_REG_3,
+ RM_0F01_REG_5,
RM_0F01_REG_7,
RM_0FAE_REG_5,
RM_0FAE_REG_6,
PREFIX_0F11,
PREFIX_0F12,
PREFIX_0F16,
+ PREFIX_0F1A,
+ PREFIX_0F1B,
PREFIX_0F2A,
PREFIX_0F2B,
PREFIX_0F2C,
PREFIX_0FAE_REG_1,
PREFIX_0FAE_REG_2,
PREFIX_0FAE_REG_3,
+ PREFIX_MOD_0_0FAE_REG_4,
+ PREFIX_MOD_3_0FAE_REG_4,
+ PREFIX_0FAE_REG_6,
+ PREFIX_0FAE_REG_7,
+ PREFIX_RM_0_0FAE_REG_7,
PREFIX_0FB8,
+ PREFIX_0FBC,
PREFIX_0FBD,
PREFIX_0FC2,
- PREFIX_0FC3,
- PREFIX_0FC7_REG_6,
+ PREFIX_MOD_0_0FC3,
+ PREFIX_MOD_0_0FC7_REG_6,
+ PREFIX_MOD_3_0FC7_REG_6,
+ PREFIX_MOD_3_0FC7_REG_7,
PREFIX_0FD0,
PREFIX_0FD6,
PREFIX_0FE6,
PREFIX_0F3841,
PREFIX_0F3880,
PREFIX_0F3881,
+ PREFIX_0F3882,
+ PREFIX_0F38C8,
+ PREFIX_0F38C9,
+ PREFIX_0F38CA,
+ PREFIX_0F38CB,
+ PREFIX_0F38CC,
+ PREFIX_0F38CD,
PREFIX_0F38DB,
PREFIX_0F38DC,
PREFIX_0F38DD,
PREFIX_0F38DF,
PREFIX_0F38F0,
PREFIX_0F38F1,
+ PREFIX_0F38F6,
PREFIX_0F3A08,
PREFIX_0F3A09,
PREFIX_0F3A0A,
PREFIX_0F3A61,
PREFIX_0F3A62,
PREFIX_0F3A63,
+ PREFIX_0F3ACC,
PREFIX_0F3ADF,
PREFIX_VEX_0F10,
PREFIX_VEX_0F11,
PREFIX_VEX_0F2D,
PREFIX_VEX_0F2E,
PREFIX_VEX_0F2F,
+ PREFIX_VEX_0F41,
+ PREFIX_VEX_0F42,
+ PREFIX_VEX_0F44,
+ PREFIX_VEX_0F45,
+ PREFIX_VEX_0F46,
+ PREFIX_VEX_0F47,
+ PREFIX_VEX_0F4A,
+ PREFIX_VEX_0F4B,
PREFIX_VEX_0F51,
PREFIX_VEX_0F52,
PREFIX_VEX_0F53,
PREFIX_VEX_0F7D,
PREFIX_VEX_0F7E,
PREFIX_VEX_0F7F,
+ PREFIX_VEX_0F90,
+ PREFIX_VEX_0F91,
+ PREFIX_VEX_0F92,
+ PREFIX_VEX_0F93,
+ PREFIX_VEX_0F98,
+ PREFIX_VEX_0F99,
PREFIX_VEX_0FC2,
PREFIX_VEX_0FC4,
PREFIX_VEX_0FC5,
PREFIX_VEX_0F380E,
PREFIX_VEX_0F380F,
PREFIX_VEX_0F3813,
+ PREFIX_VEX_0F3816,
PREFIX_VEX_0F3817,
PREFIX_VEX_0F3818,
PREFIX_VEX_0F3819,
PREFIX_VEX_0F3833,
PREFIX_VEX_0F3834,
PREFIX_VEX_0F3835,
+ PREFIX_VEX_0F3836,
PREFIX_VEX_0F3837,
PREFIX_VEX_0F3838,
PREFIX_VEX_0F3839,
PREFIX_VEX_0F383F,
PREFIX_VEX_0F3840,
PREFIX_VEX_0F3841,
+ PREFIX_VEX_0F3845,
+ PREFIX_VEX_0F3846,
+ PREFIX_VEX_0F3847,
+ PREFIX_VEX_0F3858,
+ PREFIX_VEX_0F3859,
+ PREFIX_VEX_0F385A,
+ PREFIX_VEX_0F3878,
+ PREFIX_VEX_0F3879,
+ PREFIX_VEX_0F388C,
+ PREFIX_VEX_0F388E,
+ PREFIX_VEX_0F3890,
+ PREFIX_VEX_0F3891,
+ PREFIX_VEX_0F3892,
+ PREFIX_VEX_0F3893,
PREFIX_VEX_0F3896,
PREFIX_VEX_0F3897,
PREFIX_VEX_0F3898,
PREFIX_VEX_0F38DD,
PREFIX_VEX_0F38DE,
PREFIX_VEX_0F38DF,
+ PREFIX_VEX_0F38F2,
+ PREFIX_VEX_0F38F3_REG_1,
+ PREFIX_VEX_0F38F3_REG_2,
+ PREFIX_VEX_0F38F3_REG_3,
+ PREFIX_VEX_0F38F5,
+ PREFIX_VEX_0F38F6,
+ PREFIX_VEX_0F38F7,
+ PREFIX_VEX_0F3A00,
+ PREFIX_VEX_0F3A01,
+ PREFIX_VEX_0F3A02,
PREFIX_VEX_0F3A04,
PREFIX_VEX_0F3A05,
PREFIX_VEX_0F3A06,
PREFIX_VEX_0F3A20,
PREFIX_VEX_0F3A21,
PREFIX_VEX_0F3A22,
+ PREFIX_VEX_0F3A30,
+ PREFIX_VEX_0F3A31,
+ PREFIX_VEX_0F3A32,
+ PREFIX_VEX_0F3A33,
+ PREFIX_VEX_0F3A38,
+ PREFIX_VEX_0F3A39,
PREFIX_VEX_0F3A40,
PREFIX_VEX_0F3A41,
PREFIX_VEX_0F3A42,
PREFIX_VEX_0F3A44,
+ PREFIX_VEX_0F3A46,
PREFIX_VEX_0F3A48,
PREFIX_VEX_0F3A49,
PREFIX_VEX_0F3A4A,
PREFIX_VEX_0F3A7D,
PREFIX_VEX_0F3A7E,
PREFIX_VEX_0F3A7F,
- PREFIX_VEX_0F3ADF
+ PREFIX_VEX_0F3ADF,
+ PREFIX_VEX_0F3AF0,
+
+ PREFIX_EVEX_0F10,
+ PREFIX_EVEX_0F11,
+ PREFIX_EVEX_0F12,
+ PREFIX_EVEX_0F13,
+ PREFIX_EVEX_0F14,
+ PREFIX_EVEX_0F15,
+ PREFIX_EVEX_0F16,
+ PREFIX_EVEX_0F17,
+ PREFIX_EVEX_0F28,
+ PREFIX_EVEX_0F29,
+ PREFIX_EVEX_0F2A,
+ PREFIX_EVEX_0F2B,
+ PREFIX_EVEX_0F2C,
+ PREFIX_EVEX_0F2D,
+ PREFIX_EVEX_0F2E,
+ PREFIX_EVEX_0F2F,
+ PREFIX_EVEX_0F51,
+ PREFIX_EVEX_0F54,
+ PREFIX_EVEX_0F55,
+ PREFIX_EVEX_0F56,
+ PREFIX_EVEX_0F57,
+ PREFIX_EVEX_0F58,
+ PREFIX_EVEX_0F59,
+ PREFIX_EVEX_0F5A,
+ PREFIX_EVEX_0F5B,
+ PREFIX_EVEX_0F5C,
+ PREFIX_EVEX_0F5D,
+ PREFIX_EVEX_0F5E,
+ PREFIX_EVEX_0F5F,
+ PREFIX_EVEX_0F60,
+ PREFIX_EVEX_0F61,
+ PREFIX_EVEX_0F62,
+ PREFIX_EVEX_0F63,
+ PREFIX_EVEX_0F64,
+ PREFIX_EVEX_0F65,
+ PREFIX_EVEX_0F66,
+ PREFIX_EVEX_0F67,
+ PREFIX_EVEX_0F68,
+ PREFIX_EVEX_0F69,
+ PREFIX_EVEX_0F6A,
+ PREFIX_EVEX_0F6B,
+ PREFIX_EVEX_0F6C,
+ PREFIX_EVEX_0F6D,
+ PREFIX_EVEX_0F6E,
+ PREFIX_EVEX_0F6F,
+ PREFIX_EVEX_0F70,
+ PREFIX_EVEX_0F71_REG_2,
+ PREFIX_EVEX_0F71_REG_4,
+ PREFIX_EVEX_0F71_REG_6,
+ PREFIX_EVEX_0F72_REG_0,
+ PREFIX_EVEX_0F72_REG_1,
+ PREFIX_EVEX_0F72_REG_2,
+ PREFIX_EVEX_0F72_REG_4,
+ PREFIX_EVEX_0F72_REG_6,
+ PREFIX_EVEX_0F73_REG_2,
+ PREFIX_EVEX_0F73_REG_3,
+ PREFIX_EVEX_0F73_REG_6,
+ PREFIX_EVEX_0F73_REG_7,
+ PREFIX_EVEX_0F74,
+ PREFIX_EVEX_0F75,
+ PREFIX_EVEX_0F76,
+ PREFIX_EVEX_0F78,
+ PREFIX_EVEX_0F79,
+ PREFIX_EVEX_0F7A,
+ PREFIX_EVEX_0F7B,
+ PREFIX_EVEX_0F7E,
+ PREFIX_EVEX_0F7F,
+ PREFIX_EVEX_0FC2,
+ PREFIX_EVEX_0FC4,
+ PREFIX_EVEX_0FC5,
+ PREFIX_EVEX_0FC6,
+ PREFIX_EVEX_0FD1,
+ PREFIX_EVEX_0FD2,
+ PREFIX_EVEX_0FD3,
+ PREFIX_EVEX_0FD4,
+ PREFIX_EVEX_0FD5,
+ PREFIX_EVEX_0FD6,
+ PREFIX_EVEX_0FD8,
+ PREFIX_EVEX_0FD9,
+ PREFIX_EVEX_0FDA,
+ PREFIX_EVEX_0FDB,
+ PREFIX_EVEX_0FDC,
+ PREFIX_EVEX_0FDD,
+ PREFIX_EVEX_0FDE,
+ PREFIX_EVEX_0FDF,
+ PREFIX_EVEX_0FE0,
+ PREFIX_EVEX_0FE1,
+ PREFIX_EVEX_0FE2,
+ PREFIX_EVEX_0FE3,
+ PREFIX_EVEX_0FE4,
+ PREFIX_EVEX_0FE5,
+ PREFIX_EVEX_0FE6,
+ PREFIX_EVEX_0FE7,
+ PREFIX_EVEX_0FE8,
+ PREFIX_EVEX_0FE9,
+ PREFIX_EVEX_0FEA,
+ PREFIX_EVEX_0FEB,
+ PREFIX_EVEX_0FEC,
+ PREFIX_EVEX_0FED,
+ PREFIX_EVEX_0FEE,
+ PREFIX_EVEX_0FEF,
+ PREFIX_EVEX_0FF1,
+ PREFIX_EVEX_0FF2,
+ PREFIX_EVEX_0FF3,
+ PREFIX_EVEX_0FF4,
+ PREFIX_EVEX_0FF5,
+ PREFIX_EVEX_0FF6,
+ PREFIX_EVEX_0FF8,
+ PREFIX_EVEX_0FF9,
+ PREFIX_EVEX_0FFA,
+ PREFIX_EVEX_0FFB,
+ PREFIX_EVEX_0FFC,
+ PREFIX_EVEX_0FFD,
+ PREFIX_EVEX_0FFE,
+ PREFIX_EVEX_0F3800,
+ PREFIX_EVEX_0F3804,
+ PREFIX_EVEX_0F380B,
+ PREFIX_EVEX_0F380C,
+ PREFIX_EVEX_0F380D,
+ PREFIX_EVEX_0F3810,
+ PREFIX_EVEX_0F3811,
+ PREFIX_EVEX_0F3812,
+ PREFIX_EVEX_0F3813,
+ PREFIX_EVEX_0F3814,
+ PREFIX_EVEX_0F3815,
+ PREFIX_EVEX_0F3816,
+ PREFIX_EVEX_0F3818,
+ PREFIX_EVEX_0F3819,
+ PREFIX_EVEX_0F381A,
+ PREFIX_EVEX_0F381B,
+ PREFIX_EVEX_0F381C,
+ PREFIX_EVEX_0F381D,
+ PREFIX_EVEX_0F381E,
+ PREFIX_EVEX_0F381F,
+ PREFIX_EVEX_0F3820,
+ PREFIX_EVEX_0F3821,
+ PREFIX_EVEX_0F3822,
+ PREFIX_EVEX_0F3823,
+ PREFIX_EVEX_0F3824,
+ PREFIX_EVEX_0F3825,
+ PREFIX_EVEX_0F3826,
+ PREFIX_EVEX_0F3827,
+ PREFIX_EVEX_0F3828,
+ PREFIX_EVEX_0F3829,
+ PREFIX_EVEX_0F382A,
+ PREFIX_EVEX_0F382B,
+ PREFIX_EVEX_0F382C,
+ PREFIX_EVEX_0F382D,
+ PREFIX_EVEX_0F3830,
+ PREFIX_EVEX_0F3831,
+ PREFIX_EVEX_0F3832,
+ PREFIX_EVEX_0F3833,
+ PREFIX_EVEX_0F3834,
+ PREFIX_EVEX_0F3835,
+ PREFIX_EVEX_0F3836,
+ PREFIX_EVEX_0F3837,
+ PREFIX_EVEX_0F3838,
+ PREFIX_EVEX_0F3839,
+ PREFIX_EVEX_0F383A,
+ PREFIX_EVEX_0F383B,
+ PREFIX_EVEX_0F383C,
+ PREFIX_EVEX_0F383D,
+ PREFIX_EVEX_0F383E,
+ PREFIX_EVEX_0F383F,
+ PREFIX_EVEX_0F3840,
+ PREFIX_EVEX_0F3842,
+ PREFIX_EVEX_0F3843,
+ PREFIX_EVEX_0F3844,
+ PREFIX_EVEX_0F3845,
+ PREFIX_EVEX_0F3846,
+ PREFIX_EVEX_0F3847,
+ PREFIX_EVEX_0F384C,
+ PREFIX_EVEX_0F384D,
+ PREFIX_EVEX_0F384E,
+ PREFIX_EVEX_0F384F,
+ PREFIX_EVEX_0F3858,
+ PREFIX_EVEX_0F3859,
+ PREFIX_EVEX_0F385A,
+ PREFIX_EVEX_0F385B,
+ PREFIX_EVEX_0F3864,
+ PREFIX_EVEX_0F3865,
+ PREFIX_EVEX_0F3866,
+ PREFIX_EVEX_0F3875,
+ PREFIX_EVEX_0F3876,
+ PREFIX_EVEX_0F3877,
+ PREFIX_EVEX_0F3878,
+ PREFIX_EVEX_0F3879,
+ PREFIX_EVEX_0F387A,
+ PREFIX_EVEX_0F387B,
+ PREFIX_EVEX_0F387C,
+ PREFIX_EVEX_0F387D,
+ PREFIX_EVEX_0F387E,
+ PREFIX_EVEX_0F387F,
+ PREFIX_EVEX_0F3883,
+ PREFIX_EVEX_0F3888,
+ PREFIX_EVEX_0F3889,
+ PREFIX_EVEX_0F388A,
+ PREFIX_EVEX_0F388B,
+ PREFIX_EVEX_0F388D,
+ PREFIX_EVEX_0F3890,
+ PREFIX_EVEX_0F3891,
+ PREFIX_EVEX_0F3892,
+ PREFIX_EVEX_0F3893,
+ PREFIX_EVEX_0F3896,
+ PREFIX_EVEX_0F3897,
+ PREFIX_EVEX_0F3898,
+ PREFIX_EVEX_0F3899,
+ PREFIX_EVEX_0F389A,
+ PREFIX_EVEX_0F389B,
+ PREFIX_EVEX_0F389C,
+ PREFIX_EVEX_0F389D,
+ PREFIX_EVEX_0F389E,
+ PREFIX_EVEX_0F389F,
+ PREFIX_EVEX_0F38A0,
+ PREFIX_EVEX_0F38A1,
+ PREFIX_EVEX_0F38A2,
+ PREFIX_EVEX_0F38A3,
+ PREFIX_EVEX_0F38A6,
+ PREFIX_EVEX_0F38A7,
+ PREFIX_EVEX_0F38A8,
+ PREFIX_EVEX_0F38A9,
+ PREFIX_EVEX_0F38AA,
+ PREFIX_EVEX_0F38AB,
+ PREFIX_EVEX_0F38AC,
+ PREFIX_EVEX_0F38AD,
+ PREFIX_EVEX_0F38AE,
+ PREFIX_EVEX_0F38AF,
+ PREFIX_EVEX_0F38B4,
+ PREFIX_EVEX_0F38B5,
+ PREFIX_EVEX_0F38B6,
+ PREFIX_EVEX_0F38B7,
+ PREFIX_EVEX_0F38B8,
+ PREFIX_EVEX_0F38B9,
+ PREFIX_EVEX_0F38BA,
+ PREFIX_EVEX_0F38BB,
+ PREFIX_EVEX_0F38BC,
+ PREFIX_EVEX_0F38BD,
+ PREFIX_EVEX_0F38BE,
+ PREFIX_EVEX_0F38BF,
+ PREFIX_EVEX_0F38C4,
+ PREFIX_EVEX_0F38C6_REG_1,
+ PREFIX_EVEX_0F38C6_REG_2,
+ PREFIX_EVEX_0F38C6_REG_5,
+ PREFIX_EVEX_0F38C6_REG_6,
+ PREFIX_EVEX_0F38C7_REG_1,
+ PREFIX_EVEX_0F38C7_REG_2,
+ PREFIX_EVEX_0F38C7_REG_5,
+ PREFIX_EVEX_0F38C7_REG_6,
+ PREFIX_EVEX_0F38C8,
+ PREFIX_EVEX_0F38CA,
+ PREFIX_EVEX_0F38CB,
+ PREFIX_EVEX_0F38CC,
+ PREFIX_EVEX_0F38CD,
+
+ PREFIX_EVEX_0F3A00,
+ PREFIX_EVEX_0F3A01,
+ PREFIX_EVEX_0F3A03,
+ PREFIX_EVEX_0F3A04,
+ PREFIX_EVEX_0F3A05,
+ PREFIX_EVEX_0F3A08,
+ PREFIX_EVEX_0F3A09,
+ PREFIX_EVEX_0F3A0A,
+ PREFIX_EVEX_0F3A0B,
+ PREFIX_EVEX_0F3A0F,
+ PREFIX_EVEX_0F3A14,
+ PREFIX_EVEX_0F3A15,
+ PREFIX_EVEX_0F3A16,
+ PREFIX_EVEX_0F3A17,
+ PREFIX_EVEX_0F3A18,
+ PREFIX_EVEX_0F3A19,
+ PREFIX_EVEX_0F3A1A,
+ PREFIX_EVEX_0F3A1B,
+ PREFIX_EVEX_0F3A1D,
+ PREFIX_EVEX_0F3A1E,
+ PREFIX_EVEX_0F3A1F,
+ PREFIX_EVEX_0F3A20,
+ PREFIX_EVEX_0F3A21,
+ PREFIX_EVEX_0F3A22,
+ PREFIX_EVEX_0F3A23,
+ PREFIX_EVEX_0F3A25,
+ PREFIX_EVEX_0F3A26,
+ PREFIX_EVEX_0F3A27,
+ PREFIX_EVEX_0F3A38,
+ PREFIX_EVEX_0F3A39,
+ PREFIX_EVEX_0F3A3A,
+ PREFIX_EVEX_0F3A3B,
+ PREFIX_EVEX_0F3A3E,
+ PREFIX_EVEX_0F3A3F,
+ PREFIX_EVEX_0F3A42,
+ PREFIX_EVEX_0F3A43,
+ PREFIX_EVEX_0F3A50,
+ PREFIX_EVEX_0F3A51,
+ PREFIX_EVEX_0F3A54,
+ PREFIX_EVEX_0F3A55,
+ PREFIX_EVEX_0F3A56,
+ PREFIX_EVEX_0F3A57,
+ PREFIX_EVEX_0F3A66,
+ PREFIX_EVEX_0F3A67
};
enum
X86_64_CE,
X86_64_D4,
X86_64_D5,
+ X86_64_E8,
+ X86_64_E9,
X86_64_EA,
X86_64_0F01_REG_0,
X86_64_0F01_REG_1,
VEX_0F3A
};
+enum
+{
+ EVEX_0F = 0,
+ EVEX_0F38,
+ EVEX_0F3A
+};
+
enum
{
VEX_LEN_0F10_P_1 = 0,
VEX_LEN_0F2E_P_2,
VEX_LEN_0F2F_P_0,
VEX_LEN_0F2F_P_2,
+ VEX_LEN_0F41_P_0,
+ VEX_LEN_0F41_P_2,
+ VEX_LEN_0F42_P_0,
+ VEX_LEN_0F42_P_2,
+ VEX_LEN_0F44_P_0,
+ VEX_LEN_0F44_P_2,
+ VEX_LEN_0F45_P_0,
+ VEX_LEN_0F45_P_2,
+ VEX_LEN_0F46_P_0,
+ VEX_LEN_0F46_P_2,
+ VEX_LEN_0F47_P_0,
+ VEX_LEN_0F47_P_2,
+ VEX_LEN_0F4A_P_0,
+ VEX_LEN_0F4A_P_2,
+ VEX_LEN_0F4B_P_0,
+ VEX_LEN_0F4B_P_2,
VEX_LEN_0F51_P_1,
VEX_LEN_0F51_P_3,
VEX_LEN_0F52_P_1,
VEX_LEN_0F5E_P_3,
VEX_LEN_0F5F_P_1,
VEX_LEN_0F5F_P_3,
- VEX_LEN_0F60_P_2,
- VEX_LEN_0F61_P_2,
- VEX_LEN_0F62_P_2,
- VEX_LEN_0F63_P_2,
- VEX_LEN_0F64_P_2,
- VEX_LEN_0F65_P_2,
- VEX_LEN_0F66_P_2,
- VEX_LEN_0F67_P_2,
- VEX_LEN_0F68_P_2,
- VEX_LEN_0F69_P_2,
- VEX_LEN_0F6A_P_2,
- VEX_LEN_0F6B_P_2,
- VEX_LEN_0F6C_P_2,
- VEX_LEN_0F6D_P_2,
VEX_LEN_0F6E_P_2,
- VEX_LEN_0F70_P_1,
- VEX_LEN_0F70_P_2,
- VEX_LEN_0F70_P_3,
- VEX_LEN_0F71_R_2_P_2,
- VEX_LEN_0F71_R_4_P_2,
- VEX_LEN_0F71_R_6_P_2,
- VEX_LEN_0F72_R_2_P_2,
- VEX_LEN_0F72_R_4_P_2,
- VEX_LEN_0F72_R_6_P_2,
- VEX_LEN_0F73_R_2_P_2,
- VEX_LEN_0F73_R_3_P_2,
- VEX_LEN_0F73_R_6_P_2,
- VEX_LEN_0F73_R_7_P_2,
- VEX_LEN_0F74_P_2,
- VEX_LEN_0F75_P_2,
- VEX_LEN_0F76_P_2,
VEX_LEN_0F7E_P_1,
VEX_LEN_0F7E_P_2,
+ VEX_LEN_0F90_P_0,
+ VEX_LEN_0F90_P_2,
+ VEX_LEN_0F91_P_0,
+ VEX_LEN_0F91_P_2,
+ VEX_LEN_0F92_P_0,
+ VEX_LEN_0F92_P_2,
+ VEX_LEN_0F92_P_3,
+ VEX_LEN_0F93_P_0,
+ VEX_LEN_0F93_P_2,
+ VEX_LEN_0F93_P_3,
+ VEX_LEN_0F98_P_0,
+ VEX_LEN_0F98_P_2,
+ VEX_LEN_0F99_P_0,
+ VEX_LEN_0F99_P_2,
VEX_LEN_0FAE_R_2_M_0,
VEX_LEN_0FAE_R_3_M_0,
VEX_LEN_0FC2_P_1,
VEX_LEN_0FC2_P_3,
VEX_LEN_0FC4_P_2,
VEX_LEN_0FC5_P_2,
- VEX_LEN_0FD1_P_2,
- VEX_LEN_0FD2_P_2,
- VEX_LEN_0FD3_P_2,
- VEX_LEN_0FD4_P_2,
- VEX_LEN_0FD5_P_2,
VEX_LEN_0FD6_P_2,
- VEX_LEN_0FD7_P_2_M_1,
- VEX_LEN_0FD8_P_2,
- VEX_LEN_0FD9_P_2,
- VEX_LEN_0FDA_P_2,
- VEX_LEN_0FDB_P_2,
- VEX_LEN_0FDC_P_2,
- VEX_LEN_0FDD_P_2,
- VEX_LEN_0FDE_P_2,
- VEX_LEN_0FDF_P_2,
- VEX_LEN_0FE0_P_2,
- VEX_LEN_0FE1_P_2,
- VEX_LEN_0FE2_P_2,
- VEX_LEN_0FE3_P_2,
- VEX_LEN_0FE4_P_2,
- VEX_LEN_0FE5_P_2,
- VEX_LEN_0FE8_P_2,
- VEX_LEN_0FE9_P_2,
- VEX_LEN_0FEA_P_2,
- VEX_LEN_0FEB_P_2,
- VEX_LEN_0FEC_P_2,
- VEX_LEN_0FED_P_2,
- VEX_LEN_0FEE_P_2,
- VEX_LEN_0FEF_P_2,
- VEX_LEN_0FF1_P_2,
- VEX_LEN_0FF2_P_2,
- VEX_LEN_0FF3_P_2,
- VEX_LEN_0FF4_P_2,
- VEX_LEN_0FF5_P_2,
- VEX_LEN_0FF6_P_2,
VEX_LEN_0FF7_P_2,
- VEX_LEN_0FF8_P_2,
- VEX_LEN_0FF9_P_2,
- VEX_LEN_0FFA_P_2,
- VEX_LEN_0FFB_P_2,
- VEX_LEN_0FFC_P_2,
- VEX_LEN_0FFD_P_2,
- VEX_LEN_0FFE_P_2,
- VEX_LEN_0F3800_P_2,
- VEX_LEN_0F3801_P_2,
- VEX_LEN_0F3802_P_2,
- VEX_LEN_0F3803_P_2,
- VEX_LEN_0F3804_P_2,
- VEX_LEN_0F3805_P_2,
- VEX_LEN_0F3806_P_2,
- VEX_LEN_0F3807_P_2,
- VEX_LEN_0F3808_P_2,
- VEX_LEN_0F3809_P_2,
- VEX_LEN_0F380A_P_2,
- VEX_LEN_0F380B_P_2,
- VEX_LEN_0F3819_P_2_M_0,
+ VEX_LEN_0F3816_P_2,
+ VEX_LEN_0F3819_P_2,
VEX_LEN_0F381A_P_2_M_0,
- VEX_LEN_0F381C_P_2,
- VEX_LEN_0F381D_P_2,
- VEX_LEN_0F381E_P_2,
- VEX_LEN_0F3820_P_2,
- VEX_LEN_0F3821_P_2,
- VEX_LEN_0F3822_P_2,
- VEX_LEN_0F3823_P_2,
- VEX_LEN_0F3824_P_2,
- VEX_LEN_0F3825_P_2,
- VEX_LEN_0F3828_P_2,
- VEX_LEN_0F3829_P_2,
- VEX_LEN_0F382A_P_2_M_0,
- VEX_LEN_0F382B_P_2,
- VEX_LEN_0F3830_P_2,
- VEX_LEN_0F3831_P_2,
- VEX_LEN_0F3832_P_2,
- VEX_LEN_0F3833_P_2,
- VEX_LEN_0F3834_P_2,
- VEX_LEN_0F3835_P_2,
- VEX_LEN_0F3837_P_2,
- VEX_LEN_0F3838_P_2,
- VEX_LEN_0F3839_P_2,
- VEX_LEN_0F383A_P_2,
- VEX_LEN_0F383B_P_2,
- VEX_LEN_0F383C_P_2,
- VEX_LEN_0F383D_P_2,
- VEX_LEN_0F383E_P_2,
- VEX_LEN_0F383F_P_2,
- VEX_LEN_0F3840_P_2,
+ VEX_LEN_0F3836_P_2,
VEX_LEN_0F3841_P_2,
+ VEX_LEN_0F385A_P_2_M_0,
VEX_LEN_0F38DB_P_2,
VEX_LEN_0F38DC_P_2,
VEX_LEN_0F38DD_P_2,
VEX_LEN_0F38DE_P_2,
VEX_LEN_0F38DF_P_2,
+ VEX_LEN_0F38F2_P_0,
+ VEX_LEN_0F38F3_R_1_P_0,
+ VEX_LEN_0F38F3_R_2_P_0,
+ VEX_LEN_0F38F3_R_3_P_0,
+ VEX_LEN_0F38F5_P_0,
+ VEX_LEN_0F38F5_P_1,
+ VEX_LEN_0F38F5_P_3,
+ VEX_LEN_0F38F6_P_3,
+ VEX_LEN_0F38F7_P_0,
+ VEX_LEN_0F38F7_P_1,
+ VEX_LEN_0F38F7_P_2,
+ VEX_LEN_0F38F7_P_3,
+ VEX_LEN_0F3A00_P_2,
+ VEX_LEN_0F3A01_P_2,
VEX_LEN_0F3A06_P_2,
VEX_LEN_0F3A0A_P_2,
VEX_LEN_0F3A0B_P_2,
- VEX_LEN_0F3A0E_P_2,
- VEX_LEN_0F3A0F_P_2,
VEX_LEN_0F3A14_P_2,
VEX_LEN_0F3A15_P_2,
VEX_LEN_0F3A16_P_2,
VEX_LEN_0F3A20_P_2,
VEX_LEN_0F3A21_P_2,
VEX_LEN_0F3A22_P_2,
+ VEX_LEN_0F3A30_P_2,
+ VEX_LEN_0F3A31_P_2,
+ VEX_LEN_0F3A32_P_2,
+ VEX_LEN_0F3A33_P_2,
+ VEX_LEN_0F3A38_P_2,
+ VEX_LEN_0F3A39_P_2,
VEX_LEN_0F3A41_P_2,
- VEX_LEN_0F3A42_P_2,
VEX_LEN_0F3A44_P_2,
- VEX_LEN_0F3A4C_P_2,
+ VEX_LEN_0F3A46_P_2,
VEX_LEN_0F3A60_P_2,
VEX_LEN_0F3A61_P_2,
VEX_LEN_0F3A62_P_2,
VEX_LEN_0F3A7E_P_2,
VEX_LEN_0F3A7F_P_2,
VEX_LEN_0F3ADF_P_2,
+ VEX_LEN_0F3AF0_P_3,
+ VEX_LEN_0FXOP_08_CC,
+ VEX_LEN_0FXOP_08_CD,
+ VEX_LEN_0FXOP_08_CE,
+ VEX_LEN_0FXOP_08_CF,
+ VEX_LEN_0FXOP_08_EC,
+ VEX_LEN_0FXOP_08_ED,
+ VEX_LEN_0FXOP_08_EE,
+ VEX_LEN_0FXOP_08_EF,
VEX_LEN_0FXOP_09_80,
VEX_LEN_0FXOP_09_81
};
VEX_W_0F2E_P_2,
VEX_W_0F2F_P_0,
VEX_W_0F2F_P_2,
+ VEX_W_0F41_P_0_LEN_1,
+ VEX_W_0F41_P_2_LEN_1,
+ VEX_W_0F42_P_0_LEN_1,
+ VEX_W_0F42_P_2_LEN_1,
+ VEX_W_0F44_P_0_LEN_0,
+ VEX_W_0F44_P_2_LEN_0,
+ VEX_W_0F45_P_0_LEN_1,
+ VEX_W_0F45_P_2_LEN_1,
+ VEX_W_0F46_P_0_LEN_1,
+ VEX_W_0F46_P_2_LEN_1,
+ VEX_W_0F47_P_0_LEN_1,
+ VEX_W_0F47_P_2_LEN_1,
+ VEX_W_0F4A_P_0_LEN_1,
+ VEX_W_0F4A_P_2_LEN_1,
+ VEX_W_0F4B_P_0_LEN_1,
+ VEX_W_0F4B_P_2_LEN_1,
VEX_W_0F50_M_0,
VEX_W_0F51_P_0,
VEX_W_0F51_P_1,
VEX_W_0F7E_P_1,
VEX_W_0F7F_P_1,
VEX_W_0F7F_P_2,
+ VEX_W_0F90_P_0_LEN_0,
+ VEX_W_0F90_P_2_LEN_0,
+ VEX_W_0F91_P_0_LEN_0,
+ VEX_W_0F91_P_2_LEN_0,
+ VEX_W_0F92_P_0_LEN_0,
+ VEX_W_0F92_P_2_LEN_0,
+ VEX_W_0F92_P_3_LEN_0,
+ VEX_W_0F93_P_0_LEN_0,
+ VEX_W_0F93_P_2_LEN_0,
+ VEX_W_0F93_P_3_LEN_0,
+ VEX_W_0F98_P_0_LEN_0,
+ VEX_W_0F98_P_2_LEN_0,
+ VEX_W_0F99_P_0_LEN_0,
+ VEX_W_0F99_P_2_LEN_0,
VEX_W_0FAE_R_2_M_0,
VEX_W_0FAE_R_3_M_0,
VEX_W_0FC2_P_0,
VEX_W_0F380D_P_2,
VEX_W_0F380E_P_2,
VEX_W_0F380F_P_2,
+ VEX_W_0F3816_P_2,
VEX_W_0F3817_P_2,
- VEX_W_0F3818_P_2_M_0,
- VEX_W_0F3819_P_2_M_0,
+ VEX_W_0F3818_P_2,
+ VEX_W_0F3819_P_2,
VEX_W_0F381A_P_2_M_0,
VEX_W_0F381C_P_2,
VEX_W_0F381D_P_2,
VEX_W_0F3833_P_2,
VEX_W_0F3834_P_2,
VEX_W_0F3835_P_2,
+ VEX_W_0F3836_P_2,
VEX_W_0F3837_P_2,
VEX_W_0F3838_P_2,
VEX_W_0F3839_P_2,
VEX_W_0F383F_P_2,
VEX_W_0F3840_P_2,
VEX_W_0F3841_P_2,
+ VEX_W_0F3846_P_2,
+ VEX_W_0F3858_P_2,
+ VEX_W_0F3859_P_2,
+ VEX_W_0F385A_P_2_M_0,
+ VEX_W_0F3878_P_2,
+ VEX_W_0F3879_P_2,
VEX_W_0F38DB_P_2,
VEX_W_0F38DC_P_2,
VEX_W_0F38DD_P_2,
VEX_W_0F38DE_P_2,
VEX_W_0F38DF_P_2,
+ VEX_W_0F3A00_P_2,
+ VEX_W_0F3A01_P_2,
+ VEX_W_0F3A02_P_2,
VEX_W_0F3A04_P_2,
VEX_W_0F3A05_P_2,
VEX_W_0F3A06_P_2,
VEX_W_0F3A19_P_2,
VEX_W_0F3A20_P_2,
VEX_W_0F3A21_P_2,
+ VEX_W_0F3A30_P_2_LEN_0,
+ VEX_W_0F3A31_P_2_LEN_0,
+ VEX_W_0F3A32_P_2_LEN_0,
+ VEX_W_0F3A33_P_2_LEN_0,
+ VEX_W_0F3A38_P_2,
+ VEX_W_0F3A39_P_2,
VEX_W_0F3A40_P_2,
VEX_W_0F3A41_P_2,
VEX_W_0F3A42_P_2,
VEX_W_0F3A44_P_2,
+ VEX_W_0F3A46_P_2,
VEX_W_0F3A48_P_2,
VEX_W_0F3A49_P_2,
VEX_W_0F3A4A_P_2,
VEX_W_0F3A61_P_2,
VEX_W_0F3A62_P_2,
VEX_W_0F3A63_P_2,
- VEX_W_0F3ADF_P_2
+ VEX_W_0F3ADF_P_2,
+
+ EVEX_W_0F10_P_0,
+ EVEX_W_0F10_P_1_M_0,
+ EVEX_W_0F10_P_1_M_1,
+ EVEX_W_0F10_P_2,
+ EVEX_W_0F10_P_3_M_0,
+ EVEX_W_0F10_P_3_M_1,
+ EVEX_W_0F11_P_0,
+ EVEX_W_0F11_P_1_M_0,
+ EVEX_W_0F11_P_1_M_1,
+ EVEX_W_0F11_P_2,
+ EVEX_W_0F11_P_3_M_0,
+ EVEX_W_0F11_P_3_M_1,
+ EVEX_W_0F12_P_0_M_0,
+ EVEX_W_0F12_P_0_M_1,
+ EVEX_W_0F12_P_1,
+ EVEX_W_0F12_P_2,
+ EVEX_W_0F12_P_3,
+ EVEX_W_0F13_P_0,
+ EVEX_W_0F13_P_2,
+ EVEX_W_0F14_P_0,
+ EVEX_W_0F14_P_2,
+ EVEX_W_0F15_P_0,
+ EVEX_W_0F15_P_2,
+ EVEX_W_0F16_P_0_M_0,
+ EVEX_W_0F16_P_0_M_1,
+ EVEX_W_0F16_P_1,
+ EVEX_W_0F16_P_2,
+ EVEX_W_0F17_P_0,
+ EVEX_W_0F17_P_2,
+ EVEX_W_0F28_P_0,
+ EVEX_W_0F28_P_2,
+ EVEX_W_0F29_P_0,
+ EVEX_W_0F29_P_2,
+ EVEX_W_0F2A_P_1,
+ EVEX_W_0F2A_P_3,
+ EVEX_W_0F2B_P_0,
+ EVEX_W_0F2B_P_2,
+ EVEX_W_0F2E_P_0,
+ EVEX_W_0F2E_P_2,
+ EVEX_W_0F2F_P_0,
+ EVEX_W_0F2F_P_2,
+ EVEX_W_0F51_P_0,
+ EVEX_W_0F51_P_1,
+ EVEX_W_0F51_P_2,
+ EVEX_W_0F51_P_3,
+ EVEX_W_0F54_P_0,
+ EVEX_W_0F54_P_2,
+ EVEX_W_0F55_P_0,
+ EVEX_W_0F55_P_2,
+ EVEX_W_0F56_P_0,
+ EVEX_W_0F56_P_2,
+ EVEX_W_0F57_P_0,
+ EVEX_W_0F57_P_2,
+ EVEX_W_0F58_P_0,
+ EVEX_W_0F58_P_1,
+ EVEX_W_0F58_P_2,
+ EVEX_W_0F58_P_3,
+ EVEX_W_0F59_P_0,
+ EVEX_W_0F59_P_1,
+ EVEX_W_0F59_P_2,
+ EVEX_W_0F59_P_3,
+ EVEX_W_0F5A_P_0,
+ EVEX_W_0F5A_P_1,
+ EVEX_W_0F5A_P_2,
+ EVEX_W_0F5A_P_3,
+ EVEX_W_0F5B_P_0,
+ EVEX_W_0F5B_P_1,
+ EVEX_W_0F5B_P_2,
+ EVEX_W_0F5C_P_0,
+ EVEX_W_0F5C_P_1,
+ EVEX_W_0F5C_P_2,
+ EVEX_W_0F5C_P_3,
+ EVEX_W_0F5D_P_0,
+ EVEX_W_0F5D_P_1,
+ EVEX_W_0F5D_P_2,
+ EVEX_W_0F5D_P_3,
+ EVEX_W_0F5E_P_0,
+ EVEX_W_0F5E_P_1,
+ EVEX_W_0F5E_P_2,
+ EVEX_W_0F5E_P_3,
+ EVEX_W_0F5F_P_0,
+ EVEX_W_0F5F_P_1,
+ EVEX_W_0F5F_P_2,
+ EVEX_W_0F5F_P_3,
+ EVEX_W_0F62_P_2,
+ EVEX_W_0F66_P_2,
+ EVEX_W_0F6A_P_2,
+ EVEX_W_0F6B_P_2,
+ EVEX_W_0F6C_P_2,
+ EVEX_W_0F6D_P_2,
+ EVEX_W_0F6E_P_2,
+ EVEX_W_0F6F_P_1,
+ EVEX_W_0F6F_P_2,
+ EVEX_W_0F6F_P_3,
+ EVEX_W_0F70_P_2,
+ EVEX_W_0F72_R_2_P_2,
+ EVEX_W_0F72_R_6_P_2,
+ EVEX_W_0F73_R_2_P_2,
+ EVEX_W_0F73_R_6_P_2,
+ EVEX_W_0F76_P_2,
+ EVEX_W_0F78_P_0,
+ EVEX_W_0F78_P_2,
+ EVEX_W_0F79_P_0,
+ EVEX_W_0F79_P_2,
+ EVEX_W_0F7A_P_1,
+ EVEX_W_0F7A_P_2,
+ EVEX_W_0F7A_P_3,
+ EVEX_W_0F7B_P_1,
+ EVEX_W_0F7B_P_2,
+ EVEX_W_0F7B_P_3,
+ EVEX_W_0F7E_P_1,
+ EVEX_W_0F7E_P_2,
+ EVEX_W_0F7F_P_1,
+ EVEX_W_0F7F_P_2,
+ EVEX_W_0F7F_P_3,
+ EVEX_W_0FC2_P_0,
+ EVEX_W_0FC2_P_1,
+ EVEX_W_0FC2_P_2,
+ EVEX_W_0FC2_P_3,
+ EVEX_W_0FC6_P_0,
+ EVEX_W_0FC6_P_2,
+ EVEX_W_0FD2_P_2,
+ EVEX_W_0FD3_P_2,
+ EVEX_W_0FD4_P_2,
+ EVEX_W_0FD6_P_2,
+ EVEX_W_0FE6_P_1,
+ EVEX_W_0FE6_P_2,
+ EVEX_W_0FE6_P_3,
+ EVEX_W_0FE7_P_2,
+ EVEX_W_0FF2_P_2,
+ EVEX_W_0FF3_P_2,
+ EVEX_W_0FF4_P_2,
+ EVEX_W_0FFA_P_2,
+ EVEX_W_0FFB_P_2,
+ EVEX_W_0FFE_P_2,
+ EVEX_W_0F380C_P_2,
+ EVEX_W_0F380D_P_2,
+ EVEX_W_0F3810_P_1,
+ EVEX_W_0F3810_P_2,
+ EVEX_W_0F3811_P_1,
+ EVEX_W_0F3811_P_2,
+ EVEX_W_0F3812_P_1,
+ EVEX_W_0F3812_P_2,
+ EVEX_W_0F3813_P_1,
+ EVEX_W_0F3813_P_2,
+ EVEX_W_0F3814_P_1,
+ EVEX_W_0F3815_P_1,
+ EVEX_W_0F3818_P_2,
+ EVEX_W_0F3819_P_2,
+ EVEX_W_0F381A_P_2,
+ EVEX_W_0F381B_P_2,
+ EVEX_W_0F381E_P_2,
+ EVEX_W_0F381F_P_2,
+ EVEX_W_0F3820_P_1,
+ EVEX_W_0F3821_P_1,
+ EVEX_W_0F3822_P_1,
+ EVEX_W_0F3823_P_1,
+ EVEX_W_0F3824_P_1,
+ EVEX_W_0F3825_P_1,
+ EVEX_W_0F3825_P_2,
+ EVEX_W_0F3826_P_1,
+ EVEX_W_0F3826_P_2,
+ EVEX_W_0F3828_P_1,
+ EVEX_W_0F3828_P_2,
+ EVEX_W_0F3829_P_1,
+ EVEX_W_0F3829_P_2,
+ EVEX_W_0F382A_P_1,
+ EVEX_W_0F382A_P_2,
+ EVEX_W_0F382B_P_2,
+ EVEX_W_0F3830_P_1,
+ EVEX_W_0F3831_P_1,
+ EVEX_W_0F3832_P_1,
+ EVEX_W_0F3833_P_1,
+ EVEX_W_0F3834_P_1,
+ EVEX_W_0F3835_P_1,
+ EVEX_W_0F3835_P_2,
+ EVEX_W_0F3837_P_2,
+ EVEX_W_0F3838_P_1,
+ EVEX_W_0F3839_P_1,
+ EVEX_W_0F383A_P_1,
+ EVEX_W_0F3840_P_2,
+ EVEX_W_0F3858_P_2,
+ EVEX_W_0F3859_P_2,
+ EVEX_W_0F385A_P_2,
+ EVEX_W_0F385B_P_2,
+ EVEX_W_0F3866_P_2,
+ EVEX_W_0F3875_P_2,
+ EVEX_W_0F3878_P_2,
+ EVEX_W_0F3879_P_2,
+ EVEX_W_0F387A_P_2,
+ EVEX_W_0F387B_P_2,
+ EVEX_W_0F387D_P_2,
+ EVEX_W_0F3883_P_2,
+ EVEX_W_0F388D_P_2,
+ EVEX_W_0F3891_P_2,
+ EVEX_W_0F3893_P_2,
+ EVEX_W_0F38A1_P_2,
+ EVEX_W_0F38A3_P_2,
+ EVEX_W_0F38C7_R_1_P_2,
+ EVEX_W_0F38C7_R_2_P_2,
+ EVEX_W_0F38C7_R_5_P_2,
+ EVEX_W_0F38C7_R_6_P_2,
+
+ EVEX_W_0F3A00_P_2,
+ EVEX_W_0F3A01_P_2,
+ EVEX_W_0F3A04_P_2,
+ EVEX_W_0F3A05_P_2,
+ EVEX_W_0F3A08_P_2,
+ EVEX_W_0F3A09_P_2,
+ EVEX_W_0F3A0A_P_2,
+ EVEX_W_0F3A0B_P_2,
+ EVEX_W_0F3A16_P_2,
+ EVEX_W_0F3A18_P_2,
+ EVEX_W_0F3A19_P_2,
+ EVEX_W_0F3A1A_P_2,
+ EVEX_W_0F3A1B_P_2,
+ EVEX_W_0F3A1D_P_2,
+ EVEX_W_0F3A21_P_2,
+ EVEX_W_0F3A22_P_2,
+ EVEX_W_0F3A23_P_2,
+ EVEX_W_0F3A38_P_2,
+ EVEX_W_0F3A39_P_2,
+ EVEX_W_0F3A3A_P_2,
+ EVEX_W_0F3A3B_P_2,
+ EVEX_W_0F3A3E_P_2,
+ EVEX_W_0F3A3F_P_2,
+ EVEX_W_0F3A42_P_2,
+ EVEX_W_0F3A43_P_2,
+ EVEX_W_0F3A50_P_2,
+ EVEX_W_0F3A51_P_2,
+ EVEX_W_0F3A56_P_2,
+ EVEX_W_0F3A57_P_2,
+ EVEX_W_0F3A66_P_2,
+ EVEX_W_0F3A67_P_2
};
typedef void (*op_rtn) (int bytemode, int sizeflag);
op_rtn rtn;
int bytemode;
} op[MAX_OPERANDS];
+ unsigned int prefix_requirement;
};
/* Upper case letters in the instruction names here are macros.
is true
'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
'S' => print 'w', 'l' or 'q' if suffix_always is true
- 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
- 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
- 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
+ 'T' => print 'q' in 64bit mode if instruction has no operand size
+ prefix and behave as 'P' otherwise
+ 'U' => print 'q' in 64bit mode if instruction has no operand size
+ prefix and behave as 'Q' otherwise
+ 'V' => print 'q' in 64bit mode if instruction has no operand size
+ prefix and behave as 'S' otherwise
'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
'X' => print 's', 'd' depending on data16 prefix (for XMM)
'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
'!' => change condition from true to false or from false to true.
'%' => add 1 upper case letter to the macro.
+ '^' => print 'w' or 'l' depending on operand size prefix or
+ suffix_always is true (lcall/ljmp).
+ '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
+ on operand size prefix.
+ '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
+ has no operand size prefix for AMD64 ISA, behave as 'P'
+ otherwise
2 upper case letter macros:
- "XY" => print 'x' or 'y' if no register operands or suffix_always
- is true.
+ "XY" => print 'x' or 'y' if suffix_always is true or no register
+ operands and no broadcast.
+ "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
+ register operands and no broadcast.
"XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
"LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
or suffix_always is true
"LB" => print "abs" in 64bit mode and behave as 'B' otherwise
"LS" => print "abs" in 64bit mode and behave as 'S' otherwise
"LV" => print "abs" for 64bit operand and behave as 'S' otherwise
+ "LW" => print 'd', 'q' depending on the VEX.W bit
+ "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
+ an operand size prefix, or suffix_always is true. print
+ 'q' if rex prefix is present.
Many of the above letters print nothing in Intel mode. See "putop"
for the details.
static const struct dis386 dis386[] = {
/* 00 */
- { "addB", { Eb, Gb } },
- { "addS", { Ev, Gv } },
- { "addB", { Gb, EbS } },
- { "addS", { Gv, EvS } },
- { "addB", { AL, Ib } },
- { "addS", { eAX, Iv } },
+ { "addB", { Ebh1, Gb }, 0 },
+ { "addS", { Evh1, Gv }, 0 },
+ { "addB", { Gb, EbS }, 0 },
+ { "addS", { Gv, EvS }, 0 },
+ { "addB", { AL, Ib }, 0 },
+ { "addS", { eAX, Iv }, 0 },
{ X86_64_TABLE (X86_64_06) },
{ X86_64_TABLE (X86_64_07) },
/* 08 */
- { "orB", { Eb, Gb } },
- { "orS", { Ev, Gv } },
- { "orB", { Gb, EbS } },
- { "orS", { Gv, EvS } },
- { "orB", { AL, Ib } },
- { "orS", { eAX, Iv } },
+ { "orB", { Ebh1, Gb }, 0 },
+ { "orS", { Evh1, Gv }, 0 },
+ { "orB", { Gb, EbS }, 0 },
+ { "orS", { Gv, EvS }, 0 },
+ { "orB", { AL, Ib }, 0 },
+ { "orS", { eAX, Iv }, 0 },
{ X86_64_TABLE (X86_64_0D) },
{ Bad_Opcode }, /* 0x0f extended opcode escape */
/* 10 */
- { "adcB", { Eb, Gb } },
- { "adcS", { Ev, Gv } },
- { "adcB", { Gb, EbS } },
- { "adcS", { Gv, EvS } },
- { "adcB", { AL, Ib } },
- { "adcS", { eAX, Iv } },
+ { "adcB", { Ebh1, Gb }, 0 },
+ { "adcS", { Evh1, Gv }, 0 },
+ { "adcB", { Gb, EbS }, 0 },
+ { "adcS", { Gv, EvS }, 0 },
+ { "adcB", { AL, Ib }, 0 },
+ { "adcS", { eAX, Iv }, 0 },
{ X86_64_TABLE (X86_64_16) },
{ X86_64_TABLE (X86_64_17) },
/* 18 */
- { "sbbB", { Eb, Gb } },
- { "sbbS", { Ev, Gv } },
- { "sbbB", { Gb, EbS } },
- { "sbbS", { Gv, EvS } },
- { "sbbB", { AL, Ib } },
- { "sbbS", { eAX, Iv } },
+ { "sbbB", { Ebh1, Gb }, 0 },
+ { "sbbS", { Evh1, Gv }, 0 },
+ { "sbbB", { Gb, EbS }, 0 },
+ { "sbbS", { Gv, EvS }, 0 },
+ { "sbbB", { AL, Ib }, 0 },
+ { "sbbS", { eAX, Iv }, 0 },
{ X86_64_TABLE (X86_64_1E) },
{ X86_64_TABLE (X86_64_1F) },
/* 20 */
- { "andB", { Eb, Gb } },
- { "andS", { Ev, Gv } },
- { "andB", { Gb, EbS } },
- { "andS", { Gv, EvS } },
- { "andB", { AL, Ib } },
- { "andS", { eAX, Iv } },
+ { "andB", { Ebh1, Gb }, 0 },
+ { "andS", { Evh1, Gv }, 0 },
+ { "andB", { Gb, EbS }, 0 },
+ { "andS", { Gv, EvS }, 0 },
+ { "andB", { AL, Ib }, 0 },
+ { "andS", { eAX, Iv }, 0 },
{ Bad_Opcode }, /* SEG ES prefix */
{ X86_64_TABLE (X86_64_27) },
/* 28 */
- { "subB", { Eb, Gb } },
- { "subS", { Ev, Gv } },
- { "subB", { Gb, EbS } },
- { "subS", { Gv, EvS } },
- { "subB", { AL, Ib } },
- { "subS", { eAX, Iv } },
+ { "subB", { Ebh1, Gb }, 0 },
+ { "subS", { Evh1, Gv }, 0 },
+ { "subB", { Gb, EbS }, 0 },
+ { "subS", { Gv, EvS }, 0 },
+ { "subB", { AL, Ib }, 0 },
+ { "subS", { eAX, Iv }, 0 },
{ Bad_Opcode }, /* SEG CS prefix */
{ X86_64_TABLE (X86_64_2F) },
/* 30 */
- { "xorB", { Eb, Gb } },
- { "xorS", { Ev, Gv } },
- { "xorB", { Gb, EbS } },
- { "xorS", { Gv, EvS } },
- { "xorB", { AL, Ib } },
- { "xorS", { eAX, Iv } },
+ { "xorB", { Ebh1, Gb }, 0 },
+ { "xorS", { Evh1, Gv }, 0 },
+ { "xorB", { Gb, EbS }, 0 },
+ { "xorS", { Gv, EvS }, 0 },
+ { "xorB", { AL, Ib }, 0 },
+ { "xorS", { eAX, Iv }, 0 },
{ Bad_Opcode }, /* SEG SS prefix */
{ X86_64_TABLE (X86_64_37) },
/* 38 */
- { "cmpB", { Eb, Gb } },
- { "cmpS", { Ev, Gv } },
- { "cmpB", { Gb, EbS } },
- { "cmpS", { Gv, EvS } },
- { "cmpB", { AL, Ib } },
- { "cmpS", { eAX, Iv } },
+ { "cmpB", { Eb, Gb }, 0 },
+ { "cmpS", { Ev, Gv }, 0 },
+ { "cmpB", { Gb, EbS }, 0 },
+ { "cmpS", { Gv, EvS }, 0 },
+ { "cmpB", { AL, Ib }, 0 },
+ { "cmpS", { eAX, Iv }, 0 },
{ Bad_Opcode }, /* SEG DS prefix */
{ X86_64_TABLE (X86_64_3F) },
/* 40 */
- { "inc{S|}", { RMeAX } },
- { "inc{S|}", { RMeCX } },
- { "inc{S|}", { RMeDX } },
- { "inc{S|}", { RMeBX } },
- { "inc{S|}", { RMeSP } },
- { "inc{S|}", { RMeBP } },
- { "inc{S|}", { RMeSI } },
- { "inc{S|}", { RMeDI } },
+ { "inc{S|}", { RMeAX }, 0 },
+ { "inc{S|}", { RMeCX }, 0 },
+ { "inc{S|}", { RMeDX }, 0 },
+ { "inc{S|}", { RMeBX }, 0 },
+ { "inc{S|}", { RMeSP }, 0 },
+ { "inc{S|}", { RMeBP }, 0 },
+ { "inc{S|}", { RMeSI }, 0 },
+ { "inc{S|}", { RMeDI }, 0 },
/* 48 */
- { "dec{S|}", { RMeAX } },
- { "dec{S|}", { RMeCX } },
- { "dec{S|}", { RMeDX } },
- { "dec{S|}", { RMeBX } },
- { "dec{S|}", { RMeSP } },
- { "dec{S|}", { RMeBP } },
- { "dec{S|}", { RMeSI } },
- { "dec{S|}", { RMeDI } },
+ { "dec{S|}", { RMeAX }, 0 },
+ { "dec{S|}", { RMeCX }, 0 },
+ { "dec{S|}", { RMeDX }, 0 },
+ { "dec{S|}", { RMeBX }, 0 },
+ { "dec{S|}", { RMeSP }, 0 },
+ { "dec{S|}", { RMeBP }, 0 },
+ { "dec{S|}", { RMeSI }, 0 },
+ { "dec{S|}", { RMeDI }, 0 },
/* 50 */
- { "pushV", { RMrAX } },
- { "pushV", { RMrCX } },
- { "pushV", { RMrDX } },
- { "pushV", { RMrBX } },
- { "pushV", { RMrSP } },
- { "pushV", { RMrBP } },
- { "pushV", { RMrSI } },
- { "pushV", { RMrDI } },
+ { "pushV", { RMrAX }, 0 },
+ { "pushV", { RMrCX }, 0 },
+ { "pushV", { RMrDX }, 0 },
+ { "pushV", { RMrBX }, 0 },
+ { "pushV", { RMrSP }, 0 },
+ { "pushV", { RMrBP }, 0 },
+ { "pushV", { RMrSI }, 0 },
+ { "pushV", { RMrDI }, 0 },
/* 58 */
- { "popV", { RMrAX } },
- { "popV", { RMrCX } },
- { "popV", { RMrDX } },
- { "popV", { RMrBX } },
- { "popV", { RMrSP } },
- { "popV", { RMrBP } },
- { "popV", { RMrSI } },
- { "popV", { RMrDI } },
+ { "popV", { RMrAX }, 0 },
+ { "popV", { RMrCX }, 0 },
+ { "popV", { RMrDX }, 0 },
+ { "popV", { RMrBX }, 0 },
+ { "popV", { RMrSP }, 0 },
+ { "popV", { RMrBP }, 0 },
+ { "popV", { RMrSI }, 0 },
+ { "popV", { RMrDI }, 0 },
/* 60 */
{ X86_64_TABLE (X86_64_60) },
{ X86_64_TABLE (X86_64_61) },
{ Bad_Opcode }, /* op size prefix */
{ Bad_Opcode }, /* adr size prefix */
/* 68 */
- { "pushT", { sIv } },
- { "imulS", { Gv, Ev, Iv } },
- { "pushT", { sIb } },
- { "imulS", { Gv, Ev, sIb } },
- { "ins{b|}", { Ybr, indirDX } },
+ { "pushT", { sIv }, 0 },
+ { "imulS", { Gv, Ev, Iv }, 0 },
+ { "pushT", { sIbT }, 0 },
+ { "imulS", { Gv, Ev, sIb }, 0 },
+ { "ins{b|}", { Ybr, indirDX }, 0 },
{ X86_64_TABLE (X86_64_6D) },
- { "outs{b|}", { indirDXr, Xb } },
+ { "outs{b|}", { indirDXr, Xb }, 0 },
{ X86_64_TABLE (X86_64_6F) },
/* 70 */
- { "joH", { Jb, XX, cond_jump_flag } },
- { "jnoH", { Jb, XX, cond_jump_flag } },
- { "jbH", { Jb, XX, cond_jump_flag } },
- { "jaeH", { Jb, XX, cond_jump_flag } },
- { "jeH", { Jb, XX, cond_jump_flag } },
- { "jneH", { Jb, XX, cond_jump_flag } },
- { "jbeH", { Jb, XX, cond_jump_flag } },
- { "jaH", { Jb, XX, cond_jump_flag } },
+ { "joH", { Jb, BND, cond_jump_flag }, 0 },
+ { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
+ { "jbH", { Jb, BND, cond_jump_flag }, 0 },
+ { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
+ { "jeH", { Jb, BND, cond_jump_flag }, 0 },
+ { "jneH", { Jb, BND, cond_jump_flag }, 0 },
+ { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
+ { "jaH", { Jb, BND, cond_jump_flag }, 0 },
/* 78 */
- { "jsH", { Jb, XX, cond_jump_flag } },
- { "jnsH", { Jb, XX, cond_jump_flag } },
- { "jpH", { Jb, XX, cond_jump_flag } },
- { "jnpH", { Jb, XX, cond_jump_flag } },
- { "jlH", { Jb, XX, cond_jump_flag } },
- { "jgeH", { Jb, XX, cond_jump_flag } },
- { "jleH", { Jb, XX, cond_jump_flag } },
- { "jgH", { Jb, XX, cond_jump_flag } },
+ { "jsH", { Jb, BND, cond_jump_flag }, 0 },
+ { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
+ { "jpH", { Jb, BND, cond_jump_flag }, 0 },
+ { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
+ { "jlH", { Jb, BND, cond_jump_flag }, 0 },
+ { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
+ { "jleH", { Jb, BND, cond_jump_flag }, 0 },
+ { "jgH", { Jb, BND, cond_jump_flag }, 0 },
/* 80 */
{ REG_TABLE (REG_80) },
{ REG_TABLE (REG_81) },
{ Bad_Opcode },
{ REG_TABLE (REG_82) },
- { "testB", { Eb, Gb } },
- { "testS", { Ev, Gv } },
- { "xchgB", { Eb, Gb } },
- { "xchgS", { Ev, Gv } },
+ { "testB", { Eb, Gb }, 0 },
+ { "testS", { Ev, Gv }, 0 },
+ { "xchgB", { Ebh2, Gb }, 0 },
+ { "xchgS", { Evh2, Gv }, 0 },
/* 88 */
- { "movB", { Eb, Gb } },
- { "movS", { Ev, Gv } },
- { "movB", { Gb, EbS } },
- { "movS", { Gv, EvS } },
- { "movD", { Sv, Sw } },
+ { "movB", { Ebh3, Gb }, 0 },
+ { "movS", { Evh3, Gv }, 0 },
+ { "movB", { Gb, EbS }, 0 },
+ { "movS", { Gv, EvS }, 0 },
+ { "movD", { Sv, Sw }, 0 },
{ MOD_TABLE (MOD_8D) },
- { "movD", { Sw, Sv } },
+ { "movD", { Sw, Sv }, 0 },
{ REG_TABLE (REG_8F) },
/* 90 */
{ PREFIX_TABLE (PREFIX_90) },
- { "xchgS", { RMeCX, eAX } },
- { "xchgS", { RMeDX, eAX } },
- { "xchgS", { RMeBX, eAX } },
- { "xchgS", { RMeSP, eAX } },
- { "xchgS", { RMeBP, eAX } },
- { "xchgS", { RMeSI, eAX } },
- { "xchgS", { RMeDI, eAX } },
+ { "xchgS", { RMeCX, eAX }, 0 },
+ { "xchgS", { RMeDX, eAX }, 0 },
+ { "xchgS", { RMeBX, eAX }, 0 },
+ { "xchgS", { RMeSP, eAX }, 0 },
+ { "xchgS", { RMeBP, eAX }, 0 },
+ { "xchgS", { RMeSI, eAX }, 0 },
+ { "xchgS", { RMeDI, eAX }, 0 },
/* 98 */
- { "cW{t|}R", { XX } },
- { "cR{t|}O", { XX } },
+ { "cW{t|}R", { XX }, 0 },
+ { "cR{t|}O", { XX }, 0 },
{ X86_64_TABLE (X86_64_9A) },
{ Bad_Opcode }, /* fwait */
- { "pushfT", { XX } },
- { "popfT", { XX } },
- { "sahf", { XX } },
- { "lahf", { XX } },
+ { "pushfT", { XX }, 0 },
+ { "popfT", { XX }, 0 },
+ { "sahf", { XX }, 0 },
+ { "lahf", { XX }, 0 },
/* a0 */
- { "mov%LB", { AL, Ob } },
- { "mov%LS", { eAX, Ov } },
- { "mov%LB", { Ob, AL } },
- { "mov%LS", { Ov, eAX } },
- { "movs{b|}", { Ybr, Xb } },
- { "movs{R|}", { Yvr, Xv } },
- { "cmps{b|}", { Xb, Yb } },
- { "cmps{R|}", { Xv, Yv } },
+ { "mov%LB", { AL, Ob }, 0 },
+ { "mov%LS", { eAX, Ov }, 0 },
+ { "mov%LB", { Ob, AL }, 0 },
+ { "mov%LS", { Ov, eAX }, 0 },
+ { "movs{b|}", { Ybr, Xb }, 0 },
+ { "movs{R|}", { Yvr, Xv }, 0 },
+ { "cmps{b|}", { Xb, Yb }, 0 },
+ { "cmps{R|}", { Xv, Yv }, 0 },
/* a8 */
- { "testB", { AL, Ib } },
- { "testS", { eAX, Iv } },
- { "stosB", { Ybr, AL } },
- { "stosS", { Yvr, eAX } },
- { "lodsB", { ALr, Xb } },
- { "lodsS", { eAXr, Xv } },
- { "scasB", { AL, Yb } },
- { "scasS", { eAX, Yv } },
+ { "testB", { AL, Ib }, 0 },
+ { "testS", { eAX, Iv }, 0 },
+ { "stosB", { Ybr, AL }, 0 },
+ { "stosS", { Yvr, eAX }, 0 },
+ { "lodsB", { ALr, Xb }, 0 },
+ { "lodsS", { eAXr, Xv }, 0 },
+ { "scasB", { AL, Yb }, 0 },
+ { "scasS", { eAX, Yv }, 0 },
/* b0 */
- { "movB", { RMAL, Ib } },
- { "movB", { RMCL, Ib } },
- { "movB", { RMDL, Ib } },
- { "movB", { RMBL, Ib } },
- { "movB", { RMAH, Ib } },
- { "movB", { RMCH, Ib } },
- { "movB", { RMDH, Ib } },
- { "movB", { RMBH, Ib } },
+ { "movB", { RMAL, Ib }, 0 },
+ { "movB", { RMCL, Ib }, 0 },
+ { "movB", { RMDL, Ib }, 0 },
+ { "movB", { RMBL, Ib }, 0 },
+ { "movB", { RMAH, Ib }, 0 },
+ { "movB", { RMCH, Ib }, 0 },
+ { "movB", { RMDH, Ib }, 0 },
+ { "movB", { RMBH, Ib }, 0 },
/* b8 */
- { "mov%LV", { RMeAX, Iv64 } },
- { "mov%LV", { RMeCX, Iv64 } },
- { "mov%LV", { RMeDX, Iv64 } },
- { "mov%LV", { RMeBX, Iv64 } },
- { "mov%LV", { RMeSP, Iv64 } },
- { "mov%LV", { RMeBP, Iv64 } },
- { "mov%LV", { RMeSI, Iv64 } },
- { "mov%LV", { RMeDI, Iv64 } },
+ { "mov%LV", { RMeAX, Iv64 }, 0 },
+ { "mov%LV", { RMeCX, Iv64 }, 0 },
+ { "mov%LV", { RMeDX, Iv64 }, 0 },
+ { "mov%LV", { RMeBX, Iv64 }, 0 },
+ { "mov%LV", { RMeSP, Iv64 }, 0 },
+ { "mov%LV", { RMeBP, Iv64 }, 0 },
+ { "mov%LV", { RMeSI, Iv64 }, 0 },
+ { "mov%LV", { RMeDI, Iv64 }, 0 },
/* c0 */
{ REG_TABLE (REG_C0) },
{ REG_TABLE (REG_C1) },
- { "retT", { Iw } },
- { "retT", { XX } },
+ { "retT", { Iw, BND }, 0 },
+ { "retT", { BND }, 0 },
{ X86_64_TABLE (X86_64_C4) },
{ X86_64_TABLE (X86_64_C5) },
{ REG_TABLE (REG_C6) },
{ REG_TABLE (REG_C7) },
/* c8 */
- { "enterT", { Iw, Ib } },
- { "leaveT", { XX } },
- { "Jret{|f}P", { Iw } },
- { "Jret{|f}P", { XX } },
- { "int3", { XX } },
- { "int", { Ib } },
+ { "enterT", { Iw, Ib }, 0 },
+ { "leaveT", { XX }, 0 },
+ { "Jret{|f}P", { Iw }, 0 },
+ { "Jret{|f}P", { XX }, 0 },
+ { "int3", { XX }, 0 },
+ { "int", { Ib }, 0 },
{ X86_64_TABLE (X86_64_CE) },
- { "iretP", { XX } },
+ { "iret%LP", { XX }, 0 },
/* d0 */
{ REG_TABLE (REG_D0) },
{ REG_TABLE (REG_D1) },
{ X86_64_TABLE (X86_64_D4) },
{ X86_64_TABLE (X86_64_D5) },
{ Bad_Opcode },
- { "xlat", { DSBX } },
+ { "xlat", { DSBX }, 0 },
/* d8 */
{ FLOAT },
{ FLOAT },
{ FLOAT },
{ FLOAT },
/* e0 */
- { "loopneFH", { Jb, XX, loop_jcxz_flag } },
- { "loopeFH", { Jb, XX, loop_jcxz_flag } },
- { "loopFH", { Jb, XX, loop_jcxz_flag } },
- { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
- { "inB", { AL, Ib } },
- { "inG", { zAX, Ib } },
- { "outB", { Ib, AL } },
- { "outG", { Ib, zAX } },
+ { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
+ { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
+ { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
+ { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
+ { "inB", { AL, Ib }, 0 },
+ { "inG", { zAX, Ib }, 0 },
+ { "outB", { Ib, AL }, 0 },
+ { "outG", { Ib, zAX }, 0 },
/* e8 */
- { "callT", { Jv } },
- { "jmpT", { Jv } },
+ { X86_64_TABLE (X86_64_E8) },
+ { X86_64_TABLE (X86_64_E9) },
{ X86_64_TABLE (X86_64_EA) },
- { "jmp", { Jb } },
- { "inB", { AL, indirDX } },
- { "inG", { zAX, indirDX } },
- { "outB", { indirDX, AL } },
- { "outG", { indirDX, zAX } },
+ { "jmp", { Jb, BND }, 0 },
+ { "inB", { AL, indirDX }, 0 },
+ { "inG", { zAX, indirDX }, 0 },
+ { "outB", { indirDX, AL }, 0 },
+ { "outG", { indirDX, zAX }, 0 },
/* f0 */
{ Bad_Opcode }, /* lock prefix */
- { "icebp", { XX } },
+ { "icebp", { XX }, 0 },
{ Bad_Opcode }, /* repne */
{ Bad_Opcode }, /* repz */
- { "hlt", { XX } },
- { "cmc", { XX } },
+ { "hlt", { XX }, 0 },
+ { "cmc", { XX }, 0 },
{ REG_TABLE (REG_F6) },
{ REG_TABLE (REG_F7) },
/* f8 */
- { "clc", { XX } },
- { "stc", { XX } },
- { "cli", { XX } },
- { "sti", { XX } },
- { "cld", { XX } },
- { "std", { XX } },
+ { "clc", { XX }, 0 },
+ { "stc", { XX }, 0 },
+ { "cli", { XX }, 0 },
+ { "sti", { XX }, 0 },
+ { "cld", { XX }, 0 },
+ { "std", { XX }, 0 },
{ REG_TABLE (REG_FE) },
{ REG_TABLE (REG_FF) },
};
/* 00 */
{ REG_TABLE (REG_0F00 ) },
{ REG_TABLE (REG_0F01 ) },
- { "larS", { Gv, Ew } },
- { "lslS", { Gv, Ew } },
+ { "larS", { Gv, Ew }, 0 },
+ { "lslS", { Gv, Ew }, 0 },
{ Bad_Opcode },
- { "syscall", { XX } },
- { "clts", { XX } },
- { "sysretP", { XX } },
+ { "syscall", { XX }, 0 },
+ { "clts", { XX }, 0 },
+ { "sysret%LP", { XX }, 0 },
/* 08 */
- { "invd", { XX } },
- { "wbinvd", { XX } },
+ { "invd", { XX }, 0 },
+ { "wbinvd", { XX }, 0 },
{ Bad_Opcode },
- { "ud2", { XX } },
+ { "ud2", { XX }, 0 },
{ Bad_Opcode },
{ REG_TABLE (REG_0F0D) },
- { "femms", { XX } },
- { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
+ { "femms", { XX }, 0 },
+ { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
/* 10 */
{ PREFIX_TABLE (PREFIX_0F10) },
{ PREFIX_TABLE (PREFIX_0F11) },
{ PREFIX_TABLE (PREFIX_0F12) },
{ MOD_TABLE (MOD_0F13) },
- { "unpcklpX", { XM, EXx } },
- { "unpckhpX", { XM, EXx } },
+ { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
+ { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
{ PREFIX_TABLE (PREFIX_0F16) },
{ MOD_TABLE (MOD_0F17) },
/* 18 */
{ REG_TABLE (REG_0F18) },
- { "nopQ", { Ev } },
- { "nopQ", { Ev } },
- { "nopQ", { Ev } },
- { "nopQ", { Ev } },
- { "nopQ", { Ev } },
- { "nopQ", { Ev } },
- { "nopQ", { Ev } },
+ { "nopQ", { Ev }, 0 },
+ { PREFIX_TABLE (PREFIX_0F1A) },
+ { PREFIX_TABLE (PREFIX_0F1B) },
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
/* 20 */
- { MOD_TABLE (MOD_0F20) },
- { MOD_TABLE (MOD_0F21) },
- { MOD_TABLE (MOD_0F22) },
- { MOD_TABLE (MOD_0F23) },
+ { "movZ", { Rm, Cm }, 0 },
+ { "movZ", { Rm, Dm }, 0 },
+ { "movZ", { Cm, Rm }, 0 },
+ { "movZ", { Dm, Rm }, 0 },
{ MOD_TABLE (MOD_0F24) },
{ Bad_Opcode },
{ MOD_TABLE (MOD_0F26) },
{ Bad_Opcode },
/* 28 */
- { "movapX", { XM, EXx } },
- { "movapX", { EXxS, XM } },
+ { "movapX", { XM, EXx }, PREFIX_OPCODE },
+ { "movapX", { EXxS, XM }, PREFIX_OPCODE },
{ PREFIX_TABLE (PREFIX_0F2A) },
{ PREFIX_TABLE (PREFIX_0F2B) },
{ PREFIX_TABLE (PREFIX_0F2C) },
{ PREFIX_TABLE (PREFIX_0F2E) },
{ PREFIX_TABLE (PREFIX_0F2F) },
/* 30 */
- { "wrmsr", { XX } },
- { "rdtsc", { XX } },
- { "rdmsr", { XX } },
- { "rdpmc", { XX } },
- { "sysenter", { XX } },
- { "sysexit", { XX } },
+ { "wrmsr", { XX }, 0 },
+ { "rdtsc", { XX }, 0 },
+ { "rdmsr", { XX }, 0 },
+ { "rdpmc", { XX }, 0 },
+ { "sysenter", { XX }, 0 },
+ { "sysexit", { XX }, 0 },
{ Bad_Opcode },
- { "getsec", { XX } },
+ { "getsec", { XX }, 0 },
/* 38 */
- { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
+ { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
{ Bad_Opcode },
- { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
+ { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 40 */
- { "cmovoS", { Gv, Ev } },
- { "cmovnoS", { Gv, Ev } },
- { "cmovbS", { Gv, Ev } },
- { "cmovaeS", { Gv, Ev } },
- { "cmoveS", { Gv, Ev } },
- { "cmovneS", { Gv, Ev } },
- { "cmovbeS", { Gv, Ev } },
- { "cmovaS", { Gv, Ev } },
+ { "cmovoS", { Gv, Ev }, 0 },
+ { "cmovnoS", { Gv, Ev }, 0 },
+ { "cmovbS", { Gv, Ev }, 0 },
+ { "cmovaeS", { Gv, Ev }, 0 },
+ { "cmoveS", { Gv, Ev }, 0 },
+ { "cmovneS", { Gv, Ev }, 0 },
+ { "cmovbeS", { Gv, Ev }, 0 },
+ { "cmovaS", { Gv, Ev }, 0 },
/* 48 */
- { "cmovsS", { Gv, Ev } },
- { "cmovnsS", { Gv, Ev } },
- { "cmovpS", { Gv, Ev } },
- { "cmovnpS", { Gv, Ev } },
- { "cmovlS", { Gv, Ev } },
- { "cmovgeS", { Gv, Ev } },
- { "cmovleS", { Gv, Ev } },
- { "cmovgS", { Gv, Ev } },
+ { "cmovsS", { Gv, Ev }, 0 },
+ { "cmovnsS", { Gv, Ev }, 0 },
+ { "cmovpS", { Gv, Ev }, 0 },
+ { "cmovnpS", { Gv, Ev }, 0 },
+ { "cmovlS", { Gv, Ev }, 0 },
+ { "cmovgeS", { Gv, Ev }, 0 },
+ { "cmovleS", { Gv, Ev }, 0 },
+ { "cmovgS", { Gv, Ev }, 0 },
/* 50 */
{ MOD_TABLE (MOD_0F51) },
{ PREFIX_TABLE (PREFIX_0F51) },
{ PREFIX_TABLE (PREFIX_0F52) },
{ PREFIX_TABLE (PREFIX_0F53) },
- { "andpX", { XM, EXx } },
- { "andnpX", { XM, EXx } },
- { "orpX", { XM, EXx } },
- { "xorpX", { XM, EXx } },
+ { "andpX", { XM, EXx }, PREFIX_OPCODE },
+ { "andnpX", { XM, EXx }, PREFIX_OPCODE },
+ { "orpX", { XM, EXx }, PREFIX_OPCODE },
+ { "xorpX", { XM, EXx }, PREFIX_OPCODE },
/* 58 */
{ PREFIX_TABLE (PREFIX_0F58) },
{ PREFIX_TABLE (PREFIX_0F59) },
{ PREFIX_TABLE (PREFIX_0F60) },
{ PREFIX_TABLE (PREFIX_0F61) },
{ PREFIX_TABLE (PREFIX_0F62) },
- { "packsswb", { MX, EM } },
- { "pcmpgtb", { MX, EM } },
- { "pcmpgtw", { MX, EM } },
- { "pcmpgtd", { MX, EM } },
- { "packuswb", { MX, EM } },
+ { "packsswb", { MX, EM }, PREFIX_OPCODE },
+ { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
+ { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
+ { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
+ { "packuswb", { MX, EM }, PREFIX_OPCODE },
/* 68 */
- { "punpckhbw", { MX, EM } },
- { "punpckhwd", { MX, EM } },
- { "punpckhdq", { MX, EM } },
- { "packssdw", { MX, EM } },
+ { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
+ { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
+ { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
+ { "packssdw", { MX, EM }, PREFIX_OPCODE },
{ PREFIX_TABLE (PREFIX_0F6C) },
{ PREFIX_TABLE (PREFIX_0F6D) },
- { "movK", { MX, Edq } },
+ { "movK", { MX, Edq }, PREFIX_OPCODE },
{ PREFIX_TABLE (PREFIX_0F6F) },
/* 70 */
{ PREFIX_TABLE (PREFIX_0F70) },
{ REG_TABLE (REG_0F71) },
{ REG_TABLE (REG_0F72) },
{ REG_TABLE (REG_0F73) },
- { "pcmpeqb", { MX, EM } },
- { "pcmpeqw", { MX, EM } },
- { "pcmpeqd", { MX, EM } },
- { "emms", { XX } },
+ { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
+ { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
+ { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
+ { "emms", { XX }, PREFIX_OPCODE },
/* 78 */
{ PREFIX_TABLE (PREFIX_0F78) },
{ PREFIX_TABLE (PREFIX_0F79) },
{ PREFIX_TABLE (PREFIX_0F7E) },
{ PREFIX_TABLE (PREFIX_0F7F) },
/* 80 */
- { "joH", { Jv, XX, cond_jump_flag } },
- { "jnoH", { Jv, XX, cond_jump_flag } },
- { "jbH", { Jv, XX, cond_jump_flag } },
- { "jaeH", { Jv, XX, cond_jump_flag } },
- { "jeH", { Jv, XX, cond_jump_flag } },
- { "jneH", { Jv, XX, cond_jump_flag } },
- { "jbeH", { Jv, XX, cond_jump_flag } },
- { "jaH", { Jv, XX, cond_jump_flag } },
+ { "joH", { Jv, BND, cond_jump_flag }, 0 },
+ { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
+ { "jbH", { Jv, BND, cond_jump_flag }, 0 },
+ { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
+ { "jeH", { Jv, BND, cond_jump_flag }, 0 },
+ { "jneH", { Jv, BND, cond_jump_flag }, 0 },
+ { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
+ { "jaH", { Jv, BND, cond_jump_flag }, 0 },
/* 88 */
- { "jsH", { Jv, XX, cond_jump_flag } },
- { "jnsH", { Jv, XX, cond_jump_flag } },
- { "jpH", { Jv, XX, cond_jump_flag } },
- { "jnpH", { Jv, XX, cond_jump_flag } },
- { "jlH", { Jv, XX, cond_jump_flag } },
- { "jgeH", { Jv, XX, cond_jump_flag } },
- { "jleH", { Jv, XX, cond_jump_flag } },
- { "jgH", { Jv, XX, cond_jump_flag } },
+ { "jsH", { Jv, BND, cond_jump_flag }, 0 },
+ { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
+ { "jpH", { Jv, BND, cond_jump_flag }, 0 },
+ { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
+ { "jlH", { Jv, BND, cond_jump_flag }, 0 },
+ { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
+ { "jleH", { Jv, BND, cond_jump_flag }, 0 },
+ { "jgH", { Jv, BND, cond_jump_flag }, 0 },
/* 90 */
- { "seto", { Eb } },
- { "setno", { Eb } },
- { "setb", { Eb } },
- { "setae", { Eb } },
- { "sete", { Eb } },
- { "setne", { Eb } },
- { "setbe", { Eb } },
- { "seta", { Eb } },
+ { "seto", { Eb }, 0 },
+ { "setno", { Eb }, 0 },
+ { "setb", { Eb }, 0 },
+ { "setae", { Eb }, 0 },
+ { "sete", { Eb }, 0 },
+ { "setne", { Eb }, 0 },
+ { "setbe", { Eb }, 0 },
+ { "seta", { Eb }, 0 },
/* 98 */
- { "sets", { Eb } },
- { "setns", { Eb } },
- { "setp", { Eb } },
- { "setnp", { Eb } },
- { "setl", { Eb } },
- { "setge", { Eb } },
- { "setle", { Eb } },
- { "setg", { Eb } },
+ { "sets", { Eb }, 0 },
+ { "setns", { Eb }, 0 },
+ { "setp", { Eb }, 0 },
+ { "setnp", { Eb }, 0 },
+ { "setl", { Eb }, 0 },
+ { "setge", { Eb }, 0 },
+ { "setle", { Eb }, 0 },
+ { "setg", { Eb }, 0 },
/* a0 */
- { "pushT", { fs } },
- { "popT", { fs } },
- { "cpuid", { XX } },
- { "btS", { Ev, Gv } },
- { "shldS", { Ev, Gv, Ib } },
- { "shldS", { Ev, Gv, CL } },
+ { "pushT", { fs }, 0 },
+ { "popT", { fs }, 0 },
+ { "cpuid", { XX }, 0 },
+ { "btS", { Ev, Gv }, 0 },
+ { "shldS", { Ev, Gv, Ib }, 0 },
+ { "shldS", { Ev, Gv, CL }, 0 },
{ REG_TABLE (REG_0FA6) },
{ REG_TABLE (REG_0FA7) },
/* a8 */
- { "pushT", { gs } },
- { "popT", { gs } },
- { "rsm", { XX } },
- { "btsS", { Ev, Gv } },
- { "shrdS", { Ev, Gv, Ib } },
- { "shrdS", { Ev, Gv, CL } },
+ { "pushT", { gs }, 0 },
+ { "popT", { gs }, 0 },
+ { "rsm", { XX }, 0 },
+ { "btsS", { Evh1, Gv }, 0 },
+ { "shrdS", { Ev, Gv, Ib }, 0 },
+ { "shrdS", { Ev, Gv, CL }, 0 },
{ REG_TABLE (REG_0FAE) },
- { "imulS", { Gv, Ev } },
+ { "imulS", { Gv, Ev }, 0 },
/* b0 */
- { "cmpxchgB", { Eb, Gb } },
- { "cmpxchgS", { Ev, Gv } },
+ { "cmpxchgB", { Ebh1, Gb }, 0 },
+ { "cmpxchgS", { Evh1, Gv }, 0 },
{ MOD_TABLE (MOD_0FB2) },
- { "btrS", { Ev, Gv } },
+ { "btrS", { Evh1, Gv }, 0 },
{ MOD_TABLE (MOD_0FB4) },
{ MOD_TABLE (MOD_0FB5) },
- { "movz{bR|x}", { Gv, Eb } },
- { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
+ { "movz{bR|x}", { Gv, Eb }, 0 },
+ { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
/* b8 */
{ PREFIX_TABLE (PREFIX_0FB8) },
- { "ud1", { XX } },
+ { "ud1", { XX }, 0 },
{ REG_TABLE (REG_0FBA) },
- { "btcS", { Ev, Gv } },
- { "bsfS", { Gv, Ev } },
+ { "btcS", { Evh1, Gv }, 0 },
+ { PREFIX_TABLE (PREFIX_0FBC) },
{ PREFIX_TABLE (PREFIX_0FBD) },
- { "movs{bR|x}", { Gv, Eb } },
- { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
+ { "movs{bR|x}", { Gv, Eb }, 0 },
+ { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
/* c0 */
- { "xaddB", { Eb, Gb } },
- { "xaddS", { Ev, Gv } },
+ { "xaddB", { Ebh1, Gb }, 0 },
+ { "xaddS", { Evh1, Gv }, 0 },
{ PREFIX_TABLE (PREFIX_0FC2) },
- { PREFIX_TABLE (PREFIX_0FC3) },
- { "pinsrw", { MX, Edqw, Ib } },
- { "pextrw", { Gdq, MS, Ib } },
- { "shufpX", { XM, EXx, Ib } },
+ { MOD_TABLE (MOD_0FC3) },
+ { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
+ { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
+ { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
{ REG_TABLE (REG_0FC7) },
/* c8 */
- { "bswap", { RMeAX } },
- { "bswap", { RMeCX } },
- { "bswap", { RMeDX } },
- { "bswap", { RMeBX } },
- { "bswap", { RMeSP } },
- { "bswap", { RMeBP } },
- { "bswap", { RMeSI } },
- { "bswap", { RMeDI } },
+ { "bswap", { RMeAX }, 0 },
+ { "bswap", { RMeCX }, 0 },
+ { "bswap", { RMeDX }, 0 },
+ { "bswap", { RMeBX }, 0 },
+ { "bswap", { RMeSP }, 0 },
+ { "bswap", { RMeBP }, 0 },
+ { "bswap", { RMeSI }, 0 },
+ { "bswap", { RMeDI }, 0 },
/* d0 */
{ PREFIX_TABLE (PREFIX_0FD0) },
- { "psrlw", { MX, EM } },
- { "psrld", { MX, EM } },
- { "psrlq", { MX, EM } },
- { "paddq", { MX, EM } },
- { "pmullw", { MX, EM } },
+ { "psrlw", { MX, EM }, PREFIX_OPCODE },
+ { "psrld", { MX, EM }, PREFIX_OPCODE },
+ { "psrlq", { MX, EM }, PREFIX_OPCODE },
+ { "paddq", { MX, EM }, PREFIX_OPCODE },
+ { "pmullw", { MX, EM }, PREFIX_OPCODE },
{ PREFIX_TABLE (PREFIX_0FD6) },
{ MOD_TABLE (MOD_0FD7) },
/* d8 */
- { "psubusb", { MX, EM } },
- { "psubusw", { MX, EM } },
- { "pminub", { MX, EM } },
- { "pand", { MX, EM } },
- { "paddusb", { MX, EM } },
- { "paddusw", { MX, EM } },
- { "pmaxub", { MX, EM } },
- { "pandn", { MX, EM } },
+ { "psubusb", { MX, EM }, PREFIX_OPCODE },
+ { "psubusw", { MX, EM }, PREFIX_OPCODE },
+ { "pminub", { MX, EM }, PREFIX_OPCODE },
+ { "pand", { MX, EM }, PREFIX_OPCODE },
+ { "paddusb", { MX, EM }, PREFIX_OPCODE },
+ { "paddusw", { MX, EM }, PREFIX_OPCODE },
+ { "pmaxub", { MX, EM }, PREFIX_OPCODE },
+ { "pandn", { MX, EM }, PREFIX_OPCODE },
/* e0 */
- { "pavgb", { MX, EM } },
- { "psraw", { MX, EM } },
- { "psrad", { MX, EM } },
- { "pavgw", { MX, EM } },
- { "pmulhuw", { MX, EM } },
- { "pmulhw", { MX, EM } },
+ { "pavgb", { MX, EM }, PREFIX_OPCODE },
+ { "psraw", { MX, EM }, PREFIX_OPCODE },
+ { "psrad", { MX, EM }, PREFIX_OPCODE },
+ { "pavgw", { MX, EM }, PREFIX_OPCODE },
+ { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
+ { "pmulhw", { MX, EM }, PREFIX_OPCODE },
{ PREFIX_TABLE (PREFIX_0FE6) },
{ PREFIX_TABLE (PREFIX_0FE7) },
/* e8 */
- { "psubsb", { MX, EM } },
- { "psubsw", { MX, EM } },
- { "pminsw", { MX, EM } },
- { "por", { MX, EM } },
- { "paddsb", { MX, EM } },
- { "paddsw", { MX, EM } },
- { "pmaxsw", { MX, EM } },
- { "pxor", { MX, EM } },
+ { "psubsb", { MX, EM }, PREFIX_OPCODE },
+ { "psubsw", { MX, EM }, PREFIX_OPCODE },
+ { "pminsw", { MX, EM }, PREFIX_OPCODE },
+ { "por", { MX, EM }, PREFIX_OPCODE },
+ { "paddsb", { MX, EM }, PREFIX_OPCODE },
+ { "paddsw", { MX, EM }, PREFIX_OPCODE },
+ { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
+ { "pxor", { MX, EM }, PREFIX_OPCODE },
/* f0 */
{ PREFIX_TABLE (PREFIX_0FF0) },
- { "psllw", { MX, EM } },
- { "pslld", { MX, EM } },
- { "psllq", { MX, EM } },
- { "pmuludq", { MX, EM } },
- { "pmaddwd", { MX, EM } },
- { "psadbw", { MX, EM } },
+ { "psllw", { MX, EM }, PREFIX_OPCODE },
+ { "pslld", { MX, EM }, PREFIX_OPCODE },
+ { "psllq", { MX, EM }, PREFIX_OPCODE },
+ { "pmuludq", { MX, EM }, PREFIX_OPCODE },
+ { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
+ { "psadbw", { MX, EM }, PREFIX_OPCODE },
{ PREFIX_TABLE (PREFIX_0FF7) },
/* f8 */
- { "psubb", { MX, EM } },
- { "psubw", { MX, EM } },
- { "psubd", { MX, EM } },
- { "psubq", { MX, EM } },
- { "paddb", { MX, EM } },
- { "paddw", { MX, EM } },
- { "paddd", { MX, EM } },
+ { "psubb", { MX, EM }, PREFIX_OPCODE },
+ { "psubw", { MX, EM }, PREFIX_OPCODE },
+ { "psubd", { MX, EM }, PREFIX_OPCODE },
+ { "psubq", { MX, EM }, PREFIX_OPCODE },
+ { "paddb", { MX, EM }, PREFIX_OPCODE },
+ { "paddw", { MX, EM }, PREFIX_OPCODE },
+ { "paddd", { MX, EM }, PREFIX_OPCODE },
{ Bad_Opcode },
};
static unsigned char *start_codep;
static unsigned char *insn_codep;
static unsigned char *codep;
+static unsigned char *end_codep;
static int last_lock_prefix;
static int last_repz_prefix;
static int last_repnz_prefix;
static int last_addr_prefix;
static int last_rex_prefix;
static int last_seg_prefix;
+static int fwait_prefix;
+/* The active segment register prefix. */
+static int active_seg_prefix;
#define MAX_CODE_LENGTH 15
/* We can up to 14 prefixes since the maximum instruction length is
15bytes. */
int length;
int prefix;
int w;
+ int evex;
+ int r;
+ int v;
+ int mask_register_specifier;
+ int zeroing;
+ int ll;
+ int b;
}
vex;
static unsigned char need_vex;
static const char *index64;
static const char *index32;
static const char **index16;
+static const char **names_bnd;
static const char *intel_names64[] = {
"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
"%mm4", "%mm5", "%mm6", "%mm7"
};
+static const char *intel_names_bnd[] = {
+ "bnd0", "bnd1", "bnd2", "bnd3"
+};
+
+static const char *att_names_bnd[] = {
+ "%bnd0", "%bnd1", "%bnd2", "%bnd3"
+};
+
static const char **names_xmm;
static const char *intel_names_xmm[] = {
"xmm0", "xmm1", "xmm2", "xmm3",
"xmm4", "xmm5", "xmm6", "xmm7",
"xmm8", "xmm9", "xmm10", "xmm11",
- "xmm12", "xmm13", "xmm14", "xmm15"
+ "xmm12", "xmm13", "xmm14", "xmm15",
+ "xmm16", "xmm17", "xmm18", "xmm19",
+ "xmm20", "xmm21", "xmm22", "xmm23",
+ "xmm24", "xmm25", "xmm26", "xmm27",
+ "xmm28", "xmm29", "xmm30", "xmm31"
};
static const char *att_names_xmm[] = {
"%xmm0", "%xmm1", "%xmm2", "%xmm3",
"%xmm4", "%xmm5", "%xmm6", "%xmm7",
"%xmm8", "%xmm9", "%xmm10", "%xmm11",
- "%xmm12", "%xmm13", "%xmm14", "%xmm15"
+ "%xmm12", "%xmm13", "%xmm14", "%xmm15",
+ "%xmm16", "%xmm17", "%xmm18", "%xmm19",
+ "%xmm20", "%xmm21", "%xmm22", "%xmm23",
+ "%xmm24", "%xmm25", "%xmm26", "%xmm27",
+ "%xmm28", "%xmm29", "%xmm30", "%xmm31"
};
static const char **names_ymm;
"ymm0", "ymm1", "ymm2", "ymm3",
"ymm4", "ymm5", "ymm6", "ymm7",
"ymm8", "ymm9", "ymm10", "ymm11",
- "ymm12", "ymm13", "ymm14", "ymm15"
+ "ymm12", "ymm13", "ymm14", "ymm15",
+ "ymm16", "ymm17", "ymm18", "ymm19",
+ "ymm20", "ymm21", "ymm22", "ymm23",
+ "ymm24", "ymm25", "ymm26", "ymm27",
+ "ymm28", "ymm29", "ymm30", "ymm31"
};
static const char *att_names_ymm[] = {
"%ymm0", "%ymm1", "%ymm2", "%ymm3",
"%ymm4", "%ymm5", "%ymm6", "%ymm7",
"%ymm8", "%ymm9", "%ymm10", "%ymm11",
- "%ymm12", "%ymm13", "%ymm14", "%ymm15"
+ "%ymm12", "%ymm13", "%ymm14", "%ymm15",
+ "%ymm16", "%ymm17", "%ymm18", "%ymm19",
+ "%ymm20", "%ymm21", "%ymm22", "%ymm23",
+ "%ymm24", "%ymm25", "%ymm26", "%ymm27",
+ "%ymm28", "%ymm29", "%ymm30", "%ymm31"
+};
+
+static const char **names_zmm;
+static const char *intel_names_zmm[] = {
+ "zmm0", "zmm1", "zmm2", "zmm3",
+ "zmm4", "zmm5", "zmm6", "zmm7",
+ "zmm8", "zmm9", "zmm10", "zmm11",
+ "zmm12", "zmm13", "zmm14", "zmm15",
+ "zmm16", "zmm17", "zmm18", "zmm19",
+ "zmm20", "zmm21", "zmm22", "zmm23",
+ "zmm24", "zmm25", "zmm26", "zmm27",
+ "zmm28", "zmm29", "zmm30", "zmm31"
+};
+static const char *att_names_zmm[] = {
+ "%zmm0", "%zmm1", "%zmm2", "%zmm3",
+ "%zmm4", "%zmm5", "%zmm6", "%zmm7",
+ "%zmm8", "%zmm9", "%zmm10", "%zmm11",
+ "%zmm12", "%zmm13", "%zmm14", "%zmm15",
+ "%zmm16", "%zmm17", "%zmm18", "%zmm19",
+ "%zmm20", "%zmm21", "%zmm22", "%zmm23",
+ "%zmm24", "%zmm25", "%zmm26", "%zmm27",
+ "%zmm28", "%zmm29", "%zmm30", "%zmm31"
+};
+
+static const char **names_mask;
+static const char *intel_names_mask[] = {
+ "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
+};
+static const char *att_names_mask[] = {
+ "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
+};
+
+static const char *names_rounding[] =
+{
+ "{rn-sae}",
+ "{rd-sae}",
+ "{ru-sae}",
+ "{rz-sae}"
};
static const struct dis386 reg_table[][8] = {
/* REG_80 */
{
- { "addA", { Eb, Ib } },
- { "orA", { Eb, Ib } },
- { "adcA", { Eb, Ib } },
- { "sbbA", { Eb, Ib } },
- { "andA", { Eb, Ib } },
- { "subA", { Eb, Ib } },
- { "xorA", { Eb, Ib } },
- { "cmpA", { Eb, Ib } },
+ { "addA", { Ebh1, Ib }, 0 },
+ { "orA", { Ebh1, Ib }, 0 },
+ { "adcA", { Ebh1, Ib }, 0 },
+ { "sbbA", { Ebh1, Ib }, 0 },
+ { "andA", { Ebh1, Ib }, 0 },
+ { "subA", { Ebh1, Ib }, 0 },
+ { "xorA", { Ebh1, Ib }, 0 },
+ { "cmpA", { Eb, Ib }, 0 },
},
/* REG_81 */
{
- { "addQ", { Ev, Iv } },
- { "orQ", { Ev, Iv } },
- { "adcQ", { Ev, Iv } },
- { "sbbQ", { Ev, Iv } },
- { "andQ", { Ev, Iv } },
- { "subQ", { Ev, Iv } },
- { "xorQ", { Ev, Iv } },
- { "cmpQ", { Ev, Iv } },
+ { "addQ", { Evh1, Iv }, 0 },
+ { "orQ", { Evh1, Iv }, 0 },
+ { "adcQ", { Evh1, Iv }, 0 },
+ { "sbbQ", { Evh1, Iv }, 0 },
+ { "andQ", { Evh1, Iv }, 0 },
+ { "subQ", { Evh1, Iv }, 0 },
+ { "xorQ", { Evh1, Iv }, 0 },
+ { "cmpQ", { Ev, Iv }, 0 },
},
/* REG_82 */
{
- { "addQ", { Ev, sIb } },
- { "orQ", { Ev, sIb } },
- { "adcQ", { Ev, sIb } },
- { "sbbQ", { Ev, sIb } },
- { "andQ", { Ev, sIb } },
- { "subQ", { Ev, sIb } },
- { "xorQ", { Ev, sIb } },
- { "cmpQ", { Ev, sIb } },
+ { "addQ", { Evh1, sIb }, 0 },
+ { "orQ", { Evh1, sIb }, 0 },
+ { "adcQ", { Evh1, sIb }, 0 },
+ { "sbbQ", { Evh1, sIb }, 0 },
+ { "andQ", { Evh1, sIb }, 0 },
+ { "subQ", { Evh1, sIb }, 0 },
+ { "xorQ", { Evh1, sIb }, 0 },
+ { "cmpQ", { Ev, sIb }, 0 },
},
/* REG_8F */
{
- { "popU", { stackEv } },
+ { "popU", { stackEv }, 0 },
{ XOP_8F_TABLE (XOP_09) },
{ Bad_Opcode },
{ Bad_Opcode },
},
/* REG_C0 */
{
- { "rolA", { Eb, Ib } },
- { "rorA", { Eb, Ib } },
- { "rclA", { Eb, Ib } },
- { "rcrA", { Eb, Ib } },
- { "shlA", { Eb, Ib } },
- { "shrA", { Eb, Ib } },
+ { "rolA", { Eb, Ib }, 0 },
+ { "rorA", { Eb, Ib }, 0 },
+ { "rclA", { Eb, Ib }, 0 },
+ { "rcrA", { Eb, Ib }, 0 },
+ { "shlA", { Eb, Ib }, 0 },
+ { "shrA", { Eb, Ib }, 0 },
{ Bad_Opcode },
- { "sarA", { Eb, Ib } },
+ { "sarA", { Eb, Ib }, 0 },
},
/* REG_C1 */
{
- { "rolQ", { Ev, Ib } },
- { "rorQ", { Ev, Ib } },
- { "rclQ", { Ev, Ib } },
- { "rcrQ", { Ev, Ib } },
- { "shlQ", { Ev, Ib } },
- { "shrQ", { Ev, Ib } },
+ { "rolQ", { Ev, Ib }, 0 },
+ { "rorQ", { Ev, Ib }, 0 },
+ { "rclQ", { Ev, Ib }, 0 },
+ { "rcrQ", { Ev, Ib }, 0 },
+ { "shlQ", { Ev, Ib }, 0 },
+ { "shrQ", { Ev, Ib }, 0 },
{ Bad_Opcode },
- { "sarQ", { Ev, Ib } },
+ { "sarQ", { Ev, Ib }, 0 },
},
/* REG_C6 */
{
- { "movA", { Eb, Ib } },
+ { "movA", { Ebh3, Ib }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_C6_REG_7) },
},
/* REG_C7 */
{
- { "movQ", { Ev, Iv } },
+ { "movQ", { Evh3, Iv }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_C7_REG_7) },
},
/* REG_D0 */
{
- { "rolA", { Eb, I1 } },
- { "rorA", { Eb, I1 } },
- { "rclA", { Eb, I1 } },
- { "rcrA", { Eb, I1 } },
- { "shlA", { Eb, I1 } },
- { "shrA", { Eb, I1 } },
+ { "rolA", { Eb, I1 }, 0 },
+ { "rorA", { Eb, I1 }, 0 },
+ { "rclA", { Eb, I1 }, 0 },
+ { "rcrA", { Eb, I1 }, 0 },
+ { "shlA", { Eb, I1 }, 0 },
+ { "shrA", { Eb, I1 }, 0 },
{ Bad_Opcode },
- { "sarA", { Eb, I1 } },
+ { "sarA", { Eb, I1 }, 0 },
},
/* REG_D1 */
{
- { "rolQ", { Ev, I1 } },
- { "rorQ", { Ev, I1 } },
- { "rclQ", { Ev, I1 } },
- { "rcrQ", { Ev, I1 } },
- { "shlQ", { Ev, I1 } },
- { "shrQ", { Ev, I1 } },
+ { "rolQ", { Ev, I1 }, 0 },
+ { "rorQ", { Ev, I1 }, 0 },
+ { "rclQ", { Ev, I1 }, 0 },
+ { "rcrQ", { Ev, I1 }, 0 },
+ { "shlQ", { Ev, I1 }, 0 },
+ { "shrQ", { Ev, I1 }, 0 },
{ Bad_Opcode },
- { "sarQ", { Ev, I1 } },
+ { "sarQ", { Ev, I1 }, 0 },
},
/* REG_D2 */
{
- { "rolA", { Eb, CL } },
- { "rorA", { Eb, CL } },
- { "rclA", { Eb, CL } },
- { "rcrA", { Eb, CL } },
- { "shlA", { Eb, CL } },
- { "shrA", { Eb, CL } },
+ { "rolA", { Eb, CL }, 0 },
+ { "rorA", { Eb, CL }, 0 },
+ { "rclA", { Eb, CL }, 0 },
+ { "rcrA", { Eb, CL }, 0 },
+ { "shlA", { Eb, CL }, 0 },
+ { "shrA", { Eb, CL }, 0 },
{ Bad_Opcode },
- { "sarA", { Eb, CL } },
+ { "sarA", { Eb, CL }, 0 },
},
/* REG_D3 */
{
- { "rolQ", { Ev, CL } },
- { "rorQ", { Ev, CL } },
- { "rclQ", { Ev, CL } },
- { "rcrQ", { Ev, CL } },
- { "shlQ", { Ev, CL } },
- { "shrQ", { Ev, CL } },
+ { "rolQ", { Ev, CL }, 0 },
+ { "rorQ", { Ev, CL }, 0 },
+ { "rclQ", { Ev, CL }, 0 },
+ { "rcrQ", { Ev, CL }, 0 },
+ { "shlQ", { Ev, CL }, 0 },
+ { "shrQ", { Ev, CL }, 0 },
{ Bad_Opcode },
- { "sarQ", { Ev, CL } },
+ { "sarQ", { Ev, CL }, 0 },
},
/* REG_F6 */
{
- { "testA", { Eb, Ib } },
+ { "testA", { Eb, Ib }, 0 },
{ Bad_Opcode },
- { "notA", { Eb } },
- { "negA", { Eb } },
- { "mulA", { Eb } }, /* Don't print the implicit %al register, */
- { "imulA", { Eb } }, /* to distinguish these opcodes from other */
- { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
- { "idivA", { Eb } }, /* and idiv for consistency. */
+ { "notA", { Ebh1 }, 0 },
+ { "negA", { Ebh1 }, 0 },
+ { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
+ { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
+ { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
+ { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
},
/* REG_F7 */
{
- { "testQ", { Ev, Iv } },
+ { "testQ", { Ev, Iv }, 0 },
{ Bad_Opcode },
- { "notQ", { Ev } },
- { "negQ", { Ev } },
- { "mulQ", { Ev } }, /* Don't print the implicit register. */
- { "imulQ", { Ev } },
- { "divQ", { Ev } },
- { "idivQ", { Ev } },
+ { "notQ", { Evh1 }, 0 },
+ { "negQ", { Evh1 }, 0 },
+ { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
+ { "imulQ", { Ev }, 0 },
+ { "divQ", { Ev }, 0 },
+ { "idivQ", { Ev }, 0 },
},
/* REG_FE */
{
- { "incA", { Eb } },
- { "decA", { Eb } },
+ { "incA", { Ebh1 }, 0 },
+ { "decA", { Ebh1 }, 0 },
},
/* REG_FF */
{
- { "incQ", { Ev } },
- { "decQ", { Ev } },
- { "call{T|}", { indirEv } },
- { "Jcall{T|}", { indirEp } },
- { "jmp{T|}", { indirEv } },
- { "Jjmp{T|}", { indirEp } },
- { "pushU", { stackEv } },
+ { "incQ", { Evh1 }, 0 },
+ { "decQ", { Evh1 }, 0 },
+ { "call{&|}", { indirEv, BND }, 0 },
+ { MOD_TABLE (MOD_FF_REG_3) },
+ { "jmp{&|}", { indirEv, BND }, 0 },
+ { MOD_TABLE (MOD_FF_REG_5) },
+ { "pushU", { stackEv }, 0 },
{ Bad_Opcode },
},
/* REG_0F00 */
{
- { "sldtD", { Sv } },
- { "strD", { Sv } },
- { "lldt", { Ew } },
- { "ltr", { Ew } },
- { "verr", { Ew } },
- { "verw", { Ew } },
+ { "sldtD", { Sv }, 0 },
+ { "strD", { Sv }, 0 },
+ { "lldt", { Ew }, 0 },
+ { "ltr", { Ew }, 0 },
+ { "verr", { Ew }, 0 },
+ { "verw", { Ew }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
},
{ MOD_TABLE (MOD_0F01_REG_1) },
{ MOD_TABLE (MOD_0F01_REG_2) },
{ MOD_TABLE (MOD_0F01_REG_3) },
- { "smswD", { Sv } },
- { Bad_Opcode },
- { "lmsw", { Ew } },
+ { "smswD", { Sv }, 0 },
+ { MOD_TABLE (MOD_0F01_REG_5) },
+ { "lmsw", { Ew }, 0 },
{ MOD_TABLE (MOD_0F01_REG_7) },
},
/* REG_0F0D */
{
- { "prefetch", { Mb } },
- { "prefetchw", { Mb } },
+ { "prefetch", { Mb }, 0 },
+ { "prefetchw", { Mb }, 0 },
+ { "prefetchwt1", { Mb }, 0 },
+ { "prefetch", { Mb }, 0 },
+ { "prefetch", { Mb }, 0 },
+ { "prefetch", { Mb }, 0 },
+ { "prefetch", { Mb }, 0 },
+ { "prefetch", { Mb }, 0 },
},
/* REG_0F18 */
{
{ MOD_TABLE (MOD_0F18_REG_1) },
{ MOD_TABLE (MOD_0F18_REG_2) },
{ MOD_TABLE (MOD_0F18_REG_3) },
+ { MOD_TABLE (MOD_0F18_REG_4) },
+ { MOD_TABLE (MOD_0F18_REG_5) },
+ { MOD_TABLE (MOD_0F18_REG_6) },
+ { MOD_TABLE (MOD_0F18_REG_7) },
},
/* REG_0F71 */
{
},
/* REG_0FA6 */
{
- { "montmul", { { OP_0f07, 0 } } },
- { "xsha1", { { OP_0f07, 0 } } },
- { "xsha256", { { OP_0f07, 0 } } },
+ { "montmul", { { OP_0f07, 0 } }, 0 },
+ { "xsha1", { { OP_0f07, 0 } }, 0 },
+ { "xsha256", { { OP_0f07, 0 } }, 0 },
},
/* REG_0FA7 */
{
- { "xstore-rng", { { OP_0f07, 0 } } },
- { "xcrypt-ecb", { { OP_0f07, 0 } } },
- { "xcrypt-cbc", { { OP_0f07, 0 } } },
- { "xcrypt-ctr", { { OP_0f07, 0 } } },
- { "xcrypt-cfb", { { OP_0f07, 0 } } },
- { "xcrypt-ofb", { { OP_0f07, 0 } } },
+ { "xstore-rng", { { OP_0f07, 0 } }, 0 },
+ { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
+ { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
+ { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
+ { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
+ { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
},
/* REG_0FAE */
{
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "btQ", { Ev, Ib } },
- { "btsQ", { Ev, Ib } },
- { "btrQ", { Ev, Ib } },
- { "btcQ", { Ev, Ib } },
+ { "btQ", { Ev, Ib }, 0 },
+ { "btsQ", { Evh1, Ib }, 0 },
+ { "btrQ", { Evh1, Ib }, 0 },
+ { "btcQ", { Evh1, Ib }, 0 },
},
/* REG_0FC7 */
{
{ Bad_Opcode },
- { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
{ Bad_Opcode },
+ { MOD_TABLE (MOD_0FC7_REG_3) },
+ { MOD_TABLE (MOD_0FC7_REG_4) },
+ { MOD_TABLE (MOD_0FC7_REG_5) },
{ MOD_TABLE (MOD_0FC7_REG_6) },
{ MOD_TABLE (MOD_0FC7_REG_7) },
},
{ MOD_TABLE (MOD_VEX_0FAE_REG_2) },
{ MOD_TABLE (MOD_VEX_0FAE_REG_3) },
},
+ /* REG_VEX_0F38F3 */
+ {
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
+ },
/* REG_XOP_LWPCB */
{
- { "llwpcb", { { OP_LWPCB_E, 0 } } },
- { "slwpcb", { { OP_LWPCB_E, 0 } } },
+ { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
+ { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
},
/* REG_XOP_LWP */
{
- { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
- { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
+ { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
+ { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
},
+ /* REG_XOP_TBM_01 */
+ {
+ { Bad_Opcode },
+ { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 },
+ { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 },
+ { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 },
+ { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
+ { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 },
+ { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 },
+ { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
+ },
+ /* REG_XOP_TBM_02 */
+ {
+ { Bad_Opcode },
+ { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "blci", { { OP_LWP_E, 0 }, Ev }, 0 },
+ },
+#define NEED_REG_TABLE
+#include "i386-dis-evex.h"
+#undef NEED_REG_TABLE
};
static const struct dis386 prefix_table[][4] = {
/* PREFIX_90 */
{
- { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
- { "pause", { XX } },
- { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
+ { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
+ { "pause", { XX }, 0 },
+ { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
+ { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
},
/* PREFIX_0F10 */
{
- { "movups", { XM, EXx } },
- { "movss", { XM, EXd } },
- { "movupd", { XM, EXx } },
- { "movsd", { XM, EXq } },
+ { "movups", { XM, EXx }, PREFIX_OPCODE },
+ { "movss", { XM, EXd }, PREFIX_OPCODE },
+ { "movupd", { XM, EXx }, PREFIX_OPCODE },
+ { "movsd", { XM, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F11 */
{
- { "movups", { EXxS, XM } },
- { "movss", { EXdS, XM } },
- { "movupd", { EXxS, XM } },
- { "movsd", { EXqS, XM } },
+ { "movups", { EXxS, XM }, PREFIX_OPCODE },
+ { "movss", { EXdS, XM }, PREFIX_OPCODE },
+ { "movupd", { EXxS, XM }, PREFIX_OPCODE },
+ { "movsd", { EXqS, XM }, PREFIX_OPCODE },
},
/* PREFIX_0F12 */
{
{ MOD_TABLE (MOD_0F12_PREFIX_0) },
- { "movsldup", { XM, EXx } },
- { "movlpd", { XM, EXq } },
- { "movddup", { XM, EXq } },
+ { "movsldup", { XM, EXx }, PREFIX_OPCODE },
+ { "movlpd", { XM, EXq }, PREFIX_OPCODE },
+ { "movddup", { XM, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F16 */
{
{ MOD_TABLE (MOD_0F16_PREFIX_0) },
- { "movshdup", { XM, EXx } },
- { "movhpd", { XM, EXq } },
+ { "movshdup", { XM, EXx }, PREFIX_OPCODE },
+ { "movhpd", { XM, EXq }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_0F1A */
+ {
+ { MOD_TABLE (MOD_0F1A_PREFIX_0) },
+ { "bndcl", { Gbnd, Ev_bnd }, 0 },
+ { "bndmov", { Gbnd, Ebnd }, 0 },
+ { "bndcu", { Gbnd, Ev_bnd }, 0 },
+ },
+
+ /* PREFIX_0F1B */
+ {
+ { MOD_TABLE (MOD_0F1B_PREFIX_0) },
+ { MOD_TABLE (MOD_0F1B_PREFIX_1) },
+ { "bndmov", { Ebnd, Gbnd }, 0 },
+ { "bndcn", { Gbnd, Ev_bnd }, 0 },
},
/* PREFIX_0F2A */
{
- { "cvtpi2ps", { XM, EMCq } },
- { "cvtsi2ss%LQ", { XM, Ev } },
- { "cvtpi2pd", { XM, EMCq } },
- { "cvtsi2sd%LQ", { XM, Ev } },
+ { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
+ { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
+ { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
+ { "cvtsi2sd%LQ", { XM, Ev }, 0 },
},
/* PREFIX_0F2B */
/* PREFIX_0F2C */
{
- { "cvttps2pi", { MXC, EXq } },
- { "cvttss2siY", { Gv, EXd } },
- { "cvttpd2pi", { MXC, EXx } },
- { "cvttsd2siY", { Gv, EXq } },
+ { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
+ { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
+ { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
+ { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F2D */
{
- { "cvtps2pi", { MXC, EXq } },
- { "cvtss2siY", { Gv, EXd } },
- { "cvtpd2pi", { MXC, EXx } },
- { "cvtsd2siY", { Gv, EXq } },
+ { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
+ { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
+ { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
+ { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F2E */
{
- { "ucomiss",{ XM, EXd } },
+ { "ucomiss",{ XM, EXd }, 0 },
{ Bad_Opcode },
- { "ucomisd",{ XM, EXq } },
+ { "ucomisd",{ XM, EXq }, 0 },
},
/* PREFIX_0F2F */
{
- { "comiss", { XM, EXd } },
+ { "comiss", { XM, EXd }, 0 },
{ Bad_Opcode },
- { "comisd", { XM, EXq } },
+ { "comisd", { XM, EXq }, 0 },
},
/* PREFIX_0F51 */
{
- { "sqrtps", { XM, EXx } },
- { "sqrtss", { XM, EXd } },
- { "sqrtpd", { XM, EXx } },
- { "sqrtsd", { XM, EXq } },
+ { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
+ { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
+ { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
+ { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F52 */
{
- { "rsqrtps",{ XM, EXx } },
- { "rsqrtss",{ XM, EXd } },
+ { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
+ { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
},
/* PREFIX_0F53 */
{
- { "rcpps", { XM, EXx } },
- { "rcpss", { XM, EXd } },
+ { "rcpps", { XM, EXx }, PREFIX_OPCODE },
+ { "rcpss", { XM, EXd }, PREFIX_OPCODE },
},
/* PREFIX_0F58 */
{
- { "addps", { XM, EXx } },
- { "addss", { XM, EXd } },
- { "addpd", { XM, EXx } },
- { "addsd", { XM, EXq } },
+ { "addps", { XM, EXx }, PREFIX_OPCODE },
+ { "addss", { XM, EXd }, PREFIX_OPCODE },
+ { "addpd", { XM, EXx }, PREFIX_OPCODE },
+ { "addsd", { XM, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F59 */
{
- { "mulps", { XM, EXx } },
- { "mulss", { XM, EXd } },
- { "mulpd", { XM, EXx } },
- { "mulsd", { XM, EXq } },
+ { "mulps", { XM, EXx }, PREFIX_OPCODE },
+ { "mulss", { XM, EXd }, PREFIX_OPCODE },
+ { "mulpd", { XM, EXx }, PREFIX_OPCODE },
+ { "mulsd", { XM, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F5A */
{
- { "cvtps2pd", { XM, EXq } },
- { "cvtss2sd", { XM, EXd } },
- { "cvtpd2ps", { XM, EXx } },
- { "cvtsd2ss", { XM, EXq } },
+ { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
+ { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
+ { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
+ { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F5B */
{
- { "cvtdq2ps", { XM, EXx } },
- { "cvttps2dq", { XM, EXx } },
- { "cvtps2dq", { XM, EXx } },
+ { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
+ { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
+ { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F5C */
{
- { "subps", { XM, EXx } },
- { "subss", { XM, EXd } },
- { "subpd", { XM, EXx } },
- { "subsd", { XM, EXq } },
+ { "subps", { XM, EXx }, PREFIX_OPCODE },
+ { "subss", { XM, EXd }, PREFIX_OPCODE },
+ { "subpd", { XM, EXx }, PREFIX_OPCODE },
+ { "subsd", { XM, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F5D */
{
- { "minps", { XM, EXx } },
- { "minss", { XM, EXd } },
- { "minpd", { XM, EXx } },
- { "minsd", { XM, EXq } },
+ { "minps", { XM, EXx }, PREFIX_OPCODE },
+ { "minss", { XM, EXd }, PREFIX_OPCODE },
+ { "minpd", { XM, EXx }, PREFIX_OPCODE },
+ { "minsd", { XM, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F5E */
{
- { "divps", { XM, EXx } },
- { "divss", { XM, EXd } },
- { "divpd", { XM, EXx } },
- { "divsd", { XM, EXq } },
+ { "divps", { XM, EXx }, PREFIX_OPCODE },
+ { "divss", { XM, EXd }, PREFIX_OPCODE },
+ { "divpd", { XM, EXx }, PREFIX_OPCODE },
+ { "divsd", { XM, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F5F */
{
- { "maxps", { XM, EXx } },
- { "maxss", { XM, EXd } },
- { "maxpd", { XM, EXx } },
- { "maxsd", { XM, EXq } },
+ { "maxps", { XM, EXx }, PREFIX_OPCODE },
+ { "maxss", { XM, EXd }, PREFIX_OPCODE },
+ { "maxpd", { XM, EXx }, PREFIX_OPCODE },
+ { "maxsd", { XM, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F60 */
{
- { "punpcklbw",{ MX, EMd } },
+ { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
{ Bad_Opcode },
- { "punpcklbw",{ MX, EMx } },
+ { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
},
/* PREFIX_0F61 */
{
- { "punpcklwd",{ MX, EMd } },
+ { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
{ Bad_Opcode },
- { "punpcklwd",{ MX, EMx } },
+ { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
},
/* PREFIX_0F62 */
{
- { "punpckldq",{ MX, EMd } },
+ { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
{ Bad_Opcode },
- { "punpckldq",{ MX, EMx } },
+ { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
},
/* PREFIX_0F6C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "punpcklqdq", { XM, EXx } },
+ { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F6D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "punpckhqdq", { XM, EXx } },
+ { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F6F */
{
- { "movq", { MX, EM } },
- { "movdqu", { XM, EXx } },
- { "movdqa", { XM, EXx } },
+ { "movq", { MX, EM }, PREFIX_OPCODE },
+ { "movdqu", { XM, EXx }, PREFIX_OPCODE },
+ { "movdqa", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F70 */
{
- { "pshufw", { MX, EM, Ib } },
- { "pshufhw",{ XM, EXx, Ib } },
- { "pshufd", { XM, EXx, Ib } },
- { "pshuflw",{ XM, EXx, Ib } },
+ { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
+ { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
+ { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
+ { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F73_REG_3 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "psrldq", { XS, Ib } },
+ { "psrldq", { XS, Ib }, 0 },
},
/* PREFIX_0F73_REG_7 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pslldq", { XS, Ib } },
+ { "pslldq", { XS, Ib }, 0 },
},
/* PREFIX_0F78 */
{
- {"vmread", { Em, Gm } },
+ {"vmread", { Em, Gm }, 0 },
{ Bad_Opcode },
- {"extrq", { XS, Ib, Ib } },
- {"insertq", { XM, XS, Ib, Ib } },
+ {"extrq", { XS, Ib, Ib }, 0 },
+ {"insertq", { XM, XS, Ib, Ib }, 0 },
},
/* PREFIX_0F79 */
{
- {"vmwrite", { Gm, Em } },
+ {"vmwrite", { Gm, Em }, 0 },
{ Bad_Opcode },
- {"extrq", { XM, XS } },
- {"insertq", { XM, XS } },
+ {"extrq", { XM, XS }, 0 },
+ {"insertq", { XM, XS }, 0 },
},
/* PREFIX_0F7C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "haddpd", { XM, EXx } },
- { "haddps", { XM, EXx } },
+ { "haddpd", { XM, EXx }, PREFIX_OPCODE },
+ { "haddps", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F7D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "hsubpd", { XM, EXx } },
- { "hsubps", { XM, EXx } },
+ { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
+ { "hsubps", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F7E */
{
- { "movK", { Edq, MX } },
- { "movq", { XM, EXq } },
- { "movK", { Edq, XM } },
+ { "movK", { Edq, MX }, PREFIX_OPCODE },
+ { "movq", { XM, EXq }, PREFIX_OPCODE },
+ { "movK", { Edq, XM }, PREFIX_OPCODE },
},
/* PREFIX_0F7F */
{
- { "movq", { EMS, MX } },
- { "movdqu", { EXxS, XM } },
- { "movdqa", { EXxS, XM } },
+ { "movq", { EMS, MX }, PREFIX_OPCODE },
+ { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
+ { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
},
/* PREFIX_0FAE_REG_0 */
{
{ Bad_Opcode },
- { "rdfsbase", { Ev } },
+ { "rdfsbase", { Ev }, 0 },
},
/* PREFIX_0FAE_REG_1 */
{
{ Bad_Opcode },
- { "rdgsbase", { Ev } },
+ { "rdgsbase", { Ev }, 0 },
},
/* PREFIX_0FAE_REG_2 */
{
{ Bad_Opcode },
- { "wrfsbase", { Ev } },
+ { "wrfsbase", { Ev }, 0 },
},
/* PREFIX_0FAE_REG_3 */
{
{ Bad_Opcode },
- { "wrgsbase", { Ev } },
+ { "wrgsbase", { Ev }, 0 },
+ },
+
+ /* PREFIX_MOD_0_0FAE_REG_4 */
+ {
+ { "xsave", { FXSAVE }, 0 },
+ { "ptwrite%LQ", { Edq }, 0 },
+ },
+
+ /* PREFIX_MOD_3_0FAE_REG_4 */
+ {
+ { Bad_Opcode },
+ { "ptwrite%LQ", { Edq }, 0 },
+ },
+
+ /* PREFIX_0FAE_REG_6 */
+ {
+ { "xsaveopt", { FXSAVE }, 0 },
+ { Bad_Opcode },
+ { "clwb", { Mb }, 0 },
+ },
+
+ /* PREFIX_0FAE_REG_7 */
+ {
+ { "clflush", { Mb }, 0 },
+ { Bad_Opcode },
+ { "clflushopt", { Mb }, 0 },
+ },
+
+ /* PREFIX_RM_0_0FAE_REG_7 */
+ {
+ { "sfence", { Skip_MODRM }, 0 },
+ { Bad_Opcode },
+ { "pcommit", { Skip_MODRM }, 0 },
},
/* PREFIX_0FB8 */
{
{ Bad_Opcode },
- { "popcntS", { Gv, Ev } },
+ { "popcntS", { Gv, Ev }, 0 },
+ },
+
+ /* PREFIX_0FBC */
+ {
+ { "bsfS", { Gv, Ev }, 0 },
+ { "tzcntS", { Gv, Ev }, 0 },
+ { "bsfS", { Gv, Ev }, 0 },
},
/* PREFIX_0FBD */
{
- { "bsrS", { Gv, Ev } },
- { "lzcntS", { Gv, Ev } },
- { "bsrS", { Gv, Ev } },
+ { "bsrS", { Gv, Ev }, 0 },
+ { "lzcntS", { Gv, Ev }, 0 },
+ { "bsrS", { Gv, Ev }, 0 },
},
/* PREFIX_0FC2 */
{
- { "cmpps", { XM, EXx, CMP } },
- { "cmpss", { XM, EXd, CMP } },
- { "cmppd", { XM, EXx, CMP } },
- { "cmpsd", { XM, EXq, CMP } },
+ { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
+ { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
+ { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
+ { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_MOD_0_0FC3 */
+ {
+ { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_MOD_0_0FC7_REG_6 */
+ {
+ { "vmptrld",{ Mq }, 0 },
+ { "vmxon", { Mq }, 0 },
+ { "vmclear",{ Mq }, 0 },
},
- /* PREFIX_0FC3 */
+ /* PREFIX_MOD_3_0FC7_REG_6 */
{
- { "movntiS", { Ma, Gv } },
+ { "rdrand", { Ev }, 0 },
+ { Bad_Opcode },
+ { "rdrand", { Ev }, 0 }
},
- /* PREFIX_0FC7_REG_6 */
+ /* PREFIX_MOD_3_0FC7_REG_7 */
{
- { "vmptrld",{ Mq } },
- { "vmxon", { Mq } },
- { "vmclear",{ Mq } },
+ { "rdseed", { Ev }, 0 },
+ { "rdpid", { Em }, 0 },
+ { "rdseed", { Ev }, 0 },
},
/* PREFIX_0FD0 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "addsubpd", { XM, EXx } },
- { "addsubps", { XM, EXx } },
+ { "addsubpd", { XM, EXx }, 0 },
+ { "addsubps", { XM, EXx }, 0 },
},
/* PREFIX_0FD6 */
{
{ Bad_Opcode },
- { "movq2dq",{ XM, MS } },
- { "movq", { EXqS, XM } },
- { "movdq2q",{ MX, XS } },
+ { "movq2dq",{ XM, MS }, 0 },
+ { "movq", { EXqS, XM }, 0 },
+ { "movdq2q",{ MX, XS }, 0 },
},
/* PREFIX_0FE6 */
{
{ Bad_Opcode },
- { "cvtdq2pd", { XM, EXq } },
- { "cvttpd2dq", { XM, EXx } },
- { "cvtpd2dq", { XM, EXx } },
+ { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
+ { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
+ { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0FE7 */
{
- { "movntq", { Mq, MX } },
+ { "movntq", { Mq, MX }, PREFIX_OPCODE },
{ Bad_Opcode },
{ MOD_TABLE (MOD_0FE7_PREFIX_2) },
},
/* PREFIX_0FF7 */
{
- { "maskmovq", { MX, MS } },
+ { "maskmovq", { MX, MS }, PREFIX_OPCODE },
{ Bad_Opcode },
- { "maskmovdqu", { XM, XS } },
+ { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
},
/* PREFIX_0F3810 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pblendvb", { XM, EXx, XMM0 } },
+ { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
},
/* PREFIX_0F3814 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "blendvps", { XM, EXx, XMM0 } },
+ { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
},
/* PREFIX_0F3815 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "blendvpd", { XM, EXx, XMM0 } },
+ { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
},
/* PREFIX_0F3817 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "ptest", { XM, EXx } },
+ { "ptest", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F3820 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pmovsxbw", { XM, EXq } },
+ { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F3821 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pmovsxbd", { XM, EXd } },
+ { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
},
/* PREFIX_0F3822 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pmovsxbq", { XM, EXw } },
+ { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
},
/* PREFIX_0F3823 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pmovsxwd", { XM, EXq } },
+ { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F3824 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pmovsxwq", { XM, EXd } },
+ { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
},
/* PREFIX_0F3825 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pmovsxdq", { XM, EXq } },
+ { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F3828 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pmuldq", { XM, EXx } },
+ { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F3829 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pcmpeqq", { XM, EXx } },
+ { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F382A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "packusdw", { XM, EXx } },
+ { "packusdw", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F3830 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pmovzxbw", { XM, EXq } },
+ { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F3831 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pmovzxbd", { XM, EXd } },
+ { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
},
/* PREFIX_0F3832 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pmovzxbq", { XM, EXw } },
+ { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
},
/* PREFIX_0F3833 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pmovzxwd", { XM, EXq } },
+ { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F3834 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pmovzxwq", { XM, EXd } },
+ { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
},
/* PREFIX_0F3835 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pmovzxdq", { XM, EXq } },
+ { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F3837 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pcmpgtq", { XM, EXx } },
+ { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F3838 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pminsb", { XM, EXx } },
+ { "pminsb", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F3839 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pminsd", { XM, EXx } },
+ { "pminsd", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F383A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pminuw", { XM, EXx } },
+ { "pminuw", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F383B */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pminud", { XM, EXx } },
+ { "pminud", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F383C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pmaxsb", { XM, EXx } },
+ { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F383D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pmaxsd", { XM, EXx } },
+ { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F383E */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pmaxuw", { XM, EXx } },
+ { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F383F */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pmaxud", { XM, EXx } },
+ { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F3840 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pmulld", { XM, EXx } },
+ { "pmulld", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F3841 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "phminposuw", { XM, EXx } },
+ { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F3880 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "invept", { Gm, Mo } },
+ { "invept", { Gm, Mo }, PREFIX_OPCODE },
},
/* PREFIX_0F3881 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "invvpid", { Gm, Mo } },
+ { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_0F3882 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "invpcid", { Gm, M }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_0F38C8 */
+ {
+ { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_0F38C9 */
+ {
+ { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_0F38CA */
+ {
+ { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_0F38CB */
+ {
+ { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_0F38CC */
+ {
+ { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_0F38CD */
+ {
+ { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
},
/* PREFIX_0F38DB */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "aesimc", { XM, EXx } },
+ { "aesimc", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F38DC */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "aesenc", { XM, EXx } },
+ { "aesenc", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F38DD */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "aesenclast", { XM, EXx } },
+ { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F38DE */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "aesdec", { XM, EXx } },
+ { "aesdec", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F38DF */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "aesdeclast", { XM, EXx } },
+ { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
},
/* PREFIX_0F38F0 */
{
- { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
+ { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
{ Bad_Opcode },
- { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
- { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
+ { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
+ { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
},
/* PREFIX_0F38F1 */
{
- { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
+ { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
+ { Bad_Opcode },
+ { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
+ { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_0F38F6 */
+ {
+ { Bad_Opcode },
+ { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
+ { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
{ Bad_Opcode },
- { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
- { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
},
/* PREFIX_0F3A08 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "roundps", { XM, EXx, Ib } },
+ { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3A09 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "roundpd", { XM, EXx, Ib } },
+ { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3A0A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "roundss", { XM, EXd, Ib } },
+ { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3A0B */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "roundsd", { XM, EXq, Ib } },
+ { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3A0C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "blendps", { XM, EXx, Ib } },
+ { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3A0D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "blendpd", { XM, EXx, Ib } },
+ { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3A0E */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pblendw", { XM, EXx, Ib } },
+ { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3A14 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pextrb", { Edqb, XM, Ib } },
+ { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3A15 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pextrw", { Edqw, XM, Ib } },
+ { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3A16 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pextrK", { Edq, XM, Ib } },
+ { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3A17 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "extractps", { Edqd, XM, Ib } },
+ { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3A20 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pinsrb", { XM, Edqb, Ib } },
+ { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3A21 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "insertps", { XM, EXd, Ib } },
+ { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3A22 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pinsrK", { XM, Edq, Ib } },
+ { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3A40 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "dpps", { XM, EXx, Ib } },
+ { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3A41 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "dppd", { XM, EXx, Ib } },
+ { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3A42 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "mpsadbw", { XM, EXx, Ib } },
+ { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3A44 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pclmulqdq", { XM, EXx, PCLMUL } },
+ { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
},
/* PREFIX_0F3A60 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pcmpestrm", { XM, EXx, Ib } },
+ { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3A61 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pcmpestri", { XM, EXx, Ib } },
+ { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3A62 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pcmpistrm", { XM, EXx, Ib } },
+ { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3A63 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "pcmpistri", { XM, EXx, Ib } },
+ { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_0F3ACC */
+ {
+ { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
},
/* PREFIX_0F3ADF */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "aeskeygenassist", { XM, EXx, Ib } },
+ { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
},
/* PREFIX_VEX_0F10 */
{ VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
},
+ /* PREFIX_VEX_0F41 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
+ },
+
+ /* PREFIX_VEX_0F42 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
+ },
+
+ /* PREFIX_VEX_0F44 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
+ },
+
+ /* PREFIX_VEX_0F45 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
+ },
+
+ /* PREFIX_VEX_0F46 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
+ },
+
+ /* PREFIX_VEX_0F47 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
+ },
+
+ /* PREFIX_VEX_0F4A */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
+ },
+
+ /* PREFIX_VEX_0F4B */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
+ },
+
/* PREFIX_VEX_0F51 */
{
{ VEX_W_TABLE (VEX_W_0F51_P_0) },
{
{ VEX_W_TABLE (VEX_W_0F5A_P_0) },
{ VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
- { "vcvtpd2ps%XY", { XMM, EXx } },
+ { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
{ VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
},
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F60_P_2) },
+ { VEX_W_TABLE (VEX_W_0F60_P_2) },
},
/* PREFIX_VEX_0F61 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F61_P_2) },
+ { VEX_W_TABLE (VEX_W_0F61_P_2) },
},
/* PREFIX_VEX_0F62 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F62_P_2) },
+ { VEX_W_TABLE (VEX_W_0F62_P_2) },
},
/* PREFIX_VEX_0F63 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F63_P_2) },
+ { VEX_W_TABLE (VEX_W_0F63_P_2) },
},
/* PREFIX_VEX_0F64 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F64_P_2) },
+ { VEX_W_TABLE (VEX_W_0F64_P_2) },
},
/* PREFIX_VEX_0F65 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F65_P_2) },
+ { VEX_W_TABLE (VEX_W_0F65_P_2) },
},
/* PREFIX_VEX_0F66 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F66_P_2) },
+ { VEX_W_TABLE (VEX_W_0F66_P_2) },
},
/* PREFIX_VEX_0F67 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F67_P_2) },
+ { VEX_W_TABLE (VEX_W_0F67_P_2) },
},
/* PREFIX_VEX_0F68 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F68_P_2) },
+ { VEX_W_TABLE (VEX_W_0F68_P_2) },
},
/* PREFIX_VEX_0F69 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F69_P_2) },
+ { VEX_W_TABLE (VEX_W_0F69_P_2) },
},
/* PREFIX_VEX_0F6A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F6A_P_2) },
+ { VEX_W_TABLE (VEX_W_0F6A_P_2) },
},
/* PREFIX_VEX_0F6B */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F6B_P_2) },
+ { VEX_W_TABLE (VEX_W_0F6B_P_2) },
},
/* PREFIX_VEX_0F6C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F6C_P_2) },
+ { VEX_W_TABLE (VEX_W_0F6C_P_2) },
},
/* PREFIX_VEX_0F6D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F6D_P_2) },
+ { VEX_W_TABLE (VEX_W_0F6D_P_2) },
},
/* PREFIX_VEX_0F6E */
/* PREFIX_VEX_0F70 */
{
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F70_P_1) },
- { VEX_LEN_TABLE (VEX_LEN_0F70_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F70_P_3) },
+ { VEX_W_TABLE (VEX_W_0F70_P_1) },
+ { VEX_W_TABLE (VEX_W_0F70_P_2) },
+ { VEX_W_TABLE (VEX_W_0F70_P_3) },
},
/* PREFIX_VEX_0F71_REG_2 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F71_R_2_P_2) },
+ { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
},
/* PREFIX_VEX_0F71_REG_4 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F71_R_4_P_2) },
+ { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
},
/* PREFIX_VEX_0F71_REG_6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F71_R_6_P_2) },
+ { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
},
/* PREFIX_VEX_0F72_REG_2 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F72_R_2_P_2) },
+ { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
},
/* PREFIX_VEX_0F72_REG_4 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F72_R_4_P_2) },
+ { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
},
/* PREFIX_VEX_0F72_REG_6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F72_R_6_P_2) },
+ { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
},
/* PREFIX_VEX_0F73_REG_2 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F73_R_2_P_2) },
+ { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
},
/* PREFIX_VEX_0F73_REG_3 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F73_R_3_P_2) },
+ { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
},
/* PREFIX_VEX_0F73_REG_6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F73_R_6_P_2) },
+ { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
},
/* PREFIX_VEX_0F73_REG_7 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F73_R_7_P_2) },
+ { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
},
/* PREFIX_VEX_0F74 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F74_P_2) },
+ { VEX_W_TABLE (VEX_W_0F74_P_2) },
},
/* PREFIX_VEX_0F75 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F75_P_2) },
+ { VEX_W_TABLE (VEX_W_0F75_P_2) },
},
/* PREFIX_VEX_0F76 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F76_P_2) },
+ { VEX_W_TABLE (VEX_W_0F76_P_2) },
},
/* PREFIX_VEX_0F77 */
{ VEX_W_TABLE (VEX_W_0F7F_P_2) },
},
+ /* PREFIX_VEX_0F90 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
+ },
+
+ /* PREFIX_VEX_0F91 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
+ },
+
+ /* PREFIX_VEX_0F92 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
+ { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
+ },
+
+ /* PREFIX_VEX_0F93 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
+ { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
+ },
+
+ /* PREFIX_VEX_0F98 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
+ },
+
+ /* PREFIX_VEX_0F99 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
+ },
+
/* PREFIX_VEX_0FC2 */
{
{ VEX_W_TABLE (VEX_W_0FC2_P_0) },
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FD1_P_2) },
+ { VEX_W_TABLE (VEX_W_0FD1_P_2) },
},
/* PREFIX_VEX_0FD2 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FD2_P_2) },
+ { VEX_W_TABLE (VEX_W_0FD2_P_2) },
},
/* PREFIX_VEX_0FD3 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FD3_P_2) },
+ { VEX_W_TABLE (VEX_W_0FD3_P_2) },
},
/* PREFIX_VEX_0FD4 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FD4_P_2) },
+ { VEX_W_TABLE (VEX_W_0FD4_P_2) },
},
/* PREFIX_VEX_0FD5 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FD5_P_2) },
+ { VEX_W_TABLE (VEX_W_0FD5_P_2) },
},
/* PREFIX_VEX_0FD6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FD8_P_2) },
+ { VEX_W_TABLE (VEX_W_0FD8_P_2) },
},
/* PREFIX_VEX_0FD9 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FD9_P_2) },
+ { VEX_W_TABLE (VEX_W_0FD9_P_2) },
},
/* PREFIX_VEX_0FDA */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FDA_P_2) },
+ { VEX_W_TABLE (VEX_W_0FDA_P_2) },
},
/* PREFIX_VEX_0FDB */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FDB_P_2) },
+ { VEX_W_TABLE (VEX_W_0FDB_P_2) },
},
/* PREFIX_VEX_0FDC */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FDC_P_2) },
+ { VEX_W_TABLE (VEX_W_0FDC_P_2) },
},
/* PREFIX_VEX_0FDD */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FDD_P_2) },
+ { VEX_W_TABLE (VEX_W_0FDD_P_2) },
},
/* PREFIX_VEX_0FDE */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FDE_P_2) },
+ { VEX_W_TABLE (VEX_W_0FDE_P_2) },
},
/* PREFIX_VEX_0FDF */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FDF_P_2) },
+ { VEX_W_TABLE (VEX_W_0FDF_P_2) },
},
/* PREFIX_VEX_0FE0 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FE0_P_2) },
+ { VEX_W_TABLE (VEX_W_0FE0_P_2) },
},
/* PREFIX_VEX_0FE1 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FE1_P_2) },
+ { VEX_W_TABLE (VEX_W_0FE1_P_2) },
},
/* PREFIX_VEX_0FE2 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FE2_P_2) },
+ { VEX_W_TABLE (VEX_W_0FE2_P_2) },
},
/* PREFIX_VEX_0FE3 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FE3_P_2) },
+ { VEX_W_TABLE (VEX_W_0FE3_P_2) },
},
/* PREFIX_VEX_0FE4 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FE4_P_2) },
+ { VEX_W_TABLE (VEX_W_0FE4_P_2) },
},
/* PREFIX_VEX_0FE5 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FE5_P_2) },
+ { VEX_W_TABLE (VEX_W_0FE5_P_2) },
},
/* PREFIX_VEX_0FE6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FE8_P_2) },
+ { VEX_W_TABLE (VEX_W_0FE8_P_2) },
},
/* PREFIX_VEX_0FE9 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FE9_P_2) },
+ { VEX_W_TABLE (VEX_W_0FE9_P_2) },
},
/* PREFIX_VEX_0FEA */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FEA_P_2) },
+ { VEX_W_TABLE (VEX_W_0FEA_P_2) },
},
/* PREFIX_VEX_0FEB */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FEB_P_2) },
+ { VEX_W_TABLE (VEX_W_0FEB_P_2) },
},
/* PREFIX_VEX_0FEC */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FEC_P_2) },
+ { VEX_W_TABLE (VEX_W_0FEC_P_2) },
},
/* PREFIX_VEX_0FED */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FED_P_2) },
+ { VEX_W_TABLE (VEX_W_0FED_P_2) },
},
/* PREFIX_VEX_0FEE */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FEE_P_2) },
+ { VEX_W_TABLE (VEX_W_0FEE_P_2) },
},
/* PREFIX_VEX_0FEF */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FEF_P_2) },
+ { VEX_W_TABLE (VEX_W_0FEF_P_2) },
},
/* PREFIX_VEX_0FF0 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FF1_P_2) },
+ { VEX_W_TABLE (VEX_W_0FF1_P_2) },
},
/* PREFIX_VEX_0FF2 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FF2_P_2) },
+ { VEX_W_TABLE (VEX_W_0FF2_P_2) },
},
/* PREFIX_VEX_0FF3 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FF3_P_2) },
+ { VEX_W_TABLE (VEX_W_0FF3_P_2) },
},
/* PREFIX_VEX_0FF4 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FF4_P_2) },
+ { VEX_W_TABLE (VEX_W_0FF4_P_2) },
},
/* PREFIX_VEX_0FF5 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FF5_P_2) },
+ { VEX_W_TABLE (VEX_W_0FF5_P_2) },
},
/* PREFIX_VEX_0FF6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FF6_P_2) },
+ { VEX_W_TABLE (VEX_W_0FF6_P_2) },
},
/* PREFIX_VEX_0FF7 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FF8_P_2) },
+ { VEX_W_TABLE (VEX_W_0FF8_P_2) },
},
/* PREFIX_VEX_0FF9 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FF9_P_2) },
+ { VEX_W_TABLE (VEX_W_0FF9_P_2) },
},
/* PREFIX_VEX_0FFA */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FFA_P_2) },
+ { VEX_W_TABLE (VEX_W_0FFA_P_2) },
},
/* PREFIX_VEX_0FFB */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FFB_P_2) },
+ { VEX_W_TABLE (VEX_W_0FFB_P_2) },
},
/* PREFIX_VEX_0FFC */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FFC_P_2) },
+ { VEX_W_TABLE (VEX_W_0FFC_P_2) },
},
/* PREFIX_VEX_0FFD */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FFD_P_2) },
+ { VEX_W_TABLE (VEX_W_0FFD_P_2) },
},
/* PREFIX_VEX_0FFE */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FFE_P_2) },
+ { VEX_W_TABLE (VEX_W_0FFE_P_2) },
},
/* PREFIX_VEX_0F3800 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3800_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3800_P_2) },
},
/* PREFIX_VEX_0F3801 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3801_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3801_P_2) },
},
/* PREFIX_VEX_0F3802 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3802_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3802_P_2) },
},
/* PREFIX_VEX_0F3803 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3803_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3803_P_2) },
},
/* PREFIX_VEX_0F3804 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3804_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3804_P_2) },
},
/* PREFIX_VEX_0F3805 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3805_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3805_P_2) },
},
/* PREFIX_VEX_0F3806 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3806_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3806_P_2) },
},
/* PREFIX_VEX_0F3807 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3807_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3807_P_2) },
},
/* PREFIX_VEX_0F3808 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3808_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3808_P_2) },
},
/* PREFIX_VEX_0F3809 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3809_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3809_P_2) },
},
/* PREFIX_VEX_0F380A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F380A_P_2) },
+ { VEX_W_TABLE (VEX_W_0F380A_P_2) },
},
/* PREFIX_VEX_0F380B */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F380B_P_2) },
+ { VEX_W_TABLE (VEX_W_0F380B_P_2) },
},
/* PREFIX_VEX_0F380C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vcvtph2ps", { XM, EXxmmq } },
+ { "vcvtph2ps", { XM, EXxmmq }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3816 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
},
/* PREFIX_VEX_0F3817 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { MOD_TABLE (MOD_VEX_0F3818_PREFIX_2) },
+ { VEX_W_TABLE (VEX_W_0F3818_P_2) },
},
/* PREFIX_VEX_0F3819 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { MOD_TABLE (MOD_VEX_0F3819_PREFIX_2) },
+ { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
},
/* PREFIX_VEX_0F381A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F381C_P_2) },
+ { VEX_W_TABLE (VEX_W_0F381C_P_2) },
},
/* PREFIX_VEX_0F381D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F381D_P_2) },
+ { VEX_W_TABLE (VEX_W_0F381D_P_2) },
},
/* PREFIX_VEX_0F381E */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F381E_P_2) },
+ { VEX_W_TABLE (VEX_W_0F381E_P_2) },
},
/* PREFIX_VEX_0F3820 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3820_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3820_P_2) },
},
/* PREFIX_VEX_0F3821 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3821_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3821_P_2) },
},
/* PREFIX_VEX_0F3822 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3822_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3822_P_2) },
},
/* PREFIX_VEX_0F3823 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3823_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3823_P_2) },
},
/* PREFIX_VEX_0F3824 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3824_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3824_P_2) },
},
/* PREFIX_VEX_0F3825 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3825_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3825_P_2) },
},
/* PREFIX_VEX_0F3828 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3828_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3828_P_2) },
},
/* PREFIX_VEX_0F3829 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3829_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3829_P_2) },
},
/* PREFIX_VEX_0F382A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F382B_P_2) },
+ { VEX_W_TABLE (VEX_W_0F382B_P_2) },
},
/* PREFIX_VEX_0F382C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3830_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3830_P_2) },
},
/* PREFIX_VEX_0F3831 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3831_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3831_P_2) },
},
/* PREFIX_VEX_0F3832 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3832_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3832_P_2) },
},
/* PREFIX_VEX_0F3833 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3833_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3833_P_2) },
},
/* PREFIX_VEX_0F3834 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3834_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3834_P_2) },
},
/* PREFIX_VEX_0F3835 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3835_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3835_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3836 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
},
/* PREFIX_VEX_0F3837 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3837_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3837_P_2) },
},
/* PREFIX_VEX_0F3838 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3838_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3838_P_2) },
},
/* PREFIX_VEX_0F3839 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3839_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3839_P_2) },
},
/* PREFIX_VEX_0F383A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F383A_P_2) },
+ { VEX_W_TABLE (VEX_W_0F383A_P_2) },
},
/* PREFIX_VEX_0F383B */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F383B_P_2) },
+ { VEX_W_TABLE (VEX_W_0F383B_P_2) },
},
/* PREFIX_VEX_0F383C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F383C_P_2) },
+ { VEX_W_TABLE (VEX_W_0F383C_P_2) },
},
/* PREFIX_VEX_0F383D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F383D_P_2) },
+ { VEX_W_TABLE (VEX_W_0F383D_P_2) },
},
/* PREFIX_VEX_0F383E */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F383E_P_2) },
+ { VEX_W_TABLE (VEX_W_0F383E_P_2) },
},
/* PREFIX_VEX_0F383F */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F383F_P_2) },
+ { VEX_W_TABLE (VEX_W_0F383F_P_2) },
},
/* PREFIX_VEX_0F3840 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3840_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3840_P_2) },
},
/* PREFIX_VEX_0F3841 */
{ VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
},
+ /* PREFIX_VEX_0F3845 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3846 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3846_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3847 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vpsllv%LW", { XM, Vex, EXx }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3858 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3858_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3859 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3859_P_2) },
+ },
+
+ /* PREFIX_VEX_0F385A */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
+ },
+
+ /* PREFIX_VEX_0F3878 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3878_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3879 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3879_P_2) },
+ },
+
+ /* PREFIX_VEX_0F388C */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
+ },
+
+ /* PREFIX_VEX_0F388E */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
+ },
+
+ /* PREFIX_VEX_0F3890 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3891 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3892 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
+ },
+
+ /* PREFIX_VEX_0F3893 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
+ },
+
/* PREFIX_VEX_0F3896 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddsub132p%XW", { XM, Vex, EXx } },
+ { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3897 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubadd132p%XW", { XM, Vex, EXx } },
+ { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3898 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmadd132p%XW", { XM, Vex, EXx } },
+ { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3899 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
+ { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
},
/* PREFIX_VEX_0F389A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsub132p%XW", { XM, Vex, EXx } },
+ { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F389B */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
+ { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
},
/* PREFIX_VEX_0F389C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmadd132p%XW", { XM, Vex, EXx } },
+ { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F389D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
+ { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
},
/* PREFIX_VEX_0F389E */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsub132p%XW", { XM, Vex, EXx } },
+ { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F389F */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
+ { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
},
/* PREFIX_VEX_0F38A6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddsub213p%XW", { XM, Vex, EXx } },
+ { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
{ Bad_Opcode },
},
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubadd213p%XW", { XM, Vex, EXx } },
+ { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F38A8 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmadd213p%XW", { XM, Vex, EXx } },
+ { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F38A9 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
+ { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
},
/* PREFIX_VEX_0F38AA */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsub213p%XW", { XM, Vex, EXx } },
+ { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F38AB */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
+ { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
},
/* PREFIX_VEX_0F38AC */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmadd213p%XW", { XM, Vex, EXx } },
+ { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F38AD */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
+ { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
},
/* PREFIX_VEX_0F38AE */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsub213p%XW", { XM, Vex, EXx } },
+ { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F38AF */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
+ { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
},
/* PREFIX_VEX_0F38B6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddsub231p%XW", { XM, Vex, EXx } },
+ { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F38B7 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubadd231p%XW", { XM, Vex, EXx } },
+ { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F38B8 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmadd231p%XW", { XM, Vex, EXx } },
+ { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F38B9 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
+ { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
},
/* PREFIX_VEX_0F38BA */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsub231p%XW", { XM, Vex, EXx } },
+ { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F38BB */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
+ { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
},
/* PREFIX_VEX_0F38BC */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmadd231p%XW", { XM, Vex, EXx } },
+ { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F38BD */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
+ { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
},
/* PREFIX_VEX_0F38BE */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsub231p%XW", { XM, Vex, EXx } },
+ { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F38BF */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
+ { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
},
/* PREFIX_VEX_0F38DB */
{ VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
},
+ /* PREFIX_VEX_0F38F2 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
+ },
+
+ /* PREFIX_VEX_0F38F3_REG_1 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
+ },
+
+ /* PREFIX_VEX_0F38F3_REG_2 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
+ },
+
+ /* PREFIX_VEX_0F38F3_REG_3 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
+ },
+
+ /* PREFIX_VEX_0F38F5 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
+ { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
+ },
+
+ /* PREFIX_VEX_0F38F6 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
+ },
+
+ /* PREFIX_VEX_0F38F7 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
+ { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
+ { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
+ { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
+ },
+
+ /* PREFIX_VEX_0F3A00 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A01 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A02 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
+ },
+
/* PREFIX_VEX_0F3A04 */
{
{ Bad_Opcode },
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A0E_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
},
/* PREFIX_VEX_0F3A0F */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A0F_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
},
/* PREFIX_VEX_0F3A14 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vcvtps2ph", { EXxmmq, XM, Ib } },
+ { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
},
/* PREFIX_VEX_0F3A20 */
{ VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
},
+ /* PREFIX_VEX_0F3A30 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A31 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A32 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A33 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A38 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
+ },
+
+ /* PREFIX_VEX_0F3A39 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
+ },
+
/* PREFIX_VEX_0F3A40 */
{
{ Bad_Opcode },
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A42_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
},
/* PREFIX_VEX_0F3A44 */
{ VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
},
+ /* PREFIX_VEX_0F3A46 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
+ },
+
/* PREFIX_VEX_0F3A48 */
{
{ Bad_Opcode },
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A4C_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
},
/* PREFIX_VEX_0F3A5C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
+ { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
},
/* PREFIX_VEX_0F3A5D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
+ { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
},
/* PREFIX_VEX_0F3A5E */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
+ { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
},
/* PREFIX_VEX_0F3A5F */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
+ { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
},
/* PREFIX_VEX_0F3A60 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
+ { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
},
/* PREFIX_VEX_0F3A69 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
+ { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
},
/* PREFIX_VEX_0F3A6A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
+ { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
},
/* PREFIX_VEX_0F3A6D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
+ { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
},
/* PREFIX_VEX_0F3A6E */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
+ { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
},
/* PREFIX_VEX_0F3A79 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
+ { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
},
/* PREFIX_VEX_0F3A7A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
+ { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
{ Bad_Opcode },
},
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
+ { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
},
/* PREFIX_VEX_0F3A7E */
{ Bad_Opcode },
{ VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
},
+
+ /* PREFIX_VEX_0F3AF0 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
+ },
+
+#define NEED_PREFIX_TABLE
+#include "i386-dis-evex.h"
+#undef NEED_PREFIX_TABLE
};
static const struct dis386 x86_64_table[][2] = {
/* X86_64_06 */
{
- { "pushP", { es } },
+ { "pushP", { es }, 0 },
},
/* X86_64_07 */
{
- { "popP", { es } },
+ { "popP", { es }, 0 },
},
/* X86_64_0D */
{
- { "pushP", { cs } },
+ { "pushP", { cs }, 0 },
},
/* X86_64_16 */
{
- { "pushP", { ss } },
+ { "pushP", { ss }, 0 },
},
/* X86_64_17 */
{
- { "popP", { ss } },
+ { "popP", { ss }, 0 },
},
/* X86_64_1E */
{
- { "pushP", { ds } },
+ { "pushP", { ds }, 0 },
},
/* X86_64_1F */
{
- { "popP", { ds } },
+ { "popP", { ds }, 0 },
},
/* X86_64_27 */
{
- { "daa", { XX } },
+ { "daa", { XX }, 0 },
},
/* X86_64_2F */
{
- { "das", { XX } },
+ { "das", { XX }, 0 },
},
/* X86_64_37 */
{
- { "aaa", { XX } },
+ { "aaa", { XX }, 0 },
},
/* X86_64_3F */
{
- { "aas", { XX } },
+ { "aas", { XX }, 0 },
},
/* X86_64_60 */
{
- { "pushaP", { XX } },
+ { "pushaP", { XX }, 0 },
},
/* X86_64_61 */
{
- { "popaP", { XX } },
+ { "popaP", { XX }, 0 },
},
/* X86_64_62 */
{
{ MOD_TABLE (MOD_62_32BIT) },
+ { EVEX_TABLE (EVEX_0F) },
},
/* X86_64_63 */
{
- { "arpl", { Ew, Gw } },
- { "movs{lq|xd}", { Gv, Ed } },
+ { "arpl", { Ew, Gw }, 0 },
+ { "movs{lq|xd}", { Gv, Ed }, 0 },
},
/* X86_64_6D */
{
- { "ins{R|}", { Yzr, indirDX } },
- { "ins{G|}", { Yzr, indirDX } },
+ { "ins{R|}", { Yzr, indirDX }, 0 },
+ { "ins{G|}", { Yzr, indirDX }, 0 },
},
/* X86_64_6F */
{
- { "outs{R|}", { indirDXr, Xz } },
- { "outs{G|}", { indirDXr, Xz } },
+ { "outs{R|}", { indirDXr, Xz }, 0 },
+ { "outs{G|}", { indirDXr, Xz }, 0 },
},
/* X86_64_9A */
{
- { "Jcall{T|}", { Ap } },
+ { "Jcall{T|}", { Ap }, 0 },
},
/* X86_64_C4 */
/* X86_64_CE */
{
- { "into", { XX } },
+ { "into", { XX }, 0 },
},
/* X86_64_D4 */
{
- { "aam", { sIb } },
+ { "aam", { Ib }, 0 },
},
/* X86_64_D5 */
{
- { "aad", { sIb } },
+ { "aad", { Ib }, 0 },
+ },
+
+ /* X86_64_E8 */
+ {
+ { "callP", { Jv, BND }, 0 },
+ { "call@", { Jv, BND }, 0 }
+ },
+
+ /* X86_64_E9 */
+ {
+ { "jmpP", { Jv, BND }, 0 },
+ { "jmp@", { Jv, BND }, 0 }
},
/* X86_64_EA */
{
- { "Jjmp{T|}", { Ap } },
+ { "Jjmp{T|}", { Ap }, 0 },
},
/* X86_64_0F01_REG_0 */
{
- { "sgdt{Q|IQ}", { M } },
- { "sgdt", { M } },
+ { "sgdt{Q|IQ}", { M }, 0 },
+ { "sgdt", { M }, 0 },
},
/* X86_64_0F01_REG_1 */
{
- { "sidt{Q|IQ}", { M } },
- { "sidt", { M } },
+ { "sidt{Q|IQ}", { M }, 0 },
+ { "sidt", { M }, 0 },
},
/* X86_64_0F01_REG_2 */
{
- { "lgdt{Q|Q}", { M } },
- { "lgdt", { M } },
+ { "lgdt{Q|Q}", { M }, 0 },
+ { "lgdt", { M }, 0 },
},
/* X86_64_0F01_REG_3 */
{
- { "lidt{Q|Q}", { M } },
- { "lidt", { M } },
+ { "lidt{Q|Q}", { M }, 0 },
+ { "lidt", { M }, 0 },
},
};
/* THREE_BYTE_0F38 */
{
/* 00 */
- { "pshufb", { MX, EM } },
- { "phaddw", { MX, EM } },
- { "phaddd", { MX, EM } },
- { "phaddsw", { MX, EM } },
- { "pmaddubsw", { MX, EM } },
- { "phsubw", { MX, EM } },
- { "phsubd", { MX, EM } },
- { "phsubsw", { MX, EM } },
+ { "pshufb", { MX, EM }, PREFIX_OPCODE },
+ { "phaddw", { MX, EM }, PREFIX_OPCODE },
+ { "phaddd", { MX, EM }, PREFIX_OPCODE },
+ { "phaddsw", { MX, EM }, PREFIX_OPCODE },
+ { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
+ { "phsubw", { MX, EM }, PREFIX_OPCODE },
+ { "phsubd", { MX, EM }, PREFIX_OPCODE },
+ { "phsubsw", { MX, EM }, PREFIX_OPCODE },
/* 08 */
- { "psignb", { MX, EM } },
- { "psignw", { MX, EM } },
- { "psignd", { MX, EM } },
- { "pmulhrsw", { MX, EM } },
+ { "psignb", { MX, EM }, PREFIX_OPCODE },
+ { "psignw", { MX, EM }, PREFIX_OPCODE },
+ { "psignd", { MX, EM }, PREFIX_OPCODE },
+ { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "pabsb", { MX, EM } },
- { "pabsw", { MX, EM } },
- { "pabsd", { MX, EM } },
+ { "pabsb", { MX, EM }, PREFIX_OPCODE },
+ { "pabsw", { MX, EM }, PREFIX_OPCODE },
+ { "pabsd", { MX, EM }, PREFIX_OPCODE },
{ Bad_Opcode },
/* 20 */
{ PREFIX_TABLE (PREFIX_0F3820) },
/* 80 */
{ PREFIX_TABLE (PREFIX_0F3880) },
{ PREFIX_TABLE (PREFIX_0F3881) },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_0F3882) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* c8 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_0F38C8) },
+ { PREFIX_TABLE (PREFIX_0F38C9) },
+ { PREFIX_TABLE (PREFIX_0F38CA) },
+ { PREFIX_TABLE (PREFIX_0F38CB) },
+ { PREFIX_TABLE (PREFIX_0F38CC) },
+ { PREFIX_TABLE (PREFIX_0F38CD) },
{ Bad_Opcode },
{ Bad_Opcode },
/* d0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_0F38F6) },
{ Bad_Opcode },
/* f8 */
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_0F3A0C) },
{ PREFIX_TABLE (PREFIX_0F3A0D) },
{ PREFIX_TABLE (PREFIX_0F3A0E) },
- { "palignr", { MX, EM, Ib } },
+ { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
/* 10 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_0F3ACC) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 20 */
- { "ptest", { XX } },
+ { "ptest", { XX }, PREFIX_OPCODE },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 40 */
{ Bad_Opcode },
- { "phaddbw", { XM, EXq } },
- { "phaddbd", { XM, EXq } },
- { "phaddbq", { XM, EXq } },
+ { "phaddbw", { XM, EXq }, PREFIX_OPCODE },
+ { "phaddbd", { XM, EXq }, PREFIX_OPCODE },
+ { "phaddbq", { XM, EXq }, PREFIX_OPCODE },
{ Bad_Opcode },
{ Bad_Opcode },
- { "phaddwd", { XM, EXq } },
- { "phaddwq", { XM, EXq } },
+ { "phaddwd", { XM, EXq }, PREFIX_OPCODE },
+ { "phaddwq", { XM, EXq }, PREFIX_OPCODE },
/* 48 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "phadddq", { XM, EXq } },
+ { "phadddq", { XM, EXq }, PREFIX_OPCODE },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 50 */
{ Bad_Opcode },
- { "phaddubw", { XM, EXq } },
- { "phaddubd", { XM, EXq } },
- { "phaddubq", { XM, EXq } },
+ { "phaddubw", { XM, EXq }, PREFIX_OPCODE },
+ { "phaddubd", { XM, EXq }, PREFIX_OPCODE },
+ { "phaddubq", { XM, EXq }, PREFIX_OPCODE },
{ Bad_Opcode },
{ Bad_Opcode },
- { "phadduwd", { XM, EXq } },
- { "phadduwq", { XM, EXq } },
+ { "phadduwd", { XM, EXq }, PREFIX_OPCODE },
+ { "phadduwq", { XM, EXq }, PREFIX_OPCODE },
/* 58 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "phaddudq", { XM, EXq } },
+ { "phaddudq", { XM, EXq }, PREFIX_OPCODE },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 60 */
{ Bad_Opcode },
- { "phsubbw", { XM, EXq } },
- { "phsubbd", { XM, EXq } },
- { "phsubbq", { XM, EXq } },
+ { "phsubbw", { XM, EXq }, PREFIX_OPCODE },
+ { "phsubbd", { XM, EXq }, PREFIX_OPCODE },
+ { "phsubbq", { XM, EXq }, PREFIX_OPCODE },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
- { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
- { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
+ { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
/* 88 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
- { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
+ { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
/* 90 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
- { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
- { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
+ { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
/* 98 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
- { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
+ { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
/* a0 */
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
- { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
+ { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
+ { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
+ { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
{ Bad_Opcode },
/* a8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
+ { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
{ Bad_Opcode },
/* b8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* c0 */
- { "vprotb", { XM, Vex_2src_1, Ib } },
- { "vprotw", { XM, Vex_2src_1, Ib } },
- { "vprotd", { XM, Vex_2src_1, Ib } },
- { "vprotq", { XM, Vex_2src_1, Ib } },
+ { "vprotb", { XM, Vex_2src_1, Ib }, 0 },
+ { "vprotw", { XM, Vex_2src_1, Ib }, 0 },
+ { "vprotd", { XM, Vex_2src_1, Ib }, 0 },
+ { "vprotq", { XM, Vex_2src_1, Ib }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpcomb", { XM, Vex128, EXx, Ib } },
- { "vpcomw", { XM, Vex128, EXx, Ib } },
- { "vpcomd", { XM, Vex128, EXx, Ib } },
- { "vpcomq", { XM, Vex128, EXx, Ib } },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
/* d0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpcomub", { XM, Vex128, EXx, Ib } },
- { "vpcomuw", { XM, Vex128, EXx, Ib } },
- { "vpcomud", { XM, Vex128, EXx, Ib } },
- { "vpcomuq", { XM, Vex128, EXx, Ib } },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
/* f0 */
{ Bad_Opcode },
{ Bad_Opcode },
{
/* 00 */
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { REG_TABLE (REG_XOP_TBM_01) },
+ { REG_TABLE (REG_XOP_TBM_02) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 80 */
{ VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
{ VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
- { "vfrczss", { XM, EXd } },
- { "vfrczsd", { XM, EXq } },
+ { "vfrczss", { XM, EXd }, 0 },
+ { "vfrczsd", { XM, EXq }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 90 */
- { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } },
- { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } },
- { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } },
- { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } },
- { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } },
- { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } },
- { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } },
- { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } },
+ { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
/* 98 */
- { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } },
- { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } },
- { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } },
- { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } },
+ { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* c0 */
{ Bad_Opcode },
- { "vphaddbw", { XM, EXxmm } },
- { "vphaddbd", { XM, EXxmm } },
- { "vphaddbq", { XM, EXxmm } },
+ { "vphaddbw", { XM, EXxmm }, 0 },
+ { "vphaddbd", { XM, EXxmm }, 0 },
+ { "vphaddbq", { XM, EXxmm }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vphaddwd", { XM, EXxmm } },
- { "vphaddwq", { XM, EXxmm } },
+ { "vphaddwd", { XM, EXxmm }, 0 },
+ { "vphaddwq", { XM, EXxmm }, 0 },
/* c8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vphadddq", { XM, EXxmm } },
+ { "vphadddq", { XM, EXxmm }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* d0 */
{ Bad_Opcode },
- { "vphaddubw", { XM, EXxmm } },
- { "vphaddubd", { XM, EXxmm } },
- { "vphaddubq", { XM, EXxmm } },
+ { "vphaddubw", { XM, EXxmm }, 0 },
+ { "vphaddubd", { XM, EXxmm }, 0 },
+ { "vphaddubq", { XM, EXxmm }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vphadduwd", { XM, EXxmm } },
- { "vphadduwq", { XM, EXxmm } },
+ { "vphadduwd", { XM, EXxmm }, 0 },
+ { "vphadduwq", { XM, EXxmm }, 0 },
/* d8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vphaddudq", { XM, EXxmm } },
+ { "vphaddudq", { XM, EXxmm }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* e0 */
{ Bad_Opcode },
- { "vphsubbw", { XM, EXxmm } },
- { "vphsubwd", { XM, EXxmm } },
- { "vphsubdq", { XM, EXxmm } },
+ { "vphsubbw", { XM, EXxmm }, 0 },
+ { "vphsubwd", { XM, EXxmm }, 0 },
+ { "vphsubdq", { XM, EXxmm }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 10 */
- { Bad_Opcode },
+ { "bextr", { Gv, Ev, Iq }, 0 },
{ Bad_Opcode },
{ REG_TABLE (REG_XOP_LWP) },
{ Bad_Opcode },
{ Bad_Opcode },
/* 40 */
{ Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F41) },
+ { PREFIX_TABLE (PREFIX_VEX_0F42) },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F44) },
+ { PREFIX_TABLE (PREFIX_VEX_0F45) },
+ { PREFIX_TABLE (PREFIX_VEX_0F46) },
+ { PREFIX_TABLE (PREFIX_VEX_0F47) },
/* 48 */
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F4A) },
+ { PREFIX_TABLE (PREFIX_VEX_0F4B) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_VEX_0F51) },
{ PREFIX_TABLE (PREFIX_VEX_0F52) },
{ PREFIX_TABLE (PREFIX_VEX_0F53) },
- { "vandpX", { XM, Vex, EXx } },
- { "vandnpX", { XM, Vex, EXx } },
- { "vorpX", { XM, Vex, EXx } },
- { "vxorpX", { XM, Vex, EXx } },
+ { "vandpX", { XM, Vex, EXx }, 0 },
+ { "vandnpX", { XM, Vex, EXx }, 0 },
+ { "vorpX", { XM, Vex, EXx }, 0 },
+ { "vxorpX", { XM, Vex, EXx }, 0 },
/* 58 */
{ PREFIX_TABLE (PREFIX_VEX_0F58) },
{ PREFIX_TABLE (PREFIX_VEX_0F59) },
{ Bad_Opcode },
{ Bad_Opcode },
/* 90 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F90) },
+ { PREFIX_TABLE (PREFIX_VEX_0F91) },
+ { PREFIX_TABLE (PREFIX_VEX_0F92) },
+ { PREFIX_TABLE (PREFIX_VEX_0F93) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 98 */
- { Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F98) },
+ { PREFIX_TABLE (PREFIX_VEX_0F99) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_VEX_0FC4) },
{ PREFIX_TABLE (PREFIX_VEX_0FC5) },
- { "vshufpX", { XM, Vex, EXx, Ib } },
+ { "vshufpX", { XM, Vex, EXx, Ib }, 0 },
{ Bad_Opcode },
/* c8 */
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_VEX_0F3813) },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3816) },
{ PREFIX_TABLE (PREFIX_VEX_0F3817) },
/* 18 */
{ PREFIX_TABLE (PREFIX_VEX_0F3818) },
{ PREFIX_TABLE (PREFIX_VEX_0F3833) },
{ PREFIX_TABLE (PREFIX_VEX_0F3834) },
{ PREFIX_TABLE (PREFIX_VEX_0F3835) },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3836) },
{ PREFIX_TABLE (PREFIX_VEX_0F3837) },
/* 38 */
{ PREFIX_TABLE (PREFIX_VEX_0F3838) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3845) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3846) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3847) },
/* 48 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 58 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3858) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3859) },
+ { PREFIX_TABLE (PREFIX_VEX_0F385A) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 78 */
- { Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3878) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3879) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F388C) },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F388E) },
{ Bad_Opcode },
/* 90 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3890) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3891) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3892) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3893) },
{ Bad_Opcode },
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_VEX_0F3896) },
/* f0 */
{ Bad_Opcode },
{ Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
+ { REG_TABLE (REG_VEX_0F38F3) },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
/* f8 */
{ Bad_Opcode },
{ Bad_Opcode },
/* VEX_0F3A */
{
/* 00 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_VEX_0F3A04) },
{ PREFIX_TABLE (PREFIX_VEX_0F3A05) },
{ Bad_Opcode },
{ Bad_Opcode },
/* 30 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 38 */
- { Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_VEX_0F3A44) },
{ Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
{ Bad_Opcode },
/* 48 */
{ PREFIX_TABLE (PREFIX_VEX_0F3A48) },
{ Bad_Opcode },
{ Bad_Opcode },
/* f0 */
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
},
};
+#define NEED_OPCODE_TABLE
+#include "i386-dis-evex.h"
+#undef NEED_OPCODE_TABLE
static const struct dis386 vex_len_table[][2] = {
/* VEX_LEN_0F10_P_1 */
{
/* VEX_LEN_0F2A_P_1 */
{
- { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
- { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
+ { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
+ { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
},
/* VEX_LEN_0F2A_P_3 */
{
- { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
- { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
+ { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
+ { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
},
/* VEX_LEN_0F2C_P_1 */
{
- { "vcvttss2siY", { Gv, EXdScalar } },
- { "vcvttss2siY", { Gv, EXdScalar } },
+ { "vcvttss2siY", { Gv, EXdScalar }, 0 },
+ { "vcvttss2siY", { Gv, EXdScalar }, 0 },
},
/* VEX_LEN_0F2C_P_3 */
{
- { "vcvttsd2siY", { Gv, EXqScalar } },
- { "vcvttsd2siY", { Gv, EXqScalar } },
+ { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
+ { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
},
/* VEX_LEN_0F2D_P_1 */
{
- { "vcvtss2siY", { Gv, EXdScalar } },
- { "vcvtss2siY", { Gv, EXdScalar } },
+ { "vcvtss2siY", { Gv, EXdScalar }, 0 },
+ { "vcvtss2siY", { Gv, EXdScalar }, 0 },
},
/* VEX_LEN_0F2D_P_3 */
{
- { "vcvtsd2siY", { Gv, EXqScalar } },
- { "vcvtsd2siY", { Gv, EXqScalar } },
+ { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
+ { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
},
/* VEX_LEN_0F2E_P_0 */
{ VEX_W_TABLE (VEX_W_0F2F_P_2) },
},
+ /* VEX_LEN_0F41_P_0 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
+ },
+ /* VEX_LEN_0F41_P_2 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
+ },
+ /* VEX_LEN_0F42_P_0 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
+ },
+ /* VEX_LEN_0F42_P_2 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
+ },
+ /* VEX_LEN_0F44_P_0 */
+ {
+ { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
+ },
+ /* VEX_LEN_0F44_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
+ },
+ /* VEX_LEN_0F45_P_0 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
+ },
+ /* VEX_LEN_0F45_P_2 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
+ },
+ /* VEX_LEN_0F46_P_0 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
+ },
+ /* VEX_LEN_0F46_P_2 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
+ },
+ /* VEX_LEN_0F47_P_0 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
+ },
+ /* VEX_LEN_0F47_P_2 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
+ },
+ /* VEX_LEN_0F4A_P_0 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
+ },
+ /* VEX_LEN_0F4A_P_2 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
+ },
+ /* VEX_LEN_0F4B_P_0 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
+ },
+ /* VEX_LEN_0F4B_P_2 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
+ },
+
/* VEX_LEN_0F51_P_1 */
{
{ VEX_W_TABLE (VEX_W_0F51_P_1) },
{ VEX_W_TABLE (VEX_W_0F5F_P_3) },
},
- /* VEX_LEN_0F60_P_2 */
+ /* VEX_LEN_0F6E_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F60_P_2) },
+ { "vmovK", { XMScalar, Edq }, 0 },
+ { "vmovK", { XMScalar, Edq }, 0 },
},
- /* VEX_LEN_0F61_P_2 */
+ /* VEX_LEN_0F7E_P_1 */
{
- { VEX_W_TABLE (VEX_W_0F61_P_2) },
+ { VEX_W_TABLE (VEX_W_0F7E_P_1) },
+ { VEX_W_TABLE (VEX_W_0F7E_P_1) },
},
- /* VEX_LEN_0F62_P_2 */
+ /* VEX_LEN_0F7E_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F62_P_2) },
+ { "vmovK", { Edq, XMScalar }, 0 },
+ { "vmovK", { Edq, XMScalar }, 0 },
},
- /* VEX_LEN_0F63_P_2 */
+ /* VEX_LEN_0F90_P_0 */
{
- { VEX_W_TABLE (VEX_W_0F63_P_2) },
+ { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
},
- /* VEX_LEN_0F64_P_2 */
+ /* VEX_LEN_0F90_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F64_P_2) },
+ { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
},
- /* VEX_LEN_0F65_P_2 */
+ /* VEX_LEN_0F91_P_0 */
{
- { VEX_W_TABLE (VEX_W_0F65_P_2) },
+ { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
},
- /* VEX_LEN_0F66_P_2 */
+ /* VEX_LEN_0F91_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F66_P_2) },
+ { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
},
- /* VEX_LEN_0F67_P_2 */
+ /* VEX_LEN_0F92_P_0 */
{
- { VEX_W_TABLE (VEX_W_0F67_P_2) },
+ { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
},
- /* VEX_LEN_0F68_P_2 */
+ /* VEX_LEN_0F92_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F68_P_2) },
+ { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
},
- /* VEX_LEN_0F69_P_2 */
+ /* VEX_LEN_0F92_P_3 */
{
- { VEX_W_TABLE (VEX_W_0F69_P_2) },
+ { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
},
- /* VEX_LEN_0F6A_P_2 */
+ /* VEX_LEN_0F93_P_0 */
{
- { VEX_W_TABLE (VEX_W_0F6A_P_2) },
+ { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
},
- /* VEX_LEN_0F6B_P_2 */
+ /* VEX_LEN_0F93_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F6B_P_2) },
+ { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
},
- /* VEX_LEN_0F6C_P_2 */
+ /* VEX_LEN_0F93_P_3 */
{
- { VEX_W_TABLE (VEX_W_0F6C_P_2) },
+ { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
},
- /* VEX_LEN_0F6D_P_2 */
+ /* VEX_LEN_0F98_P_0 */
{
- { VEX_W_TABLE (VEX_W_0F6D_P_2) },
+ { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
},
- /* VEX_LEN_0F6E_P_2 */
+ /* VEX_LEN_0F98_P_2 */
{
- { "vmovK", { XMScalar, Edq } },
- { "vmovK", { XMScalar, Edq } },
+ { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
},
- /* VEX_LEN_0F70_P_1 */
+ /* VEX_LEN_0F99_P_0 */
{
- { VEX_W_TABLE (VEX_W_0F70_P_1) },
+ { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
},
- /* VEX_LEN_0F70_P_2 */
+ /* VEX_LEN_0F99_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F70_P_2) },
+ { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
},
- /* VEX_LEN_0F70_P_3 */
+ /* VEX_LEN_0FAE_R_2_M_0 */
{
- { VEX_W_TABLE (VEX_W_0F70_P_3) },
+ { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
},
- /* VEX_LEN_0F71_R_2_P_2 */
+ /* VEX_LEN_0FAE_R_3_M_0 */
{
- { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
+ { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
},
- /* VEX_LEN_0F71_R_4_P_2 */
+ /* VEX_LEN_0FC2_P_1 */
{
- { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
+ { VEX_W_TABLE (VEX_W_0FC2_P_1) },
+ { VEX_W_TABLE (VEX_W_0FC2_P_1) },
},
- /* VEX_LEN_0F71_R_6_P_2 */
+ /* VEX_LEN_0FC2_P_3 */
{
- { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
+ { VEX_W_TABLE (VEX_W_0FC2_P_3) },
+ { VEX_W_TABLE (VEX_W_0FC2_P_3) },
},
- /* VEX_LEN_0F72_R_2_P_2 */
+ /* VEX_LEN_0FC4_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
+ { VEX_W_TABLE (VEX_W_0FC4_P_2) },
},
- /* VEX_LEN_0F72_R_4_P_2 */
+ /* VEX_LEN_0FC5_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
+ { VEX_W_TABLE (VEX_W_0FC5_P_2) },
},
- /* VEX_LEN_0F72_R_6_P_2 */
+ /* VEX_LEN_0FD6_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
+ { VEX_W_TABLE (VEX_W_0FD6_P_2) },
+ { VEX_W_TABLE (VEX_W_0FD6_P_2) },
},
- /* VEX_LEN_0F73_R_2_P_2 */
+ /* VEX_LEN_0FF7_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
+ { VEX_W_TABLE (VEX_W_0FF7_P_2) },
},
- /* VEX_LEN_0F73_R_3_P_2 */
+ /* VEX_LEN_0F3816_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3816_P_2) },
},
- /* VEX_LEN_0F73_R_6_P_2 */
+ /* VEX_LEN_0F3819_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3819_P_2) },
},
- /* VEX_LEN_0F73_R_7_P_2 */
+ /* VEX_LEN_0F381A_P_2_M_0 */
{
- { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
},
- /* VEX_LEN_0F74_P_2 */
+ /* VEX_LEN_0F3836_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F74_P_2) },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3836_P_2) },
},
- /* VEX_LEN_0F75_P_2 */
+ /* VEX_LEN_0F3841_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F75_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3841_P_2) },
},
- /* VEX_LEN_0F76_P_2 */
+ /* VEX_LEN_0F385A_P_2_M_0 */
{
- { VEX_W_TABLE (VEX_W_0F76_P_2) },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
},
- /* VEX_LEN_0F7E_P_1 */
+ /* VEX_LEN_0F38DB_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F7E_P_1) },
- { VEX_W_TABLE (VEX_W_0F7E_P_1) },
+ { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
},
- /* VEX_LEN_0F7E_P_2 */
+ /* VEX_LEN_0F38DC_P_2 */
{
- { "vmovK", { Edq, XMScalar } },
- { "vmovK", { Edq, XMScalar } },
+ { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
},
- /* VEX_LEN_0FAE_R_2_M_0 */
+ /* VEX_LEN_0F38DD_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
+ { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
},
- /* VEX_LEN_0FAE_R_3_M_0 */
+ /* VEX_LEN_0F38DE_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
+ { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
},
- /* VEX_LEN_0FC2_P_1 */
+ /* VEX_LEN_0F38DF_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FC2_P_1) },
- { VEX_W_TABLE (VEX_W_0FC2_P_1) },
+ { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
},
- /* VEX_LEN_0FC2_P_3 */
+ /* VEX_LEN_0F38F2_P_0 */
{
- { VEX_W_TABLE (VEX_W_0FC2_P_3) },
- { VEX_W_TABLE (VEX_W_0FC2_P_3) },
+ { "andnS", { Gdq, VexGdq, Edq }, 0 },
},
- /* VEX_LEN_0FC4_P_2 */
+ /* VEX_LEN_0F38F3_R_1_P_0 */
{
- { VEX_W_TABLE (VEX_W_0FC4_P_2) },
+ { "blsrS", { VexGdq, Edq }, 0 },
},
- /* VEX_LEN_0FC5_P_2 */
+ /* VEX_LEN_0F38F3_R_2_P_0 */
{
- { VEX_W_TABLE (VEX_W_0FC5_P_2) },
+ { "blsmskS", { VexGdq, Edq }, 0 },
},
- /* VEX_LEN_0FD1_P_2 */
+ /* VEX_LEN_0F38F3_R_3_P_0 */
{
- { VEX_W_TABLE (VEX_W_0FD1_P_2) },
+ { "blsiS", { VexGdq, Edq }, 0 },
},
- /* VEX_LEN_0FD2_P_2 */
+ /* VEX_LEN_0F38F5_P_0 */
{
- { VEX_W_TABLE (VEX_W_0FD2_P_2) },
+ { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
},
- /* VEX_LEN_0FD3_P_2 */
+ /* VEX_LEN_0F38F5_P_1 */
{
- { VEX_W_TABLE (VEX_W_0FD3_P_2) },
+ { "pextS", { Gdq, VexGdq, Edq }, 0 },
},
- /* VEX_LEN_0FD4_P_2 */
+ /* VEX_LEN_0F38F5_P_3 */
{
- { VEX_W_TABLE (VEX_W_0FD4_P_2) },
+ { "pdepS", { Gdq, VexGdq, Edq }, 0 },
},
- /* VEX_LEN_0FD5_P_2 */
+ /* VEX_LEN_0F38F6_P_3 */
{
- { VEX_W_TABLE (VEX_W_0FD5_P_2) },
+ { "mulxS", { Gdq, VexGdq, Edq }, 0 },
},
- /* VEX_LEN_0FD6_P_2 */
+ /* VEX_LEN_0F38F7_P_0 */
{
- { VEX_W_TABLE (VEX_W_0FD6_P_2) },
- { VEX_W_TABLE (VEX_W_0FD6_P_2) },
+ { "bextrS", { Gdq, Edq, VexGdq }, 0 },
},
- /* VEX_LEN_0FD7_P_2_M_1 */
+ /* VEX_LEN_0F38F7_P_1 */
{
- { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
+ { "sarxS", { Gdq, Edq, VexGdq }, 0 },
},
- /* VEX_LEN_0FD8_P_2 */
+ /* VEX_LEN_0F38F7_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FD8_P_2) },
+ { "shlxS", { Gdq, Edq, VexGdq }, 0 },
},
- /* VEX_LEN_0FD9_P_2 */
+ /* VEX_LEN_0F38F7_P_3 */
{
- { VEX_W_TABLE (VEX_W_0FD9_P_2) },
+ { "shrxS", { Gdq, Edq, VexGdq }, 0 },
},
- /* VEX_LEN_0FDA_P_2 */
+ /* VEX_LEN_0F3A00_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FDA_P_2) },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
},
- /* VEX_LEN_0FDB_P_2 */
+ /* VEX_LEN_0F3A01_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FDB_P_2) },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
},
- /* VEX_LEN_0FDC_P_2 */
+ /* VEX_LEN_0F3A06_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FDC_P_2) },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
},
- /* VEX_LEN_0FDD_P_2 */
+ /* VEX_LEN_0F3A0A_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FDD_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
},
- /* VEX_LEN_0FDE_P_2 */
+ /* VEX_LEN_0F3A0B_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FDE_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
},
- /* VEX_LEN_0FDF_P_2 */
+ /* VEX_LEN_0F3A14_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FDF_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
},
- /* VEX_LEN_0FE0_P_2 */
+ /* VEX_LEN_0F3A15_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FE0_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
},
- /* VEX_LEN_0FE1_P_2 */
+ /* VEX_LEN_0F3A16_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FE1_P_2) },
+ { "vpextrK", { Edq, XM, Ib }, 0 },
},
- /* VEX_LEN_0FE2_P_2 */
+ /* VEX_LEN_0F3A17_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FE2_P_2) },
+ { "vextractps", { Edqd, XM, Ib }, 0 },
},
- /* VEX_LEN_0FE3_P_2 */
+ /* VEX_LEN_0F3A18_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FE3_P_2) },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
},
- /* VEX_LEN_0FE4_P_2 */
+ /* VEX_LEN_0F3A19_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FE4_P_2) },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
},
- /* VEX_LEN_0FE5_P_2 */
+ /* VEX_LEN_0F3A20_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FE5_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
},
- /* VEX_LEN_0FE8_P_2 */
+ /* VEX_LEN_0F3A21_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FE8_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
},
- /* VEX_LEN_0FE9_P_2 */
+ /* VEX_LEN_0F3A22_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FE9_P_2) },
+ { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 },
},
- /* VEX_LEN_0FEA_P_2 */
+ /* VEX_LEN_0F3A30_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FEA_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
},
- /* VEX_LEN_0FEB_P_2 */
+ /* VEX_LEN_0F3A31_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FEB_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
},
- /* VEX_LEN_0FEC_P_2 */
+ /* VEX_LEN_0F3A32_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FEC_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
},
- /* VEX_LEN_0FED_P_2 */
+ /* VEX_LEN_0F3A33_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FED_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
},
- /* VEX_LEN_0FEE_P_2 */
+ /* VEX_LEN_0F3A38_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FEE_P_2) },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
},
- /* VEX_LEN_0FEF_P_2 */
+ /* VEX_LEN_0F3A39_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FEF_P_2) },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
},
- /* VEX_LEN_0FF1_P_2 */
+ /* VEX_LEN_0F3A41_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FF1_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
},
- /* VEX_LEN_0FF2_P_2 */
+ /* VEX_LEN_0F3A44_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FF2_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
},
- /* VEX_LEN_0FF3_P_2 */
+ /* VEX_LEN_0F3A46_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FF3_P_2) },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
},
- /* VEX_LEN_0FF4_P_2 */
+ /* VEX_LEN_0F3A60_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FF4_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
},
- /* VEX_LEN_0FF5_P_2 */
+ /* VEX_LEN_0F3A61_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FF5_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
},
- /* VEX_LEN_0FF6_P_2 */
+ /* VEX_LEN_0F3A62_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FF6_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
},
- /* VEX_LEN_0FF7_P_2 */
+ /* VEX_LEN_0F3A63_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FF7_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
},
- /* VEX_LEN_0FF8_P_2 */
+ /* VEX_LEN_0F3A6A_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FF8_P_2) },
+ { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
},
- /* VEX_LEN_0FF9_P_2 */
+ /* VEX_LEN_0F3A6B_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FF9_P_2) },
+ { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
},
- /* VEX_LEN_0FFA_P_2 */
+ /* VEX_LEN_0F3A6E_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FFA_P_2) },
+ { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
},
- /* VEX_LEN_0FFB_P_2 */
+ /* VEX_LEN_0F3A6F_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FFB_P_2) },
+ { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
},
- /* VEX_LEN_0FFC_P_2 */
+ /* VEX_LEN_0F3A7A_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FFC_P_2) },
+ { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
},
- /* VEX_LEN_0FFD_P_2 */
+ /* VEX_LEN_0F3A7B_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FFD_P_2) },
+ { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
},
- /* VEX_LEN_0FFE_P_2 */
+ /* VEX_LEN_0F3A7E_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FFE_P_2) },
+ { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
},
- /* VEX_LEN_0F3800_P_2 */
+ /* VEX_LEN_0F3A7F_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3800_P_2) },
+ { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
},
- /* VEX_LEN_0F3801_P_2 */
+ /* VEX_LEN_0F3ADF_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3801_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
},
- /* VEX_LEN_0F3802_P_2 */
+ /* VEX_LEN_0F3AF0_P_3 */
{
- { VEX_W_TABLE (VEX_W_0F3802_P_2) },
+ { "rorxS", { Gdq, Edq, Ib }, 0 },
},
- /* VEX_LEN_0F3803_P_2 */
+ /* VEX_LEN_0FXOP_08_CC */
{
- { VEX_W_TABLE (VEX_W_0F3803_P_2) },
+ { "vpcomb", { XM, Vex128, EXx, Ib }, 0 },
},
- /* VEX_LEN_0F3804_P_2 */
+ /* VEX_LEN_0FXOP_08_CD */
{
- { VEX_W_TABLE (VEX_W_0F3804_P_2) },
+ { "vpcomw", { XM, Vex128, EXx, Ib }, 0 },
},
- /* VEX_LEN_0F3805_P_2 */
+ /* VEX_LEN_0FXOP_08_CE */
{
- { VEX_W_TABLE (VEX_W_0F3805_P_2) },
+ { "vpcomd", { XM, Vex128, EXx, Ib }, 0 },
},
- /* VEX_LEN_0F3806_P_2 */
+ /* VEX_LEN_0FXOP_08_CF */
{
- { VEX_W_TABLE (VEX_W_0F3806_P_2) },
+ { "vpcomq", { XM, Vex128, EXx, Ib }, 0 },
},
- /* VEX_LEN_0F3807_P_2 */
+ /* VEX_LEN_0FXOP_08_EC */
{
- { VEX_W_TABLE (VEX_W_0F3807_P_2) },
+ { "vpcomub", { XM, Vex128, EXx, Ib }, 0 },
},
- /* VEX_LEN_0F3808_P_2 */
+ /* VEX_LEN_0FXOP_08_ED */
{
- { VEX_W_TABLE (VEX_W_0F3808_P_2) },
+ { "vpcomuw", { XM, Vex128, EXx, Ib }, 0 },
},
- /* VEX_LEN_0F3809_P_2 */
+ /* VEX_LEN_0FXOP_08_EE */
{
- { VEX_W_TABLE (VEX_W_0F3809_P_2) },
+ { "vpcomud", { XM, Vex128, EXx, Ib }, 0 },
},
- /* VEX_LEN_0F380A_P_2 */
+ /* VEX_LEN_0FXOP_08_EF */
{
- { VEX_W_TABLE (VEX_W_0F380A_P_2) },
- },
-
- /* VEX_LEN_0F380B_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F380B_P_2) },
- },
-
- /* VEX_LEN_0F3819_P_2_M_0 */
- {
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3819_P_2_M_0) },
- },
-
- /* VEX_LEN_0F381A_P_2_M_0 */
- {
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
- },
-
- /* VEX_LEN_0F381C_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F381C_P_2) },
- },
-
- /* VEX_LEN_0F381D_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F381D_P_2) },
- },
-
- /* VEX_LEN_0F381E_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F381E_P_2) },
- },
-
- /* VEX_LEN_0F3820_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3820_P_2) },
- },
-
- /* VEX_LEN_0F3821_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3821_P_2) },
- },
-
- /* VEX_LEN_0F3822_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3822_P_2) },
- },
-
- /* VEX_LEN_0F3823_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3823_P_2) },
- },
-
- /* VEX_LEN_0F3824_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3824_P_2) },
- },
-
- /* VEX_LEN_0F3825_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3825_P_2) },
- },
-
- /* VEX_LEN_0F3828_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3828_P_2) },
- },
-
- /* VEX_LEN_0F3829_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3829_P_2) },
- },
-
- /* VEX_LEN_0F382A_P_2_M_0 */
- {
- { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
- },
-
- /* VEX_LEN_0F382B_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F382B_P_2) },
- },
-
- /* VEX_LEN_0F3830_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3830_P_2) },
- },
-
- /* VEX_LEN_0F3831_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3831_P_2) },
- },
-
- /* VEX_LEN_0F3832_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3832_P_2) },
- },
-
- /* VEX_LEN_0F3833_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3833_P_2) },
- },
-
- /* VEX_LEN_0F3834_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3834_P_2) },
- },
-
- /* VEX_LEN_0F3835_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3835_P_2) },
- },
-
- /* VEX_LEN_0F3837_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3837_P_2) },
- },
-
- /* VEX_LEN_0F3838_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3838_P_2) },
- },
-
- /* VEX_LEN_0F3839_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3839_P_2) },
- },
-
- /* VEX_LEN_0F383A_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F383A_P_2) },
- },
-
- /* VEX_LEN_0F383B_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F383B_P_2) },
- },
-
- /* VEX_LEN_0F383C_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F383C_P_2) },
- },
-
- /* VEX_LEN_0F383D_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F383D_P_2) },
- },
-
- /* VEX_LEN_0F383E_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F383E_P_2) },
- },
-
- /* VEX_LEN_0F383F_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F383F_P_2) },
- },
-
- /* VEX_LEN_0F3840_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3840_P_2) },
- },
-
- /* VEX_LEN_0F3841_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3841_P_2) },
- },
-
- /* VEX_LEN_0F38DB_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
- },
-
- /* VEX_LEN_0F38DC_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
- },
-
- /* VEX_LEN_0F38DD_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
- },
-
- /* VEX_LEN_0F38DE_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
- },
-
- /* VEX_LEN_0F38DF_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
- },
-
- /* VEX_LEN_0F3A06_P_2 */
- {
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
- },
-
- /* VEX_LEN_0F3A0A_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
- { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
- },
-
- /* VEX_LEN_0F3A0B_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
- { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
- },
-
- /* VEX_LEN_0F3A0E_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
- },
-
- /* VEX_LEN_0F3A0F_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
- },
-
- /* VEX_LEN_0F3A14_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
- },
-
- /* VEX_LEN_0F3A15_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
- },
-
- /* VEX_LEN_0F3A16_P_2 */
- {
- { "vpextrK", { Edq, XM, Ib } },
- },
-
- /* VEX_LEN_0F3A17_P_2 */
- {
- { "vextractps", { Edqd, XM, Ib } },
- },
-
- /* VEX_LEN_0F3A18_P_2 */
- {
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
- },
-
- /* VEX_LEN_0F3A19_P_2 */
- {
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
- },
-
- /* VEX_LEN_0F3A20_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
- },
-
- /* VEX_LEN_0F3A21_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
- },
-
- /* VEX_LEN_0F3A22_P_2 */
- {
- { "vpinsrK", { XM, Vex128, Edq, Ib } },
- },
-
- /* VEX_LEN_0F3A41_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
- },
-
- /* VEX_LEN_0F3A42_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
- },
-
- /* VEX_LEN_0F3A44_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
- },
-
- /* VEX_LEN_0F3A4C_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
- },
-
- /* VEX_LEN_0F3A60_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
- },
-
- /* VEX_LEN_0F3A61_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
- },
-
- /* VEX_LEN_0F3A62_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
- },
-
- /* VEX_LEN_0F3A63_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
- },
-
- /* VEX_LEN_0F3A6A_P_2 */
- {
- { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
- },
-
- /* VEX_LEN_0F3A6B_P_2 */
- {
- { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
- },
-
- /* VEX_LEN_0F3A6E_P_2 */
- {
- { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
- },
-
- /* VEX_LEN_0F3A6F_P_2 */
- {
- { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
- },
-
- /* VEX_LEN_0F3A7A_P_2 */
- {
- { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
- },
-
- /* VEX_LEN_0F3A7B_P_2 */
- {
- { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
- },
-
- /* VEX_LEN_0F3A7E_P_2 */
- {
- { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
- },
-
- /* VEX_LEN_0F3A7F_P_2 */
- {
- { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
- },
-
- /* VEX_LEN_0F3ADF_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
+ { "vpcomuq", { XM, Vex128, EXx, Ib }, 0 },
},
/* VEX_LEN_0FXOP_09_80 */
{
- { "vfrczps", { XM, EXxmm } },
- { "vfrczps", { XM, EXymmq } },
+ { "vfrczps", { XM, EXxmm }, 0 },
+ { "vfrczps", { XM, EXymmq }, 0 },
},
/* VEX_LEN_0FXOP_09_81 */
{
- { "vfrczpd", { XM, EXxmm } },
- { "vfrczpd", { XM, EXymmq } },
+ { "vfrczpd", { XM, EXxmm }, 0 },
+ { "vfrczpd", { XM, EXymmq }, 0 },
},
};
static const struct dis386 vex_w_table[][2] = {
{
/* VEX_W_0F10_P_0 */
- { "vmovups", { XM, EXx } },
+ { "vmovups", { XM, EXx }, 0 },
},
{
/* VEX_W_0F10_P_1 */
- { "vmovss", { XMVexScalar, VexScalar, EXdScalar } },
+ { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
},
{
/* VEX_W_0F10_P_2 */
- { "vmovupd", { XM, EXx } },
+ { "vmovupd", { XM, EXx }, 0 },
},
{
/* VEX_W_0F10_P_3 */
- { "vmovsd", { XMVexScalar, VexScalar, EXqScalar } },
+ { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
},
{
/* VEX_W_0F11_P_0 */
- { "vmovups", { EXxS, XM } },
+ { "vmovups", { EXxS, XM }, 0 },
},
{
/* VEX_W_0F11_P_1 */
- { "vmovss", { EXdVexScalarS, VexScalar, XMScalar } },
+ { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 },
},
{
/* VEX_W_0F11_P_2 */
- { "vmovupd", { EXxS, XM } },
+ { "vmovupd", { EXxS, XM }, 0 },
},
{
/* VEX_W_0F11_P_3 */
- { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar } },
+ { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 },
},
{
/* VEX_W_0F12_P_0_M_0 */
- { "vmovlps", { XM, Vex128, EXq } },
+ { "vmovlps", { XM, Vex128, EXq }, 0 },
},
{
/* VEX_W_0F12_P_0_M_1 */
- { "vmovhlps", { XM, Vex128, EXq } },
+ { "vmovhlps", { XM, Vex128, EXq }, 0 },
},
{
/* VEX_W_0F12_P_1 */
- { "vmovsldup", { XM, EXx } },
+ { "vmovsldup", { XM, EXx }, 0 },
},
{
/* VEX_W_0F12_P_2 */
- { "vmovlpd", { XM, Vex128, EXq } },
+ { "vmovlpd", { XM, Vex128, EXq }, 0 },
},
{
/* VEX_W_0F12_P_3 */
- { "vmovddup", { XM, EXymmq } },
+ { "vmovddup", { XM, EXymmq }, 0 },
},
{
/* VEX_W_0F13_M_0 */
- { "vmovlpX", { EXq, XM } },
+ { "vmovlpX", { EXq, XM }, 0 },
},
{
/* VEX_W_0F14 */
- { "vunpcklpX", { XM, Vex, EXx } },
+ { "vunpcklpX", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F15 */
- { "vunpckhpX", { XM, Vex, EXx } },
+ { "vunpckhpX", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F16_P_0_M_0 */
- { "vmovhps", { XM, Vex128, EXq } },
+ { "vmovhps", { XM, Vex128, EXq }, 0 },
},
{
/* VEX_W_0F16_P_0_M_1 */
- { "vmovlhps", { XM, Vex128, EXq } },
+ { "vmovlhps", { XM, Vex128, EXq }, 0 },
},
{
/* VEX_W_0F16_P_1 */
- { "vmovshdup", { XM, EXx } },
+ { "vmovshdup", { XM, EXx }, 0 },
},
{
/* VEX_W_0F16_P_2 */
- { "vmovhpd", { XM, Vex128, EXq } },
+ { "vmovhpd", { XM, Vex128, EXq }, 0 },
},
{
/* VEX_W_0F17_M_0 */
- { "vmovhpX", { EXq, XM } },
+ { "vmovhpX", { EXq, XM }, 0 },
},
{
/* VEX_W_0F28 */
- { "vmovapX", { XM, EXx } },
+ { "vmovapX", { XM, EXx }, 0 },
},
{
/* VEX_W_0F29 */
- { "vmovapX", { EXxS, XM } },
+ { "vmovapX", { EXxS, XM }, 0 },
},
{
/* VEX_W_0F2B_M_0 */
- { "vmovntpX", { Mx, XM } },
+ { "vmovntpX", { Mx, XM }, 0 },
},
{
/* VEX_W_0F2E_P_0 */
- { "vucomiss", { XMScalar, EXdScalar } },
+ { "vucomiss", { XMScalar, EXdScalar }, 0 },
},
{
/* VEX_W_0F2E_P_2 */
- { "vucomisd", { XMScalar, EXqScalar } },
+ { "vucomisd", { XMScalar, EXqScalar }, 0 },
},
{
/* VEX_W_0F2F_P_0 */
- { "vcomiss", { XMScalar, EXdScalar } },
+ { "vcomiss", { XMScalar, EXdScalar }, 0 },
},
{
/* VEX_W_0F2F_P_2 */
- { "vcomisd", { XMScalar, EXqScalar } },
+ { "vcomisd", { XMScalar, EXqScalar }, 0 },
+ },
+ {
+ /* VEX_W_0F41_P_0_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
+ },
+ {
+ /* VEX_W_0F41_P_2_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
+ },
+ {
+ /* VEX_W_0F42_P_0_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
+ },
+ {
+ /* VEX_W_0F42_P_2_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
+ },
+ {
+ /* VEX_W_0F44_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
+ },
+ {
+ /* VEX_W_0F44_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
+ },
+ {
+ /* VEX_W_0F45_P_0_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
+ },
+ {
+ /* VEX_W_0F45_P_2_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
+ },
+ {
+ /* VEX_W_0F46_P_0_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
+ },
+ {
+ /* VEX_W_0F46_P_2_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
+ },
+ {
+ /* VEX_W_0F47_P_0_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
+ },
+ {
+ /* VEX_W_0F47_P_2_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
+ },
+ {
+ /* VEX_W_0F4A_P_0_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
+ },
+ {
+ /* VEX_W_0F4A_P_2_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
+ },
+ {
+ /* VEX_W_0F4B_P_0_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
+ { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
+ },
+ {
+ /* VEX_W_0F4B_P_2_LEN_1 */
+ { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
},
{
/* VEX_W_0F50_M_0 */
- { "vmovmskpX", { Gdq, XS } },
+ { "vmovmskpX", { Gdq, XS }, 0 },
},
{
/* VEX_W_0F51_P_0 */
- { "vsqrtps", { XM, EXx } },
+ { "vsqrtps", { XM, EXx }, 0 },
},
{
/* VEX_W_0F51_P_1 */
- { "vsqrtss", { XMScalar, VexScalar, EXdScalar } },
+ { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
},
{
/* VEX_W_0F51_P_2 */
- { "vsqrtpd", { XM, EXx } },
+ { "vsqrtpd", { XM, EXx }, 0 },
},
{
/* VEX_W_0F51_P_3 */
- { "vsqrtsd", { XMScalar, VexScalar, EXqScalar } },
+ { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
},
{
/* VEX_W_0F52_P_0 */
- { "vrsqrtps", { XM, EXx } },
+ { "vrsqrtps", { XM, EXx }, 0 },
},
{
/* VEX_W_0F52_P_1 */
- { "vrsqrtss", { XMScalar, VexScalar, EXdScalar } },
+ { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
},
{
/* VEX_W_0F53_P_0 */
- { "vrcpps", { XM, EXx } },
+ { "vrcpps", { XM, EXx }, 0 },
},
{
/* VEX_W_0F53_P_1 */
- { "vrcpss", { XMScalar, VexScalar, EXdScalar } },
+ { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
},
{
/* VEX_W_0F58_P_0 */
- { "vaddps", { XM, Vex, EXx } },
+ { "vaddps", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F58_P_1 */
- { "vaddss", { XMScalar, VexScalar, EXdScalar } },
+ { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
},
{
/* VEX_W_0F58_P_2 */
- { "vaddpd", { XM, Vex, EXx } },
+ { "vaddpd", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F58_P_3 */
- { "vaddsd", { XMScalar, VexScalar, EXqScalar } },
+ { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
},
{
/* VEX_W_0F59_P_0 */
- { "vmulps", { XM, Vex, EXx } },
+ { "vmulps", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F59_P_1 */
- { "vmulss", { XMScalar, VexScalar, EXdScalar } },
+ { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
},
{
/* VEX_W_0F59_P_2 */
- { "vmulpd", { XM, Vex, EXx } },
+ { "vmulpd", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F59_P_3 */
- { "vmulsd", { XMScalar, VexScalar, EXqScalar } },
+ { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
},
{
/* VEX_W_0F5A_P_0 */
- { "vcvtps2pd", { XM, EXxmmq } },
+ { "vcvtps2pd", { XM, EXxmmq }, 0 },
},
{
/* VEX_W_0F5A_P_1 */
- { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar } },
+ { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
},
{
/* VEX_W_0F5A_P_3 */
- { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar } },
+ { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
},
{
/* VEX_W_0F5B_P_0 */
- { "vcvtdq2ps", { XM, EXx } },
+ { "vcvtdq2ps", { XM, EXx }, 0 },
},
{
/* VEX_W_0F5B_P_1 */
- { "vcvttps2dq", { XM, EXx } },
+ { "vcvttps2dq", { XM, EXx }, 0 },
},
{
/* VEX_W_0F5B_P_2 */
- { "vcvtps2dq", { XM, EXx } },
+ { "vcvtps2dq", { XM, EXx }, 0 },
},
{
/* VEX_W_0F5C_P_0 */
- { "vsubps", { XM, Vex, EXx } },
+ { "vsubps", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F5C_P_1 */
- { "vsubss", { XMScalar, VexScalar, EXdScalar } },
+ { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
},
{
/* VEX_W_0F5C_P_2 */
- { "vsubpd", { XM, Vex, EXx } },
+ { "vsubpd", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F5C_P_3 */
- { "vsubsd", { XMScalar, VexScalar, EXqScalar } },
+ { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
},
{
/* VEX_W_0F5D_P_0 */
- { "vminps", { XM, Vex, EXx } },
+ { "vminps", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F5D_P_1 */
- { "vminss", { XMScalar, VexScalar, EXdScalar } },
+ { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
},
{
/* VEX_W_0F5D_P_2 */
- { "vminpd", { XM, Vex, EXx } },
+ { "vminpd", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F5D_P_3 */
- { "vminsd", { XMScalar, VexScalar, EXqScalar } },
+ { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
},
{
/* VEX_W_0F5E_P_0 */
- { "vdivps", { XM, Vex, EXx } },
+ { "vdivps", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F5E_P_1 */
- { "vdivss", { XMScalar, VexScalar, EXdScalar } },
+ { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
},
{
/* VEX_W_0F5E_P_2 */
- { "vdivpd", { XM, Vex, EXx } },
+ { "vdivpd", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F5E_P_3 */
- { "vdivsd", { XMScalar, VexScalar, EXqScalar } },
+ { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
},
{
/* VEX_W_0F5F_P_0 */
- { "vmaxps", { XM, Vex, EXx } },
+ { "vmaxps", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F5F_P_1 */
- { "vmaxss", { XMScalar, VexScalar, EXdScalar } },
+ { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
},
{
/* VEX_W_0F5F_P_2 */
- { "vmaxpd", { XM, Vex, EXx } },
+ { "vmaxpd", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F5F_P_3 */
- { "vmaxsd", { XMScalar, VexScalar, EXqScalar } },
+ { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
},
{
/* VEX_W_0F60_P_2 */
- { "vpunpcklbw", { XM, Vex128, EXx } },
+ { "vpunpcklbw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F61_P_2 */
- { "vpunpcklwd", { XM, Vex128, EXx } },
+ { "vpunpcklwd", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F62_P_2 */
- { "vpunpckldq", { XM, Vex128, EXx } },
+ { "vpunpckldq", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F63_P_2 */
- { "vpacksswb", { XM, Vex128, EXx } },
+ { "vpacksswb", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F64_P_2 */
- { "vpcmpgtb", { XM, Vex128, EXx } },
+ { "vpcmpgtb", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F65_P_2 */
- { "vpcmpgtw", { XM, Vex128, EXx } },
+ { "vpcmpgtw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F66_P_2 */
- { "vpcmpgtd", { XM, Vex128, EXx } },
+ { "vpcmpgtd", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F67_P_2 */
- { "vpackuswb", { XM, Vex128, EXx } },
+ { "vpackuswb", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F68_P_2 */
- { "vpunpckhbw", { XM, Vex128, EXx } },
+ { "vpunpckhbw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F69_P_2 */
- { "vpunpckhwd", { XM, Vex128, EXx } },
+ { "vpunpckhwd", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F6A_P_2 */
- { "vpunpckhdq", { XM, Vex128, EXx } },
+ { "vpunpckhdq", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F6B_P_2 */
- { "vpackssdw", { XM, Vex128, EXx } },
+ { "vpackssdw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F6C_P_2 */
- { "vpunpcklqdq", { XM, Vex128, EXx } },
+ { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F6D_P_2 */
- { "vpunpckhqdq", { XM, Vex128, EXx } },
+ { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F6F_P_1 */
- { "vmovdqu", { XM, EXx } },
+ { "vmovdqu", { XM, EXx }, 0 },
},
{
/* VEX_W_0F6F_P_2 */
- { "vmovdqa", { XM, EXx } },
+ { "vmovdqa", { XM, EXx }, 0 },
},
{
/* VEX_W_0F70_P_1 */
- { "vpshufhw", { XM, EXx, Ib } },
+ { "vpshufhw", { XM, EXx, Ib }, 0 },
},
{
/* VEX_W_0F70_P_2 */
- { "vpshufd", { XM, EXx, Ib } },
+ { "vpshufd", { XM, EXx, Ib }, 0 },
},
{
/* VEX_W_0F70_P_3 */
- { "vpshuflw", { XM, EXx, Ib } },
+ { "vpshuflw", { XM, EXx, Ib }, 0 },
},
{
/* VEX_W_0F71_R_2_P_2 */
- { "vpsrlw", { Vex128, XS, Ib } },
+ { "vpsrlw", { Vex, XS, Ib }, 0 },
},
{
/* VEX_W_0F71_R_4_P_2 */
- { "vpsraw", { Vex128, XS, Ib } },
+ { "vpsraw", { Vex, XS, Ib }, 0 },
},
{
/* VEX_W_0F71_R_6_P_2 */
- { "vpsllw", { Vex128, XS, Ib } },
+ { "vpsllw", { Vex, XS, Ib }, 0 },
},
{
/* VEX_W_0F72_R_2_P_2 */
- { "vpsrld", { Vex128, XS, Ib } },
+ { "vpsrld", { Vex, XS, Ib }, 0 },
},
{
/* VEX_W_0F72_R_4_P_2 */
- { "vpsrad", { Vex128, XS, Ib } },
+ { "vpsrad", { Vex, XS, Ib }, 0 },
},
{
/* VEX_W_0F72_R_6_P_2 */
- { "vpslld", { Vex128, XS, Ib } },
+ { "vpslld", { Vex, XS, Ib }, 0 },
},
{
/* VEX_W_0F73_R_2_P_2 */
- { "vpsrlq", { Vex128, XS, Ib } },
+ { "vpsrlq", { Vex, XS, Ib }, 0 },
},
{
/* VEX_W_0F73_R_3_P_2 */
- { "vpsrldq", { Vex128, XS, Ib } },
+ { "vpsrldq", { Vex, XS, Ib }, 0 },
},
{
/* VEX_W_0F73_R_6_P_2 */
- { "vpsllq", { Vex128, XS, Ib } },
+ { "vpsllq", { Vex, XS, Ib }, 0 },
},
{
/* VEX_W_0F73_R_7_P_2 */
- { "vpslldq", { Vex128, XS, Ib } },
+ { "vpslldq", { Vex, XS, Ib }, 0 },
},
{
/* VEX_W_0F74_P_2 */
- { "vpcmpeqb", { XM, Vex128, EXx } },
+ { "vpcmpeqb", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F75_P_2 */
- { "vpcmpeqw", { XM, Vex128, EXx } },
+ { "vpcmpeqw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F76_P_2 */
- { "vpcmpeqd", { XM, Vex128, EXx } },
+ { "vpcmpeqd", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F77_P_0 */
- { "", { VZERO } },
+ { "", { VZERO }, 0 },
},
{
/* VEX_W_0F7C_P_2 */
- { "vhaddpd", { XM, Vex, EXx } },
+ { "vhaddpd", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F7C_P_3 */
- { "vhaddps", { XM, Vex, EXx } },
+ { "vhaddps", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F7D_P_2 */
- { "vhsubpd", { XM, Vex, EXx } },
+ { "vhsubpd", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F7D_P_3 */
- { "vhsubps", { XM, Vex, EXx } },
+ { "vhsubps", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F7E_P_1 */
- { "vmovq", { XMScalar, EXqScalar } },
+ { "vmovq", { XMScalar, EXqScalar }, 0 },
},
{
/* VEX_W_0F7F_P_1 */
- { "vmovdqu", { EXxS, XM } },
+ { "vmovdqu", { EXxS, XM }, 0 },
},
{
/* VEX_W_0F7F_P_2 */
- { "vmovdqa", { EXxS, XM } },
+ { "vmovdqa", { EXxS, XM }, 0 },
+ },
+ {
+ /* VEX_W_0F90_P_0_LEN_0 */
+ { "kmovw", { MaskG, MaskE }, 0 },
+ { "kmovq", { MaskG, MaskE }, 0 },
+ },
+ {
+ /* VEX_W_0F90_P_2_LEN_0 */
+ { "kmovb", { MaskG, MaskBDE }, 0 },
+ { "kmovd", { MaskG, MaskBDE }, 0 },
+ },
+ {
+ /* VEX_W_0F91_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
+ },
+ {
+ /* VEX_W_0F91_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
+ },
+ {
+ /* VEX_W_0F92_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
+ },
+ {
+ /* VEX_W_0F92_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
+ },
+ {
+ /* VEX_W_0F92_P_3_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
+ },
+ {
+ /* VEX_W_0F93_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
+ },
+ {
+ /* VEX_W_0F93_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
+ },
+ {
+ /* VEX_W_0F93_P_3_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
+ },
+ {
+ /* VEX_W_0F98_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
+ },
+ {
+ /* VEX_W_0F98_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
+ },
+ {
+ /* VEX_W_0F99_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
+ },
+ {
+ /* VEX_W_0F99_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
},
{
/* VEX_W_0FAE_R_2_M_0 */
- { "vldmxcsr", { Md } },
+ { "vldmxcsr", { Md }, 0 },
},
{
/* VEX_W_0FAE_R_3_M_0 */
- { "vstmxcsr", { Md } },
+ { "vstmxcsr", { Md }, 0 },
},
{
/* VEX_W_0FC2_P_0 */
- { "vcmpps", { XM, Vex, EXx, VCMP } },
+ { "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
},
{
/* VEX_W_0FC2_P_1 */
- { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP } },
+ { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
},
{
/* VEX_W_0FC2_P_2 */
- { "vcmppd", { XM, Vex, EXx, VCMP } },
+ { "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
},
{
/* VEX_W_0FC2_P_3 */
- { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP } },
+ { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
},
{
/* VEX_W_0FC4_P_2 */
- { "vpinsrw", { XM, Vex128, Edqw, Ib } },
+ { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
},
{
/* VEX_W_0FC5_P_2 */
- { "vpextrw", { Gdq, XS, Ib } },
+ { "vpextrw", { Gdq, XS, Ib }, 0 },
},
{
/* VEX_W_0FD0_P_2 */
- { "vaddsubpd", { XM, Vex, EXx } },
+ { "vaddsubpd", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FD0_P_3 */
- { "vaddsubps", { XM, Vex, EXx } },
+ { "vaddsubps", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FD1_P_2 */
- { "vpsrlw", { XM, Vex128, EXx } },
+ { "vpsrlw", { XM, Vex, EXxmm }, 0 },
},
{
/* VEX_W_0FD2_P_2 */
- { "vpsrld", { XM, Vex128, EXx } },
+ { "vpsrld", { XM, Vex, EXxmm }, 0 },
},
{
/* VEX_W_0FD3_P_2 */
- { "vpsrlq", { XM, Vex128, EXx } },
+ { "vpsrlq", { XM, Vex, EXxmm }, 0 },
},
{
/* VEX_W_0FD4_P_2 */
- { "vpaddq", { XM, Vex128, EXx } },
+ { "vpaddq", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FD5_P_2 */
- { "vpmullw", { XM, Vex128, EXx } },
+ { "vpmullw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FD6_P_2 */
- { "vmovq", { EXqScalarS, XMScalar } },
+ { "vmovq", { EXqScalarS, XMScalar }, 0 },
},
{
/* VEX_W_0FD7_P_2_M_1 */
- { "vpmovmskb", { Gdq, XS } },
+ { "vpmovmskb", { Gdq, XS }, 0 },
},
{
/* VEX_W_0FD8_P_2 */
- { "vpsubusb", { XM, Vex128, EXx } },
+ { "vpsubusb", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FD9_P_2 */
- { "vpsubusw", { XM, Vex128, EXx } },
+ { "vpsubusw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FDA_P_2 */
- { "vpminub", { XM, Vex128, EXx } },
+ { "vpminub", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FDB_P_2 */
- { "vpand", { XM, Vex128, EXx } },
+ { "vpand", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FDC_P_2 */
- { "vpaddusb", { XM, Vex128, EXx } },
+ { "vpaddusb", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FDD_P_2 */
- { "vpaddusw", { XM, Vex128, EXx } },
+ { "vpaddusw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FDE_P_2 */
- { "vpmaxub", { XM, Vex128, EXx } },
+ { "vpmaxub", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FDF_P_2 */
- { "vpandn", { XM, Vex128, EXx } },
+ { "vpandn", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FE0_P_2 */
- { "vpavgb", { XM, Vex128, EXx } },
+ { "vpavgb", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FE1_P_2 */
- { "vpsraw", { XM, Vex128, EXx } },
+ { "vpsraw", { XM, Vex, EXxmm }, 0 },
},
{
/* VEX_W_0FE2_P_2 */
- { "vpsrad", { XM, Vex128, EXx } },
+ { "vpsrad", { XM, Vex, EXxmm }, 0 },
},
{
/* VEX_W_0FE3_P_2 */
- { "vpavgw", { XM, Vex128, EXx } },
+ { "vpavgw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FE4_P_2 */
- { "vpmulhuw", { XM, Vex128, EXx } },
+ { "vpmulhuw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FE5_P_2 */
- { "vpmulhw", { XM, Vex128, EXx } },
+ { "vpmulhw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FE6_P_1 */
- { "vcvtdq2pd", { XM, EXxmmq } },
+ { "vcvtdq2pd", { XM, EXxmmq }, 0 },
},
{
/* VEX_W_0FE6_P_2 */
- { "vcvttpd2dq%XY", { XMM, EXx } },
+ { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
},
{
/* VEX_W_0FE6_P_3 */
- { "vcvtpd2dq%XY", { XMM, EXx } },
+ { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
},
{
/* VEX_W_0FE7_P_2_M_0 */
- { "vmovntdq", { Mx, XM } },
+ { "vmovntdq", { Mx, XM }, 0 },
},
{
/* VEX_W_0FE8_P_2 */
- { "vpsubsb", { XM, Vex128, EXx } },
+ { "vpsubsb", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FE9_P_2 */
- { "vpsubsw", { XM, Vex128, EXx } },
+ { "vpsubsw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FEA_P_2 */
- { "vpminsw", { XM, Vex128, EXx } },
+ { "vpminsw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FEB_P_2 */
- { "vpor", { XM, Vex128, EXx } },
+ { "vpor", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FEC_P_2 */
- { "vpaddsb", { XM, Vex128, EXx } },
+ { "vpaddsb", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FED_P_2 */
- { "vpaddsw", { XM, Vex128, EXx } },
+ { "vpaddsw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FEE_P_2 */
- { "vpmaxsw", { XM, Vex128, EXx } },
+ { "vpmaxsw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FEF_P_2 */
- { "vpxor", { XM, Vex128, EXx } },
+ { "vpxor", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FF0_P_3_M_0 */
- { "vlddqu", { XM, M } },
+ { "vlddqu", { XM, M }, 0 },
},
{
/* VEX_W_0FF1_P_2 */
- { "vpsllw", { XM, Vex128, EXx } },
+ { "vpsllw", { XM, Vex, EXxmm }, 0 },
},
{
/* VEX_W_0FF2_P_2 */
- { "vpslld", { XM, Vex128, EXx } },
+ { "vpslld", { XM, Vex, EXxmm }, 0 },
},
{
/* VEX_W_0FF3_P_2 */
- { "vpsllq", { XM, Vex128, EXx } },
+ { "vpsllq", { XM, Vex, EXxmm }, 0 },
},
{
/* VEX_W_0FF4_P_2 */
- { "vpmuludq", { XM, Vex128, EXx } },
+ { "vpmuludq", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FF5_P_2 */
- { "vpmaddwd", { XM, Vex128, EXx } },
+ { "vpmaddwd", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FF6_P_2 */
- { "vpsadbw", { XM, Vex128, EXx } },
+ { "vpsadbw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FF7_P_2 */
- { "vmaskmovdqu", { XM, XS } },
+ { "vmaskmovdqu", { XM, XS }, 0 },
},
{
/* VEX_W_0FF8_P_2 */
- { "vpsubb", { XM, Vex128, EXx } },
+ { "vpsubb", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FF9_P_2 */
- { "vpsubw", { XM, Vex128, EXx } },
+ { "vpsubw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FFA_P_2 */
- { "vpsubd", { XM, Vex128, EXx } },
+ { "vpsubd", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FFB_P_2 */
- { "vpsubq", { XM, Vex128, EXx } },
+ { "vpsubq", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FFC_P_2 */
- { "vpaddb", { XM, Vex128, EXx } },
+ { "vpaddb", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FFD_P_2 */
- { "vpaddw", { XM, Vex128, EXx } },
+ { "vpaddw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0FFE_P_2 */
- { "vpaddd", { XM, Vex128, EXx } },
+ { "vpaddd", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F3800_P_2 */
- { "vpshufb", { XM, Vex128, EXx } },
+ { "vpshufb", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F3801_P_2 */
- { "vphaddw", { XM, Vex128, EXx } },
+ { "vphaddw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F3802_P_2 */
- { "vphaddd", { XM, Vex128, EXx } },
+ { "vphaddd", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F3803_P_2 */
- { "vphaddsw", { XM, Vex128, EXx } },
+ { "vphaddsw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F3804_P_2 */
- { "vpmaddubsw", { XM, Vex128, EXx } },
+ { "vpmaddubsw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F3805_P_2 */
- { "vphsubw", { XM, Vex128, EXx } },
+ { "vphsubw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F3806_P_2 */
- { "vphsubd", { XM, Vex128, EXx } },
+ { "vphsubd", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F3807_P_2 */
- { "vphsubsw", { XM, Vex128, EXx } },
+ { "vphsubsw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F3808_P_2 */
- { "vpsignb", { XM, Vex128, EXx } },
+ { "vpsignb", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F3809_P_2 */
- { "vpsignw", { XM, Vex128, EXx } },
+ { "vpsignw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F380A_P_2 */
- { "vpsignd", { XM, Vex128, EXx } },
+ { "vpsignd", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F380B_P_2 */
- { "vpmulhrsw", { XM, Vex128, EXx } },
+ { "vpmulhrsw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F380C_P_2 */
- { "vpermilps", { XM, Vex, EXx } },
+ { "vpermilps", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F380D_P_2 */
- { "vpermilpd", { XM, Vex, EXx } },
+ { "vpermilpd", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F380E_P_2 */
- { "vtestps", { XM, EXx } },
+ { "vtestps", { XM, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F380F_P_2 */
+ { "vtestpd", { XM, EXx }, 0 },
},
{
- /* VEX_W_0F380F_P_2 */
- { "vtestpd", { XM, EXx } },
+ /* VEX_W_0F3816_P_2 */
+ { "vpermps", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F3817_P_2 */
- { "vptest", { XM, EXx } },
+ { "vptest", { XM, EXx }, 0 },
},
{
- /* VEX_W_0F3818_P_2_M_0 */
- { "vbroadcastss", { XM, Md } },
+ /* VEX_W_0F3818_P_2 */
+ { "vbroadcastss", { XM, EXxmm_md }, 0 },
},
{
- /* VEX_W_0F3819_P_2_M_0 */
- { "vbroadcastsd", { XM, Mq } },
+ /* VEX_W_0F3819_P_2 */
+ { "vbroadcastsd", { XM, EXxmm_mq }, 0 },
},
{
/* VEX_W_0F381A_P_2_M_0 */
- { "vbroadcastf128", { XM, Mxmm } },
+ { "vbroadcastf128", { XM, Mxmm }, 0 },
},
{
/* VEX_W_0F381C_P_2 */
- { "vpabsb", { XM, EXx } },
+ { "vpabsb", { XM, EXx }, 0 },
},
{
/* VEX_W_0F381D_P_2 */
- { "vpabsw", { XM, EXx } },
+ { "vpabsw", { XM, EXx }, 0 },
},
{
/* VEX_W_0F381E_P_2 */
- { "vpabsd", { XM, EXx } },
+ { "vpabsd", { XM, EXx }, 0 },
},
{
/* VEX_W_0F3820_P_2 */
- { "vpmovsxbw", { XM, EXq } },
+ { "vpmovsxbw", { XM, EXxmmq }, 0 },
},
{
/* VEX_W_0F3821_P_2 */
- { "vpmovsxbd", { XM, EXd } },
+ { "vpmovsxbd", { XM, EXxmmqd }, 0 },
},
{
/* VEX_W_0F3822_P_2 */
- { "vpmovsxbq", { XM, EXw } },
+ { "vpmovsxbq", { XM, EXxmmdw }, 0 },
},
{
/* VEX_W_0F3823_P_2 */
- { "vpmovsxwd", { XM, EXq } },
+ { "vpmovsxwd", { XM, EXxmmq }, 0 },
},
{
/* VEX_W_0F3824_P_2 */
- { "vpmovsxwq", { XM, EXd } },
+ { "vpmovsxwq", { XM, EXxmmqd }, 0 },
},
{
/* VEX_W_0F3825_P_2 */
- { "vpmovsxdq", { XM, EXq } },
+ { "vpmovsxdq", { XM, EXxmmq }, 0 },
},
{
/* VEX_W_0F3828_P_2 */
- { "vpmuldq", { XM, Vex128, EXx } },
+ { "vpmuldq", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F3829_P_2 */
- { "vpcmpeqq", { XM, Vex128, EXx } },
+ { "vpcmpeqq", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F382A_P_2_M_0 */
- { "vmovntdqa", { XM, Mx } },
+ { "vmovntdqa", { XM, Mx }, 0 },
},
{
/* VEX_W_0F382B_P_2 */
- { "vpackusdw", { XM, Vex128, EXx } },
+ { "vpackusdw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F382C_P_2_M_0 */
- { "vmaskmovps", { XM, Vex, Mx } },
+ { "vmaskmovps", { XM, Vex, Mx }, 0 },
},
{
/* VEX_W_0F382D_P_2_M_0 */
- { "vmaskmovpd", { XM, Vex, Mx } },
+ { "vmaskmovpd", { XM, Vex, Mx }, 0 },
},
{
/* VEX_W_0F382E_P_2_M_0 */
- { "vmaskmovps", { Mx, Vex, XM } },
+ { "vmaskmovps", { Mx, Vex, XM }, 0 },
},
{
/* VEX_W_0F382F_P_2_M_0 */
- { "vmaskmovpd", { Mx, Vex, XM } },
+ { "vmaskmovpd", { Mx, Vex, XM }, 0 },
},
{
/* VEX_W_0F3830_P_2 */
- { "vpmovzxbw", { XM, EXq } },
+ { "vpmovzxbw", { XM, EXxmmq }, 0 },
},
{
/* VEX_W_0F3831_P_2 */
- { "vpmovzxbd", { XM, EXd } },
+ { "vpmovzxbd", { XM, EXxmmqd }, 0 },
},
{
/* VEX_W_0F3832_P_2 */
- { "vpmovzxbq", { XM, EXw } },
+ { "vpmovzxbq", { XM, EXxmmdw }, 0 },
},
{
/* VEX_W_0F3833_P_2 */
- { "vpmovzxwd", { XM, EXq } },
+ { "vpmovzxwd", { XM, EXxmmq }, 0 },
},
{
/* VEX_W_0F3834_P_2 */
- { "vpmovzxwq", { XM, EXd } },
+ { "vpmovzxwq", { XM, EXxmmqd }, 0 },
},
{
/* VEX_W_0F3835_P_2 */
- { "vpmovzxdq", { XM, EXq } },
+ { "vpmovzxdq", { XM, EXxmmq }, 0 },
+ },
+ {
+ /* VEX_W_0F3836_P_2 */
+ { "vpermd", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F3837_P_2 */
- { "vpcmpgtq", { XM, Vex128, EXx } },
+ { "vpcmpgtq", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F3838_P_2 */
- { "vpminsb", { XM, Vex128, EXx } },
+ { "vpminsb", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F3839_P_2 */
- { "vpminsd", { XM, Vex128, EXx } },
+ { "vpminsd", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F383A_P_2 */
- { "vpminuw", { XM, Vex128, EXx } },
+ { "vpminuw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F383B_P_2 */
- { "vpminud", { XM, Vex128, EXx } },
+ { "vpminud", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F383C_P_2 */
- { "vpmaxsb", { XM, Vex128, EXx } },
+ { "vpmaxsb", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F383D_P_2 */
- { "vpmaxsd", { XM, Vex128, EXx } },
+ { "vpmaxsd", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F383E_P_2 */
- { "vpmaxuw", { XM, Vex128, EXx } },
+ { "vpmaxuw", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F383F_P_2 */
- { "vpmaxud", { XM, Vex128, EXx } },
+ { "vpmaxud", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F3840_P_2 */
- { "vpmulld", { XM, Vex128, EXx } },
+ { "vpmulld", { XM, Vex, EXx }, 0 },
},
{
/* VEX_W_0F3841_P_2 */
- { "vphminposuw", { XM, EXx } },
+ { "vphminposuw", { XM, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3846_P_2 */
+ { "vpsravd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3858_P_2 */
+ { "vpbroadcastd", { XM, EXxmm_md }, 0 },
+ },
+ {
+ /* VEX_W_0F3859_P_2 */
+ { "vpbroadcastq", { XM, EXxmm_mq }, 0 },
+ },
+ {
+ /* VEX_W_0F385A_P_2_M_0 */
+ { "vbroadcasti128", { XM, Mxmm }, 0 },
+ },
+ {
+ /* VEX_W_0F3878_P_2 */
+ { "vpbroadcastb", { XM, EXxmm_mb }, 0 },
+ },
+ {
+ /* VEX_W_0F3879_P_2 */
+ { "vpbroadcastw", { XM, EXxmm_mw }, 0 },
},
{
/* VEX_W_0F38DB_P_2 */
- { "vaesimc", { XM, EXx } },
+ { "vaesimc", { XM, EXx }, 0 },
},
{
/* VEX_W_0F38DC_P_2 */
- { "vaesenc", { XM, Vex128, EXx } },
+ { "vaesenc", { XM, Vex128, EXx }, 0 },
},
{
/* VEX_W_0F38DD_P_2 */
- { "vaesenclast", { XM, Vex128, EXx } },
+ { "vaesenclast", { XM, Vex128, EXx }, 0 },
},
{
/* VEX_W_0F38DE_P_2 */
- { "vaesdec", { XM, Vex128, EXx } },
+ { "vaesdec", { XM, Vex128, EXx }, 0 },
},
{
/* VEX_W_0F38DF_P_2 */
- { "vaesdeclast", { XM, Vex128, EXx } },
+ { "vaesdeclast", { XM, Vex128, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3A00_P_2 */
+ { Bad_Opcode },
+ { "vpermq", { XM, EXx, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A01_P_2 */
+ { Bad_Opcode },
+ { "vpermpd", { XM, EXx, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A02_P_2 */
+ { "vpblendd", { XM, Vex, EXx, Ib }, 0 },
},
{
/* VEX_W_0F3A04_P_2 */
- { "vpermilps", { XM, EXx, Ib } },
+ { "vpermilps", { XM, EXx, Ib }, 0 },
},
{
/* VEX_W_0F3A05_P_2 */
- { "vpermilpd", { XM, EXx, Ib } },
+ { "vpermilpd", { XM, EXx, Ib }, 0 },
},
{
/* VEX_W_0F3A06_P_2 */
- { "vperm2f128", { XM, Vex256, EXx, Ib } },
+ { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 },
},
{
/* VEX_W_0F3A08_P_2 */
- { "vroundps", { XM, EXx, Ib } },
+ { "vroundps", { XM, EXx, Ib }, 0 },
},
{
/* VEX_W_0F3A09_P_2 */
- { "vroundpd", { XM, EXx, Ib } },
+ { "vroundpd", { XM, EXx, Ib }, 0 },
},
{
/* VEX_W_0F3A0A_P_2 */
- { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib } },
+ { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
},
{
/* VEX_W_0F3A0B_P_2 */
- { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib } },
+ { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
},
{
/* VEX_W_0F3A0C_P_2 */
- { "vblendps", { XM, Vex, EXx, Ib } },
+ { "vblendps", { XM, Vex, EXx, Ib }, 0 },
},
{
/* VEX_W_0F3A0D_P_2 */
- { "vblendpd", { XM, Vex, EXx, Ib } },
+ { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
},
{
/* VEX_W_0F3A0E_P_2 */
- { "vpblendw", { XM, Vex128, EXx, Ib } },
+ { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
},
{
/* VEX_W_0F3A0F_P_2 */
- { "vpalignr", { XM, Vex128, EXx, Ib } },
+ { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
},
{
/* VEX_W_0F3A14_P_2 */
- { "vpextrb", { Edqb, XM, Ib } },
+ { "vpextrb", { Edqb, XM, Ib }, 0 },
},
{
/* VEX_W_0F3A15_P_2 */
- { "vpextrw", { Edqw, XM, Ib } },
+ { "vpextrw", { Edqw, XM, Ib }, 0 },
},
{
/* VEX_W_0F3A18_P_2 */
- { "vinsertf128", { XM, Vex256, EXxmm, Ib } },
+ { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 },
},
{
/* VEX_W_0F3A19_P_2 */
- { "vextractf128", { EXxmm, XM, Ib } },
+ { "vextractf128", { EXxmm, XM, Ib }, 0 },
},
{
/* VEX_W_0F3A20_P_2 */
- { "vpinsrb", { XM, Vex128, Edqb, Ib } },
+ { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
},
{
/* VEX_W_0F3A21_P_2 */
- { "vinsertps", { XM, Vex128, EXd, Ib } },
+ { "vinsertps", { XM, Vex128, EXd, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A30_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
+ },
+ {
+ /* VEX_W_0F3A31_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
+ },
+ {
+ /* VEX_W_0F3A32_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
+ },
+ {
+ /* VEX_W_0F3A33_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
+ },
+ {
+ /* VEX_W_0F3A38_P_2 */
+ { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 },
+ },
+ {
+ /* VEX_W_0F3A39_P_2 */
+ { "vextracti128", { EXxmm, XM, Ib }, 0 },
},
{
/* VEX_W_0F3A40_P_2 */
- { "vdpps", { XM, Vex, EXx, Ib } },
+ { "vdpps", { XM, Vex, EXx, Ib }, 0 },
},
{
/* VEX_W_0F3A41_P_2 */
- { "vdppd", { XM, Vex128, EXx, Ib } },
+ { "vdppd", { XM, Vex128, EXx, Ib }, 0 },
},
{
/* VEX_W_0F3A42_P_2 */
- { "vmpsadbw", { XM, Vex128, EXx, Ib } },
+ { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
},
{
/* VEX_W_0F3A44_P_2 */
- { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } },
+ { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL }, 0 },
+ },
+ {
+ /* VEX_W_0F3A46_P_2 */
+ { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
},
{
/* VEX_W_0F3A48_P_2 */
- { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
- { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
+ { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
+ { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
},
{
/* VEX_W_0F3A49_P_2 */
- { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
- { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
+ { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
+ { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
},
{
/* VEX_W_0F3A4A_P_2 */
- { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
+ { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 },
},
{
/* VEX_W_0F3A4B_P_2 */
- { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
+ { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 },
},
{
/* VEX_W_0F3A4C_P_2 */
- { "vpblendvb", { XM, Vex128, EXx, XMVexI4 } },
+ { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 },
},
{
/* VEX_W_0F3A60_P_2 */
- { "vpcmpestrm", { XM, EXx, Ib } },
+ { "vpcmpestrm", { XM, EXx, Ib }, 0 },
},
{
/* VEX_W_0F3A61_P_2 */
- { "vpcmpestri", { XM, EXx, Ib } },
+ { "vpcmpestri", { XM, EXx, Ib }, 0 },
},
{
/* VEX_W_0F3A62_P_2 */
- { "vpcmpistrm", { XM, EXx, Ib } },
+ { "vpcmpistrm", { XM, EXx, Ib }, 0 },
},
{
/* VEX_W_0F3A63_P_2 */
- { "vpcmpistri", { XM, EXx, Ib } },
+ { "vpcmpistri", { XM, EXx, Ib }, 0 },
},
{
/* VEX_W_0F3ADF_P_2 */
- { "vaeskeygenassist", { XM, EXx, Ib } },
+ { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
},
+#define NEED_VEX_W_TABLE
+#include "i386-dis-evex.h"
+#undef NEED_VEX_W_TABLE
};
static const struct dis386 mod_table[][2] = {
{
/* MOD_8D */
- { "leaS", { Gv, M } },
+ { "leaS", { Gv, M }, 0 },
+ },
+ {
+ /* MOD_C6_REG_7 */
+ { Bad_Opcode },
+ { RM_TABLE (RM_C6_REG_7) },
+ },
+ {
+ /* MOD_C7_REG_7 */
+ { Bad_Opcode },
+ { RM_TABLE (RM_C7_REG_7) },
+ },
+ {
+ /* MOD_FF_REG_3 */
+ { "Jcall^", { indirEp }, 0 },
+ },
+ {
+ /* MOD_FF_REG_5 */
+ { "Jjmp^", { indirEp }, 0 },
},
{
/* MOD_0F01_REG_0 */
{ X86_64_TABLE (X86_64_0F01_REG_3) },
{ RM_TABLE (RM_0F01_REG_3) },
},
+ {
+ /* MOD_0F01_REG_5 */
+ { Bad_Opcode },
+ { RM_TABLE (RM_0F01_REG_5) },
+ },
{
/* MOD_0F01_REG_7 */
- { "invlpg", { Mb } },
+ { "invlpg", { Mb }, 0 },
{ RM_TABLE (RM_0F01_REG_7) },
},
{
/* MOD_0F12_PREFIX_0 */
- { "movlps", { XM, EXq } },
- { "movhlps", { XM, EXq } },
+ { "movlps", { XM, EXq }, PREFIX_OPCODE },
+ { "movhlps", { XM, EXq }, PREFIX_OPCODE },
},
{
/* MOD_0F13 */
- { "movlpX", { EXq, XM } },
+ { "movlpX", { EXq, XM }, PREFIX_OPCODE },
},
{
/* MOD_0F16_PREFIX_0 */
- { "movhps", { XM, EXq } },
- { "movlhps", { XM, EXq } },
+ { "movhps", { XM, EXq }, 0 },
+ { "movlhps", { XM, EXq }, 0 },
},
{
/* MOD_0F17 */
- { "movhpX", { EXq, XM } },
+ { "movhpX", { EXq, XM }, PREFIX_OPCODE },
},
{
/* MOD_0F18_REG_0 */
- { "prefetchnta", { Mb } },
+ { "prefetchnta", { Mb }, 0 },
},
{
/* MOD_0F18_REG_1 */
- { "prefetcht0", { Mb } },
+ { "prefetcht0", { Mb }, 0 },
},
{
/* MOD_0F18_REG_2 */
- { "prefetcht1", { Mb } },
+ { "prefetcht1", { Mb }, 0 },
},
{
/* MOD_0F18_REG_3 */
- { "prefetcht2", { Mb } },
+ { "prefetcht2", { Mb }, 0 },
},
{
- /* MOD_0F20 */
- { Bad_Opcode },
- { "movZ", { Rm, Cm } },
+ /* MOD_0F18_REG_4 */
+ { "nop/reserved", { Mb }, 0 },
},
{
- /* MOD_0F21 */
- { Bad_Opcode },
- { "movZ", { Rm, Dm } },
+ /* MOD_0F18_REG_5 */
+ { "nop/reserved", { Mb }, 0 },
},
{
- /* MOD_0F22 */
- { Bad_Opcode },
- { "movZ", { Cm, Rm } },
+ /* MOD_0F18_REG_6 */
+ { "nop/reserved", { Mb }, 0 },
},
{
- /* MOD_0F23 */
- { Bad_Opcode },
- { "movZ", { Dm, Rm } },
+ /* MOD_0F18_REG_7 */
+ { "nop/reserved", { Mb }, 0 },
+ },
+ {
+ /* MOD_0F1A_PREFIX_0 */
+ { "bndldx", { Gbnd, Ev_bnd }, 0 },
+ { "nopQ", { Ev }, 0 },
+ },
+ {
+ /* MOD_0F1B_PREFIX_0 */
+ { "bndstx", { Ev_bnd, Gbnd }, 0 },
+ { "nopQ", { Ev }, 0 },
+ },
+ {
+ /* MOD_0F1B_PREFIX_1 */
+ { "bndmk", { Gbnd, Ev_bnd }, 0 },
+ { "nopQ", { Ev }, 0 },
},
{
/* MOD_0F24 */
- { Bad_Opcode },
- { "movL", { Rd, Td } },
+ { Bad_Opcode },
+ { "movL", { Rd, Td }, 0 },
},
{
/* MOD_0F26 */
{ Bad_Opcode },
- { "movL", { Td, Rd } },
+ { "movL", { Td, Rd }, 0 },
},
{
/* MOD_0F2B_PREFIX_0 */
- {"movntps", { Mx, XM } },
+ {"movntps", { Mx, XM }, PREFIX_OPCODE },
},
{
/* MOD_0F2B_PREFIX_1 */
- {"movntss", { Md, XM } },
+ {"movntss", { Md, XM }, PREFIX_OPCODE },
},
{
/* MOD_0F2B_PREFIX_2 */
- {"movntpd", { Mx, XM } },
+ {"movntpd", { Mx, XM }, PREFIX_OPCODE },
},
{
/* MOD_0F2B_PREFIX_3 */
- {"movntsd", { Mq, XM } },
+ {"movntsd", { Mq, XM }, PREFIX_OPCODE },
},
{
/* MOD_0F51 */
{ Bad_Opcode },
- { "movmskpX", { Gdq, XS } },
+ { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
},
{
/* MOD_0F71_REG_2 */
{ Bad_Opcode },
- { "psrlw", { MS, Ib } },
+ { "psrlw", { MS, Ib }, 0 },
},
{
/* MOD_0F71_REG_4 */
{ Bad_Opcode },
- { "psraw", { MS, Ib } },
+ { "psraw", { MS, Ib }, 0 },
},
{
/* MOD_0F71_REG_6 */
{ Bad_Opcode },
- { "psllw", { MS, Ib } },
+ { "psllw", { MS, Ib }, 0 },
},
{
/* MOD_0F72_REG_2 */
{ Bad_Opcode },
- { "psrld", { MS, Ib } },
+ { "psrld", { MS, Ib }, 0 },
},
{
/* MOD_0F72_REG_4 */
{ Bad_Opcode },
- { "psrad", { MS, Ib } },
+ { "psrad", { MS, Ib }, 0 },
},
{
/* MOD_0F72_REG_6 */
{ Bad_Opcode },
- { "pslld", { MS, Ib } },
+ { "pslld", { MS, Ib }, 0 },
},
{
/* MOD_0F73_REG_2 */
{ Bad_Opcode },
- { "psrlq", { MS, Ib } },
+ { "psrlq", { MS, Ib }, 0 },
},
{
/* MOD_0F73_REG_3 */
{
/* MOD_0F73_REG_6 */
{ Bad_Opcode },
- { "psllq", { MS, Ib } },
+ { "psllq", { MS, Ib }, 0 },
},
{
/* MOD_0F73_REG_7 */
},
{
/* MOD_0FAE_REG_0 */
- { "fxsave", { FXSAVE } },
+ { "fxsave", { FXSAVE }, 0 },
{ PREFIX_TABLE (PREFIX_0FAE_REG_0) },
},
{
/* MOD_0FAE_REG_1 */
- { "fxrstor", { FXSAVE } },
+ { "fxrstor", { FXSAVE }, 0 },
{ PREFIX_TABLE (PREFIX_0FAE_REG_1) },
},
{
/* MOD_0FAE_REG_2 */
- { "ldmxcsr", { Md } },
+ { "ldmxcsr", { Md }, 0 },
{ PREFIX_TABLE (PREFIX_0FAE_REG_2) },
},
{
/* MOD_0FAE_REG_3 */
- { "stmxcsr", { Md } },
+ { "stmxcsr", { Md }, 0 },
{ PREFIX_TABLE (PREFIX_0FAE_REG_3) },
},
{
/* MOD_0FAE_REG_4 */
- { "xsave", { FXSAVE } },
+ { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
+ { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
},
{
/* MOD_0FAE_REG_5 */
- { "xrstor", { FXSAVE } },
+ { "xrstor", { FXSAVE }, 0 },
{ RM_TABLE (RM_0FAE_REG_5) },
},
{
/* MOD_0FAE_REG_6 */
- { "xsaveopt", { FXSAVE } },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
{ RM_TABLE (RM_0FAE_REG_6) },
},
{
/* MOD_0FAE_REG_7 */
- { "clflush", { Mb } },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
{ RM_TABLE (RM_0FAE_REG_7) },
},
{
/* MOD_0FB2 */
- { "lssS", { Gv, Mp } },
+ { "lssS", { Gv, Mp }, 0 },
},
{
/* MOD_0FB4 */
- { "lfsS", { Gv, Mp } },
+ { "lfsS", { Gv, Mp }, 0 },
},
{
/* MOD_0FB5 */
- { "lgsS", { Gv, Mp } },
+ { "lgsS", { Gv, Mp }, 0 },
+ },
+ {
+ /* MOD_0FC3 */
+ { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
+ },
+ {
+ /* MOD_0FC7_REG_3 */
+ { "xrstors", { FXSAVE }, 0 },
+ },
+ {
+ /* MOD_0FC7_REG_4 */
+ { "xsavec", { FXSAVE }, 0 },
+ },
+ {
+ /* MOD_0FC7_REG_5 */
+ { "xsaves", { FXSAVE }, 0 },
},
{
/* MOD_0FC7_REG_6 */
- { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
- { "rdrand", { Ev } },
+ { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
+ { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
},
{
/* MOD_0FC7_REG_7 */
- { "vmptrst", { Mq } },
+ { "vmptrst", { Mq }, 0 },
+ { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
},
{
/* MOD_0FD7 */
{ Bad_Opcode },
- { "pmovmskb", { Gdq, MS } },
+ { "pmovmskb", { Gdq, MS }, 0 },
},
{
/* MOD_0FE7_PREFIX_2 */
- { "movntdq", { Mx, XM } },
+ { "movntdq", { Mx, XM }, 0 },
},
{
/* MOD_0FF0_PREFIX_3 */
- { "lddqu", { XM, M } },
+ { "lddqu", { XM, M }, 0 },
},
{
/* MOD_0F382A_PREFIX_2 */
- { "movntdqa", { XM, Mx } },
+ { "movntdqa", { XM, Mx }, 0 },
},
{
/* MOD_62_32BIT */
- { "bound{S|}", { Gv, Ma } },
+ { "bound{S|}", { Gv, Ma }, 0 },
+ { EVEX_TABLE (EVEX_0F) },
},
{
/* MOD_C4_32BIT */
- { "lesS", { Gv, Mp } },
+ { "lesS", { Gv, Mp }, 0 },
{ VEX_C4_TABLE (VEX_0F) },
},
{
/* MOD_C5_32BIT */
- { "ldsS", { Gv, Mp } },
+ { "ldsS", { Gv, Mp }, 0 },
{ VEX_C5_TABLE (VEX_0F) },
},
{
/* MOD_VEX_0F2B */
{ VEX_W_TABLE (VEX_W_0F2B_M_0) },
},
+ {
+ /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kandw", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kandq", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kandb", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kandd", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "knotw", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "knotq", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "knotb", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "knotd", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "korw", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "korq", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "korb", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kord", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kxord", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
+ { Bad_Opcode },
+ { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
+ { Bad_Opcode },
+ { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
+ },
{
/* MOD_VEX_0F50 */
{ Bad_Opcode },
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
},
+ {
+ /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
+ { "kmovw", { Ew, MaskG }, 0 },
+ { Bad_Opcode },
+ },
+ {
+ /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
+ { "kmovq", { Eq, MaskG }, 0 },
+ { Bad_Opcode },
+ },
+ {
+ /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
+ { "kmovb", { Eb, MaskG }, 0 },
+ { Bad_Opcode },
+ },
+ {
+ /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
+ { "kmovd", { Ed, MaskG }, 0 },
+ { Bad_Opcode },
+ },
+ {
+ /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "kmovw", { MaskG, Rdq }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kmovb", { MaskG, Rdq }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
+ { Bad_Opcode },
+ { "kmovd", { MaskG, Rdq }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
+ { Bad_Opcode },
+ { "kmovq", { MaskG, Rdq }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "kmovw", { Gdq, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kmovb", { Gdq, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
+ { Bad_Opcode },
+ { "kmovd", { Gdq, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
+ { Bad_Opcode },
+ { "kmovq", { Gdq, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "kortestw", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "kortestq", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kortestb", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kortestd", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "ktestw", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
+ { Bad_Opcode },
+ { "ktestq", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "ktestb", { MaskG, MaskR }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "ktestd", { MaskG, MaskR }, 0 },
+ },
{
/* MOD_VEX_0FAE_REG_2 */
{ VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
{
/* MOD_VEX_0FD7_PREFIX_2 */
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FD7_P_2_M_1) },
+ { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
},
{
/* MOD_VEX_0FE7_PREFIX_2 */
/* MOD_VEX_0FF0_PREFIX_3 */
{ VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
},
- {
- /* MOD_VEX_0F3818_PREFIX_2 */
- { VEX_W_TABLE (VEX_W_0F3818_P_2_M_0) },
- },
- {
- /* MOD_VEX_0F3819_PREFIX_2 */
- { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2_M_0) },
- },
{
/* MOD_VEX_0F381A_PREFIX_2 */
{ VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
},
{
/* MOD_VEX_0F382A_PREFIX_2 */
- { VEX_LEN_TABLE (VEX_LEN_0F382A_P_2_M_0) },
+ { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
},
{
/* MOD_VEX_0F382C_PREFIX_2 */
/* MOD_VEX_0F382F_PREFIX_2 */
{ VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
},
+ {
+ /* MOD_VEX_0F385A_PREFIX_2 */
+ { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
+ },
+ {
+ /* MOD_VEX_0F388C_PREFIX_2 */
+ { "vpmaskmov%LW", { XM, Vex, Mx }, 0 },
+ },
+ {
+ /* MOD_VEX_0F388E_PREFIX_2 */
+ { "vpmaskmov%LW", { Mx, Vex, XM }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kshiftrb", { MaskG, MaskR, Ib }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kshiftrw", { MaskG, MaskR, Ib }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kshiftrd", { MaskG, MaskR, Ib }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kshiftrq", { MaskG, MaskR, Ib }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kshiftlb", { MaskG, MaskR, Ib }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kshiftlw", { MaskG, MaskR, Ib }, 0 },
+ },
+ {
+ /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kshiftld", { MaskG, MaskR, Ib }, 0 },
+ },
+ {
+ /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
+ { Bad_Opcode },
+ { "kshiftlq", { MaskG, MaskR, Ib }, 0 },
+ },
+#define NEED_MOD_TABLE
+#include "i386-dis-evex.h"
+#undef NEED_MOD_TABLE
};
static const struct dis386 rm_table[][8] = {
+ {
+ /* RM_C6_REG_7 */
+ { "xabort", { Skip_MODRM, Ib }, 0 },
+ },
+ {
+ /* RM_C7_REG_7 */
+ { "xbeginT", { Skip_MODRM, Jv }, 0 },
+ },
{
/* RM_0F01_REG_0 */
{ Bad_Opcode },
- { "vmcall", { Skip_MODRM } },
- { "vmlaunch", { Skip_MODRM } },
- { "vmresume", { Skip_MODRM } },
- { "vmxoff", { Skip_MODRM } },
+ { "vmcall", { Skip_MODRM }, 0 },
+ { "vmlaunch", { Skip_MODRM }, 0 },
+ { "vmresume", { Skip_MODRM }, 0 },
+ { "vmxoff", { Skip_MODRM }, 0 },
},
{
/* RM_0F01_REG_1 */
- { "monitor", { { OP_Monitor, 0 } } },
- { "mwait", { { OP_Mwait, 0 } } },
+ { "monitor", { { OP_Monitor, 0 } }, 0 },
+ { "mwait", { { OP_Mwait, 0 } }, 0 },
+ { "clac", { Skip_MODRM }, 0 },
+ { "stac", { Skip_MODRM }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "encls", { Skip_MODRM }, 0 },
},
{
/* RM_0F01_REG_2 */
- { "xgetbv", { Skip_MODRM } },
- { "xsetbv", { Skip_MODRM } },
+ { "xgetbv", { Skip_MODRM }, 0 },
+ { "xsetbv", { Skip_MODRM }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "vmfunc", { Skip_MODRM }, 0 },
+ { "xend", { Skip_MODRM }, 0 },
+ { "xtest", { Skip_MODRM }, 0 },
+ { "enclu", { Skip_MODRM }, 0 },
},
{
/* RM_0F01_REG_3 */
- { "vmrun", { Skip_MODRM } },
- { "vmmcall", { Skip_MODRM } },
- { "vmload", { Skip_MODRM } },
- { "vmsave", { Skip_MODRM } },
- { "stgi", { Skip_MODRM } },
- { "clgi", { Skip_MODRM } },
- { "skinit", { Skip_MODRM } },
- { "invlpga", { Skip_MODRM } },
+ { "vmrun", { Skip_MODRM }, 0 },
+ { "vmmcall", { Skip_MODRM }, 0 },
+ { "vmload", { Skip_MODRM }, 0 },
+ { "vmsave", { Skip_MODRM }, 0 },
+ { "stgi", { Skip_MODRM }, 0 },
+ { "clgi", { Skip_MODRM }, 0 },
+ { "skinit", { Skip_MODRM }, 0 },
+ { "invlpga", { Skip_MODRM }, 0 },
+ },
+ {
+ /* RM_0F01_REG_5 */
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "rdpkru", { Skip_MODRM }, 0 },
+ { "wrpkru", { Skip_MODRM }, 0 },
},
{
/* RM_0F01_REG_7 */
- { "swapgs", { Skip_MODRM } },
- { "rdtscp", { Skip_MODRM } },
+ { "swapgs", { Skip_MODRM }, 0 },
+ { "rdtscp", { Skip_MODRM }, 0 },
+ { "monitorx", { { OP_Monitor, 0 } }, 0 },
+ { "mwaitx", { { OP_Mwaitx, 0 } }, 0 },
+ { "clzero", { Skip_MODRM }, 0 },
},
{
/* RM_0FAE_REG_5 */
- { "lfence", { Skip_MODRM } },
+ { "lfence", { Skip_MODRM }, 0 },
},
{
/* RM_0FAE_REG_6 */
- { "mfence", { Skip_MODRM } },
+ { "mfence", { Skip_MODRM }, 0 },
},
{
/* RM_0FAE_REG_7 */
- { "sfence", { Skip_MODRM } },
+ { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) },
},
};
/* We use the high bit to indicate different name for the same
prefix. */
-#define ADDR16_PREFIX (0x67 | 0x100)
-#define ADDR32_PREFIX (0x67 | 0x200)
-#define DATA16_PREFIX (0x66 | 0x100)
-#define DATA32_PREFIX (0x66 | 0x200)
#define REP_PREFIX (0xf3 | 0x100)
+#define XACQUIRE_PREFIX (0xf2 | 0x200)
+#define XRELEASE_PREFIX (0xf3 | 0x400)
+#define BND_PREFIX (0xf2 | 0x400)
static int
ckprefix (void)
last_addr_prefix = -1;
last_rex_prefix = -1;
last_seg_prefix = -1;
+ fwait_prefix = -1;
+ active_seg_prefix = 0;
for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
all_prefixes[i] = 0;
i = 0;
case 0x2e:
prefixes |= PREFIX_CS;
last_seg_prefix = i;
+ active_seg_prefix = PREFIX_CS;
break;
case 0x36:
prefixes |= PREFIX_SS;
last_seg_prefix = i;
+ active_seg_prefix = PREFIX_SS;
break;
case 0x3e:
prefixes |= PREFIX_DS;
last_seg_prefix = i;
+ active_seg_prefix = PREFIX_DS;
break;
case 0x26:
prefixes |= PREFIX_ES;
last_seg_prefix = i;
+ active_seg_prefix = PREFIX_ES;
break;
case 0x64:
prefixes |= PREFIX_FS;
last_seg_prefix = i;
+ active_seg_prefix = PREFIX_FS;
break;
case 0x65:
prefixes |= PREFIX_GS;
last_seg_prefix = i;
+ active_seg_prefix = PREFIX_GS;
break;
case 0x66:
prefixes |= PREFIX_DATA;
/* fwait is really an instruction. If there are prefixes
before the fwait, they belong to the fwait, *not* to the
following instruction. */
+ fwait_prefix = i;
if (prefixes || rex)
{
prefixes |= PREFIX_FWAIT;
codep++;
+ /* This ensures that the previous REX prefixes are noticed
+ as unused prefixes, as in the return case below. */
+ rex_used = rex;
return 1;
}
prefixes = PREFIX_FWAIT;
return 0;
}
-static int
-seg_prefix (int pref)
-{
- switch (pref)
- {
- case 0x2e:
- return PREFIX_CS;
- case 0x36:
- return PREFIX_SS;
- case 0x3e:
- return PREFIX_DS;
- case 0x26:
- return PREFIX_ES;
- case 0x64:
- return PREFIX_FS;
- case 0x65:
- return PREFIX_GS;
- default:
- return 0;
- }
-}
-
/* Return the name of the prefix byte PREF, or NULL if PREF is not a
prefix byte. */
return (sizeflag & AFLAG) ? "addr16" : "addr32";
case FWAIT_OPCODE:
return "fwait";
- case ADDR16_PREFIX:
- return "addr16";
- case ADDR32_PREFIX:
- return "addr32";
- case DATA16_PREFIX:
- return "data16";
- case DATA32_PREFIX:
- return "data32";
case REP_PREFIX:
return "rep";
+ case XACQUIRE_PREFIX:
+ return "xacquire";
+ case XRELEASE_PREFIX:
+ return "xrelease";
+ case BND_PREFIX:
+ return "bnd";
default:
return NULL;
}
static char separator_char;
static char scale_char;
+enum x86_64_isa
+{
+ amd64 = 0,
+ intel64
+};
+
+static enum x86_64_isa isa64;
+
/* Here for backwards compatibility. When gdb stops using
print_insn_i386_att and print_insn_i386_intel these functions can
disappear, and print_insn_i386 be merged into print_insn. */
fprintf (stream, _(" data32 Assume 32bit data size\n"));
fprintf (stream, _(" data16 Assume 16bit data size\n"));
fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
+ fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
+ fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
}
/* Bad opcode. */
-static const struct dis386 bad_opcode = { "(bad)", { XX } };
+static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
/* Get a pointer to struct dis386 with a valid name. */
break;
}
}
- else
+ else
{
+ int last_prefix = -1;
+ int prefix = 0;
vindex = 0;
- used_prefixes |= (prefixes & PREFIX_REPZ);
- if (prefixes & PREFIX_REPZ)
- {
- vindex = 1;
- all_prefixes[last_repz_prefix] = 0;
- }
- else
+ /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
+ When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
+ last one wins. */
+ if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
{
- /* We should check PREFIX_REPNZ and PREFIX_REPZ before
- PREFIX_DATA. */
- used_prefixes |= (prefixes & PREFIX_REPNZ);
- if (prefixes & PREFIX_REPNZ)
+ if (last_repz_prefix > last_repnz_prefix)
{
- vindex = 3;
- all_prefixes[last_repnz_prefix] = 0;
+ vindex = 1;
+ prefix = PREFIX_REPZ;
+ last_prefix = last_repz_prefix;
}
else
{
- used_prefixes |= (prefixes & PREFIX_DATA);
- if (prefixes & PREFIX_DATA)
- {
- vindex = 2;
- all_prefixes[last_data_prefix] = 0;
- }
+ vindex = 3;
+ prefix = PREFIX_REPNZ;
+ last_prefix = last_repnz_prefix;
}
+
+ /* Check if prefix should be ignored. */
+ if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
+ & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
+ & prefix) != 0)
+ vindex = 0;
+ }
+
+ if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
+ {
+ vindex = 2;
+ prefix = PREFIX_DATA;
+ last_prefix = last_data_prefix;
+ }
+
+ if (vindex != 0)
+ {
+ used_prefixes |= prefix;
+ all_prefixes[last_prefix] = 0;
}
}
dp = &prefix_table[dp->op[1].bytemode][vindex];
FETCH_DATA (info, codep + 2);
vindex = *codep++;
dp = &three_byte_table[dp->op[1].bytemode][vindex];
+ end_codep = codep;
modrm.mod = (*codep >> 6) & 3;
modrm.reg = (*codep >> 3) & 7;
modrm.rm = *codep & 7;
vindex = *codep++;
dp = &xop_table[vex_table_index][vindex];
+ end_codep = codep;
FETCH_DATA (info, codep + 1);
modrm.mod = (*codep >> 6) & 3;
modrm.reg = (*codep >> 3) & 7;
break;
case USE_VEX_C4_TABLE:
+ /* VEX prefix. */
FETCH_DATA (info, codep + 3);
/* All bits in the REX prefix are ignored. */
rex_ignored = rex;
codep++;
vindex = *codep++;
dp = &vex_table[vex_table_index][vindex];
+ end_codep = codep;
/* There is no MODRM byte for VEX [82|77]. */
if (vindex != 0x77 && vindex != 0x82)
{
break;
case USE_VEX_C5_TABLE:
+ /* VEX prefix. */
FETCH_DATA (info, codep + 2);
/* All bits in the REX prefix are ignored. */
rex_ignored = rex;
codep++;
vindex = *codep++;
dp = &vex_table[dp->op[1].bytemode][vindex];
+ end_codep = codep;
/* There is no MODRM byte for VEX [82|77]. */
if (vindex != 0x77 && vindex != 0x82)
{
dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
break;
+ case USE_EVEX_TABLE:
+ two_source_ops = 0;
+ /* EVEX prefix. */
+ vex.evex = 1;
+ FETCH_DATA (info, codep + 4);
+ /* All bits in the REX prefix are ignored. */
+ rex_ignored = rex;
+ /* The first byte after 0x62. */
+ rex = ~(*codep >> 5) & 0x7;
+ vex.r = *codep & 0x10;
+ switch ((*codep & 0xf))
+ {
+ default:
+ return &bad_opcode;
+ case 0x1:
+ vex_table_index = EVEX_0F;
+ break;
+ case 0x2:
+ vex_table_index = EVEX_0F38;
+ break;
+ case 0x3:
+ vex_table_index = EVEX_0F3A;
+ break;
+ }
+
+ /* The second byte after 0x62. */
+ codep++;
+ vex.w = *codep & 0x80;
+ if (vex.w && address_mode == mode_64bit)
+ rex |= REX_W;
+
+ vex.register_specifier = (~(*codep >> 3)) & 0xf;
+ if (address_mode != mode_64bit)
+ {
+ /* In 16/32-bit mode silently ignore following bits. */
+ rex &= ~REX_B;
+ vex.r = 1;
+ vex.v = 1;
+ vex.register_specifier &= 0x7;
+ }
+
+ /* The U bit. */
+ if (!(*codep & 0x4))
+ return &bad_opcode;
+
+ switch ((*codep & 0x3))
+ {
+ case 0:
+ vex.prefix = 0;
+ break;
+ case 1:
+ vex.prefix = DATA_PREFIX_OPCODE;
+ break;
+ case 2:
+ vex.prefix = REPE_PREFIX_OPCODE;
+ break;
+ case 3:
+ vex.prefix = REPNE_PREFIX_OPCODE;
+ break;
+ }
+
+ /* The third byte after 0x62. */
+ codep++;
+
+ /* Remember the static rounding bits. */
+ vex.ll = (*codep >> 5) & 3;
+ vex.b = (*codep & 0x10) != 0;
+
+ vex.v = *codep & 0x8;
+ vex.mask_register_specifier = *codep & 0x7;
+ vex.zeroing = *codep & 0x80;
+
+ need_vex = 1;
+ need_vex_reg = 1;
+ codep++;
+ vindex = *codep++;
+ dp = &evex_table[vex_table_index][vindex];
+ end_codep = codep;
+ FETCH_DATA (info, codep + 1);
+ modrm.mod = (*codep >> 6) & 3;
+ modrm.reg = (*codep >> 3) & 7;
+ modrm.rm = *codep & 7;
+
+ /* Set vector length. */
+ if (modrm.mod == 3 && vex.b)
+ vex.length = 512;
+ else
+ {
+ switch (vex.ll)
+ {
+ case 0x0:
+ vex.length = 128;
+ break;
+ case 0x1:
+ vex.length = 256;
+ break;
+ case 0x2:
+ vex.length = 512;
+ break;
+ default:
+ return &bad_opcode;
+ }
+ }
+ break;
+
case 0:
dp = &bad_opcode;
break;
}
static void
-get_sib (disassemble_info *info)
+get_sib (disassemble_info *info, int sizeflag)
{
/* If modrm.mod == 3, operand must be register. */
if (need_modrm
- && address_mode != mode_16bit
+ && ((sizeflag & AFLAG) || address_mode == mode_64bit)
&& modrm.mod != 3
&& modrm.rm == 4)
{
int i;
char *op_txt[MAX_OPERANDS];
int needcomma;
- int sizeflag;
+ int sizeflag, orig_sizeflag;
const char *p;
struct dis_private priv;
int prefix_length;
- int default_prefixes;
-
- if (info->mach == bfd_mach_x86_64_intel_syntax
- || info->mach == bfd_mach_x86_64
- || info->mach == bfd_mach_x64_32_intel_syntax
- || info->mach == bfd_mach_x64_32
- || info->mach == bfd_mach_l1om
- || info->mach == bfd_mach_l1om_intel_syntax)
- address_mode = mode_64bit;
- else
- address_mode = mode_32bit;
- if (intel_syntax == (char) -1)
- intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
- || info->mach == bfd_mach_x86_64_intel_syntax
- || info->mach == bfd_mach_x64_32_intel_syntax
- || info->mach == bfd_mach_l1om_intel_syntax);
-
- if (info->mach == bfd_mach_i386_i386
- || info->mach == bfd_mach_x86_64
- || info->mach == bfd_mach_x64_32
- || info->mach == bfd_mach_l1om
- || info->mach == bfd_mach_i386_i386_intel_syntax
- || info->mach == bfd_mach_x86_64_intel_syntax
- || info->mach == bfd_mach_x64_32_intel_syntax
- || info->mach == bfd_mach_l1om_intel_syntax)
- priv.orig_sizeflag = AFLAG | DFLAG;
+ priv.orig_sizeflag = AFLAG | DFLAG;
+ if ((info->mach & bfd_mach_i386_i386) != 0)
+ address_mode = mode_32bit;
else if (info->mach == bfd_mach_i386_i8086)
- priv.orig_sizeflag = 0;
+ {
+ address_mode = mode_16bit;
+ priv.orig_sizeflag = 0;
+ }
else
- abort ();
+ address_mode = mode_64bit;
+
+ if (intel_syntax == (char) -1)
+ intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
for (p = info->disassembler_options; p != NULL; )
{
- if (CONST_STRNEQ (p, "x86-64"))
+ if (CONST_STRNEQ (p, "amd64"))
+ isa64 = amd64;
+ else if (CONST_STRNEQ (p, "intel64"))
+ isa64 = intel64;
+ else if (CONST_STRNEQ (p, "x86-64"))
{
address_mode = mode_64bit;
priv.orig_sizeflag = AFLAG | DFLAG;
p++;
}
+ if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
+ {
+ (*info->fprintf_func) (info->stream,
+ _("64-bit address is disabled"));
+ return -1;
+ }
+
if (intel_syntax)
{
names64 = intel_names64;
names8rex = intel_names8rex;
names_seg = intel_names_seg;
names_mm = intel_names_mm;
+ names_bnd = intel_names_bnd;
names_xmm = intel_names_xmm;
names_ymm = intel_names_ymm;
+ names_zmm = intel_names_zmm;
index64 = intel_index64;
index32 = intel_index32;
+ names_mask = intel_names_mask;
index16 = intel_index16;
open_char = '[';
close_char = ']';
names8rex = att_names8rex;
names_seg = att_names_seg;
names_mm = att_names_mm;
+ names_bnd = att_names_bnd;
names_xmm = att_names_xmm;
names_ymm = att_names_ymm;
+ names_zmm = att_names_zmm;
index64 = att_index64;
index32 = att_index32;
+ names_mask = att_names_mask;
index16 = att_index16;
open_char = '(';
close_char = ')';
/* The output looks better if we put 7 bytes on a line, since that
puts most long word instructions on a single line. Use 8 bytes
for Intel L1OM. */
- if (info->mach == bfd_mach_l1om
- || info->mach == bfd_mach_l1om_intel_syntax)
+ if ((info->mach & bfd_mach_l1om) != 0)
info->bytes_per_line = 8;
else
info->bytes_per_line = 7;
start_codep = priv.the_buffer;
codep = priv.the_buffer;
- if (setjmp (priv.bailout) != 0)
+ if (OPCODES_SIGSETJMP (priv.bailout) != 0)
{
const char *name;
{
/* Too many prefixes or unused REX prefixes. */
for (i = 0;
- all_prefixes[i] && i < (int) ARRAY_SIZE (all_prefixes);
+ i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
i++)
- (*info->fprintf_func) (info->stream, "%s",
+ (*info->fprintf_func) (info->stream, "%s%s",
+ i == 0 ? "" : " ",
prefix_name (all_prefixes[i], sizeflag));
- return 1;
+ return i;
}
insn_codep = codep;
if (((prefixes & PREFIX_FWAIT)
&& ((*codep < 0xd8) || (*codep > 0xdf))))
{
+ /* Handle prefixes before fwait. */
+ for (i = 0; i < fwait_prefix && all_prefixes[i];
+ i++)
+ (*info->fprintf_func) (info->stream, "%s ",
+ prefix_name (all_prefixes[i], sizeflag));
(*info->fprintf_func) (info->stream, "fwait");
- return 1;
+ return i + 1;
}
if (*codep == 0x0f)
{
unsigned char threebyte;
- FETCH_DATA (info, codep + 2);
- threebyte = *++codep;
+
+ codep++;
+ FETCH_DATA (info, codep + 1);
+ threebyte = *codep;
dp = &dis386_twobyte[threebyte];
need_modrm = twobyte_has_modrm[*codep];
codep++;
codep++;
}
- if ((prefixes & PREFIX_REPZ))
- used_prefixes |= PREFIX_REPZ;
- if ((prefixes & PREFIX_REPNZ))
- used_prefixes |= PREFIX_REPNZ;
- if ((prefixes & PREFIX_LOCK))
- used_prefixes |= PREFIX_LOCK;
-
- default_prefixes = 0;
+ /* Save sizeflag for printing the extra prefixes later before updating
+ it for mnemonic and operand processing. The prefix names depend
+ only on the address mode. */
+ orig_sizeflag = sizeflag;
if (prefixes & PREFIX_ADDR)
- {
- sizeflag ^= AFLAG;
- if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
- {
- if ((sizeflag & AFLAG) || address_mode == mode_64bit)
- all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
- else
- all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
- default_prefixes |= PREFIX_ADDR;
- }
- }
-
+ sizeflag ^= AFLAG;
if ((prefixes & PREFIX_DATA))
- {
- sizeflag ^= DFLAG;
- if (dp->op[2].bytemode == cond_jump_mode
- && dp->op[0].bytemode == v_mode
- && !intel_syntax)
- {
- if (sizeflag & DFLAG)
- all_prefixes[last_data_prefix] = DATA32_PREFIX;
- else
- all_prefixes[last_data_prefix] = DATA16_PREFIX;
- default_prefixes |= PREFIX_DATA;
- }
- else if (rex & REX_W)
- {
- /* REX_W will override PREFIX_DATA. */
- default_prefixes |= PREFIX_DATA;
- }
- }
+ sizeflag ^= DFLAG;
+ end_codep = codep;
if (need_modrm)
{
FETCH_DATA (info, codep + 1);
modrm.rm = *codep & 7;
}
- need_vex = 0;
- need_vex_reg = 0;
- vex_w_done = 0;
+ need_vex = 0;
+ need_vex_reg = 0;
+ vex_w_done = 0;
+ vex.evex = 0;
if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
{
- get_sib (info);
+ get_sib (info, sizeflag);
dofloat (sizeflag);
}
else
{
dp = get_valid_dis386 (dp, info);
if (dp != NULL && putop (dp->name, sizeflag) == 0)
- {
- get_sib (info);
+ {
+ get_sib (info, sizeflag);
for (i = 0; i < MAX_OPERANDS; ++i)
{
obufp = op_out[i];
op_ad = MAX_OPERANDS - 1 - i;
if (dp->op[i].rtn)
(*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
+ /* For EVEX instruction after the last operand masking
+ should be printed. */
+ if (i == 0 && vex.evex)
+ {
+ /* Don't print {%k0}. */
+ if (vex.mask_register_specifier)
+ {
+ oappend ("{");
+ oappend (names_mask[vex.mask_register_specifier]);
+ oappend ("}");
+ }
+ if (vex.zeroing)
+ oappend ("{z}");
+ }
}
}
}
- /* See if any prefixes were not used. If so, print the first one
- separately. If we don't do this, we'll wind up printing an
- instruction stream which does not precisely correspond to the
- bytes we are disassembling. */
- if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
- {
- for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
- if (all_prefixes[i])
- {
- const char *name;
- name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
- if (name == NULL)
- name = INTERNAL_DISASSEMBLER_ERROR;
- (*info->fprintf_func) (info->stream, "%s", name);
- return 1;
- }
- }
-
/* Check if the REX prefix is used. */
- if (rex_ignored == 0 && (rex ^ rex_used) == 0)
+ if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
all_prefixes[last_rex_prefix] = 0;
/* Check if the SEG prefix is used. */
if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
| PREFIX_FS | PREFIX_GS)) != 0
- && (used_prefixes
- & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
+ && (used_prefixes & active_seg_prefix) != 0)
all_prefixes[last_seg_prefix] = 0;
/* Check if the ADDR prefix is used. */
&& (used_prefixes & PREFIX_DATA) != 0)
all_prefixes[last_data_prefix] = 0;
+ /* Print the extra prefixes. */
prefix_length = 0;
for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
if (all_prefixes[i])
{
const char *name;
- name = prefix_name (all_prefixes[i], sizeflag);
+ name = prefix_name (all_prefixes[i], orig_sizeflag);
if (name == NULL)
abort ();
prefix_length += strlen (name) + 1;
(*info->fprintf_func) (info->stream, "%s ", name);
}
+ /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
+ unused, opcode is invalid. Since the PREFIX_DATA prefix may be
+ used by putop and MMX/SSE operand and may be overriden by the
+ PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
+ separately. */
+ if (dp->prefix_requirement == PREFIX_OPCODE
+ && dp != &bad_opcode
+ && (((prefixes
+ & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
+ && (used_prefixes
+ & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
+ || ((((prefixes
+ & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
+ == PREFIX_DATA)
+ && (used_prefixes & PREFIX_DATA) == 0))))
+ {
+ (*info->fprintf_func) (info->stream, "(bad)");
+ return end_codep - priv.the_buffer;
+ }
+
/* Check maximum code length. */
if ((codep - start_codep) > MAX_CODE_LENGTH)
{
bfd_vma riprel;
for (i = 0; i < MAX_OPERANDS; ++i)
- op_txt[i] = op_out[i];
+ op_txt[i] = op_out[i];
+
+ if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
+ && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
+ {
+ op_txt[2] = op_out[3];
+ op_txt[3] = op_out[2];
+ }
for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
{
- op_ad = op_index[i];
- op_index[i] = op_index[MAX_OPERANDS - 1 - i];
- op_index[MAX_OPERANDS - 1 - i] = op_ad;
+ op_ad = op_index[i];
+ op_index[i] = op_index[MAX_OPERANDS - 1 - i];
+ op_index[MAX_OPERANDS - 1 - i] = op_ad;
riprel = op_riprel[i];
op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
op_riprel[MAX_OPERANDS - 1 - i] = riprel;
else
{
for (i = 0; i < MAX_OPERANDS; ++i)
- op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
+ op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
}
needcomma = 0;
if (op_index[i] != -1 && op_riprel[i])
{
(*info->fprintf_func) (info->stream, " # ");
- (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
+ (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
+ op_address[op_index[i]]), info);
break;
}
#define ST { OP_ST, 0 }
#define STi { OP_STi, 0 }
-#define FGRPd9_2 NULL, { { NULL, 0 } }
-#define FGRPd9_4 NULL, { { NULL, 1 } }
-#define FGRPd9_5 NULL, { { NULL, 2 } }
-#define FGRPd9_6 NULL, { { NULL, 3 } }
-#define FGRPd9_7 NULL, { { NULL, 4 } }
-#define FGRPda_5 NULL, { { NULL, 5 } }
-#define FGRPdb_4 NULL, { { NULL, 6 } }
-#define FGRPde_3 NULL, { { NULL, 7 } }
-#define FGRPdf_4 NULL, { { NULL, 8 } }
+#define FGRPd9_2 NULL, { { NULL, 0 } }, 0
+#define FGRPd9_4 NULL, { { NULL, 1 } }, 0
+#define FGRPd9_5 NULL, { { NULL, 2 } }, 0
+#define FGRPd9_6 NULL, { { NULL, 3 } }, 0
+#define FGRPd9_7 NULL, { { NULL, 4 } }, 0
+#define FGRPda_5 NULL, { { NULL, 5 } }, 0
+#define FGRPdb_4 NULL, { { NULL, 6 } }, 0
+#define FGRPde_3 NULL, { { NULL, 7 } }, 0
+#define FGRPdf_4 NULL, { { NULL, 8 } }, 0
static const struct dis386 float_reg[][8] = {
/* d8 */
{
- { "fadd", { ST, STi } },
- { "fmul", { ST, STi } },
- { "fcom", { STi } },
- { "fcomp", { STi } },
- { "fsub", { ST, STi } },
- { "fsubr", { ST, STi } },
- { "fdiv", { ST, STi } },
- { "fdivr", { ST, STi } },
+ { "fadd", { ST, STi }, 0 },
+ { "fmul", { ST, STi }, 0 },
+ { "fcom", { STi }, 0 },
+ { "fcomp", { STi }, 0 },
+ { "fsub", { ST, STi }, 0 },
+ { "fsubr", { ST, STi }, 0 },
+ { "fdiv", { ST, STi }, 0 },
+ { "fdivr", { ST, STi }, 0 },
},
/* d9 */
{
- { "fld", { STi } },
- { "fxch", { STi } },
+ { "fld", { STi }, 0 },
+ { "fxch", { STi }, 0 },
{ FGRPd9_2 },
{ Bad_Opcode },
{ FGRPd9_4 },
},
/* da */
{
- { "fcmovb", { ST, STi } },
- { "fcmove", { ST, STi } },
- { "fcmovbe",{ ST, STi } },
- { "fcmovu", { ST, STi } },
+ { "fcmovb", { ST, STi }, 0 },
+ { "fcmove", { ST, STi }, 0 },
+ { "fcmovbe",{ ST, STi }, 0 },
+ { "fcmovu", { ST, STi }, 0 },
{ Bad_Opcode },
{ FGRPda_5 },
{ Bad_Opcode },
},
/* db */
{
- { "fcmovnb",{ ST, STi } },
- { "fcmovne",{ ST, STi } },
- { "fcmovnbe",{ ST, STi } },
- { "fcmovnu",{ ST, STi } },
+ { "fcmovnb",{ ST, STi }, 0 },
+ { "fcmovne",{ ST, STi }, 0 },
+ { "fcmovnbe",{ ST, STi }, 0 },
+ { "fcmovnu",{ ST, STi }, 0 },
{ FGRPdb_4 },
- { "fucomi", { ST, STi } },
- { "fcomi", { ST, STi } },
+ { "fucomi", { ST, STi }, 0 },
+ { "fcomi", { ST, STi }, 0 },
{ Bad_Opcode },
},
/* dc */
{
- { "fadd", { STi, ST } },
- { "fmul", { STi, ST } },
+ { "fadd", { STi, ST }, 0 },
+ { "fmul", { STi, ST }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
- { "fsub!M", { STi, ST } },
- { "fsubM", { STi, ST } },
- { "fdiv!M", { STi, ST } },
- { "fdivM", { STi, ST } },
+ { "fsub!M", { STi, ST }, 0 },
+ { "fsubM", { STi, ST }, 0 },
+ { "fdiv!M", { STi, ST }, 0 },
+ { "fdivM", { STi, ST }, 0 },
},
/* dd */
{
- { "ffree", { STi } },
+ { "ffree", { STi }, 0 },
{ Bad_Opcode },
- { "fst", { STi } },
- { "fstp", { STi } },
- { "fucom", { STi } },
- { "fucomp", { STi } },
+ { "fst", { STi }, 0 },
+ { "fstp", { STi }, 0 },
+ { "fucom", { STi }, 0 },
+ { "fucomp", { STi }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
},
/* de */
{
- { "faddp", { STi, ST } },
- { "fmulp", { STi, ST } },
+ { "faddp", { STi, ST }, 0 },
+ { "fmulp", { STi, ST }, 0 },
{ Bad_Opcode },
{ FGRPde_3 },
- { "fsub!Mp", { STi, ST } },
- { "fsubMp", { STi, ST } },
- { "fdiv!Mp", { STi, ST } },
- { "fdivMp", { STi, ST } },
+ { "fsub!Mp", { STi, ST }, 0 },
+ { "fsubMp", { STi, ST }, 0 },
+ { "fdiv!Mp", { STi, ST }, 0 },
+ { "fdivMp", { STi, ST }, 0 },
},
/* df */
{
- { "ffreep", { STi } },
+ { "ffreep", { STi }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ FGRPdf_4 },
- { "fucomip", { ST, STi } },
- { "fcomip", { ST, STi } },
+ { "fucomip", { ST, STi }, 0 },
+ { "fcomip", { ST, STi }, 0 },
{ Bad_Opcode },
},
};
}
}
+/* Like oappend (below), but S is a string starting with '%'.
+ In Intel syntax, the '%' is elided. */
+static void
+oappend_maybe_intel (const char *s)
+{
+ oappend (s + intel_syntax);
+}
+
static void
OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
{
- oappend ("%st" + intel_syntax);
+ oappend_maybe_intel ("%st");
}
static void
OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
{
sprintf (scratchbuf, "%%st(%d)", modrm.rm);
- oappend (scratchbuf + intel_syntax);
+ oappend_maybe_intel (scratchbuf);
}
/* Capital letters in template are macros. */
cond = 0;
break;
case '{':
- alt = 0;
if (intel_syntax)
{
while (*++p != '|')
*obufp++ = 'd';
break;
case 'Z':
+ if (l != 0 || len != 1)
+ {
+ if (l != 1 || len != 2 || last[0] != 'X')
+ {
+ SAVE_LAST (*p);
+ break;
+ }
+ if (!need_vex || !vex.evex)
+ abort ();
+ if (intel_syntax
+ || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
+ break;
+ switch (vex.length)
+ {
+ case 128:
+ *obufp++ = 'x';
+ break;
+ case 256:
+ *obufp++ = 'y';
+ break;
+ case 512:
+ *obufp++ = 'z';
+ break;
+ default:
+ abort ();
+ }
+ break;
+ }
if (intel_syntax)
break;
if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
if (!(rex & REX_W))
used_prefixes |= (prefixes & PREFIX_DATA);
break;
+ case '&':
+ if (!intel_syntax
+ && address_mode == mode_64bit
+ && isa64 == intel64)
+ {
+ *obufp++ = 'q';
+ break;
+ }
+ /* Fall through. */
case 'T':
if (!intel_syntax
&& address_mode == mode_64bit
- && (sizeflag & DFLAG))
+ && ((sizeflag & DFLAG) || (rex & REX_W)))
{
*obufp++ = 'q';
break;
}
/* Fall through. */
+ goto case_P;
case 'P':
- if (intel_syntax)
+ if (l == 0 && len == 1)
{
- if ((rex & REX_W) == 0
- && (prefixes & PREFIX_DATA))
+case_P:
+ if (intel_syntax)
{
- if ((sizeflag & DFLAG) == 0)
- *obufp++ = 'w';
- used_prefixes |= (prefixes & PREFIX_DATA);
+ if ((rex & REX_W) == 0
+ && (prefixes & PREFIX_DATA))
+ {
+ if ((sizeflag & DFLAG) == 0)
+ *obufp++ = 'w';
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ break;
+ }
+ if ((prefixes & PREFIX_DATA)
+ || (rex & REX_W)
+ || (sizeflag & SUFFIX_ALWAYS))
+ {
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ *obufp++ = 'q';
+ else
+ {
+ if (sizeflag & DFLAG)
+ *obufp++ = 'l';
+ else
+ *obufp++ = 'w';
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
}
- break;
}
- if ((prefixes & PREFIX_DATA)
- || (rex & REX_W)
- || (sizeflag & SUFFIX_ALWAYS))
+ else
{
- USED_REX (REX_W);
- if (rex & REX_W)
- *obufp++ = 'q';
- else
+ if (l != 1 || len != 2 || last[0] != 'L')
+ {
+ SAVE_LAST (*p);
+ break;
+ }
+
+ if ((prefixes & PREFIX_DATA)
+ || (rex & REX_W)
+ || (sizeflag & SUFFIX_ALWAYS))
{
- if (sizeflag & DFLAG)
- *obufp++ = 'l';
- else
- *obufp++ = 'w';
- used_prefixes |= (prefixes & PREFIX_DATA);
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ *obufp++ = 'q';
+ else
+ {
+ if (sizeflag & DFLAG)
+ *obufp++ = intel_syntax ? 'd' : 'l';
+ else
+ *obufp++ = 'w';
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
}
}
break;
case 'U':
if (intel_syntax)
break;
- if (address_mode == mode_64bit && (sizeflag & DFLAG))
+ if (address_mode == mode_64bit
+ && ((sizeflag & DFLAG) || (rex & REX_W)))
{
if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
*obufp++ = 'q';
{
if (intel_syntax)
break;
- if (address_mode == mode_64bit && (sizeflag & DFLAG))
+ if (address_mode == mode_64bit
+ && ((sizeflag & DFLAG) || (rex & REX_W)))
{
if (sizeflag & SUFFIX_ALWAYS)
*obufp++ = 'q';
if (!need_vex)
abort ();
if (intel_syntax
- || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
+ || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
break;
switch (vex.length)
{
case 256:
*obufp++ = 'y';
break;
+ case 512:
+ if (!vex.evex)
default:
- abort ();
+ abort ();
}
}
break;
}
else
{
- if (l != 1 || len != 2 || last[0] != 'X')
+ if (l != 1
+ || len != 2
+ || (last[0] != 'X'
+ && last[0] != 'L'))
{
SAVE_LAST (*p);
break;
}
if (!need_vex)
abort ();
- *obufp++ = vex.w ? 'd': 's';
+ if (last[0] == 'X')
+ *obufp++ = vex.w ? 'd': 's';
+ else
+ *obufp++ = vex.w ? 'q': 'd';
+ }
+ break;
+ case '^':
+ if (intel_syntax)
+ break;
+ if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
+ {
+ if (sizeflag & DFLAG)
+ *obufp++ = 'l';
+ else
+ *obufp++ = 'w';
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ }
+ break;
+ case '@':
+ if (intel_syntax)
+ break;
+ if (address_mode == mode_64bit
+ && (isa64 == intel64
+ || ((sizeflag & DFLAG) || (rex & REX_W))))
+ *obufp++ = 'q';
+ else if ((prefixes & PREFIX_DATA))
+ {
+ if (!(sizeflag & DFLAG))
+ *obufp++ = 'w';
+ used_prefixes |= (prefixes & PREFIX_DATA);
}
break;
}
static void
append_seg (void)
{
- if (prefixes & PREFIX_CS)
- {
- used_prefixes |= PREFIX_CS;
- oappend ("%cs:" + intel_syntax);
- }
- if (prefixes & PREFIX_DS)
- {
- used_prefixes |= PREFIX_DS;
- oappend ("%ds:" + intel_syntax);
- }
- if (prefixes & PREFIX_SS)
- {
- used_prefixes |= PREFIX_SS;
- oappend ("%ss:" + intel_syntax);
- }
- if (prefixes & PREFIX_ES)
- {
- used_prefixes |= PREFIX_ES;
- oappend ("%es:" + intel_syntax);
- }
- if (prefixes & PREFIX_FS)
- {
- used_prefixes |= PREFIX_FS;
- oappend ("%fs:" + intel_syntax);
- }
- if (prefixes & PREFIX_GS)
+ /* Only print the active segment register. */
+ if (!active_seg_prefix)
+ return;
+
+ used_prefixes |= active_seg_prefix;
+ switch (active_seg_prefix)
{
- used_prefixes |= PREFIX_GS;
- oappend ("%gs:" + intel_syntax);
+ case PREFIX_CS:
+ oappend_maybe_intel ("%cs:");
+ break;
+ case PREFIX_DS:
+ oappend_maybe_intel ("%ds:");
+ break;
+ case PREFIX_SS:
+ oappend_maybe_intel ("%ss:");
+ break;
+ case PREFIX_ES:
+ oappend_maybe_intel ("%es:");
+ break;
+ case PREFIX_FS:
+ oappend_maybe_intel ("%fs:");
+ break;
+ case PREFIX_GS:
+ oappend_maybe_intel ("%gs:");
+ break;
+ default:
+ break;
}
}
static void
intel_operand_size (int bytemode, int sizeflag)
{
+ if (vex.evex
+ && vex.b
+ && (bytemode == x_mode
+ || bytemode == evex_half_bcst_xmmq_mode))
+ {
+ if (vex.w)
+ oappend ("QWORD PTR ");
+ else
+ oappend ("DWORD PTR ");
+ return;
+ }
switch (bytemode)
{
case b_mode:
case b_swap_mode:
case dqb_mode:
+ case db_mode:
oappend ("BYTE PTR ");
break;
case w_mode:
+ case dw_mode:
case dqw_mode:
+ case dqw_swap_mode:
oappend ("WORD PTR ");
break;
+ case indir_v_mode:
+ if (address_mode == mode_64bit && isa64 == intel64)
+ {
+ oappend ("QWORD PTR ");
+ break;
+ }
+ /* Fall through. */
case stack_v_mode:
- if (address_mode == mode_64bit && (sizeflag & DFLAG))
+ if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
{
oappend ("QWORD PTR ");
break;
}
- /* FALLTHRU */
+ /* Fall through. */
case v_mode:
case v_swap_mode:
case dq_mode:
break;
case x_mode:
case x_swap_mode:
+ case evex_x_gscat_mode:
+ case evex_x_nobcst_mode:
if (need_vex)
{
switch (vex.length)
case 256:
oappend ("YMMWORD PTR ");
break;
+ case 512:
+ oappend ("ZMMWORD PTR ");
+ break;
default:
abort ();
}
case xmm_mode:
oappend ("XMMWORD PTR ");
break;
+ case ymm_mode:
+ oappend ("YMMWORD PTR ");
+ break;
case xmmq_mode:
+ case evex_half_bcst_xmmq_mode:
+ if (!need_vex)
+ abort ();
+
+ switch (vex.length)
+ {
+ case 128:
+ oappend ("QWORD PTR ");
+ break;
+ case 256:
+ oappend ("XMMWORD PTR ");
+ break;
+ case 512:
+ oappend ("YMMWORD PTR ");
+ break;
+ default:
+ abort ();
+ }
+ break;
+ case xmm_mb_mode:
+ if (!need_vex)
+ abort ();
+
+ switch (vex.length)
+ {
+ case 128:
+ case 256:
+ case 512:
+ oappend ("BYTE PTR ");
+ break;
+ default:
+ abort ();
+ }
+ break;
+ case xmm_mw_mode:
+ if (!need_vex)
+ abort ();
+
+ switch (vex.length)
+ {
+ case 128:
+ case 256:
+ case 512:
+ oappend ("WORD PTR ");
+ break;
+ default:
+ abort ();
+ }
+ break;
+ case xmm_md_mode:
+ if (!need_vex)
+ abort ();
+
+ switch (vex.length)
+ {
+ case 128:
+ case 256:
+ case 512:
+ oappend ("DWORD PTR ");
+ break;
+ default:
+ abort ();
+ }
+ break;
+ case xmm_mq_mode:
+ if (!need_vex)
+ abort ();
+
+ switch (vex.length)
+ {
+ case 128:
+ case 256:
+ case 512:
+ oappend ("QWORD PTR ");
+ break;
+ default:
+ abort ();
+ }
+ break;
+ case xmmdw_mode:
if (!need_vex)
abort ();
switch (vex.length)
{
case 128:
+ oappend ("WORD PTR ");
+ break;
+ case 256:
+ oappend ("DWORD PTR ");
+ break;
+ case 512:
oappend ("QWORD PTR ");
break;
+ default:
+ abort ();
+ }
+ break;
+ case xmmqd_mode:
+ if (!need_vex)
+ abort ();
+
+ switch (vex.length)
+ {
+ case 128:
+ oappend ("DWORD PTR ");
+ break;
case 256:
+ oappend ("QWORD PTR ");
+ break;
+ case 512:
oappend ("XMMWORD PTR ");
break;
default:
case 256:
oappend ("YMMWORD PTR ");
break;
+ case 512:
+ oappend ("ZMMWORD PTR ");
+ break;
+ default:
+ abort ();
+ }
+ break;
+ case ymmxmm_mode:
+ if (!need_vex)
+ abort ();
+
+ switch (vex.length)
+ {
+ case 128:
+ case 256:
+ oappend ("XMMWORD PTR ");
+ break;
default:
abort ();
}
case o_mode:
oappend ("OWORD PTR ");
break;
+ case xmm_mdq_mode:
case vex_w_dq_mode:
case vex_scalar_w_dq_mode:
if (!need_vex)
else
oappend ("DWORD PTR ");
break;
+ case vex_vsib_d_w_dq_mode:
+ case vex_vsib_q_w_dq_mode:
+ if (!need_vex)
+ abort ();
+
+ if (!vex.evex)
+ {
+ if (vex.w)
+ oappend ("QWORD PTR ");
+ else
+ oappend ("DWORD PTR ");
+ }
+ else
+ {
+ switch (vex.length)
+ {
+ case 128:
+ oappend ("XMMWORD PTR ");
+ break;
+ case 256:
+ oappend ("YMMWORD PTR ");
+ break;
+ case 512:
+ oappend ("ZMMWORD PTR ");
+ break;
+ default:
+ abort ();
+ }
+ }
+ break;
+ case vex_vsib_q_w_d_mode:
+ case vex_vsib_d_w_d_mode:
+ if (!need_vex || !vex.evex)
+ abort ();
+
+ switch (vex.length)
+ {
+ case 128:
+ oappend ("QWORD PTR ");
+ break;
+ case 256:
+ oappend ("XMMWORD PTR ");
+ break;
+ case 512:
+ oappend ("YMMWORD PTR ");
+ break;
+ default:
+ abort ();
+ }
+
+ break;
+ case mask_bd_mode:
+ if (!need_vex || vex.length != 128)
+ abort ();
+ if (vex.w)
+ oappend ("DWORD PTR ");
+ else
+ oappend ("BYTE PTR ");
+ break;
+ case mask_mode:
+ if (!need_vex)
+ abort ();
+ if (vex.w)
+ oappend ("QWORD PTR ");
+ else
+ oappend ("WORD PTR ");
+ break;
+ case v_bnd_mode:
default:
break;
}
reg += 8;
if ((sizeflag & SUFFIX_ALWAYS)
- && (bytemode == b_swap_mode || bytemode == v_swap_mode))
+ && (bytemode == b_swap_mode
+ || bytemode == v_swap_mode
+ || bytemode == dqw_swap_mode))
swap_operand ();
switch (bytemode)
names = names16;
break;
case d_mode:
+ case dw_mode:
+ case db_mode:
names = names32;
break;
case q_mode:
names = names64;
break;
case m_mode:
+ case v_bnd_mode:
names = address_mode == mode_64bit ? names64 : names32;
break;
+ case bnd_mode:
+ names = names_bnd;
+ break;
+ case indir_v_mode:
+ if (address_mode == mode_64bit && isa64 == intel64)
+ {
+ names = names64;
+ break;
+ }
+ /* Fall through. */
case stack_v_mode:
- if (address_mode == mode_64bit && (sizeflag & DFLAG))
+ if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
{
names = names64;
break;
}
bytemode = v_mode;
- /* FALLTHRU */
+ /* Fall through. */
case v_mode:
case v_swap_mode:
case dq_mode:
case dqb_mode:
case dqd_mode:
case dqw_mode:
+ case dqw_swap_mode:
USED_REX (REX_W);
if (rex & REX_W)
names = names64;
else
{
- if ((sizeflag & DFLAG)
+ if ((sizeflag & DFLAG)
|| (bytemode != v_mode
&& bytemode != v_swap_mode))
names = names32;
used_prefixes |= (prefixes & PREFIX_DATA);
}
break;
+ case mask_bd_mode:
+ case mask_mode:
+ names = names_mask;
+ break;
case 0:
return;
default:
bfd_vma disp = 0;
int add = (rex & REX_B) ? 8 : 0;
int riprel = 0;
+ int shift;
+
+ if (vex.evex)
+ {
+ /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
+ if (vex.b
+ && bytemode != x_mode
+ && bytemode != xmmq_mode
+ && bytemode != evex_half_bcst_xmmq_mode)
+ {
+ BadOp ();
+ return;
+ }
+ switch (bytemode)
+ {
+ case dqw_mode:
+ case dw_mode:
+ case dqw_swap_mode:
+ shift = 1;
+ break;
+ case dqb_mode:
+ case db_mode:
+ shift = 0;
+ break;
+ case vex_vsib_d_w_dq_mode:
+ case vex_vsib_d_w_d_mode:
+ case vex_vsib_q_w_dq_mode:
+ case vex_vsib_q_w_d_mode:
+ case evex_x_gscat_mode:
+ case xmm_mdq_mode:
+ shift = vex.w ? 3 : 2;
+ break;
+ case x_mode:
+ case evex_half_bcst_xmmq_mode:
+ case xmmq_mode:
+ if (vex.b)
+ {
+ shift = vex.w ? 3 : 2;
+ break;
+ }
+ /* Fall through. */
+ case xmmqd_mode:
+ case xmmdw_mode:
+ case ymmq_mode:
+ case evex_x_nobcst_mode:
+ case x_swap_mode:
+ switch (vex.length)
+ {
+ case 128:
+ shift = 4;
+ break;
+ case 256:
+ shift = 5;
+ break;
+ case 512:
+ shift = 6;
+ break;
+ default:
+ abort ();
+ }
+ break;
+ case ymm_mode:
+ shift = 5;
+ break;
+ case xmm_mode:
+ shift = 4;
+ break;
+ case xmm_mq_mode:
+ case q_mode:
+ case q_scalar_mode:
+ case q_swap_mode:
+ case q_scalar_swap_mode:
+ shift = 3;
+ break;
+ case dqd_mode:
+ case xmm_md_mode:
+ case d_mode:
+ case d_scalar_mode:
+ case d_swap_mode:
+ case d_scalar_swap_mode:
+ shift = 2;
+ break;
+ case xmm_mw_mode:
+ shift = 1;
+ break;
+ case xmm_mb_mode:
+ shift = 0;
+ break;
+ default:
+ abort ();
+ }
+ /* Make necessary corrections to shift for modes that need it.
+ For these modes we currently have shift 4, 5 or 6 depending on
+ vex.length (it corresponds to xmmword, ymmword or zmmword
+ operand). We might want to make it 3, 4 or 5 (e.g. for
+ xmmq_mode). In case of broadcast enabled the corrections
+ aren't needed, as element size is always 32 or 64 bits. */
+ if (!vex.b
+ && (bytemode == xmmq_mode
+ || bytemode == evex_half_bcst_xmmq_mode))
+ shift -= 1;
+ else if (bytemode == xmmqd_mode)
+ shift -= 2;
+ else if (bytemode == xmmdw_mode)
+ shift -= 3;
+ else if (bytemode == ymmq_mode && vex.length == 128)
+ shift -= 1;
+ }
+ else
+ shift = 0;
USED_REX (REX_B);
if (intel_syntax)
int base, rbase;
int vindex = 0;
int scale = 0;
+ int addr32flag = !((sizeflag & AFLAG)
+ || bytemode == v_bnd_mode
+ || bytemode == bnd_mode);
+ const char **indexes64 = names64;
+ const char **indexes32 = names32;
havesib = 0;
havebase = 1;
{
havesib = 1;
vindex = sib.index;
+ USED_REX (REX_X);
+ if (rex & REX_X)
+ vindex += 8;
+ switch (bytemode)
+ {
+ case vex_vsib_d_w_dq_mode:
+ case vex_vsib_d_w_d_mode:
+ case vex_vsib_q_w_dq_mode:
+ case vex_vsib_q_w_d_mode:
+ if (!need_vex)
+ abort ();
+ if (vex.evex)
+ {
+ if (!vex.v)
+ vindex += 16;
+ }
+
+ haveindex = 1;
+ switch (vex.length)
+ {
+ case 128:
+ indexes64 = indexes32 = names_xmm;
+ break;
+ case 256:
+ if (!vex.w
+ || bytemode == vex_vsib_q_w_dq_mode
+ || bytemode == vex_vsib_q_w_d_mode)
+ indexes64 = indexes32 = names_ymm;
+ else
+ indexes64 = indexes32 = names_xmm;
+ break;
+ case 512:
+ if (!vex.w
+ || bytemode == vex_vsib_q_w_dq_mode
+ || bytemode == vex_vsib_q_w_d_mode)
+ indexes64 = indexes32 = names_zmm;
+ else
+ indexes64 = indexes32 = names_ymm;
+ break;
+ default:
+ abort ();
+ }
+ break;
+ default:
+ haveindex = vindex != 4;
+ break;
+ }
scale = sib.scale;
base = sib.base;
- USED_REX (REX_X);
- if (rex & REX_X)
- vindex += 8;
- haveindex = vindex != 4;
codep++;
}
rbase = base + add;
disp = *codep++;
if ((disp & 0x80) != 0)
disp -= 0x100;
+ if (vex.evex && shift > 0)
+ disp <<= shift;
break;
case 2:
disp = get32s ();
}
}
- if (havebase || haveindex || riprel)
+ if ((havebase || haveindex || riprel)
+ && (bytemode != v_bnd_mode)
+ && (bytemode != bnd_mode))
used_prefixes |= PREFIX_ADDR;
if (havedisp || (intel_syntax && riprel))
}
*obufp = '\0';
if (havebase)
- oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
+ oappend (address_mode == mode_64bit && !addr32flag
? names64[rbase] : names32[rbase]);
if (havesib)
{
*obufp = '\0';
}
if (haveindex)
- oappend (address_mode == mode_64bit
- && (sizeflag & AFLAG)
- ? names64[vindex] : names32[vindex]);
+ oappend (address_mode == mode_64bit && !addr32flag
+ ? indexes64[vindex] : indexes32[vindex]);
else
- oappend (address_mode == mode_64bit
- && (sizeflag & AFLAG)
+ oappend (address_mode == mode_64bit && !addr32flag
? index64 : index32);
*obufp++ = scale_char;
{
if (modrm.mod != 0 || base == 5)
{
- if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
- | PREFIX_ES | PREFIX_FS | PREFIX_GS))
- ;
- else
+ if (!active_seg_prefix)
{
oappend (names_seg[ds_reg - es_reg]);
oappend (":");
}
else if (intel_syntax)
{
- if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
- | PREFIX_ES | PREFIX_FS | PREFIX_GS))
- ;
- else
+ if (!active_seg_prefix)
{
oappend (names_seg[ds_reg - es_reg]);
oappend (":");
oappend (scratchbuf);
}
}
+ if (vex.evex && vex.b
+ && (bytemode == x_mode
+ || bytemode == xmmq_mode
+ || bytemode == evex_half_bcst_xmmq_mode))
+ {
+ if (vex.w
+ || bytemode == xmmq_mode
+ || bytemode == evex_half_bcst_xmmq_mode)
+ {
+ switch (vex.length)
+ {
+ case 128:
+ oappend ("{1to2}");
+ break;
+ case 256:
+ oappend ("{1to4}");
+ break;
+ case 512:
+ oappend ("{1to8}");
+ break;
+ default:
+ abort ();
+ }
+ }
+ else
+ {
+ switch (vex.length)
+ {
+ case 128:
+ oappend ("{1to4}");
+ break;
+ case 256:
+ oappend ("{1to8}");
+ break;
+ case 512:
+ oappend ("{1to16}");
+ break;
+ default:
+ abort ();
+ }
+ }
+ }
}
static void
oappend (names16[modrm.reg + add]);
break;
case d_mode:
+ case db_mode:
+ case dw_mode:
oappend (names32[modrm.reg + add]);
break;
case q_mode:
oappend (names64[modrm.reg + add]);
break;
+ case bnd_mode:
+ oappend (names_bnd[modrm.reg]);
+ break;
case v_mode:
case dq_mode:
case dqb_mode:
case dqd_mode:
case dqw_mode:
+ case dqw_swap_mode:
USED_REX (REX_W);
if (rex & REX_W)
oappend (names64[modrm.reg + add]);
else
oappend (names32[modrm.reg + add]);
break;
+ case mask_bd_mode:
+ case mask_mode:
+ oappend (names_mask[modrm.reg + add]);
+ break;
default:
oappend (INTERNAL_DISASSEMBLER_ERROR);
break;
a = *codep++ & 0xff;
a |= (*codep++ & 0xff) << 8;
a |= (*codep++ & 0xff) << 16;
- a |= (*codep++ & 0xff) << 24;
+ a |= (*codep++ & 0xffu) << 24;
b = *codep++ & 0xff;
b |= (*codep++ & 0xff) << 8;
b |= (*codep++ & 0xff) << 16;
- b |= (*codep++ & 0xff) << 24;
+ b |= (*codep++ & 0xffu) << 24;
x = a + ((bfd_vma) b << 32);
#else
abort ();
{
const char *s;
int add;
+
+ switch (code)
+ {
+ case es_reg: case ss_reg: case cs_reg:
+ case ds_reg: case fs_reg: case gs_reg:
+ oappend (names_seg[code - es_reg]);
+ return;
+ }
+
USED_REX (REX_B);
if (rex & REX_B)
add = 8;
case sp_reg: case bp_reg: case si_reg: case di_reg:
s = names16[code - ax_reg + add];
break;
- case es_reg: case ss_reg: case cs_reg:
- case ds_reg: case fs_reg: case gs_reg:
- s = names_seg[code - es_reg + add];
- break;
case al_reg: case ah_reg: case cl_reg: case ch_reg:
case dl_reg: case dh_reg: case bl_reg: case bh_reg:
USED_REX (0);
break;
case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
- if (address_mode == mode_64bit && (sizeflag & DFLAG))
+ if (address_mode == mode_64bit
+ && ((sizeflag & DFLAG) || (rex & REX_W)))
{
s = names64[code - rAX_reg + add];
break;
break;
case const_1_mode:
if (intel_syntax)
- oappend ("1");
+ oappend ("1");
return;
default:
oappend (INTERNAL_DISASSEMBLER_ERROR);
op &= mask;
scratchbuf[0] = '$';
print_operand_value (scratchbuf + 1, 1, op);
- oappend (scratchbuf + intel_syntax);
+ oappend_maybe_intel (scratchbuf);
scratchbuf[0] = '\0';
}
op &= mask;
scratchbuf[0] = '$';
print_operand_value (scratchbuf + 1, 1, op);
- oappend (scratchbuf + intel_syntax);
+ oappend_maybe_intel (scratchbuf);
scratchbuf[0] = '\0';
}
switch (bytemode)
{
case b_mode:
+ case b_T_mode:
FETCH_DATA (the_info, codep + 1);
op = *codep++;
if ((op & 0x80) != 0)
op -= 0x100;
+ if (bytemode == b_T_mode)
+ {
+ if (address_mode != mode_64bit
+ || !((sizeflag & DFLAG) || (rex & REX_W)))
+ {
+ /* The operand-size prefix is overridden by a REX prefix. */
+ if ((sizeflag & DFLAG) || (rex & REX_W))
+ op &= 0xffffffff;
+ else
+ op &= 0xffff;
+ }
+ }
+ else
+ {
+ if (!(rex & REX_W))
+ {
+ if (sizeflag & DFLAG)
+ op &= 0xffffffff;
+ else
+ op &= 0xffff;
+ }
+ }
break;
case v_mode:
- if (sizeflag & DFLAG)
+ /* The operand-size prefix is overridden by a REX prefix. */
+ if ((sizeflag & DFLAG) || (rex & REX_W))
op = get32s ();
else
op = get16 ();
scratchbuf[0] = '$';
print_operand_value (scratchbuf + 1, 1, op);
- oappend (scratchbuf + intel_syntax);
+ oappend_maybe_intel (scratchbuf);
}
static void
disp -= 0x100;
break;
case v_mode:
- USED_REX (REX_W);
- if ((sizeflag & DFLAG) || (rex & REX_W))
+ if (isa64 == amd64)
+ USED_REX (REX_W);
+ if ((sizeflag & DFLAG)
+ || (address_mode == mode_64bit
+ && (isa64 != amd64 || (rex & REX_W))))
disp = get32s ();
else
{
the displacement is added! */
mask = 0xffff;
if ((prefixes & PREFIX_DATA) == 0)
- segment = ((start_pc + codep - start_codep)
+ segment = ((start_pc + (codep - start_codep))
& ~((bfd_vma) 0xffff));
}
- if (!(rex & REX_W))
+ if (address_mode != mode_64bit
+ || (isa64 == amd64 && !(rex & REX_W)))
used_prefixes |= (prefixes & PREFIX_DATA);
break;
default:
oappend (INTERNAL_DISASSEMBLER_ERROR);
return;
}
- disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
+ disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
set_op (disp, 0);
print_operand_value (scratchbuf, 1, disp);
oappend (scratchbuf);
if (intel_syntax)
{
- if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
- | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
+ if (!active_seg_prefix)
{
oappend (names_seg[ds_reg - es_reg]);
oappend (":");
if (intel_syntax)
{
- if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
- | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
+ if (!active_seg_prefix)
{
oappend (names_seg[ds_reg - es_reg]);
oappend (":");
intel_operand_size (b_mode, sizeflag);
}
}
- oappend ("%es:" + intel_syntax);
+ oappend_maybe_intel ("%es:");
ptr_reg (code, sizeflag);
}
intel_operand_size (b_mode, sizeflag);
}
}
- if ((prefixes
- & (PREFIX_CS
- | PREFIX_DS
- | PREFIX_SS
- | PREFIX_ES
- | PREFIX_FS
- | PREFIX_GS)) == 0)
- prefixes |= PREFIX_DS;
+ /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
+ default segment register DS is printed. */
+ if (!active_seg_prefix)
+ active_seg_prefix = PREFIX_DS;
append_seg ();
ptr_reg (code, sizeflag);
}
else
add = 0;
sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
- oappend (scratchbuf + intel_syntax);
+ oappend_maybe_intel (scratchbuf);
}
static void
OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
{
sprintf (scratchbuf, "%%tr%d", modrm.reg);
- oappend (scratchbuf + intel_syntax);
+ oappend_maybe_intel (scratchbuf);
}
static void
OP_R (int bytemode, int sizeflag)
{
- if (modrm.mod == 3)
- OP_E (bytemode, sizeflag);
- else
- BadOp ();
+ /* Skip mod/rm byte. */
+ MODRM_CHECK;
+ codep++;
+ OP_E_register (bytemode, sizeflag);
}
static void
USED_REX (REX_R);
if (rex & REX_R)
reg += 8;
+ if (vex.evex)
+ {
+ if (!vex.r)
+ reg += 16;
+ }
+
if (need_vex
&& bytemode != xmm_mode
+ && bytemode != xmmq_mode
+ && bytemode != evex_half_bcst_xmmq_mode
+ && bytemode != ymm_mode
&& bytemode != scalar_mode)
{
switch (vex.length)
names = names_xmm;
break;
case 256:
+ if (vex.w
+ || (bytemode != vex_vsib_q_w_dq_mode
+ && bytemode != vex_vsib_q_w_d_mode))
+ names = names_ymm;
+ else
+ names = names_xmm;
+ break;
+ case 512:
+ names = names_zmm;
+ break;
+ default:
+ abort ();
+ }
+ }
+ else if (bytemode == xmmq_mode
+ || bytemode == evex_half_bcst_xmmq_mode)
+ {
+ switch (vex.length)
+ {
+ case 128:
+ case 256:
+ names = names_xmm;
+ break;
+ case 512:
names = names_ymm;
break;
default:
abort ();
}
}
+ else if (bytemode == ymm_mode)
+ names = names_ymm;
else
names = names_xmm;
oappend (names[reg]);
{
bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
used_prefixes |= (prefixes & PREFIX_DATA);
- }
+ }
OP_E (bytemode, sizeflag);
return;
}
{
bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
used_prefixes |= (prefixes & PREFIX_DATA);
- }
+ }
OP_E (bytemode, sizeflag);
return;
}
USED_REX (REX_B);
if (rex & REX_B)
reg += 8;
+ if (vex.evex)
+ {
+ USED_REX (REX_X);
+ if ((rex & REX_X))
+ reg += 16;
+ }
if ((sizeflag & SUFFIX_ALWAYS)
&& (bytemode == x_swap_mode
|| bytemode == d_swap_mode
- || bytemode == d_scalar_swap_mode
+ || bytemode == dqw_swap_mode
+ || bytemode == d_scalar_swap_mode
|| bytemode == q_swap_mode
|| bytemode == q_scalar_swap_mode))
swap_operand ();
if (need_vex
&& bytemode != xmm_mode
+ && bytemode != xmmdw_mode
+ && bytemode != xmmqd_mode
+ && bytemode != xmm_mb_mode
+ && bytemode != xmm_mw_mode
+ && bytemode != xmm_md_mode
+ && bytemode != xmm_mq_mode
+ && bytemode != xmm_mdq_mode
&& bytemode != xmmq_mode
+ && bytemode != evex_half_bcst_xmmq_mode
+ && bytemode != ymm_mode
&& bytemode != d_scalar_mode
- && bytemode != d_scalar_swap_mode
+ && bytemode != d_scalar_swap_mode
&& bytemode != q_scalar_mode
&& bytemode != q_scalar_swap_mode
&& bytemode != vex_scalar_w_dq_mode)
case 256:
names = names_ymm;
break;
+ case 512:
+ names = names_zmm;
+ break;
+ default:
+ abort ();
+ }
+ }
+ else if (bytemode == xmmq_mode
+ || bytemode == evex_half_bcst_xmmq_mode)
+ {
+ switch (vex.length)
+ {
+ case 128:
+ case 256:
+ names = names_xmm;
+ break;
+ case 512:
+ names = names_ymm;
+ break;
default:
abort ();
}
}
+ else if (bytemode == ymm_mode)
+ names = names_ymm;
else
names = names_xmm;
oappend (names[reg]);
/* We have a reserved extension byte. Output it directly. */
scratchbuf[0] = '$';
print_operand_value (scratchbuf + 1, 1, cmp_type);
- oappend (scratchbuf + intel_syntax);
+ oappend_maybe_intel (scratchbuf);
scratchbuf[0] = '\0';
}
}
+static void
+OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
+ int sizeflag ATTRIBUTE_UNUSED)
+{
+ /* mwaitx %eax,%ecx,%ebx */
+ if (!intel_syntax)
+ {
+ const char **names = (address_mode == mode_64bit
+ ? names64 : names32);
+ strcpy (op_out[0], names[0]);
+ strcpy (op_out[1], names[1]);
+ strcpy (op_out[2], names[3]);
+ two_source_ops = 1;
+ }
+ /* Skip mod/rm byte. */
+ MODRM_CHECK;
+ codep++;
+}
+
static void
OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
int sizeflag ATTRIBUTE_UNUSED)
}
}
+/* For BND-prefixed instructions 0xF2 prefix should be displayed as
+ "bnd". */
+
+static void
+BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
+{
+ if (prefixes & PREFIX_REPNZ)
+ all_prefixes[last_repnz_prefix] = BND_PREFIX;
+}
+
+/* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
+ "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
+ */
+
+static void
+HLE_Fixup1 (int bytemode, int sizeflag)
+{
+ if (modrm.mod != 3
+ && (prefixes & PREFIX_LOCK) != 0)
+ {
+ if (prefixes & PREFIX_REPZ)
+ all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
+ if (prefixes & PREFIX_REPNZ)
+ all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
+ }
+
+ OP_E (bytemode, sizeflag);
+}
+
+/* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
+ "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
+ */
+
+static void
+HLE_Fixup2 (int bytemode, int sizeflag)
+{
+ if (modrm.mod != 3)
+ {
+ if (prefixes & PREFIX_REPZ)
+ all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
+ if (prefixes & PREFIX_REPNZ)
+ all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
+ }
+
+ OP_E (bytemode, sizeflag);
+}
+
+/* Similar to OP_E. But the 0xf3 prefixes should be displayed as
+ "xrelease" for memory operand. No check for LOCK prefix. */
+
+static void
+HLE_Fixup3 (int bytemode, int sizeflag)
+{
+ if (modrm.mod != 3
+ && last_repz_prefix > last_repnz_prefix
+ && (prefixes & PREFIX_REPZ) != 0)
+ all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
+
+ OP_E (bytemode, sizeflag);
+}
+
static void
CMPXCHG8B_Fixup (int bytemode, int sizeflag)
{
mnemonicendp = stpcpy (p, "16b");
bytemode = o_mode;
}
+ else if ((prefixes & PREFIX_LOCK) != 0)
+ {
+ if (prefixes & PREFIX_REPZ)
+ all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
+ if (prefixes & PREFIX_REPNZ)
+ all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
+ }
+
OP_M (bytemode, sizeflag);
}
USED_REX (REX_W);
if (rex & REX_W)
*p++ = 'q';
- else
+ else
{
if (sizeflag & DFLAG)
*p++ = 'l';
return;
reg = vex.register_specifier;
+ if (vex.evex)
+ {
+ if (!vex.v)
+ reg += 16;
+ }
+
if (bytemode == vex_scalar_mode)
{
oappend (names_xmm[reg]);
{
case vex_mode:
case vex128_mode:
+ case vex_vsib_q_w_dq_mode:
+ case vex_vsib_q_w_d_mode:
names = names_xmm;
break;
case dq_mode:
else
names = names32;
break;
+ case mask_bd_mode:
+ case mask_mode:
+ names = names_mask;
+ break;
default:
abort ();
return;
{
case vex_mode:
case vex256_mode:
+ names = names_ymm;
+ break;
+ case vex_vsib_q_w_dq_mode:
+ case vex_vsib_q_w_d_mode:
+ names = vex.w ? names_ymm : names_xmm;
+ break;
+ case mask_bd_mode:
+ case mask_mode:
+ names = names_mask;
break;
default:
abort ();
return;
}
-
- names = names_ymm;
+ break;
+ case 512:
+ names = names_zmm;
break;
default:
abort ();
{
/* There are SIB/displacement bytes. */
if ((sizeflag & AFLAG) || address_mode == mode_64bit)
- {
+ {
/* 32/64 bit address mode */
- int base = modrm.rm;
+ int base = modrm.rm;
/* Check SIB byte. */
- if (base == 4)
- {
- FETCH_DATA (the_info, codep + 1);
- base = *codep & 7;
- /* When decoding the third source, don't increase
- bytes_before_imm as this has already been incremented
- by one in OP_E_memory while decoding the second
- source operand. */
- if (opnum == 0)
- bytes_before_imm++;
- }
-
- /* Don't increase bytes_before_imm when decoding the third source,
- it has already been incremented by OP_E_memory while decoding
- the second source operand. */
- if (opnum == 0)
- {
- switch (modrm.mod)
- {
- case 0:
- /* When modrm.rm == 5 or modrm.rm == 4 and base in
- SIB == 5, there is a 4 byte displacement. */
- if (base != 5)
- /* No displacement. */
- break;
- case 2:
- /* 4 byte displacement. */
- bytes_before_imm += 4;
- break;
- case 1:
- /* 1 byte displacement. */
- bytes_before_imm++;
- break;
- }
- }
- }
+ if (base == 4)
+ {
+ FETCH_DATA (the_info, codep + 1);
+ base = *codep & 7;
+ /* When decoding the third source, don't increase
+ bytes_before_imm as this has already been incremented
+ by one in OP_E_memory while decoding the second
+ source operand. */
+ if (opnum == 0)
+ bytes_before_imm++;
+ }
+
+ /* Don't increase bytes_before_imm when decoding the third source,
+ it has already been incremented by OP_E_memory while decoding
+ the second source operand. */
+ if (opnum == 0)
+ {
+ switch (modrm.mod)
+ {
+ case 0:
+ /* When modrm.rm == 5 or modrm.rm == 4 and base in
+ SIB == 5, there is a 4 byte displacement. */
+ if (base != 5)
+ /* No displacement. */
+ break;
+ /* Fall through. */
+ case 2:
+ /* 4 byte displacement. */
+ bytes_before_imm += 4;
+ break;
+ case 1:
+ /* 1 byte displacement. */
+ bytes_before_imm++;
+ break;
+ }
+ }
+ }
else
{
/* 16 bit address mode */
- /* Don't increase bytes_before_imm when decoding the third source,
- it has already been incremented by OP_E_memory while decoding
- the second source operand. */
- if (opnum == 0)
- {
+ /* Don't increase bytes_before_imm when decoding the third source,
+ it has already been incremented by OP_E_memory while decoding
+ the second source operand. */
+ if (opnum == 0)
+ {
switch (modrm.mod)
{
case 0:
if (modrm.rm != 6)
/* No displacement. */
break;
+ /* Fall through. */
case 2:
/* 2 byte displacement. */
bytes_before_imm += 2;
/* Output the imm8 directly. */
scratchbuf[0] = '$';
print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
- oappend (scratchbuf + intel_syntax);
+ oappend_maybe_intel (scratchbuf);
scratchbuf[0] = '\0';
codep++;
}
/* We have a reserved extension byte. Output it directly. */
scratchbuf[0] = '$';
print_operand_value (scratchbuf + 1, 1, cmp_type);
- oappend (scratchbuf + intel_syntax);
+ oappend_maybe_intel (scratchbuf);
+ scratchbuf[0] = '\0';
+ }
+}
+
+static void
+VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
+ int sizeflag ATTRIBUTE_UNUSED)
+{
+ unsigned int cmp_type;
+
+ if (!vex.evex)
+ abort ();
+
+ FETCH_DATA (the_info, codep + 1);
+ cmp_type = *codep++ & 0xff;
+ /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
+ If it's the case, print suffix, otherwise - print the immediate. */
+ if (cmp_type < ARRAY_SIZE (simd_cmp_op)
+ && cmp_type != 3
+ && cmp_type != 7)
+ {
+ char suffix [3];
+ char *p = mnemonicendp - 2;
+
+ /* vpcmp* can have both one- and two-lettered suffix. */
+ if (p[0] == 'p')
+ {
+ p++;
+ suffix[0] = p[0];
+ suffix[1] = '\0';
+ }
+ else
+ {
+ suffix[0] = p[0];
+ suffix[1] = p[1];
+ suffix[2] = '\0';
+ }
+
+ sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
+ mnemonicendp += simd_cmp_op[cmp_type].len;
+ }
+ else
+ {
+ /* We have a reserved extension byte. Output it directly. */
+ scratchbuf[0] = '$';
+ print_operand_value (scratchbuf + 1, 1, cmp_type);
+ oappend_maybe_intel (scratchbuf);
scratchbuf[0] = '\0';
}
}
break;
default:
break;
- }
+ }
if (pclmul_type < ARRAY_SIZE (pclmul_op))
{
char suffix [4];
/* We have a reserved extension byte. Output it directly. */
scratchbuf[0] = '$';
print_operand_value (scratchbuf + 1, 1, pclmul_type);
- oappend (scratchbuf + intel_syntax);
+ oappend_maybe_intel (scratchbuf);
scratchbuf[0] = '\0';
}
}
oappend (names[vex.register_specifier]);
}
+static void
+OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
+{
+ if (!vex.evex
+ || (bytemode != mask_mode && bytemode != mask_bd_mode))
+ abort ();
+
+ USED_REX (REX_R);
+ if ((rex & REX_R) != 0 || !vex.r)
+ {
+ BadOp ();
+ return;
+ }
+
+ oappend (names_mask [modrm.reg]);
+}
+
+static void
+OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
+{
+ if (!vex.evex
+ || (bytemode != evex_rounding_mode
+ && bytemode != evex_sae_mode))
+ abort ();
+ if (modrm.mod == 3 && vex.b)
+ switch (bytemode)
+ {
+ case evex_rounding_mode:
+ oappend (names_rounding[vex.ll]);
+ break;
+ case evex_sae_mode:
+ oappend ("{sae}");
+ break;
+ default:
+ break;
+ }
+}
projects / deliverable / binutils-gdb.git / blobdiff