x86: Rename VecSIB to SIB for Intel AMX

[deliverable/binutils-gdb.git] / opcodes / i386-opc.h

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index fc69d4d0fb689c6c490a06044774a72935a56957..174438698e02f3043c17bbdbbbf8b1f7a56cec53 100644 (file)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -243,10 +243,16 @@ enum
   CpuMOVDIR64B,
   /* ENQCMD instruction required */
   CpuENQCMD,
+  /* SERIALIZE instruction required */
+  CpuSERIALIZE,
   /* RDPRU instruction required */
   CpuRDPRU,
   /* MCOMMIT instruction required */
   CpuMCOMMIT,
+  /* SEV-ES instruction(s) required */
+  CpuSEV_ES,
+  /* TSXLDTRK instruction required */
+  CpuTSXLDTRK,
   /* 64bit support required  */
   Cpu64,
   /* Not supported in the 64bit mode  */
@@ -376,8 +382,11 @@ typedef union i386_cpu_flags
       unsigned int cpumovdiri:1;
       unsigned int cpumovdir64b:1;
       unsigned int cpuenqcmd:1;
+      unsigned int cpuserialize:1;
       unsigned int cpurdpru:1;
       unsigned int cpumcommit:1;
+      unsigned int cpusev_es:1;
+      unsigned int cputsxldtrk:1;
       unsigned int cpu64:1;
       unsigned int cpuno64:1;
 #ifdef CpuUnused
@@ -427,9 +436,10 @@ enum
   CheckRegSize,
   /* instruction ignores operand size prefix and in Intel mode ignores
      mnemonic size suffix check.  */
-  IgnoreSize,
+#define IGNORESIZE     1
   /* default insn size depends on mode */
-  DefaultSize,
+#define DEFAULTSIZE    2
+  MnemonicSize,
   /* any memory size */
   Anysize,
   /* b suffix on instruction illegal */
@@ -492,8 +502,6 @@ enum
   ImmExt,
   /* instruction don't need Rex64 prefix.  */
   NoRex64,
-  /* instruction require Rex64 prefix.  */
-  Rex64,
   /* deprecated fp insn, gets a warning */
   Ugh,
   /* insn has VEX prefix:
@@ -558,15 +566,15 @@ enum
 #define XOP2SOURCES    1
 #define VEX3SOURCES    2
   VexSources,
-  /* Instruction with vector SIB byte:
+  /* Instruction with a mandatory SIB byte:
        1: 128bit vector register.
        2: 256bit vector register.
        3: 512bit vector register.
    */
-#define VecSIB128      1
-#define VecSIB256      2
-#define VecSIB512      3
-  VecSIB,
+#define VECSIB128      1
+#define VECSIB256      2
+#define VECSIB512      3
+  SIB,
   /* SSE to AVX support required */
   SSE2AVX,
   /* No AVX equivalent */
@@ -661,8 +669,7 @@ typedef struct i386_opcode_modifier
   unsigned int floatr:1;
   unsigned int size:2;
   unsigned int checkregsize:1;
-  unsigned int ignoresize:1;
-  unsigned int defaultsize:1;
+  unsigned int mnemonicsize:2;
   unsigned int anysize:1;
   unsigned int no_bsuf:1;
   unsigned int no_wsuf:1;
@@ -686,14 +693,13 @@ typedef struct i386_opcode_modifier
   unsigned int isprefix:1;
   unsigned int immext:1;
   unsigned int norex64:1;
-  unsigned int rex64:1;
   unsigned int ugh:1;
   unsigned int vex:2;
   unsigned int vexvvvv:2;
   unsigned int vexw:2;
   unsigned int vexopcode:3;
   unsigned int vexsources:2;
-  unsigned int vecsib:2;
+  unsigned int sib:2;
   unsigned int sse2avx:1;
   unsigned int noavx:1;
   unsigned int evex:3;
@@ -900,7 +906,7 @@ extern const insn_template i386_optab[];
 /* these are for register name --> number & type hash lookup */
 typedef struct
 {
-  char *reg_name;
+  const char *reg_name;
   i386_operand_type reg_type;
   unsigned char reg_flags;
 #define RegRex     0x1  /* Extended register.  */