/* Declarations for Intel 80386 opcode table
- Copyright (C) 2007-2018 Free Software Foundation, Inc.
+ Copyright (C) 2007-2020 Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
Cpu586,
/* i686 or better required */
Cpu686,
+ /* CMOV Instruction support required */
+ CpuCMOV,
+ /* FXSR Instruction support required */
+ CpuFXSR,
/* CLFLUSH Instruction support required */
CpuClflush,
/* NOP Instruction support required */
CpuSSSE3,
/* SSE4a support required */
CpuSSE4a,
- /* ABM New Instructions required */
- CpuABM,
+ /* LZCNT support required */
+ CpuLZCNT,
+ /* POPCNT support required */
+ CpuPOPCNT,
/* SSE4.1 support required */
CpuSSE4_1,
/* SSE4.2 support required */
CpuF16C,
/* Intel BMI2 support required */
CpuBMI2,
- /* LZCNT support required */
- CpuLZCNT,
/* HLE support required */
CpuHLE,
/* RTM support required */
CpuSMAP,
/* SHA instructions required. */
CpuSHA,
- /* VREX support required */
- CpuVREX,
/* CLFLUSHOPT instruction required */
CpuClflushOpt,
/* XSAVES/XRSTORS instruction required */
CpuAVX512_VNNI,
/* Intel AVX-512 BITALG Instructions support required. */
CpuAVX512_BITALG,
+ /* Intel AVX-512 BF16 Instructions support required. */
+ CpuAVX512_BF16,
+ /* Intel AVX-512 VP2INTERSECT Instructions support required. */
+ CpuAVX512_VP2INTERSECT,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
CpuWBNOINVD,
/* PCONFIG instructions required */
CpuPCONFIG,
- /* MMX register support required */
- CpuRegMMX,
- /* XMM register support required */
- CpuRegXMM,
- /* YMM register support required */
- CpuRegYMM,
- /* ZMM register support required */
- CpuRegZMM,
- /* Mask register support required */
- CpuRegMask,
+ /* WAITPKG instructions required */
+ CpuWAITPKG,
+ /* CLDEMOTE instruction required */
+ CpuCLDEMOTE,
+ /* MOVDIRI instruction support required */
+ CpuMOVDIRI,
+ /* MOVDIRR64B instruction required */
+ CpuMOVDIR64B,
+ /* ENQCMD instruction required */
+ CpuENQCMD,
+ /* SERIALIZE instruction required */
+ CpuSERIALIZE,
+ /* RDPRU instruction required */
+ CpuRDPRU,
+ /* MCOMMIT instruction required */
+ CpuMCOMMIT,
+ /* SEV-ES instruction(s) required */
+ CpuSEV_ES,
+ /* TSXLDTRK instruction required */
+ CpuTSXLDTRK,
/* 64bit support required */
Cpu64,
/* Not supported in the 64bit mode */
unsigned int cpui486:1;
unsigned int cpui586:1;
unsigned int cpui686:1;
+ unsigned int cpucmov:1;
+ unsigned int cpufxsr:1;
unsigned int cpuclflush:1;
unsigned int cpunop:1;
unsigned int cpusyscall:1;
unsigned int cpusmx:1;
unsigned int cpussse3:1;
unsigned int cpusse4a:1;
- unsigned int cpuabm:1;
+ unsigned int cpulzcnt:1;
+ unsigned int cpupopcnt:1;
unsigned int cpusse4_1:1;
unsigned int cpusse4_2:1;
unsigned int cpuavx:1;
unsigned int cpurdrnd:1;
unsigned int cpuf16c:1;
unsigned int cpubmi2:1;
- unsigned int cpulzcnt:1;
unsigned int cpuhle:1;
unsigned int cpurtm:1;
unsigned int cpuinvpcid:1;
unsigned int cpuprfchw:1;
unsigned int cpusmap:1;
unsigned int cpusha:1;
- unsigned int cpuvrex:1;
unsigned int cpuclflushopt:1;
unsigned int cpuxsaves:1;
unsigned int cpuxsavec:1;
unsigned int cpuavx512_vbmi2:1;
unsigned int cpuavx512_vnni:1;
unsigned int cpuavx512_bitalg:1;
+ unsigned int cpuavx512_bf16:1;
+ unsigned int cpuavx512_vp2intersect:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
unsigned int cpuvpclmulqdq:1;
unsigned int cpuwbnoinvd:1;
unsigned int cpupconfig:1;
- unsigned int cpuregmmx:1;
- unsigned int cpuregxmm:1;
- unsigned int cpuregymm:1;
- unsigned int cpuregzmm:1;
- unsigned int cpuregmask:1;
+ unsigned int cpuwaitpkg:1;
+ unsigned int cpucldemote:1;
+ unsigned int cpumovdiri:1;
+ unsigned int cpumovdir64b:1;
+ unsigned int cpuenqcmd:1;
+ unsigned int cpuserialize:1;
+ unsigned int cpurdpru:1;
+ unsigned int cpumcommit:1;
+ unsigned int cpusev_es:1;
+ unsigned int cputsxldtrk:1;
unsigned int cpu64:1;
unsigned int cpuno64:1;
#ifdef CpuUnused
{
/* has direction bit. */
D = 0,
- /* set if operands can be words or dwords encoded the canonical way */
+ /* set if operands can be both bytes and words/dwords/qwords, encoded the
+ canonical way; the base_opcode field should hold the encoding for byte
+ operands */
W,
/* load form instruction. Must be placed before store form. */
Load,
/* insn has a modrm byte. */
Modrm,
- /* register is in low 3 bits of opcode */
- ShortForm,
- /* special case for jump insns. */
- Jump,
+ /* special case for jump insns; value has to be 1 */
+#define JUMP 1
/* call and jump */
- JumpDword,
+#define JUMP_DWORD 2
/* loop and jecxz */
- JumpByte,
+#define JUMP_BYTE 3
/* special case for intersegment leaps/calls */
- JumpInterSegment,
+#define JUMP_INTERSEGMENT 4
+ /* absolute address for jump */
+#define JUMP_ABSOLUTE 5
+ Jump,
/* FP insn memory format bit, sized by 0x4 */
FloatMF,
/* src/dest swap for floats. */
FloatR,
/* needs size prefix if in 32-bit mode */
- Size16,
+#define SIZE16 1
/* needs size prefix if in 16-bit mode */
- Size32,
+#define SIZE32 2
/* needs size prefix if in 64-bit mode */
- Size64,
+#define SIZE64 3
+ Size,
/* check register size. */
CheckRegSize,
/* instruction ignores operand size prefix and in Intel mode ignores
mnemonic size suffix check. */
- IgnoreSize,
+#define IGNORESIZE 1
/* default insn size depends on mode */
- DefaultSize,
+#define DEFAULTSIZE 2
+ MnemonicSize,
+ /* any memory size */
+ Anysize,
/* b suffix on instruction illegal */
No_bSuf,
/* w suffix on instruction illegal */
No_ldSuf,
/* instruction needs FWAIT */
FWait,
- /* quick test for string instructions */
+ /* IsString provides for a quick test for string instructions, and
+ its actual value also indicates which of the operands (if any)
+ requires use of the %es segment. */
+#define IS_STRING_ES_OP0 2
+#define IS_STRING_ES_OP1 3
IsString,
+ /* RegMem is for instructions with a modrm byte where the register
+ destination operand should be encoded in the mod and regmem fields.
+ Normally, it will be encoded in the reg field. We add a RegMem
+ flag to indicate that it should be encoded in the regmem field. */
+ RegMem,
/* quick test if branch instruction is MPX supported */
BNDPrefixOk,
/* quick test if NOTRACK prefix is supported */
ToDword,
/* Convert to QWORD */
ToQword,
- /* Address prefix changes operand 0 */
- AddrPrefixOp0,
+ /* Address prefix changes register operand */
+ AddrPrefixOpReg,
/* opcode is a prefix */
IsPrefix,
/* instruction has extension in 8 bit imm */
ImmExt,
/* instruction don't need Rex64 prefix. */
NoRex64,
- /* instruction require Rex64 prefix. */
- Rex64,
/* deprecated fp insn, gets a warning */
Ugh,
/* insn has VEX prefix:
0: Set by the REX.W bit.
1: VEX.W0. Should always be 0.
2: VEX.W1. Should always be 1.
+ 3: VEX.WIG. The VEX.W bit is ignored.
*/
#define VEXW0 1
#define VEXW1 2
+#define VEXWIG 3
VexW,
/* VEX opcode prefix:
0: VEX 0x0F opcode prefix.
#define XOP2SOURCES 1
#define VEX3SOURCES 2
VexSources,
- /* instruction has VEX 8 bit imm */
- VexImmExt,
/* Instruction with vector SIB byte:
1: 128bit vector register.
2: 256bit vector register.
EVex,
/* AVX512 masking support:
- 1: Zeroing-masking.
+ 1: Zeroing or merging masking depending on operands.
2: Merging-masking.
3: Both zeroing and merging masking.
*/
-#define ZEROING_MASKING 1
+#define DYNAMIC_MASKING 1
#define MERGING_MASKING 2
#define BOTH_MASKING 3
Masking,
+ /* AVX512 broadcast support. The number of bytes to broadcast is
+ 1 << (Broadcast - 1):
+ 1: Byte broadcast.
+ 2: Word broadcast.
+ 3: Dword broadcast.
+ 4: Qword broadcast.
+ */
+#define BYTE_BROADCAST 1
+#define WORD_BROADCAST 2
+#define DWORD_BROADCAST 3
+#define QWORD_BROADCAST 4
Broadcast,
/* Static rounding control is supported. */
/* Supress All Exceptions is supported. */
SAE,
- /* Copressed Disp8*N attribute. */
+ /* Compressed Disp8*N attribute. */
+#define DISP8_SHIFT_VL 7
Disp8MemShift,
/* Default mask isn't allowed. */
ATTSyntax,
/* Intel syntax. */
IntelSyntax,
- /* AMD64. */
- AMD64,
- /* Intel64. */
- Intel64,
+ /* ISA64: Don't change the order without other code adjustments.
+ 0: Common to AMD64 and Intel64.
+ 1: AMD64.
+ 2: Intel64.
+ 3: Only in Intel64.
+ */
+#define AMD64 1
+#define INTEL64 2
+#define INTEL64ONLY 3
+ ISA64,
/* The last bitfield in i386_opcode_modifier. */
- Opcode_Modifier_Max
+ Opcode_Modifier_Num
};
typedef struct i386_opcode_modifier
unsigned int w:1;
unsigned int load:1;
unsigned int modrm:1;
- unsigned int shortform:1;
- unsigned int jump:1;
- unsigned int jumpdword:1;
- unsigned int jumpbyte:1;
- unsigned int jumpintersegment:1;
+ unsigned int jump:3;
unsigned int floatmf:1;
unsigned int floatr:1;
- unsigned int size16:1;
- unsigned int size32:1;
- unsigned int size64:1;
+ unsigned int size:2;
unsigned int checkregsize:1;
- unsigned int ignoresize:1;
- unsigned int defaultsize:1;
+ unsigned int mnemonicsize:2;
+ unsigned int anysize:1;
unsigned int no_bsuf:1;
unsigned int no_wsuf:1;
unsigned int no_lsuf:1;
unsigned int no_qsuf:1;
unsigned int no_ldsuf:1;
unsigned int fwait:1;
- unsigned int isstring:1;
+ unsigned int isstring:2;
+ unsigned int regmem:1;
unsigned int bndprefixok:1;
unsigned int notrackprefixok:1;
unsigned int islockable:1;
unsigned int repprefixok:1;
unsigned int todword:1;
unsigned int toqword:1;
- unsigned int addrprefixop0:1;
+ unsigned int addrprefixopreg:1;
unsigned int isprefix:1;
unsigned int immext:1;
unsigned int norex64:1;
- unsigned int rex64:1;
unsigned int ugh:1;
unsigned int vex:2;
unsigned int vexvvvv:2;
unsigned int vexw:2;
unsigned int vexopcode:3;
unsigned int vexsources:2;
- unsigned int veximmext:1;
unsigned int vecsib:2;
unsigned int sse2avx:1;
unsigned int noavx:1;
unsigned int evex:3;
unsigned int masking:2;
- unsigned int broadcast:1;
+ unsigned int broadcast:3;
unsigned int staticrounding:1;
unsigned int sae:1;
unsigned int disp8memshift:3;
unsigned int attmnemonic:1;
unsigned int attsyntax:1;
unsigned int intelsyntax:1;
- unsigned int amd64:1;
- unsigned int intel64:1;
+ unsigned int isa64:2;
} i386_opcode_modifier;
+/* Operand classes. */
+
+#define CLASS_WIDTH 4
+enum operand_class
+{
+ ClassNone,
+ Reg, /* GPRs and FP regs, distinguished by operand size */
+ SReg, /* Segment register */
+ RegCR, /* Control register */
+ RegDR, /* Debug register */
+ RegTR, /* Test register */
+ RegMMX, /* MMX register */
+ RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
+ RegMask, /* Vector Mask register */
+ RegBND, /* Bound register */
+};
+
+/* Special operand instances. */
+
+#define INSTANCE_WIDTH 3
+enum operand_instance
+{
+ InstanceNone,
+ Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
+ RegC, /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */
+ RegD, /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */
+ RegB, /* %bl / %bx / %ebx / %rbx */
+};
+
/* Position of operand_type bits. */
enum
{
- /* Register (qualified by Byte, Word, etc) */
- Reg = 0,
- /* MMX register */
- RegMMX,
- /* Vector registers */
- RegSIMD,
- /* Vector Mask registers */
- RegMask,
- /* Control register */
- Control,
- /* Debug register */
- Debug,
- /* Test register */
- Test,
- /* 2 bit segment register */
- SReg2,
- /* 3 bit segment register */
- SReg3,
+ /* Class and Instance */
+ ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1,
/* 1 bit immediate */
Imm1,
/* 8 bit immediate */
Disp32S,
/* 64 bit displacement */
Disp64,
- /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
- Acc,
/* Register which can be used for base or index in memory operand. */
BaseIndex,
- /* Register to hold in/out port addr = dx */
- InOutPortReg,
- /* Register to hold shift count = cl */
- ShiftCount,
- /* Absolute address for jump. */
- JumpAbsolute,
- /* String insn operand with fixed es segment */
- EsSeg,
- /* RegMem is for instructions with a modrm byte where the register
- destination operand should be encoded in the mod and regmem fields.
- Normally, it will be encoded in the reg field. We add a RegMem
- flag to the destination register operand to indicate that it should
- be encoded in the regmem field. */
- RegMem,
- /* Memory. */
- Mem,
- /* BYTE memory. */
+ /* BYTE size. */
Byte,
- /* WORD memory. 2 byte */
+ /* WORD size. 2 byte */
Word,
- /* DWORD memory. 4 byte */
+ /* DWORD size. 4 byte */
Dword,
- /* FWORD memory. 6 byte */
+ /* FWORD size. 6 byte */
Fword,
- /* QWORD memory. 8 byte */
+ /* QWORD size. 8 byte */
Qword,
- /* TBYTE memory. 10 byte */
+ /* TBYTE size. 10 byte */
Tbyte,
- /* XMMWORD memory. */
+ /* XMMWORD size. */
Xmmword,
- /* YMMWORD memory. */
+ /* YMMWORD size. */
Ymmword,
- /* ZMMWORD memory. */
+ /* ZMMWORD size. */
Zmmword,
/* Unspecified memory size. */
Unspecified,
- /* Any memory size. */
- Anysize,
-
- /* Vector 4 bit immediate. */
- Vec_Imm4,
-
- /* Bound register. */
- RegBND,
- /* The last bitfield in i386_operand_type. */
- OTMax
+ /* The number of bits in i386_operand_type. */
+ OTNum
};
#define OTNumOfUints \
- (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
+ ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
#define OTNumOfBits \
(OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
/* If you get a compiler error for zero width of the unused field,
comment it out. */
-#define OTUnused (OTMax + 1)
+#define OTUnused OTNum
typedef union i386_operand_type
{
struct
{
- unsigned int reg:1;
- unsigned int regmmx:1;
- unsigned int regsimd:1;
- unsigned int regmask:1;
- unsigned int control:1;
- unsigned int debug:1;
- unsigned int test:1;
- unsigned int sreg2:1;
- unsigned int sreg3:1;
+ unsigned int class:CLASS_WIDTH;
+ unsigned int instance:INSTANCE_WIDTH;
unsigned int imm1:1;
unsigned int imm8:1;
unsigned int imm8s:1;
unsigned int disp32:1;
unsigned int disp32s:1;
unsigned int disp64:1;
- unsigned int acc:1;
unsigned int baseindex:1;
- unsigned int inoutportreg:1;
- unsigned int shiftcount:1;
- unsigned int jumpabsolute:1;
- unsigned int esseg:1;
- unsigned int regmem:1;
- unsigned int mem:1;
unsigned int byte:1;
unsigned int word:1;
unsigned int dword:1;
unsigned int ymmword:1;
unsigned int zmmword:1;
unsigned int unspecified:1;
- unsigned int anysize:1;
- unsigned int vec_imm4:1;
- unsigned int regbnd:1;
#ifdef OTUnused
unsigned int unused:(OTNumOfBits - OTUnused);
#endif
/* instruction name sans width suffix ("mov" for movl insns) */
char *name;
- /* how many operands */
- unsigned int operands;
-
/* base_opcode is the fundamental opcode byte without optional
prefix(es). */
unsigned int base_opcode;
unset if Regmem --> Reg. */
#define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
#define Opcode_FloatD 0x400 /* Direction bit for float insns. */
+#define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
+#define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
/* extension_opcode is the 3 bit extension for group <n> insns.
This field is also used to store the 8-bit opcode suffix for the
AMD 3DNow! instructions.
If this template has no extension opcode (the usual case) use None
Instructions */
- unsigned int extension_opcode;
+ unsigned short extension_opcode;
#define None 0xffff /* If no extension_opcode is possible. */
/* Opcode length. */
unsigned char opcode_length;
+ /* how many operands */
+ unsigned char operands;
+
/* cpu feature flags */
i386_cpu_flags cpu_flags;
#define RegRex64 0x2 /* Extended 8 bit register. */
#define RegVRex 0x4 /* Extended vector register. */
unsigned char reg_num;
-#define RegRip ((unsigned char ) ~0)
-#define RegEip (RegRip - 1)
+#define RegIP ((unsigned char ) ~0)
/* EIZ and RIZ are fake index registers. */
-#define RegEiz (RegEip - 1)
-#define RegRiz (RegEiz - 1)
+#define RegIZ (RegIP - 1)
/* FLAT is a fake segment register (Intel mode). */
#define RegFlat ((unsigned char) ~0)
signed char dw2_regnum[2];
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