+/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
/* Disassembler interface for targets using CGEN. -*- C -*-
CGEN: Cpu tools GENerator
THIS FILE IS MACHINE GENERATED WITH CGEN.
- the resultant file is machine generated, cgen-dis.in isn't
- Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
- Free Software Foundation, Inc.
+ Copyright (C) 1996-2021 Free Software Foundation, Inc.
- This file is part of the GNU Binutils and GDB, the GNU debugger.
+ This file is part of libopcodes.
- This program is free software; you can redistribute it and/or modify
+ This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
+ the Free Software Foundation; either version 3, or (at your option)
any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software Foundation, Inc.,
#include "sysdep.h"
#include <stdio.h>
#include "ansidecl.h"
-#include "dis-asm.h"
+#include "disassemble.h"
#include "bfd.h"
#include "symcat.h"
#include "libiberty.h"
}
static void
-print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
+print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED,
unsigned int flags ATTRIBUTE_UNUSED)
{
/* begin-cop-ip-print-handlers */
static void
-print_fmax_cr (CGEN_CPU_DESC cd,
+print_ivc2_cr (CGEN_CPU_DESC,
+ void *,
+ CGEN_KEYWORD *,
+ long,
+ unsigned int) ATTRIBUTE_UNUSED;
+static void
+print_ivc2_cr (CGEN_CPU_DESC cd,
void *dis_info,
CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED,
long value,
unsigned int attrs)
{
- print_keyword (cd, dis_info, & mep_cgen_opval_h_cr_fmax, value, attrs);
+ print_keyword (cd, dis_info, & mep_cgen_opval_h_cr_ivc2, value, attrs);
}
static void
-print_fmax_ccr (CGEN_CPU_DESC cd,
+print_ivc2_ccr (CGEN_CPU_DESC,
+ void *,
+ CGEN_KEYWORD *,
+ long,
+ unsigned int) ATTRIBUTE_UNUSED;
+static void
+print_ivc2_ccr (CGEN_CPU_DESC cd,
void *dis_info,
CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED,
long value,
unsigned int attrs)
{
- print_keyword (cd, dis_info, & mep_cgen_opval_h_ccr_fmax, value, attrs);
+ print_keyword (cd, dis_info, & mep_cgen_opval_h_ccr_ivc2, value, attrs);
}
/* end-cop-ip-print-handlers */
if (corelength > 0)
{
int my_status = 0;
-
+
for (i = 0; i < corelength; i++ )
insnbuf[i] = buf[i];
cd->isas = & MEP_CORE_ISA;
-
+
my_status = print_insn (cd, pc, info, insnbuf, corelength);
if (my_status != corelength)
{
/* Print the + to indicate that the following copro insn is */
/* part of a vliw group. */
if (copro1length > 0)
- (*info->fprintf_func) (info->stream, " + ");
+ (*info->fprintf_func) (info->stream, " + ");
}
/* Now all that is left to be processed is the coprocessor insns
if (copro1length > 0)
{
int my_status = 0;
-
+
for (i = corelength; i < corelength + copro1length; i++ )
insnbuf[i - corelength] = buf[i];
break;
case 8:
cd->isas = & MEP_COP64_ISA;
- break;
+ break;
default:
/* Shouldn't be anything but 16,32,48,64. */
break;
for (i = corelength + copro1length; i < 64; i++)
insnbuf[i - (corelength + copro1length)] = buf[i];
-
+
switch (copro2length)
{
case 2:
cd->isas = 1 << ISA_EXT_COP1_48;
break;
case 8:
- cd->isas = 1 << ISA_EXT_COP1_64;
+ cd->isas = 1 << ISA_EXT_COP1_64;
break;
default:
/* Shouldn't be anything but 16,32,48,64. */
return status;
}
-/* The two functions mep_examine_vliw[32,64]_insns are used find out
- which vliw combinaion (16 bit core with 48 bit copro, 32 bit core
- with 32 bit copro, etc.) is present. Later on, when internally
- parallel coprocessors are handled, only these functions should
- need to be changed.
+/* The two functions mep_examine_vliw[32,64]_insns are used find out
+ which vliw combinaion (16 bit core with 48 bit copro, 32 bit core
+ with 32 bit copro, etc.) is present. Later on, when internally
+ parallel coprocessors are handled, only these functions should
+ need to be changed.
+
+ At this time only the following combinations are supported:
- At this time only the following combinations are supported:
-
VLIW32 Mode:
16 bit core insn (core) and 16 bit coprocessor insn (cop1)
32 bit core insn (core)
32 bit coprocessor insn (cop1)
Note: As of this time, I do not believe we have enough information
to distinguish a 32 bit core insn from a 32 bit cop insn. Also,
- no 16 bit coprocessor insns have been specified.
+ no 16 bit coprocessor insns have been specified.
VLIW64 Mode:
16 bit core insn (core) and 48 bit coprocessor insn (cop1)
32 bit core insn (core) and 32 bit coprocessor insn (cop1)
64 bit coprocessor insn (cop1)
-
+
The framework for an internally parallel coprocessor is also
- present (2nd coprocessor insn is cop2), but at this time it
+ present (2nd coprocessor insn is cop2), but at this time it
is not used. This only appears to be valid in VLIW64 mode. */
static int
int corebuflength;
int cop1buflength;
int cop2buflength;
- bfd_byte buf[CGEN_MAX_INSN_SIZE];
+ bfd_byte buf[CGEN_MAX_INSN_SIZE];
char indicator16[1];
- char indicatorcop32[2];
+ char indicatorcop32[2];
/* At this time we're not supporting internally parallel coprocessors,
so cop2buflength will always be 0. */
return status;
}
+#ifdef MEP_IVC2_SUPPORTED
+
+static int
+print_slot_insn (CGEN_CPU_DESC cd,
+ bfd_vma pc,
+ disassemble_info *info,
+ SLOTS_ATTR slot,
+ bfd_byte *buf)
+{
+ const CGEN_INSN_LIST *insn_list;
+ CGEN_INSN_INT insn_value;
+ CGEN_EXTRACT_INFO ex_info;
+
+ insn_value = cgen_get_insn_value (cd, buf, 32, cd->insn_endian);
+
+ /* Fill in ex_info fields like read_insn would. Don't actually call
+ read_insn, since the incoming buffer is already read (and possibly
+ modified a la m32r). */
+ ex_info.valid = (1 << 8) - 1;
+ ex_info.dis_info = info;
+ ex_info.insn_bytes = buf;
+
+ /* The instructions are stored in hash lists.
+ Pick the first one and keep trying until we find the right one. */
+
+ insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
+ while (insn_list != NULL)
+ {
+ const CGEN_INSN *insn = insn_list->insn;
+ CGEN_FIELDS fields;
+ int length;
+
+ if ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG)
+ && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) != MEP_CONFIG)
+ || ! (CGEN_ATTR_CGEN_INSN_SLOTS_VALUE (CGEN_INSN_ATTRS (insn)) & (1 << slot)))
+ {
+ insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+ continue;
+ }
+
+ if ((insn_value & CGEN_INSN_BASE_MASK (insn))
+ == CGEN_INSN_BASE_VALUE (insn))
+ {
+ /* Printing is handled in two passes. The first pass parses the
+ machine insn and extracts the fields. The second pass prints
+ them. */
+
+ length = CGEN_EXTRACT_FN (cd, insn)
+ (cd, insn, &ex_info, insn_value, &fields, pc);
+
+ /* Length < 0 -> error. */
+ if (length < 0)
+ return length;
+ if (length > 0)
+ {
+ CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
+ /* Length is in bits, result is in bytes. */
+ return length / 8;
+ }
+ }
+
+ insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+ }
+
+ if (slot == SLOTS_P0S)
+ (*info->fprintf_func) (info->stream, "*unknown-p0s*");
+ else if (slot == SLOTS_P0)
+ (*info->fprintf_func) (info->stream, "*unknown-p0*");
+ else if (slot == SLOTS_P1)
+ (*info->fprintf_func) (info->stream, "*unknown-p1*");
+ else if (slot == SLOTS_C3)
+ (*info->fprintf_func) (info->stream, "*unknown-c3*");
+ return 0;
+}
+
+static int
+mep_examine_ivc2_insns (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, disassemble_info *info ATTRIBUTE_UNUSED)
+{
+ int status;
+ int buflength;
+ bfd_byte buf[8];
+ bfd_byte insn[8];
+ int e;
+
+ /* Read in 64 bits. */
+ buflength = 8; /* VLIW insn spans 8 bytes. */
+ status = (*info->read_memory_func) (pc, buf, buflength, info);
+
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, pc, info);
+ return -1;
+ }
+
+ if (info->endian == BFD_ENDIAN_LITTLE)
+ e = 1;
+ else
+ e = 0;
+
+ if (((unsigned char)buf[0^e] & 0xf0) < 0xc0)
+ {
+ /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */
+ /* V1 [-----core-----][--------p0s-------][------------p1------------] */
+
+ print_insn (cd, pc, info, buf, 2);
+
+ insn[0^e] = 0;
+ insn[1^e] = buf[2^e];
+ insn[2^e] = buf[3^e];
+ insn[3^e] = buf[4^e] & 0xf0;
+ (*info->fprintf_func) (info->stream, " + ");
+ print_slot_insn (cd, pc, info, SLOTS_P0S, insn);
+
+ insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4;
+ insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4;
+ insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4;
+ insn[3^e] = buf[7^e] << 4;
+ (*info->fprintf_func) (info->stream, " + ");
+ print_slot_insn (cd, pc, info, SLOTS_P1, insn);
+ }
+ else if ((buf[0^e] & 0xf0) == 0xf0 && (buf[1^e] & 0x0f) == 0x07)
+ {
+ /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */
+ /* V3 1111[--p0--]0111[--------p0--------][------------p1------------] */
+ /* 00000000111111112222222233333333 */
+
+ insn[0^e] = buf[0^e] << 4 | buf[1^e] >> 4;
+ insn[1^e] = buf[2^e];
+ insn[2^e] = buf[3^e];
+ insn[3^e] = buf[4^e] & 0xf0;
+ print_slot_insn (cd, pc, info, SLOTS_P0, insn);
+
+ insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4;
+ insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4;
+ insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4;
+ insn[3^e] = buf[7^e] << 4;
+ (*info->fprintf_func) (info->stream, " + ");
+ print_slot_insn (cd, pc, info, SLOTS_P1, insn);
+ }
+ else
+ {
+ /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */
+ /* V2 [-------------core-------------]xxxx[------------p1------------] */
+ print_insn (cd, pc, info, buf, 4);
+
+ insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4;
+ insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4;
+ insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4;
+ insn[3^e] = buf[7^e] << 4;
+ (*info->fprintf_func) (info->stream, " + ");
+ print_slot_insn (cd, pc, info, SLOTS_P1, insn);
+ }
+
+ return 8;
+}
+
+#endif /* MEP_IVC2_SUPPORTED */
+
+/* This is a hack. SID calls this to update the disassembler as the
+ CPU changes modes. */
+static int mep_ivc2_disassemble_p = 0;
+static int mep_ivc2_vliw_disassemble_p = 0;
+
+void
+mep_print_insn_set_ivc2_mode (int ivc2_p, int vliw_p, int cfg_idx);
+void
+mep_print_insn_set_ivc2_mode (int ivc2_p, int vliw_p, int cfg_idx)
+{
+ mep_ivc2_disassemble_p = ivc2_p;
+ mep_ivc2_vliw_disassemble_p = vliw_p;
+ mep_config_index = cfg_idx;
+}
+
static int
mep_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
{
int status;
+ int cop_type;
+ int ivc2 = 0;
+ static CGEN_ATTR_VALUE_BITSET_TYPE *ivc2_core_isa = NULL;
+
+ if (ivc2_core_isa == NULL)
+ {
+ /* IVC2 has some core-only coprocessor instructions. We
+ use COP32 to flag those, and COP64 for the VLIW ones,
+ since they have the same names. */
+ ivc2_core_isa = cgen_bitset_create (MAX_ISAS);
+ }
/* Extract and adapt to configuration number, if available. */
if (info->section && info->section->owner)
bfd *abfd = info->section->owner;
mep_config_index = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_INDEX_MASK;
/* This instantly redefines MEP_CONFIG, MEP_OMASK, .... MEP_VLIW64 */
+
+ cop_type = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_COP_MASK;
+ if (cop_type == EF_MEP_COP_IVC2)
+ ivc2 = 1;
}
/* Picking the right ISA bitmask for the current context is tricky. */
{
if (info->section->flags & SEC_MEP_VLIW)
{
- /* Are we in 32 or 64 bit vliw mode? */
- if (MEP_VLIW64)
- status = mep_examine_vliw64_insns (cd, pc, info);
+#ifdef MEP_IVC2_SUPPORTED
+ if (ivc2)
+ {
+ /* ivc2 has its own way of selecting its functions. */
+ cd->isas = & MEP_CORE_ISA;
+ status = mep_examine_ivc2_insns (cd, pc, info);
+ }
else
- status = mep_examine_vliw32_insns (cd, pc, info);
+#endif
+ /* Are we in 32 or 64 bit vliw mode? */
+ if (MEP_VLIW64)
+ status = mep_examine_vliw64_insns (cd, pc, info);
+ else
+ status = mep_examine_vliw32_insns (cd, pc, info);
/* Both the above branches set their own isa bitmasks. */
}
else
{
- cd->isas = & MEP_CORE_ISA;
+ if (ivc2)
+ {
+ cgen_bitset_clear (ivc2_core_isa);
+ cgen_bitset_union (ivc2_core_isa, &MEP_CORE_ISA, ivc2_core_isa);
+ cgen_bitset_union (ivc2_core_isa, &MEP_COP32_ISA, ivc2_core_isa);
+ cd->isas = ivc2_core_isa;
+ }
+ else
+ cd->isas = & MEP_CORE_ISA;
status = default_print_insn (cd, pc, info);
}
}
else /* sid or gdb */
{
+#ifdef MEP_IVC2_SUPPORTED
+ if (mep_ivc2_disassemble_p)
+ {
+ if (mep_ivc2_vliw_disassemble_p)
+ {
+ cd->isas = & MEP_CORE_ISA;
+ status = mep_examine_ivc2_insns (cd, pc, info);
+ return status;
+ }
+ else
+ {
+ if (ivc2)
+ cd->isas = ivc2_core_isa;
+ }
+ }
+#endif
+
status = default_print_insn (cd, pc, info);
}
case MEP_OPERAND_ADDR24A4 :
print_normal (cd, info, fields->f_24u8a4n, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
break;
+ case MEP_OPERAND_C5RMUIMM20 :
+ print_normal (cd, info, fields->f_c5_rmuimm20, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
+ case MEP_OPERAND_C5RNMUIMM24 :
+ print_normal (cd, info, fields->f_c5_rnmuimm24, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
case MEP_OPERAND_CALLNUM :
print_normal (cd, info, fields->f_callnum, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
break;
case MEP_OPERAND_CCRN :
print_keyword (cd, info, & mep_cgen_opval_h_ccr, fields->f_ccrn, 0|(1<<CGEN_OPERAND_VIRTUAL));
break;
- case MEP_OPERAND_CDISP8 :
- print_normal (cd, info, fields->f_8s24, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ case MEP_OPERAND_CDISP10 :
+ print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ break;
+ case MEP_OPERAND_CDISP10A2 :
+ print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
- case MEP_OPERAND_CDISP8A2 :
- print_normal (cd, info, fields->f_8s24a2, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ case MEP_OPERAND_CDISP10A4 :
+ print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
- case MEP_OPERAND_CDISP8A4 :
- print_normal (cd, info, fields->f_8s24a4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ case MEP_OPERAND_CDISP10A8 :
+ print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
- case MEP_OPERAND_CDISP8A8 :
- print_normal (cd, info, fields->f_8s24a8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ case MEP_OPERAND_CDISP12 :
+ print_normal (cd, info, fields->f_12s20, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
case MEP_OPERAND_CIMM4 :
print_normal (cd, info, fields->f_rn, 0, pc, length);
case MEP_OPERAND_CRNX64 :
print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_crnx, 0|(1<<CGEN_OPERAND_VIRTUAL));
break;
+ case MEP_OPERAND_CROC :
+ print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u7, 0);
+ break;
+ case MEP_OPERAND_CROP :
+ print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u23, 0);
+ break;
+ case MEP_OPERAND_CRPC :
+ print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u26, 0);
+ break;
+ case MEP_OPERAND_CRPP :
+ print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u18, 0);
+ break;
+ case MEP_OPERAND_CRQC :
+ print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u21, 0);
+ break;
+ case MEP_OPERAND_CRQP :
+ print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u13, 0);
+ break;
case MEP_OPERAND_CSRN :
print_keyword (cd, info, & mep_cgen_opval_h_csr, fields->f_csrn, 0|(1<<CGEN_OPERAND_VIRTUAL));
break;
case MEP_OPERAND_EXC :
print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
break;
- case MEP_OPERAND_FMAX_CCRN :
- print_fmax_ccr (cd, info, & mep_cgen_opval_h_ccr, fields->f_fmax_4_4, 0);
+ case MEP_OPERAND_HI :
+ print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
break;
- case MEP_OPERAND_FMAX_FRD :
- print_fmax_cr (cd, info, & mep_cgen_opval_h_cr, fields->f_fmax_frd, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ case MEP_OPERAND_IMM16P0 :
+ print_normal (cd, info, fields->f_ivc2_imm16p0, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
break;
- case MEP_OPERAND_FMAX_FRD_INT :
- print_fmax_cr (cd, info, & mep_cgen_opval_h_cr, fields->f_fmax_frd, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ case MEP_OPERAND_IMM3P12 :
+ print_normal (cd, info, fields->f_ivc2_3u12, 0, pc, length);
break;
- case MEP_OPERAND_FMAX_FRM :
- print_fmax_cr (cd, info, & mep_cgen_opval_h_cr, fields->f_fmax_frm, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ case MEP_OPERAND_IMM3P25 :
+ print_normal (cd, info, fields->f_ivc2_3u25, 0, pc, length);
break;
- case MEP_OPERAND_FMAX_FRN :
- print_fmax_cr (cd, info, & mep_cgen_opval_h_cr, fields->f_fmax_frn, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ case MEP_OPERAND_IMM3P4 :
+ print_normal (cd, info, fields->f_ivc2_3u4, 0, pc, length);
break;
- case MEP_OPERAND_FMAX_FRN_INT :
- print_fmax_cr (cd, info, & mep_cgen_opval_h_cr, fields->f_fmax_frn, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ case MEP_OPERAND_IMM3P5 :
+ print_normal (cd, info, fields->f_ivc2_3u5, 0, pc, length);
break;
- case MEP_OPERAND_FMAX_RM :
- print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_fmax_rm, 0);
+ case MEP_OPERAND_IMM3P9 :
+ print_normal (cd, info, fields->f_ivc2_3u9, 0, pc, length);
break;
- case MEP_OPERAND_HI :
- print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
+ case MEP_OPERAND_IMM4P10 :
+ print_normal (cd, info, fields->f_ivc2_4u10, 0, pc, length);
+ break;
+ case MEP_OPERAND_IMM4P4 :
+ print_normal (cd, info, fields->f_ivc2_4u4, 0, pc, length);
+ break;
+ case MEP_OPERAND_IMM4P8 :
+ print_normal (cd, info, fields->f_ivc2_4u8, 0, pc, length);
+ break;
+ case MEP_OPERAND_IMM5P23 :
+ print_normal (cd, info, fields->f_ivc2_5u23, 0, pc, length);
+ break;
+ case MEP_OPERAND_IMM5P3 :
+ print_normal (cd, info, fields->f_ivc2_5u3, 0, pc, length);
+ break;
+ case MEP_OPERAND_IMM5P7 :
+ print_normal (cd, info, fields->f_ivc2_5u7, 0, pc, length);
+ break;
+ case MEP_OPERAND_IMM5P8 :
+ print_normal (cd, info, fields->f_ivc2_5u8, 0, pc, length);
+ break;
+ case MEP_OPERAND_IMM6P2 :
+ print_normal (cd, info, fields->f_ivc2_6u2, 0, pc, length);
+ break;
+ case MEP_OPERAND_IMM6P6 :
+ print_normal (cd, info, fields->f_ivc2_6u6, 0, pc, length);
+ break;
+ case MEP_OPERAND_IMM8P0 :
+ print_normal (cd, info, fields->f_ivc2_8u0, 0, pc, length);
+ break;
+ case MEP_OPERAND_IMM8P20 :
+ print_normal (cd, info, fields->f_ivc2_8u20, 0, pc, length);
+ break;
+ case MEP_OPERAND_IMM8P4 :
+ print_normal (cd, info, fields->f_ivc2_8u4, 0, pc, length);
+ break;
+ case MEP_OPERAND_IVC_X_0_2 :
+ print_normal (cd, info, fields->f_ivc2_2u0, 0, pc, length);
+ break;
+ case MEP_OPERAND_IVC_X_0_3 :
+ print_normal (cd, info, fields->f_ivc2_3u0, 0, pc, length);
+ break;
+ case MEP_OPERAND_IVC_X_0_4 :
+ print_normal (cd, info, fields->f_ivc2_4u0, 0, pc, length);
+ break;
+ case MEP_OPERAND_IVC_X_0_5 :
+ print_normal (cd, info, fields->f_ivc2_5u0, 0, pc, length);
+ break;
+ case MEP_OPERAND_IVC_X_6_1 :
+ print_normal (cd, info, fields->f_ivc2_1u6, 0, pc, length);
+ break;
+ case MEP_OPERAND_IVC_X_6_2 :
+ print_normal (cd, info, fields->f_ivc2_2u6, 0, pc, length);
+ break;
+ case MEP_OPERAND_IVC_X_6_3 :
+ print_normal (cd, info, fields->f_ivc2_3u6, 0, pc, length);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_0 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_1 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_2 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_3 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_4 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_5 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_6 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_7 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_0 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_1 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_2 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_3 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_4 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_5 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_6 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_7 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_CC :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_COFA0 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_COFA1 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_COFR0 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_COFR1 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_CSAR0 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_CSAR1 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2C3CCRN :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, fields->f_ivc2_ccrn_c3, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ break;
+ case MEP_OPERAND_IVC2CCRN :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, fields->f_ivc2_ccrn, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ break;
+ case MEP_OPERAND_IVC2CRN :
+ print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_crnx, 0|(1<<CGEN_OPERAND_VIRTUAL));
+ break;
+ case MEP_OPERAND_IVC2RM :
+ print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_ivc2_crm, 0);
break;
case MEP_OPERAND_LO :
print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
case MEP_OPERAND_RL :
print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rl, 0);
break;
+ case MEP_OPERAND_RL5 :
+ print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rl5, 0);
+ break;
case MEP_OPERAND_RM :
print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rm, 0);
break;
case MEP_OPERAND_SIMM16 :
print_normal (cd, info, fields->f_16s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
+ case MEP_OPERAND_SIMM16P0 :
+ print_normal (cd, info, fields->f_ivc2_simm16p0, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
+ break;
case MEP_OPERAND_SIMM6 :
print_normal (cd, info, fields->f_6s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
break;
case MEP_OPERAND_SIMM8 :
print_normal (cd, info, fields->f_8s8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW), pc, length);
break;
+ case MEP_OPERAND_SIMM8P0 :
+ print_normal (cd, info, fields->f_ivc2_8s0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ break;
+ case MEP_OPERAND_SIMM8P20 :
+ print_normal (cd, info, fields->f_ivc2_8s20, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ break;
+ case MEP_OPERAND_SIMM8P4 :
+ print_normal (cd, info, fields->f_ivc2_8s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+ break;
case MEP_OPERAND_SP :
print_keyword (cd, info, & mep_cgen_opval_h_gpr, 0, 0);
break;
default :
/* xgettext:c-format */
- fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
- opindex);
- abort ();
+ opcodes_error_handler
+ (_("internal error: unrecognized field %d while printing insn"),
+ opindex);
+ abort ();
}
}
-cgen_print_fn * const mep_cgen_print_handlers[] =
+cgen_print_fn * const mep_cgen_print_handlers[] =
{
print_insn_normal,
};
{
disassemble_info *info = (disassemble_info *) dis_info;
-#ifdef CGEN_PRINT_NORMAL
- CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
-#endif
-
/* Print the operand as directed by the attributes. */
if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
; /* nothing to do */
{
disassemble_info *info = (disassemble_info *) dis_info;
-#ifdef CGEN_PRINT_ADDRESS
- CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
-#endif
-
/* Print the operand as directed by the attributes. */
if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
; /* Nothing to do. */
/* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
basesize = cd->base_insn_bitsize < buflen * 8 ?
cd->base_insn_bitsize : buflen * 8;
- insn_value = cgen_get_insn_value (cd, buf, basesize);
+ insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian);
/* Fill in ex_info fields like read_insn would. Don't actually call
int length;
unsigned long insn_value_cropped;
-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED
/* Not needed as insn shouldn't be in hash lists if not supported. */
/* Supported by this cpu? */
if (! mep_cgen_insn_supported (cd, insn))
relevant part from the buffer. */
if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
(unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
- insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
+ insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
info->endian == BFD_ENDIAN_BIG);
else
insn_value_cropped = insn_value;
CGEN_BITSET *isa;
int mach;
int endian;
+ int insn_endian;
CGEN_CPU_DESC cd;
} cpu_desc_list;
static CGEN_BITSET *prev_isa;
static int prev_mach;
static int prev_endian;
+ static int prev_insn_endian;
int length;
CGEN_BITSET *isa;
int mach;
int endian = (info->endian == BFD_ENDIAN_BIG
? CGEN_ENDIAN_BIG
: CGEN_ENDIAN_LITTLE);
+ int insn_endian = (info->endian_code == BFD_ENDIAN_BIG
+ ? CGEN_ENDIAN_BIG
+ : CGEN_ENDIAN_LITTLE);
enum bfd_architecture arch;
/* ??? gdb will set mach but leave the architecture as "unknown" */
arch = info->arch;
if (arch == bfd_arch_unknown)
arch = CGEN_BFD_ARCH;
-
+
/* There's no standard way to compute the machine or isa number
so we leave it to the target. */
#ifdef CGEN_COMPUTE_MACH
cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
}
#else
- isa = info->insn_sets;
+ isa = info->private_data;
#endif
/* If we've switched cpu's, try to find a handle we've used before */
break;
}
}
- }
+ }
/* If we haven't initialized yet, initialize the opcode table. */
if (! cd)
prev_isa = cgen_bitset_copy (isa);
prev_mach = mach;
prev_endian = endian;
+ prev_insn_endian = insn_endian;
cd = mep_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
CGEN_CPU_OPEN_BFDMACH, mach_name,
CGEN_CPU_OPEN_ENDIAN, prev_endian,
+ CGEN_CPU_OPEN_INSN_ENDIAN, prev_insn_endian,
CGEN_CPU_OPEN_END);
if (!cd)
abort ();
projects / deliverable / binutils-gdb.git / blobdiff