/* Disassemble MSP430 instructions.
- Copyright (C) 2002-2016 Free Software Foundation, Inc.
+ Copyright (C) 2002-2021 Free Software Foundation, Inc.
Contributed by Dmitry Diky <diwil@mail.ru>
#include <stdio.h>
#include <ctype.h>
#include <sys/types.h>
+#include <errno.h>
-#include "dis-asm.h"
+#include "disassemble.h"
#include "opintl.h"
#include "libiberty.h"
#define PS(x) (0xffff & (x))
-static unsigned short
-msp430dis_opcode (bfd_vma addr, disassemble_info *info)
+static bool
+msp430dis_read_two_bytes (bfd_vma addr,
+ disassemble_info * info,
+ bfd_byte * buffer,
+ char * comm)
{
- bfd_byte buffer[2];
int status;
status = info->read_memory_func (addr, buffer, 2, info);
- if (status != 0)
+ if (status == 0)
+ return true;
+
+ /* PR 20150: A status of EIO means that there were no more bytes left
+ to read in the current section. This can happen when disassembling
+ interrupt vectors for example. Avoid cluttering the output with
+ unhelpful error messages in this case. */
+ if (status == EIO)
+ {
+ if (comm)
+ sprintf (comm, _("Warning: disassembly unreliable - not enough bytes available"));
+ }
+ else
{
info->memory_error_func (status, addr, info);
- return -1;
+ if (comm)
+ sprintf (comm, _("Error: read from memory failed"));
+ }
+
+ return false;
+}
+
+static bool
+msp430dis_opcode_unsigned (bfd_vma addr,
+ disassemble_info * info,
+ unsigned short * return_val,
+ char * comm)
+{
+ bfd_byte buffer[2];
+
+ if (msp430dis_read_two_bytes (addr, info, buffer, comm))
+ {
+ * return_val = bfd_getl16 (buffer);
+ return true;
+ }
+ else
+ {
+ * return_val = 0;
+ return false;
+ }
+}
+
+static bool
+msp430dis_opcode_signed (bfd_vma addr,
+ disassemble_info * info,
+ signed int * return_val,
+ char * comm)
+{
+ bfd_byte buffer[2];
+
+ if (msp430dis_read_two_bytes (addr, info, buffer, comm))
+ {
+ int status;
+
+ status = bfd_getl_signed_16 (buffer);
+ if (status & 0x8000)
+ status |= -1U << 16;
+ * return_val = status;
+ return true;
+ }
+ else
+ {
+ * return_val = 0;
+ return false;
}
- return bfd_getl16 (buffer);
}
static int
if (regd == 0)
{
/* PC relative. */
- dst = msp430dis_opcode (addr + 2, info);
- cmd_len += 2;
- *cycles = 4;
- sprintf (op, "0x%04x", dst);
- sprintf (comm, "PC rel. abs addr 0x%04x",
- PS ((short) (addr + 2) + dst));
- if (extended_dst)
+ if (msp430dis_opcode_signed (addr + 2, info, &dst, comm))
{
- dst |= extended_dst << 16;
- sprintf (op, "0x%05x", dst);
- sprintf (comm, "PC rel. abs addr 0x%05lx",
- (long)((addr + 2 + dst) & 0xfffff));
+ cmd_len += 2;
+ *cycles = 4;
+ sprintf (op, "0x%04x", dst);
+ sprintf (comm, "PC rel. abs addr 0x%04x",
+ PS ((short) (addr + 2) + dst));
+ if (extended_dst)
+ {
+ dst |= extended_dst << 16;
+ sprintf (op, "0x%05x", dst);
+ sprintf (comm, "PC rel. abs addr 0x%05lx",
+ (long)((addr + 2 + dst) & 0xfffff));
+ }
}
+ else
+ return -1;
}
else if (regd == 2)
{
/* Absolute. */
- dst = msp430dis_opcode (addr + 2, info);
- cmd_len += 2;
- *cycles = 4;
- sprintf (op, "&0x%04x", PS (dst));
- if (extended_dst)
+ if (msp430dis_opcode_signed (addr + 2, info, &dst, comm))
{
- dst |= extended_dst << 16;
- sprintf (op, "&0x%05x", dst & 0xfffff);
+ cmd_len += 2;
+ *cycles = 4;
+ sprintf (op, "&0x%04x", PS (dst));
+ if (extended_dst)
+ {
+ dst |= extended_dst << 16;
+ sprintf (op, "&0x%05x", dst & 0xfffff);
+ }
}
+ else
+ return -1;
}
else
{
- dst = msp430dis_opcode (addr + 2, info);
- cmd_len += 2;
- *cycles = 4;
- if (extended_dst)
+ if (msp430dis_opcode_signed (addr + 2, info, &dst, comm))
{
- dst |= extended_dst << 16;
- if (dst & 0x80000)
- dst |= -1U << 20;
+ cmd_len += 2;
+ *cycles = 4;
+ if (extended_dst)
+ {
+ dst |= extended_dst << 16;
+ if (dst & 0x80000)
+ dst |= -1U << 20;
+ }
+ sprintf (op, "%d(r%d)", dst, regd);
}
- else if (dst & 0x8000)
- dst |= -1U << 16;
- sprintf (op, "%d(r%d)", dst, regd);
+ else
+ return -1;
}
}
break;
{
*cycles = 3;
/* absolute. @pc+ */
- dst = msp430dis_opcode (addr + 2, info);
- cmd_len += 2;
- sprintf (op, "#%d", dst);
- if (dst > 9 || dst < 0)
- sprintf (comm, "#0x%04x", PS (dst));
- if (extended_dst)
+ if (msp430dis_opcode_signed (addr + 2, info, &dst, comm))
{
- dst |= extended_dst << 16;
- if (dst & 0x80000)
- dst |= -1U << 20;
+ cmd_len += 2;
sprintf (op, "#%d", dst);
if (dst > 9 || dst < 0)
- sprintf (comm, "#0x%05x", dst);
+ sprintf (comm, "#0x%04x", PS (dst));
+ if (extended_dst)
+ {
+ dst |= extended_dst << 16;
+ if (dst & 0x80000)
+ dst |= -1U << 20;
+ sprintf (op, "#%d", dst);
+ if (dst > 9 || dst < 0)
+ sprintf (comm, "#0x%05x", dst);
+ }
}
+ else
+ return -1;
}
else
* cycles = print_as3_reg_name (regd, op, comm, 1, 1, 3);
if (regd == 0)
{
/* PC relative. */
- dst = msp430dis_opcode (addr + 2, info);
- cmd_len += 2;
- sprintf (op, "0x%04x", PS (dst));
- sprintf (comm, "PC rel. 0x%04x",
- PS ((short) addr + 2 + dst));
- if (extended_dst)
+ if (msp430dis_opcode_signed (addr + 2, info, &dst, comm))
{
- dst |= extended_dst << 16;
- sprintf (op, "0x%05x", dst & 0xffff);
- sprintf (comm, "PC rel. 0x%05lx",
- (long)((addr + 2 + dst) & 0xfffff));
+ cmd_len += 2;
+ sprintf (op, "0x%04x", PS (dst));
+ sprintf (comm, "PC rel. 0x%04x",
+ PS ((short) addr + 2 + dst));
+ if (extended_dst)
+ {
+ dst |= extended_dst << 16;
+ sprintf (op, "0x%05x", dst & 0xffff);
+ sprintf (comm, "PC rel. 0x%05lx",
+ (long)((addr + 2 + dst) & 0xfffff));
+ }
}
+ else
+ return -1;
}
else if (regd == 2)
{
/* Absolute. */
- dst = msp430dis_opcode (addr + 2, info);
- cmd_len += 2;
- sprintf (op, "&0x%04x", PS (dst));
- if (extended_dst)
+ if (msp430dis_opcode_signed (addr + 2, info, &dst, comm))
{
- dst |= extended_dst << 16;
- sprintf (op, "&0x%05x", dst & 0xfffff);
+ cmd_len += 2;
+ sprintf (op, "&0x%04x", PS (dst));
+ if (extended_dst)
+ {
+ dst |= extended_dst << 16;
+ sprintf (op, "&0x%05x", dst & 0xfffff);
+ }
}
+ else
+ return -1;
}
else if (regd == 3)
{
else
{
/* Indexed. */
- dst = msp430dis_opcode (addr + 2, info);
- cmd_len += 2;
- if (extended_dst)
+ if (msp430dis_opcode_signed (addr + 2, info, &dst, comm))
{
- dst |= extended_dst << 16;
- if (dst & 0x80000)
- dst |= -1U << 20;
+ cmd_len += 2;
+ if (extended_dst)
+ {
+ dst |= extended_dst << 16;
+ if (dst & 0x80000)
+ dst |= -1U << 20;
+ }
+ sprintf (op, "%d(r%d)", dst, regd);
+ if (dst > 9 || dst < 0)
+ sprintf (comm, "%05x", dst);
}
- else if (dst & 0x8000)
- dst |= -1U << 16;
- sprintf (op, "%d(r%d)", dst, regd);
- if (dst > 9 || dst < 0)
- sprintf (comm, "%05x", dst);
+ else
+ return -1;
}
}
break;
*cycles = 2;
return 2;
break;
+
default:
cmd_len = 0;
}
/* Register mode. */
if (regd == 3)
{
- strcpy (comm1, _("Illegal as emulation instr"));
+ strcpy (comm1, _("Warning: illegal as emulation instr"));
return -1;
}
if (regd == 0)
{
/* PC relative, Symbolic. */
- dst = msp430dis_opcode (addr + 2, info);
- cmd_len += 4;
- *cycles = 6;
- sprintf (op1, "0x%04x", PS (dst));
- sprintf (comm1, "PC rel. 0x%04x",
- PS ((short) addr + 2 + dst));
- if (extension_word)
+ if (msp430dis_opcode_signed (addr + 2, info, &dst, comm1))
{
- dst |= extended_dst << 16;
- if (dst & 0x80000)
- dst |= -1U << 20;
- sprintf (op1, "0x%05x", dst & 0xfffff);
- sprintf (comm1, "PC rel. 0x%05lx",
- (long)((addr + 2 + dst) & 0xfffff));
+ cmd_len += 4;
+ *cycles = 6;
+ sprintf (op1, "0x%04x", PS (dst));
+ sprintf (comm1, "PC rel. 0x%04x",
+ PS ((short) addr + 2 + dst));
+ if (extension_word)
+ {
+ dst |= extended_dst << 16;
+ if (dst & 0x80000)
+ dst |= -1U << 20;
+ sprintf (op1, "0x%05x", dst & 0xfffff);
+ sprintf (comm1, "PC rel. 0x%05lx",
+ (long)((addr + 2 + dst) & 0xfffff));
+ }
}
+ else
+ return -1;
}
else if (regd == 2)
{
/* Absolute. */
- dst = msp430dis_opcode (addr + 2, info);
- /* If the 'src' field is not the same as the dst
- then this is not an rla instruction. */
- if (dst != msp430dis_opcode (addr + 4, info))
- return 0;
- cmd_len += 4;
- *cycles = 6;
- sprintf (op1, "&0x%04x", PS (dst));
- if (extension_word)
+ if (msp430dis_opcode_signed (addr + 2, info, &dst, comm1))
{
- dst |= extended_dst << 16;
- sprintf (op1, "&0x%05x", dst & 0xfffff);
+ int src;
+
+ /* If the 'src' field is not the same as the dst
+ then this is not an rla instruction. */
+ if (msp430dis_opcode_signed (addr + 4, info, &src, comm2))
+ {
+ if (src != dst)
+ return 0;
+ }
+ else
+ return -1;
+ cmd_len += 4;
+ *cycles = 6;
+ sprintf (op1, "&0x%04x", PS (dst));
+ if (extension_word)
+ {
+ dst |= extended_dst << 16;
+ sprintf (op1, "&0x%05x", dst & 0xfffff);
+ }
}
+ else
+ return -1;
}
else
{
/* Indexed. */
- dst = msp430dis_opcode (addr + 2, info);
- if (extension_word)
+ if (msp430dis_opcode_signed (addr + 2, info, &dst, comm1))
{
- dst |= extended_dst << 16;
- if (dst & 0x80000)
- dst |= -1U << 20;
+ if (extension_word)
+ {
+ dst |= extended_dst << 16;
+ if (dst & 0x80000)
+ dst |= -1U << 20;
+ }
+ cmd_len += 4;
+ *cycles = 6;
+ sprintf (op1, "%d(r%d)", dst, regd);
+ if (dst > 9 || dst < -9)
+ sprintf (comm1, "#0x%05x", dst);
}
- else if (dst & 0x8000)
- dst |= -1U << 16;
- cmd_len += 4;
- *cycles = 6;
- sprintf (op1, "%d(r%d)", dst, regd);
- if (dst > 9 || dst < -9)
- sprintf (comm1, "#0x%05x", dst);
+ else
+ return -1;
}
}
if (ad == 0 && regd == 3)
{
/* R2/R3 are illegal as dest: may be data section. */
- strcpy (comm1, _("Illegal as 2-op instr"));
+ strcpy (comm1, _("Warning: illegal as 2-op instr"));
return -1;
}
{
*cycles = 3;
/* Absolute. @pc+. */
- dst = msp430dis_opcode (addr + 2, info);
- cmd_len += 2;
- sprintf (op1, "#%d", dst);
- if (dst > 9 || dst < 0)
- sprintf (comm1, "#0x%04x", PS (dst));
- if (extension_word)
+ if (msp430dis_opcode_signed (addr + 2, info, &dst, comm1))
{
- dst |= extended_src << 16;
- if (dst & 0x80000)
- dst |= -1U << 20;
+ cmd_len += 2;
sprintf (op1, "#%d", dst);
if (dst > 9 || dst < 0)
- sprintf (comm1, "0x%05x", dst & 0xfffff);
+ sprintf (comm1, "#0x%04x", PS (dst));
+ if (extension_word)
+ {
+ dst &= 0xffff;
+ dst |= extended_src << 16;
+ if (dst & 0x80000)
+ dst |= -1U << 20;
+ sprintf (op1, "#%d", dst);
+ if (dst > 9 || dst < 0)
+ sprintf (comm1, "0x%05x", dst & 0xfffff);
+ }
}
+ else
+ return -1;
}
else
* cycles = print_as3_reg_name (regs, op1, comm1, 1, 1, 2);
{
*cycles = 4;
/* PC relative. */
- dst = msp430dis_opcode (addr + 2, info);
- cmd_len += 2;
- sprintf (op1, "0x%04x", PS (dst));
- sprintf (comm1, "PC rel. 0x%04x",
- PS ((short) addr + 2 + dst));
- if (extension_word)
+ if (msp430dis_opcode_signed (addr + 2, info, &dst, comm1))
{
- dst |= extended_src << 16;
- if (dst & 0x80000)
- dst |= -1U << 20;
- sprintf (op1, "0x%05x", dst & 0xfffff);
- sprintf (comm1, "PC rel. 0x%05lx",
- (long) ((addr + 2 + dst) & 0xfffff));
+ cmd_len += 2;
+ sprintf (op1, "0x%04x", PS (dst));
+ sprintf (comm1, "PC rel. 0x%04x",
+ PS ((short) addr + 2 + dst));
+ if (extension_word)
+ {
+ dst &= 0xffff;
+ dst |= extended_src << 16;
+ if (dst & 0x80000)
+ dst |= -1U << 20;
+ sprintf (op1, "0x%05x", dst & 0xfffff);
+ sprintf (comm1, "PC rel. 0x%05lx",
+ (long) ((addr + 2 + dst) & 0xfffff));
+ }
}
+ else
+ return -1;
}
else if (regs == 2)
{
*cycles = 2;
/* Absolute. */
- dst = msp430dis_opcode (addr + 2, info);
- cmd_len += 2;
- sprintf (op1, "&0x%04x", PS (dst));
- sprintf (comm1, "0x%04x", PS (dst));
- if (extension_word)
+ if (msp430dis_opcode_signed (addr + 2, info, &dst, comm1))
{
- dst |= extended_src << 16;
- sprintf (op1, "&0x%05x", dst & 0xfffff);
- * comm1 = 0;
+ cmd_len += 2;
+ sprintf (op1, "&0x%04x", PS (dst));
+ sprintf (comm1, "0x%04x", PS (dst));
+ if (extension_word)
+ {
+ dst &= 0xffff;
+ dst |= extended_src << 16;
+ sprintf (op1, "&0x%05x", dst & 0xfffff);
+ * comm1 = 0;
+ }
}
+ else
+ return -1;
}
else if (regs == 3)
{
{
*cycles = 3;
/* Indexed. */
- dst = msp430dis_opcode (addr + 2, info);
- cmd_len += 2;
- if (extension_word)
+ if (msp430dis_opcode_signed (addr + 2, info, &dst, comm1))
{
- dst |= extended_src << 16;
- if (dst & 0x80000)
- dst |= -1U << 20;
+ cmd_len += 2;
+ if (extension_word)
+ {
+ dst &= 0xffff;
+ dst |= extended_src << 16;
+ if (dst & 0x80000)
+ dst |= -1U << 20;
+ }
+ sprintf (op1, "%d(r%d)", dst, regs);
+ if (dst > 9 || dst < -9)
+ sprintf (comm1, "0x%05x", dst);
}
- else if (dst & 0x8000)
- dst |= -1U << 16;
- sprintf (op1, "%d(r%d)", dst, regs);
- if (dst > 9 || dst < -9)
- sprintf (comm1, "0x%05x", dst);
+ else
+ return -1;
}
}
{
/* PC relative. */
*cycles += 1;
- dst = msp430dis_opcode (addr + cmd_len, info);
- sprintf (op2, "0x%04x", PS (dst));
- sprintf (comm2, "PC rel. 0x%04x",
- PS ((short) addr + cmd_len + dst));
- if (extension_word)
+ if (msp430dis_opcode_signed (addr + cmd_len, info, &dst, comm2))
{
- dst |= extended_dst << 16;
- if (dst & 0x80000)
- dst |= -1U << 20;
- sprintf (op2, "0x%05x", dst & 0xfffff);
- sprintf (comm2, "PC rel. 0x%05lx",
- (long)((addr + cmd_len + dst) & 0xfffff));
+ sprintf (op2, "0x%04x", PS (dst));
+ sprintf (comm2, "PC rel. 0x%04x",
+ PS ((short) addr + cmd_len + dst));
+ if (extension_word)
+ {
+ dst |= extended_dst << 16;
+ if (dst & 0x80000)
+ dst |= -1U << 20;
+ sprintf (op2, "0x%05x", dst & 0xfffff);
+ sprintf (comm2, "PC rel. 0x%05lx",
+ (long)((addr + cmd_len + dst) & 0xfffff));
+ }
}
+ else
+ return -1;
cmd_len += 2;
}
else if (regd == 2)
{
/* Absolute. */
- dst = msp430dis_opcode (addr + cmd_len, info);
- cmd_len += 2;
- sprintf (op2, "&0x%04x", PS (dst));
- if (extension_word)
+ if (msp430dis_opcode_signed (addr + cmd_len, info, &dst, comm2))
{
- dst |= extended_dst << 16;
- sprintf (op2, "&0x%05x", dst & 0xfffff);
+ cmd_len += 2;
+ sprintf (op2, "&0x%04x", PS (dst));
+ if (extension_word)
+ {
+ dst |= extended_dst << 16;
+ sprintf (op2, "&0x%05x", dst & 0xfffff);
+ }
}
+ else
+ return -1;
}
else
{
- dst = msp430dis_opcode (addr + cmd_len, info);
- cmd_len += 2;
- if (dst & 0x8000)
- dst |= -1U << 16;
- if (dst > 9 || dst < 0)
- sprintf (comm2, "0x%04x", PS (dst));
- if (extension_word)
+ if (msp430dis_opcode_signed (addr + cmd_len, info, &dst, comm2))
{
- dst |= extended_dst << 16;
- if (dst & 0x80000)
- dst |= -1U << 20;
+ cmd_len += 2;
if (dst > 9 || dst < 0)
- sprintf (comm2, "0x%05x", dst & 0xfffff);
+ sprintf (comm2, "0x%04x", PS (dst));
+ if (extension_word)
+ {
+ dst |= extended_dst << 16;
+ if (dst & 0x80000)
+ dst |= -1U << 20;
+ if (dst > 9 || dst < 0)
+ sprintf (comm2, "0x%05x", dst & 0xfffff);
+ }
+ sprintf (op2, "%d(r%d)", dst, regd);
}
- sprintf (op2, "%d(r%d)", dst, regd);
+ else
+ return -1;
}
}
int regs = 0, regd = 0;
int as = 0;
int cmd_len = 2;
- short dst = 0;
+ int dst = 0;
+ unsigned short udst = 0;
regd = insn & 0x0f;
regs = (insn & 0x0f00) >> 8;
{
/* Absolute. @pc+ */
*cycles = 3;
- dst = msp430dis_opcode (addr + 2, info);
- cmd_len += 2;
- sprintf (op1, "#0x%04x", PS (dst));
+ if (msp430dis_opcode_unsigned (addr + 2, info, &udst, comm1))
+ {
+ cmd_len += 2;
+ sprintf (op1, "#0x%04x", PS (udst));
+ }
+ else
+ return -1;
}
else
* cycles = print_as3_reg_name (regs, op1, comm1, 1, 1, 2);
if (regs == 0)
{
/* PC relative. */
- dst = msp430dis_opcode (addr + 2, info);
- cmd_len += 2;
- (*cycles)++;
- sprintf (op1, "0x%04x", PS (dst));
- sprintf (comm1, "PC rel. 0x%04x",
- PS ((short) addr + 2 + dst));
+ if (msp430dis_opcode_signed (addr + 2, info, &dst, comm1))
+ {
+ cmd_len += 2;
+ (*cycles)++;
+ sprintf (op1, "0x%04x", PS (dst));
+ sprintf (comm1, "PC rel. 0x%04x",
+ PS ((short) addr + 2 + dst));
+ }
+ else
+ return -1;
}
else if (regs == 2)
{
/* Absolute. */
- dst = msp430dis_opcode (addr + 2, info);
- cmd_len += 2;
- sprintf (op1, "&0x%04x", PS (dst));
+ if (msp430dis_opcode_unsigned (addr + 2, info, &udst, comm1))
+ {
+ cmd_len += 2;
+ sprintf (op1, "&0x%04x", PS (udst));
+ }
+ else
+ return -1;
}
else if (regs == 3)
{
else
{
/* Indexed. */
- dst = msp430dis_opcode (addr + 2, info);
- cmd_len += 2;
- if (dst & 0x8000)
- dst |= -1U << 16;
- sprintf (op1, "%d(r%d)", dst, regs);
+ if (msp430dis_opcode_signed (addr + 2, info, &dst, comm1))
+ {
+ cmd_len += 2;
+ sprintf (op1, "%d(r%d)", dst, regs);
+ }
+ else
+ return -1;
}
}
int am = (insn & 0xf0) >> 4;
int cmd_len = 2;
unsigned short udst = 0;
- short dst = 0;
+ int dst = 0;
switch (am)
{
case 5: /* CALLA x(Rdst) */
*cycles = 3;
- dst = msp430dis_opcode (addr + 2, info);
- cmd_len += 2;
- sprintf (op1, "%d(r%d)", dst, reg);
- if (reg == 0)
- sprintf (comm1, "PC rel. 0x%05lx", (long) (addr + 2 + dst));
+ if (msp430dis_opcode_signed (addr + 2, info, &dst, comm1))
+ {
+ cmd_len += 2;
+ sprintf (op1, "%d(r%d)", dst, reg);
+ if (reg == 0)
+ sprintf (comm1, "PC rel. 0x%05lx", (long) (addr + 2 + dst));
+ else
+ sprintf (comm1, "0x%05x", dst);
+ }
else
- sprintf (comm1, "0x%05x", dst);
+ return -1;
break;
case 6: /* CALLA @Rdst */
break;
case 8: /* CALLA &abs20 */
- udst = msp430dis_opcode (addr + 2, info);
- cmd_len += 2;
- *cycles = 4;
- sprintf (op1, "&%d", (ureg << 16) + udst);
- sprintf (comm1, "0x%05x", (ureg << 16) + udst);
+ if (msp430dis_opcode_unsigned (addr + 2, info, &udst, comm1))
+ {
+ cmd_len += 2;
+ *cycles = 4;
+ sprintf (op1, "&%d", (ureg << 16) + udst);
+ sprintf (comm1, "0x%05x", (ureg << 16) + udst);
+ }
+ else
+ return -1;
break;
case 9: /* CALLA pcrel-sym */
- dst = msp430dis_opcode (addr + 2, info);
- cmd_len += 2;
- *cycles = 4;
- sprintf (op1, "%d(PC)", (reg << 16) + dst);
- sprintf (comm1, "PC rel. 0x%05lx",
- (long) (addr + 2 + dst + (reg << 16)));
+ if (msp430dis_opcode_signed (addr + 2, info, &dst, comm1))
+ {
+ cmd_len += 2;
+ *cycles = 4;
+ sprintf (op1, "%d(PC)", (reg << 16) + dst);
+ sprintf (comm1, "PC rel. 0x%05lx",
+ (long) (addr + 2 + dst + (reg << 16)));
+ }
+ else
+ return -1;
break;
case 11: /* CALLA #imm20 */
- udst = msp430dis_opcode (addr + 2, info);
- cmd_len += 2;
- *cycles = 4;
- sprintf (op1, "#%d", (ureg << 16) + udst);
- sprintf (comm1, "0x%05x", (ureg << 16) + udst);
+ if (msp430dis_opcode_unsigned (addr + 2, info, &udst, comm1))
+ {
+ cmd_len += 2;
+ *cycles = 4;
+ sprintf (op1, "#%d", (ureg << 16) + udst);
+ sprintf (comm1, "0x%05x", (ureg << 16) + udst);
+ }
+ else
+ return -1;
break;
default:
- strcpy (comm1, _("unrecognised CALLA addressing mode"));
+ strcpy (comm1, _("Warning: unrecognised CALLA addressing mode"));
return -1;
}
int cycles = 0;
char *bc = "";
unsigned short extension_word = 0;
+ unsigned short bits;
- insn = msp430dis_opcode (addr, info);
- if (insn == (unsigned short) -1)
- {
- prin (stream, ".word 0xffff; ????");
- return 2;
- }
+ if (! msp430dis_opcode_unsigned (addr, info, &insn, NULL))
+ return -1;
if (((int) addr & 0xffff) > 0xffdf)
{
{
extension_word = insn;
addr += 2;
- insn = msp430dis_opcode (addr, info);
- if (insn == (unsigned short) -1)
- {
- prin (stream, ".word 0x%04x, 0xffff; ????",
- extension_word);
- return 4;
- }
+ if (! msp430dis_opcode_unsigned (addr, info, &insn, NULL))
+ return -1;
}
for (opcode = msp430_opcodes; opcode->name; opcode++)
&& (insn & 0x000f) == 0
&& (insn & 0x0080) == 0)
{
- cmd_len +=
+ int ret =
msp430_branchinstr (info, opcode, addr, insn, op1, comm1,
&cycles);
+
+ if (ret == -1)
+ return -1;
+ cmd_len += ret;
if (cmd_len)
break;
}
{
int n;
int reg;
+ int ret;
case 4:
- cmd_len += msp430x_calla_instr (info, addr, insn,
- op1, comm1, & cycles);
+ ret = msp430x_calla_instr (info, addr, insn,
+ op1, comm1, & cycles);
+ if (ret == -1)
+ return -1;
+ cmd_len += ret;
break;
case 5: /* PUSHM/POPM */
else
{
n <<= 16;
- n |= msp430dis_opcode (addr + 2, info);
- sprintf (op1, "#%d", n);
- if (n > 9 || n < 0)
- sprintf (comm1, "0x%05x", n);
+ if (msp430dis_opcode_unsigned (addr + 2, info, &bits, comm1))
+ {
+ n |= bits;
+ sprintf (op1, "#%d", n);
+ if (n > 9 || n < 0)
+ sprintf (comm1, "0x%05x", n);
+ }
+ else
+ return -1;
cmd_len = 4;
}
sprintf (op2, "r%d", reg);
case 2: /* MOVA &abs20, Rdst */
cmd_len = 4;
n <<= 16;
- n |= msp430dis_opcode (addr + 2, info);
- sprintf (op1, "&%d", n);
- if (n > 9 || n < 0)
- sprintf (comm1, "0x%05x", n);
- if (strcmp (opcode->name, "bra") != 0)
- sprintf (op2, "r%d", reg);
+ if (msp430dis_opcode_unsigned (addr + 2, info, &bits, comm1))
+ {
+ n |= bits;
+ sprintf (op1, "&%d", n);
+ if (n > 9 || n < 0)
+ sprintf (comm1, "0x%05x", n);
+ if (strcmp (opcode->name, "bra") != 0)
+ sprintf (op2, "r%d", reg);
+ }
+ else
+ return -1;
break;
case 3: /* MOVA x(Rsrc), Rdst */
if (strcmp (opcode->name, "bra") != 0)
sprintf (op2, "r%d", reg);
reg = n;
- n = msp430dis_opcode (addr + 2, info);
- if (n & 0x8000)
- n |= -1U << 16;
- sprintf (op1, "%d(r%d)", n, reg);
- if (n > 9 || n < 0)
+ if (msp430dis_opcode_signed (addr + 2, info, &n, comm1))
{
- if (reg == 0)
- sprintf (comm1, "PC rel. 0x%05lx",
- (long) (addr + 2 + n));
- else
- sprintf (comm1, "0x%05x", n);
+ sprintf (op1, "%d(r%d)", n, reg);
+ if (n > 9 || n < 0)
+ {
+ if (reg == 0)
+ sprintf (comm1, "PC rel. 0x%05lx",
+ (long) (addr + 2 + n));
+ else
+ sprintf (comm1, "0x%05x", n);
+ }
}
+ else
+ return -1;
break;
case 6: /* MOVA Rsrc, &abs20 */
cmd_len = 4;
reg <<= 16;
- reg |= msp430dis_opcode (addr + 2, info);
- sprintf (op1, "r%d", n);
- sprintf (op2, "&%d", reg);
- if (reg > 9 || reg < 0)
- sprintf (comm2, "0x%05x", reg);
+ if (msp430dis_opcode_unsigned (addr + 2, info, &bits, comm2))
+ {
+ reg |= bits;
+ sprintf (op1, "r%d", n);
+ sprintf (op2, "&%d", reg);
+ if (reg > 9 || reg < 0)
+ sprintf (comm2, "0x%05x", reg);
+ }
+ else
+ return -1;
break;
case 7: /* MOVA Rsrc, x(Rdst) */
cmd_len = 4;
sprintf (op1, "r%d", n);
- n = msp430dis_opcode (addr + 2, info);
- if (n & 0x8000)
- n |= -1U << 16;
- sprintf (op2, "%d(r%d)", n, reg);
- if (n > 9 || n < 0)
+ if (msp430dis_opcode_signed (addr + 2, info, &n, comm2))
{
- if (reg == 0)
- sprintf (comm2, "PC rel. 0x%05lx",
- (long) (addr + 2 + n));
- else
- sprintf (comm2, "0x%05x", n);
+ sprintf (op2, "%d(r%d)", n, reg);
+ if (n > 9 || n < 0)
+ {
+ if (reg == 0)
+ sprintf (comm2, "PC rel. 0x%05lx",
+ (long) (addr + 2 + n));
+ else
+ sprintf (comm2, "0x%05x", n);
+ }
}
+ else
+ return -1;
break;
case 8: /* MOVA #imm20, Rdst */
cmd_len = 4;
n <<= 16;
- n |= msp430dis_opcode (addr + 2, info);
- if (n & 0x80000)
- n |= -1U << 20;
- sprintf (op1, "#%d", n);
- if (n > 9 || n < 0)
- sprintf (comm1, "0x%05x", n);
- if (strcmp (opcode->name, "bra") != 0)
- sprintf (op2, "r%d", reg);
+ if (msp430dis_opcode_unsigned (addr + 2, info, &bits, comm1))
+ {
+ n |= bits;
+ if (n & 0x80000)
+ n |= -1U << 20;
+ sprintf (op1, "#%d", n);
+ if (n > 9 || n < 0)
+ sprintf (comm1, "0x%05x", n);
+ if (strcmp (opcode->name, "bra") != 0)
+ sprintf (op2, "r%d", reg);
+ }
+ else
+ return -1;
break;
case 12: /* MOVA Rsrc, Rdst */
switch (opcode->insn_opnumb)
{
+ int ret;
+
case 0:
cmd_len += msp430_nooperands (opcode, addr, insn, comm1, &cycles);
break;
case 2:
- cmd_len +=
+ ret =
msp430_doubleoperand (info, opcode, addr, insn, op1, op2,
comm1, comm2,
extension_word,
&cycles);
+
+ if (ret == -1)
+ return -1;
+ cmd_len += ret;
if (insn & BYTE_OPERATION)
{
if (extension_word != 0 && ((extension_word & BYTE_OPERATION) == 0))
}
else if (extension_word)
{
- if (extension_word & (1 << 6))
+ if (extension_word & BYTE_OPERATION)
bc = ".w";
else
{
bc = ".?";
- sprintf (comm2, _("Reserved use of A/L and B/W bits detected"));
+ sprintf (comm2, _("Warning: reserved use of A/L and B/W bits detected"));
}
}
break;
case 1:
- cmd_len +=
+ ret =
msp430_singleoperand (info, opcode, addr, insn, op1, comm1,
extension_word,
&cycles);
+
+ if (ret == -1)
+ return -1;
+ cmd_len += ret;
if (extension_word
&& (strcmp (opcode->name, "swpb") == 0
|| strcmp (opcode->name, "sxt") == 0))
if (insn & BYTE_OPERATION)
{
bc = ".?";
- sprintf (comm2, _("Reserved use of A/L and B/W bits detected"));
+ sprintf (comm2, _("Warning: reserved use of A/L and B/W bits detected"));
}
else if (extension_word & BYTE_OPERATION)
bc = ".w";
else
{
bc = ".?";
- sprintf (comm2, _("Reserved use of A/L and B/W bits detected"));
+ sprintf (comm2, _("Warning: reserved use of A/L and B/W bits detected"));
}
}
break;
prin (stream, "rpt #%d { ", (extension_word & 0xf) + 1);
}
- if (extension_word && opcode->name[strlen (opcode->name) - 1] != 'x')
+ /* Special case: RRC with an extension word and the ZC bit set is actually RRU. */
+ if (extension_word
+ && (extension_word & IGNORE_CARRY_BIT)
+ && strcmp (opcode->name, "rrc") == 0)
+ (*prin) (stream, "rrux%s", bc);
+ else if (extension_word && opcode->name[strlen (opcode->name) - 1] != 'x')
(*prin) (stream, "%sx%s", opcode->name, bc);
else
(*prin) (stream, "%s%s", opcode->name, bc);
projects / deliverable / binutils-gdb.git / blobdiff