/* Print SPARC instructions.
- Copyright (C) 1989, 91-97, 1998 Free Software Foundation, Inc.
+ Copyright (C) 1989-2020 Free Software Foundation, Inc.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+ This file is part of the GNU opcodes library.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
-#include <stdio.h>
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
-#include "ansidecl.h"
#include "sysdep.h"
+#include <stdio.h>
#include "opcode/sparc.h"
#include "dis-asm.h"
#include "libiberty.h"
/* Bitmask of v9 architectures. */
#define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
- | (1 << SPARC_OPCODE_ARCH_V9A))
+ | (1 << SPARC_OPCODE_ARCH_V9A) \
+ | (1 << SPARC_OPCODE_ARCH_V9B) \
+ | (1 << SPARC_OPCODE_ARCH_V9C) \
+ | (1 << SPARC_OPCODE_ARCH_V9D) \
+ | (1 << SPARC_OPCODE_ARCH_V9E) \
+ | (1 << SPARC_OPCODE_ARCH_V9V) \
+ | (1 << SPARC_OPCODE_ARCH_V9M) \
+ | (1 << SPARC_OPCODE_ARCH_M8))
/* 1 if INSN is for v9 only. */
#define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
/* 1 if INSN is for v9. */
#define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
/* The sorted opcode table. */
-static const struct sparc_opcode **sorted_opcodes;
+static const sparc_opcode **sorted_opcodes;
/* For faster lookup, after insns are sorted they are hashed. */
/* ??? I think there is room for even more improvement. */
static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
#define HASH_INSN(INSN) \
((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
-struct opcode_hash {
- struct opcode_hash *next;
- const struct sparc_opcode *opcode;
-};
-static struct opcode_hash *opcode_hash_table[HASH_SIZE];
+typedef struct sparc_opcode_hash
+{
+ struct sparc_opcode_hash *next;
+ const sparc_opcode *opcode;
+} sparc_opcode_hash;
-static void build_hash_table
- PARAMS ((const struct sparc_opcode **, struct opcode_hash **, int));
-static int is_delayed_branch PARAMS ((unsigned long));
-static int compare_opcodes PARAMS ((const PTR, const PTR));
-static int compute_arch_mask PARAMS ((unsigned long));
+static sparc_opcode_hash *opcode_hash_table[HASH_SIZE];
/* Sign-extend a value which is N bits long. */
#define SEX(value, bits) \
- ((((int)(value)) << ((8 * sizeof (int)) - bits)) \
- >> ((8 * sizeof (int)) - bits) )
+ ((int) (((value & ((1u << (bits - 1) << 1) - 1)) \
+ ^ (1u << (bits - 1))) - (1u << (bits - 1))))
static char *reg_names[] =
-{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
- "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
- "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
- "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
- "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
- "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
+{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
+ "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
+ "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
+ "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
+ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
- "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
- "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
+ "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
+ "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
"f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
"f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
/* psr, wim, tbr, fpsr, cpsr are v8 only. */
{
"tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
"pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
- "wstate", "fq"
- /* "ver" - special cased */
+ "wstate", "fq", "gl"
+ /* "ver" and "pmcdper" - special cased */
+};
+
+/* These are ordered according to there register number in
+ rdhpr and wrhpr insns. */
+static char *v9_hpriv_reg_names[] =
+{
+ "hpstate", "htstate", "resv2", "hintp", "resv4", "htba", "hver",
+ "resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13",
+ "resv14", "resv15", "resv16", "resv17", "resv18", "resv19", "resv20",
+ "resv21", "resv22", "hmcdper", "hmcddfr", "resv25", "resv26", "hva_mask_nz",
+ "hstick_offset", "hstick_enable", "resv30", "hstick_cmpr"
};
/* These are ordered according to there register number in
rd and wr insns (-16). */
static char *v9a_asr_reg_names[] =
{
- "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
- "softint", "tick_cmpr"
+ "pcr", "pic", "dcr", "gsr", "softint_set", "softint_clear",
+ "softint", "tick_cmpr", "stick", "stick_cmpr", "cfr",
+ "pause", "mwait"
};
/* Macros used to extract instruction fields. Not all fields have
macros defined here, only those which are actually used. */
-#define X_RD(i) (((i) >> 25) & 0x1f)
-#define X_RS1(i) (((i) >> 14) & 0x1f)
-#define X_LDST_I(i) (((i) >> 13) & 1)
-#define X_ASI(i) (((i) >> 5) & 0xff)
-#define X_RS2(i) (((i) >> 0) & 0x1f)
-#define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
-#define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
-#define X_DISP22(i) (((i) >> 0) & 0x3fffff)
-#define X_IMM22(i) X_DISP22 (i)
-#define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
+#define X_RD(i) (((i) >> 25) & 0x1f)
+#define X_RS1(i) (((i) >> 14) & 0x1f)
+#define X_LDST_I(i) (((i) >> 13) & 1)
+#define X_ASI(i) (((i) >> 5) & 0xff)
+#define X_RS2(i) (((i) >> 0) & 0x1f)
+#define X_RS3(i) (((i) >> 9) & 0x1f)
+#define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
+#define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
+#define X_DISP22(i) (((i) >> 0) & 0x3fffff)
+#define X_IMM22(i) X_DISP22 (i)
+#define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
+#define X_IMM2(i) (((i & 0x10) >> 3) | (i & 0x1))
/* These are for v9. */
-#define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
-#define X_DISP19(i) (((i) >> 0) & 0x7ffff)
-#define X_MEMBAR(i) ((i) & 0x7f)
+#define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
+#define X_DISP10(i) (((((i) >> 19) & 3) << 8) | (((i) >> 5) & 0xff))
+#define X_DISP19(i) (((i) >> 0) & 0x7ffff)
+#define X_MEMBAR(i) ((i) & 0x7f)
/* Here is the union which was used to extract instruction fields
before the shift and mask macros were written.
unsigned int adisp30:30;
#define disp30 call.adisp30
} call;
- };
-
- */
+ }; */
/* Nonzero if INSN is the opcode for a delayed branch. */
+
static int
-is_delayed_branch (insn)
- unsigned long insn;
+is_delayed_branch (unsigned long insn)
{
- struct opcode_hash *op;
+ sparc_opcode_hash *op;
for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
{
- CONST struct sparc_opcode *opcode = op->opcode;
+ const sparc_opcode *opcode = op->opcode;
+
if ((opcode->match & insn) == opcode->match
&& (opcode->lose & insn) == 0)
- return (opcode->flags & F_DELAYED);
+ return opcode->flags & F_DELAYED;
}
return 0;
}
to compare_opcodes. */
static unsigned int current_arch_mask;
+/* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */
+
+static int
+compute_arch_mask (unsigned long mach)
+{
+ switch (mach)
+ {
+ case 0 :
+ case bfd_mach_sparc :
+ return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
+ | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_LEON));
+ case bfd_mach_sparc_sparclet :
+ return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
+ case bfd_mach_sparc_sparclite :
+ case bfd_mach_sparc_sparclite_le :
+ /* sparclites insns are recognized by default (because that's how
+ they've always been treated, for better or worse). Kludge this by
+ indicating generic v8 is also selected. */
+ return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
+ | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
+ case bfd_mach_sparc_v8plus :
+ case bfd_mach_sparc_v9 :
+ return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
+ case bfd_mach_sparc_v8plusa :
+ case bfd_mach_sparc_v9a :
+ return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
+ case bfd_mach_sparc_v8plusb :
+ case bfd_mach_sparc_v9b :
+ return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
+ case bfd_mach_sparc_v8plusc :
+ case bfd_mach_sparc_v9c :
+ return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9C);
+ case bfd_mach_sparc_v8plusd :
+ case bfd_mach_sparc_v9d :
+ return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9D);
+ case bfd_mach_sparc_v8pluse :
+ case bfd_mach_sparc_v9e :
+ return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9E);
+ case bfd_mach_sparc_v8plusv :
+ case bfd_mach_sparc_v9v :
+ return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9V);
+ case bfd_mach_sparc_v8plusm :
+ case bfd_mach_sparc_v9m :
+ return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9M);
+ case bfd_mach_sparc_v8plusm8 :
+ case bfd_mach_sparc_v9m8 :
+ return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_M8);
+ }
+ abort ();
+}
+
+/* Compare opcodes A and B. */
+
+static int
+compare_opcodes (const void * a, const void * b)
+{
+ sparc_opcode *op0 = * (sparc_opcode **) a;
+ sparc_opcode *op1 = * (sparc_opcode **) b;
+ unsigned long int match0 = op0->match, match1 = op1->match;
+ unsigned long int lose0 = op0->lose, lose1 = op1->lose;
+ register unsigned int i;
+
+ /* If one (and only one) insn isn't supported by the current architecture,
+ prefer the one that is. If neither are supported, but they're both for
+ the same architecture, continue processing. Otherwise (both unsupported
+ and for different architectures), prefer lower numbered arch's (fudged
+ by comparing the bitmasks). */
+ if (op0->architecture & current_arch_mask)
+ {
+ if (! (op1->architecture & current_arch_mask))
+ return -1;
+ }
+ else
+ {
+ if (op1->architecture & current_arch_mask)
+ return 1;
+ else if (op0->architecture != op1->architecture)
+ return op0->architecture - op1->architecture;
+ }
+
+ /* If a bit is set in both match and lose, there is something
+ wrong with the opcode table. */
+ if (match0 & lose0)
+ {
+ opcodes_error_handler
+ /* xgettext:c-format */
+ (_("internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
+ op0->name, match0, lose0);
+ op0->lose &= ~op0->match;
+ lose0 = op0->lose;
+ }
+
+ if (match1 & lose1)
+ {
+ opcodes_error_handler
+ /* xgettext:c-format */
+ (_("internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
+ op1->name, match1, lose1);
+ op1->lose &= ~op1->match;
+ lose1 = op1->lose;
+ }
+
+ /* Because the bits that are variable in one opcode are constant in
+ another, it is important to order the opcodes in the right order. */
+ for (i = 0; i < 32; ++i)
+ {
+ unsigned long int x = 1ul << i;
+ int x0 = (match0 & x) != 0;
+ int x1 = (match1 & x) != 0;
+
+ if (x0 != x1)
+ return x1 - x0;
+ }
+
+ for (i = 0; i < 32; ++i)
+ {
+ unsigned long int x = 1ul << i;
+ int x0 = (lose0 & x) != 0;
+ int x1 = (lose1 & x) != 0;
+
+ if (x0 != x1)
+ return x1 - x0;
+ }
+
+ /* They are functionally equal. So as long as the opcode table is
+ valid, we can put whichever one first we want, on aesthetic grounds. */
+
+ /* Our first aesthetic ground is that aliases defer to real insns. */
+ {
+ int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
+
+ if (alias_diff != 0)
+ /* Put the one that isn't an alias first. */
+ return alias_diff;
+ }
+
+ /* Except for aliases, two "identical" instructions had
+ better have the same opcode. This is a sanity check on the table. */
+ i = strcmp (op0->name, op1->name);
+ if (i)
+ {
+ if (op0->flags & F_ALIAS)
+ {
+ if (op0->flags & F_PREFERRED)
+ return -1;
+ if (op1->flags & F_PREFERRED)
+ return 1;
+
+ /* If they're both aliases, and neither is marked as preferred,
+ be arbitrary. */
+ return i;
+ }
+ else
+ opcodes_error_handler
+ /* xgettext:c-format */
+ (_("internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
+ op0->name, op1->name);
+ }
+
+ /* Fewer arguments are preferred. */
+ {
+ int length_diff = strlen (op0->args) - strlen (op1->args);
+
+ if (length_diff != 0)
+ /* Put the one with fewer arguments first. */
+ return length_diff;
+ }
+
+ /* Put 1+i before i+1. */
+ {
+ char *p0 = (char *) strchr (op0->args, '+');
+ char *p1 = (char *) strchr (op1->args, '+');
+
+ if (p0 && p1)
+ {
+ /* There is a plus in both operands. Note that a plus
+ sign cannot be the first character in args,
+ so the following [-1]'s are valid. */
+ if (p0[-1] == 'i' && p1[1] == 'i')
+ /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
+ return 1;
+ if (p0[1] == 'i' && p1[-1] == 'i')
+ /* op0 is 1+i and op1 is i+1, so op0 goes first. */
+ return -1;
+ }
+ }
+
+ /* Put 1,i before i,1. */
+ {
+ int i0 = strncmp (op0->args, "i,1", 3) == 0;
+ int i1 = strncmp (op1->args, "i,1", 3) == 0;
+
+ if (i0 ^ i1)
+ return i0 - i1;
+ }
+
+ /* They are, as far as we can tell, identical.
+ Since qsort may have rearranged the table partially, there is
+ no way to tell which one was first in the opcode table as
+ written, so just say there are equal. */
+ /* ??? This is no longer true now that we sort a vector of pointers,
+ not the table itself. */
+ return 0;
+}
+
+/* Build a hash table from the opcode table.
+ OPCODE_TABLE is a sorted list of pointers into the opcode table. */
+
+static void
+build_hash_table (const sparc_opcode **opcode_table,
+ sparc_opcode_hash **hash_table,
+ int num_opcodes)
+{
+ int i;
+ int hash_count[HASH_SIZE];
+ static sparc_opcode_hash *hash_buf = NULL;
+
+ /* Start at the end of the table and work backwards so that each
+ chain is sorted. */
+
+ memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
+ memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
+ free (hash_buf);
+ hash_buf = xmalloc (sizeof (* hash_buf) * num_opcodes);
+ for (i = num_opcodes - 1; i >= 0; --i)
+ {
+ int hash = HASH_INSN (opcode_table[i]->match);
+ sparc_opcode_hash *h = &hash_buf[i];
+
+ h->next = hash_table[hash];
+ h->opcode = opcode_table[i];
+ hash_table[hash] = h;
+ ++hash_count[hash];
+ }
+
+#if 0 /* for debugging */
+ {
+ int min_count = num_opcodes, max_count = 0;
+ int total;
+
+ for (i = 0; i < HASH_SIZE; ++i)
+ {
+ if (hash_count[i] < min_count)
+ min_count = hash_count[i];
+ if (hash_count[i] > max_count)
+ max_count = hash_count[i];
+ total += hash_count[i];
+ }
+
+ printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
+ min_count, max_count, (double) total / HASH_SIZE);
+ }
+#endif
+}
+
/* Print one instruction from MEMADDR on INFO->STREAM.
We suffix the instruction with a comment that gives the absolute
on that register. */
int
-print_insn_sparc (memaddr, info)
- bfd_vma memaddr;
- disassemble_info *info;
+print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
{
FILE *stream = info->stream;
bfd_byte buffer[4];
unsigned long insn;
- register struct opcode_hash *op;
+ sparc_opcode_hash *op;
/* Nonzero of opcode table has been initialized. */
static int opcodes_initialized = 0;
/* bfd mach number of last call. */
static unsigned long current_mach = 0;
- bfd_vma (*getword) PARAMS ((const unsigned char *));
+ bfd_vma (*getword) (const void *);
if (!opcodes_initialized
|| info->mach != current_mach)
current_arch_mask = compute_arch_mask (info->mach);
if (!opcodes_initialized)
- sorted_opcodes = (const struct sparc_opcode **)
- xmalloc (sparc_num_opcodes * sizeof (struct sparc_opcode *));
+ sorted_opcodes =
+ xmalloc (sparc_num_opcodes * sizeof (sparc_opcode *));
/* Reset the sorted table so we can resort it. */
for (i = 0; i < sparc_num_opcodes; ++i)
sorted_opcodes[i] = &sparc_opcodes[i];
{
int status =
(*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
+
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
}
/* On SPARClite variants such as DANlite (sparc86x), instructions
- are always big-endian even when the machine is in little-endian mode. */
+ are always big-endian even when the machine is in little-endian mode. */
if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite)
getword = bfd_getb32;
else
insn = getword (buffer);
- info->insn_info_valid = 1; /* We do return this info */
- info->insn_type = dis_nonbranch; /* Assume non branch insn */
- info->branch_delay_insns = 0; /* Assume no delay */
- info->target = 0; /* Assume no target known */
+ info->insn_info_valid = 1; /* We do return this info. */
+ info->insn_type = dis_nonbranch; /* Assume non branch insn. */
+ info->branch_delay_insns = 0; /* Assume no delay. */
+ info->target = 0; /* Assume no target known. */
for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
{
- CONST struct sparc_opcode *opcode = op->opcode;
+ const sparc_opcode *opcode = op->opcode;
/* If the insn isn't supported by the current architecture, skip it. */
if (! (opcode->architecture & current_arch_mask))
/* Nonzero means that we have found an instruction which has
the effect of adding or or'ing the imm13 field to rs1. */
int imm_added_to_rs1 = 0;
+ int imm_ored_to_rs1 = 0;
/* Nonzero means that we have found a plus sign in the args
field of the opcode table. */
int found_plus = 0;
-
+
/* Nonzero means we have an annulled branch. */
int is_annulled = 0;
/* Do we have an `add' or `or' instruction combining an
immediate with rs1? */
- if (opcode->match == 0x80102000 || opcode->match == 0x80002000)
- /* (or) (add) */
+ if (opcode->match == 0x80102000) /* or */
+ imm_ored_to_rs1 = 1;
+ if (opcode->match == 0x80002000) /* add */
imm_added_to_rs1 = 1;
if (X_RS1 (insn) != X_RD (insn)
/* Can't do simple format if source and dest are different. */
continue;
- (*info->fprintf_func) (stream, opcode->name);
+ (*info->fprintf_func) (stream, "%s", opcode->name);
{
- register CONST char *s;
+ const char *s;
if (opcode->args[0] != ',')
(*info->fprintf_func) (stream, " ");
+
for (s = opcode->args; *s != '\0'; ++s)
{
while (*s == ',')
{
(*info->fprintf_func) (stream, ",");
++s;
- switch (*s) {
- case 'a':
- (*info->fprintf_func) (stream, "a");
- is_annulled = 1;
- ++s;
- continue;
- case 'N':
- (*info->fprintf_func) (stream, "pn");
- ++s;
- continue;
-
- case 'T':
- (*info->fprintf_func) (stream, "pt");
- ++s;
- continue;
-
- default:
- break;
- } /* switch on arg */
- } /* while there are comma started args */
+ switch (*s)
+ {
+ case 'a':
+ (*info->fprintf_func) (stream, "a");
+ is_annulled = 1;
+ ++s;
+ continue;
+ case 'N':
+ (*info->fprintf_func) (stream, "pn");
+ ++s;
+ continue;
+
+ case 'T':
+ (*info->fprintf_func) (stream, "pt");
+ ++s;
+ continue;
+
+ default:
+ break;
+ }
+ }
(*info->fprintf_func) (stream, " ");
-
+
switch (*s)
{
case '+':
found_plus = 1;
+ /* Fall through. */
- /* note fall-through */
default:
(*info->fprintf_func) (stream, "%c", *s);
break;
case 'e':
freg (X_RS1 (insn));
break;
- case 'v': /* double/even */
- case 'V': /* quad/multiple of 4 */
+ case 'v': /* Double/even. */
+ case 'V': /* Quad/multiple of 4. */
+ case ';': /* Double/even multiple of 8 doubles. */
fregx (X_RS1 (insn));
break;
case 'f':
freg (X_RS2 (insn));
break;
- case 'B': /* double/even */
- case 'R': /* quad/multiple of 4 */
+ case 'B': /* Double/even. */
+ case 'R': /* Quad/multiple of 4. */
+ case ':': /* Double/even multiple of 8 doubles. */
fregx (X_RS2 (insn));
break;
+ case '4':
+ freg (X_RS3 (insn));
+ break;
+ case '5': /* Double/even. */
+ fregx (X_RS3 (insn));
+ break;
+
case 'g':
freg (X_RD (insn));
break;
- case 'H': /* double/even */
- case 'J': /* quad/multiple of 4 */
+ case 'H': /* Double/even. */
+ case 'J': /* Quad/multiple of 4. */
+ case '}': /* Double/even. */
fregx (X_RD (insn));
break;
+
+ case '^': /* Double/even multiple of 8 doubles. */
+ fregx (X_RD (insn) & ~0x6);
+ break;
+
+ case '\'': /* Double/even in FPCMPSHL. */
+ fregx (X_RS2 (insn | 0x11));
+ break;
+
#undef freg
#undef fregx
case 'h':
(*info->fprintf_func) (stream, "%%hi(%#x)",
- (0xFFFFFFFF
- & ((int) X_IMM22 (insn) << 10)));
+ (unsigned) X_IMM22 (insn) << 10);
break;
- case 'i': /* 13 bit immediate */
- case 'I': /* 11 bit immediate */
- case 'j': /* 10 bit immediate */
+ case 'i': /* 13 bit immediate. */
+ case 'I': /* 11 bit immediate. */
+ case 'j': /* 10 bit immediate. */
{
int imm;
not before it. */
if (found_plus)
imm_added_to_rs1 = 1;
-
+
if (imm <= 9)
(*info->fprintf_func) (stream, "%d", imm);
else
}
break;
- case 'X': /* 5 bit unsigned immediate */
- case 'Y': /* 6 bit unsigned immediate */
+ case ')': /* 5 bit unsigned immediate from RS3. */
+ (info->fprintf_func) (stream, "%#x", (unsigned int) X_RS3 (insn));
+ break;
+
+ case 'X': /* 5 bit unsigned immediate. */
+ case 'Y': /* 6 bit unsigned immediate. */
{
int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
}
break;
+ case '3':
+ (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3));
+ break;
+
case 'K':
{
int mask = X_MEMBAR (insn);
break;
}
+ case '=':
+ info->target = memaddr + SEX (X_DISP10 (insn), 10) * 4;
+ (*info->print_address_func) (info->target, info);
+ break;
+
case 'k':
info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
(*info->print_address_func) (info->target, info);
(*info->fprintf_func) (stream, "%%fprs");
break;
+ case '{':
+ (*info->fprintf_func) (stream, "%%mcdper");
+ break;
+
+ case '&':
+ (*info->fprintf_func) (stream, "%%entropy");
+ break;
+
case 'o':
(*info->fprintf_func) (stream, "%%asi");
break;
-
+
case 'W':
(*info->fprintf_func) (stream, "%%tick");
break;
case '?':
if (X_RS1 (insn) == 31)
(*info->fprintf_func) (stream, "%%ver");
- else if ((unsigned) X_RS1 (insn) < 16)
+ else if (X_RS1 (insn) == 23)
+ (*info->fprintf_func) (stream, "%%pmcdper");
+ else if ((unsigned) X_RS1 (insn) < 17)
(*info->fprintf_func) (stream, "%%%s",
v9_priv_reg_names[X_RS1 (insn)]);
else
break;
case '!':
- if ((unsigned) X_RD (insn) < 15)
+ if (X_RD (insn) == 31)
+ (*info->fprintf_func) (stream, "%%ver");
+ else if (X_RD (insn) == 23)
+ (*info->fprintf_func) (stream, "%%pmcdper");
+ else if ((unsigned) X_RD (insn) < 17)
(*info->fprintf_func) (stream, "%%%s",
v9_priv_reg_names[X_RD (insn)]);
else
(*info->fprintf_func) (stream, "%%reserved");
break;
+ case '$':
+ if ((unsigned) X_RS1 (insn) < 32)
+ (*info->fprintf_func) (stream, "%%%s",
+ v9_hpriv_reg_names[X_RS1 (insn)]);
+ else
+ (*info->fprintf_func) (stream, "%%reserved");
+ break;
+
+ case '%':
+ if ((unsigned) X_RD (insn) < 32)
+ (*info->fprintf_func) (stream, "%%%s",
+ v9_hpriv_reg_names[X_RD (insn)]);
+ else
+ (*info->fprintf_func) (stream, "%%reserved");
+ break;
+
case '/':
- if (X_RS1 (insn) < 16 || X_RS1 (insn) > 23)
+ if (X_RS1 (insn) < 16 || X_RS1 (insn) > 28)
(*info->fprintf_func) (stream, "%%reserved");
else
(*info->fprintf_func) (stream, "%%%s",
break;
case '_':
- if (X_RD (insn) < 16 || X_RD (insn) > 23)
+ if (X_RD (insn) < 16 || X_RD (insn) > 28)
(*info->fprintf_func) (stream, "%%reserved");
else
(*info->fprintf_func) (stream, "%%%s",
if (name)
(*info->fprintf_func) (stream, "%s", name);
else
- (*info->fprintf_func) (stream, "%d", X_RD (insn));
+ (*info->fprintf_func) (stream, "%ld", X_RD (insn));
break;
}
-
+
case 'M':
- (*info->fprintf_func) (stream, "%%asr%d", X_RS1 (insn));
+ (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn));
break;
-
+
case 'm':
- (*info->fprintf_func) (stream, "%%asr%d", X_RD (insn));
+ (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn));
break;
-
+
case 'L':
info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
(*info->print_address_func) (info->target, info);
if (name)
(*info->fprintf_func) (stream, "%s", name);
else
- (*info->fprintf_func) (stream, "(%d)", X_ASI (insn));
+ (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn));
break;
}
(*info->fprintf_func) (stream, "%%fsr");
break;
+ case '(':
+ (*info->fprintf_func) (stream, "%%efsr");
+ break;
+
case 'p':
(*info->fprintf_func) (stream, "%%psr");
break;
break;
case 'x':
- (*info->fprintf_func) (stream, "%d",
+ (*info->fprintf_func) (stream, "%ld",
((X_LDST_I (insn) << 8)
+ X_ASI (insn)));
break;
+ case '|': /* 2-bit immediate */
+ (*info->fprintf_func) (stream, "%ld", X_IMM2 (insn));
+ break;
+
case 'y':
(*info->fprintf_func) (stream, "%%y");
break;
If so, attempt to print the result of the add or
or (in this context add and or do the same thing)
and its symbolic value. */
- if (imm_added_to_rs1)
+ if (imm_ored_to_rs1 || imm_added_to_rs1)
{
unsigned long prev_insn;
int errcode;
- errcode =
- (*info->read_memory_func)
+ if (memaddr >= 4)
+ errcode =
+ (*info->read_memory_func)
(memaddr - 4, buffer, sizeof (buffer), info);
+ else
+ errcode = 1;
+
prev_insn = getword (buffer);
if (errcode == 0)
{
/* If it is a delayed branch, we need to look at the
instruction before the delayed branch. This handles
- sequences such as
+ sequences such as:
sethi %o1, %hi(_foo), %o1
call _printf
- or %o1, %lo(_foo), %o1
- */
+ or %o1, %lo(_foo), %o1 */
if (is_delayed_branch (prev_insn))
{
- errcode = (*info->read_memory_func)
- (memaddr - 8, buffer, sizeof (buffer), info);
+ if (memaddr >= 8)
+ errcode = (*info->read_memory_func)
+ (memaddr - 8, buffer, sizeof (buffer), info);
+ else
+ errcode = 1;
+
prev_insn = getword (buffer);
}
}
&& X_RD (prev_insn) == X_RS1 (insn))
{
(*info->fprintf_func) (stream, "\t! ");
- info->target =
- (0xFFFFFFFF & (int) X_IMM22 (prev_insn) << 10)
- | X_SIMM (insn, 13);
+ info->target = (unsigned) X_IMM22 (prev_insn) << 10;
+ if (imm_added_to_rs1)
+ info->target += X_SIMM (insn, 13);
+ else
+ info->target |= X_SIMM (insn, 13);
(*info->print_address_func) (info->target, info);
info->insn_type = dis_dref;
info->data_size = 4; /* FIXME!!! */
if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
{
- /* FIXME -- check is_annulled flag */
+ /* FIXME -- check is_annulled flag. */
+ (void) is_annulled;
if (opcode->flags & F_UNBR)
info->insn_type = dis_branch;
if (opcode->flags & F_CONDBR)
}
}
- info->insn_type = dis_noninsn; /* Mark as non-valid instruction */
+ info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */
(*info->fprintf_func) (stream, _("unknown"));
return sizeof (buffer);
}
-
-/* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */
-
-static int
-compute_arch_mask (mach)
- unsigned long mach;
-{
- switch (mach)
- {
- case 0 :
- case bfd_mach_sparc :
- return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8);
- case bfd_mach_sparc_sparclet :
- return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
- case bfd_mach_sparc_sparclite :
- case bfd_mach_sparc_sparclite_le :
- /* sparclites insns are recognized by default (because that's how
- they've always been treated, for better or worse). Kludge this by
- indicating generic v8 is also selected. */
- return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
- | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
- case bfd_mach_sparc_v8plus :
- case bfd_mach_sparc_v9 :
- return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
- case bfd_mach_sparc_v8plusa :
- case bfd_mach_sparc_v9a :
- return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
- }
- abort ();
-}
-
-/* Compare opcodes A and B. */
-
-static int
-compare_opcodes (a, b)
- const PTR a;
- const PTR b;
-{
- struct sparc_opcode *op0 = * (struct sparc_opcode **) a;
- struct sparc_opcode *op1 = * (struct sparc_opcode **) b;
- unsigned long int match0 = op0->match, match1 = op1->match;
- unsigned long int lose0 = op0->lose, lose1 = op1->lose;
- register unsigned int i;
-
- /* If one (and only one) insn isn't supported by the current architecture,
- prefer the one that is. If neither are supported, but they're both for
- the same architecture, continue processing. Otherwise (both unsupported
- and for different architectures), prefer lower numbered arch's (fudged
- by comparing the bitmasks). */
- if (op0->architecture & current_arch_mask)
- {
- if (! (op1->architecture & current_arch_mask))
- return -1;
- }
- else
- {
- if (op1->architecture & current_arch_mask)
- return 1;
- else if (op0->architecture != op1->architecture)
- return op0->architecture - op1->architecture;
- }
-
- /* If a bit is set in both match and lose, there is something
- wrong with the opcode table. */
- if (match0 & lose0)
- {
- fprintf
- (stderr,
- /* xgettext:c-format */
- _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
- op0->name, match0, lose0);
- op0->lose &= ~op0->match;
- lose0 = op0->lose;
- }
-
- if (match1 & lose1)
- {
- fprintf
- (stderr,
- /* xgettext:c-format */
- _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
- op1->name, match1, lose1);
- op1->lose &= ~op1->match;
- lose1 = op1->lose;
- }
-
- /* Because the bits that are variable in one opcode are constant in
- another, it is important to order the opcodes in the right order. */
- for (i = 0; i < 32; ++i)
- {
- unsigned long int x = 1 << i;
- int x0 = (match0 & x) != 0;
- int x1 = (match1 & x) != 0;
-
- if (x0 != x1)
- return x1 - x0;
- }
-
- for (i = 0; i < 32; ++i)
- {
- unsigned long int x = 1 << i;
- int x0 = (lose0 & x) != 0;
- int x1 = (lose1 & x) != 0;
-
- if (x0 != x1)
- return x1 - x0;
- }
-
- /* They are functionally equal. So as long as the opcode table is
- valid, we can put whichever one first we want, on aesthetic grounds. */
-
- /* Our first aesthetic ground is that aliases defer to real insns. */
- {
- int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
- if (alias_diff != 0)
- /* Put the one that isn't an alias first. */
- return alias_diff;
- }
-
- /* Except for aliases, two "identical" instructions had
- better have the same opcode. This is a sanity check on the table. */
- i = strcmp (op0->name, op1->name);
- if (i)
- {
- if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
- return i;
- else
- fprintf (stderr,
- /* xgettext:c-format */
- _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
- op0->name, op1->name);
- }
-
- /* Fewer arguments are preferred. */
- {
- int length_diff = strlen (op0->args) - strlen (op1->args);
- if (length_diff != 0)
- /* Put the one with fewer arguments first. */
- return length_diff;
- }
-
- /* Put 1+i before i+1. */
- {
- char *p0 = (char *) strchr (op0->args, '+');
- char *p1 = (char *) strchr (op1->args, '+');
-
- if (p0 && p1)
- {
- /* There is a plus in both operands. Note that a plus
- sign cannot be the first character in args,
- so the following [-1]'s are valid. */
- if (p0[-1] == 'i' && p1[1] == 'i')
- /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
- return 1;
- if (p0[1] == 'i' && p1[-1] == 'i')
- /* op0 is 1+i and op1 is i+1, so op0 goes first. */
- return -1;
- }
- }
-
- /* Put 1,i before i,1. */
- {
- int i0 = strncmp (op0->args, "i,1", 3) == 0;
- int i1 = strncmp (op1->args, "i,1", 3) == 0;
-
- if (i0 ^ i1)
- return i0 - i1;
- }
-
- /* They are, as far as we can tell, identical.
- Since qsort may have rearranged the table partially, there is
- no way to tell which one was first in the opcode table as
- written, so just say there are equal. */
- /* ??? This is no longer true now that we sort a vector of pointers,
- not the table itself. */
- return 0;
-}
-
-/* Build a hash table from the opcode table.
- OPCODE_TABLE is a sorted list of pointers into the opcode table. */
-
-static void
-build_hash_table (opcode_table, hash_table, num_opcodes)
- const struct sparc_opcode **opcode_table;
- struct opcode_hash **hash_table;
- int num_opcodes;
-{
- register int i;
- int hash_count[HASH_SIZE];
- static struct opcode_hash *hash_buf = NULL;
-
- /* Start at the end of the table and work backwards so that each
- chain is sorted. */
-
- memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
- memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
- if (hash_buf != NULL)
- free (hash_buf);
- hash_buf = (struct opcode_hash *) xmalloc (sizeof (struct opcode_hash) * num_opcodes);
- for (i = num_opcodes - 1; i >= 0; --i)
- {
- register int hash = HASH_INSN (opcode_table[i]->match);
- register struct opcode_hash *h = &hash_buf[i];
- h->next = hash_table[hash];
- h->opcode = opcode_table[i];
- hash_table[hash] = h;
- ++hash_count[hash];
- }
-
-#if 0 /* for debugging */
- {
- int min_count = num_opcodes, max_count = 0;
- int total;
-
- for (i = 0; i < HASH_SIZE; ++i)
- {
- if (hash_count[i] < min_count)
- min_count = hash_count[i];
- if (hash_count[i] > max_count)
- max_count = hash_count[i];
- total += hash_count[i];
- }
-
- printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
- min_count, max_count, (double) total / HASH_SIZE);
- }
-#endif
-}
projects / deliverable / binutils-gdb.git / blobdiff