* config/sh/tm-sh.h (BELIEVE_PCC_PROMOTION): Define, so that

[deliverable/binutils-gdb.git] / sim / mn10300 / am33.igen

diff --git a/sim/mn10300/am33.igen b/sim/mn10300/am33.igen
index f5e9c4e7547cd00b17537975697880cc80a2d2b3..06abf7b34eadbadf4ff93701260497533880b77b 100644 (file)
--- a/sim/mn10300/am33.igen
+++ b/sim/mn10300/am33.igen
@@ -19,6 +19,25 @@
     return REG_E0 + rreg;
 }
 
+:function:::int:translate_xreg:int xreg
+{
+  switch (xreg)
+    {
+    case 0:
+      return REG_SP;
+    case 1:
+      return REG_MDRQ;
+    case 2:
+      return REG_MCRH;
+    case 3:
+      return REG_MCRL;
+    case 4:
+      return REG_MCVF;
+    default:
+      abort ();
+    }
+}
+
 // 1111 0000 0010 00An; mov USP,An
 8.0xf0+4.0x2,00,2.AN0:D0m:::mov
 "mov"
@@ -589,17 +608,13 @@
 "mov"
 *am33
 {
-  int dstreg;
+  int dstreg, srcreg;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
+  srcreg = translate_xreg (SD_, XRM2);
 
-  if (XRM2 == 0)
-    {
-      State.regs[dstreg] = State.regs[REG_SP];
-    }
-  else
-    abort ();
+  State.regs[dstreg] = State.regs[srcreg];
 }
 
 // 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
@@ -607,17 +622,13 @@
 "mov"
 *am33
 {
-  int srcreg;
+  int srcreg, dstreg;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
+  dstreg = translate_xreg (SD_, XRN0);
 
-  if (XRN0 == 0)
-    {
-      State.regs[REG_SP] = State.regs[srcreg];
-    }
-  else
-    abort ();
+  State.regs[dstreg] = State.regs[srcreg];
 }
 
 // 1111 1001 0000 1001 Rm Rn; and Rm,Rn
@@ -1001,7 +1012,7 @@
 }
 
 // 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
-8.0xf9+8.0x6a+4.RN2,4.RM0:D1y:::mov
+8.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov
 "mov"
 *am33
 {
@@ -1015,7 +1026,7 @@
 }
 
 // 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+)
-8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
+8.0xf9+8.0x7a+4.RM2,4.RN0!RM2:D1z:::mov
 "mov"
 *am33
 {
@@ -1101,7 +1112,7 @@
 }
 
 // 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
-8.0xf9+8.0xea+4.RN2,4.RM0:D1y:::movhu
+8.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu
 "movhu"
 *am33
 {
@@ -1115,7 +1126,7 @@
 }
 
 // 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+)
-8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
+8.0xf9+8.0xfa+4.RM2,4.RN0!RM2:D1z:::movhu
 "movhu"
 *am33
 {
@@ -1713,11 +1724,9 @@
   int dstreg;
 
   PC = cia;
+  dstreg = translate_xreg (SD_, XRN0);
 
-  if (XRN0 == 0)
-    State.regs[REG_SP] = IMM8;
-  else
-    abort ();
+  State.regs[dstreg] = IMM8;
 }
 
 // 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
@@ -1963,7 +1972,7 @@
 }
 
 // 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
-8.0xfb+8.0x6a+4.RN2,4.RM0+8.IMM8:D2y:::mov
+8.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov
 "mov"
 *am33
 {
@@ -1972,12 +1981,12 @@
   PC = cia;
   srcreg = translate_rreg (SD_, RM0);
   dstreg = translate_rreg (SD_, RN2);
-  State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
-  State.regs[srcreg] += 4;
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND8 (IMM8);
 }
 
 // 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
-8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
+8.0xfb+8.0x7a+4.RM2,4.RN0!RM2+8.IMM8:D2z:::mov
 "mov"
 {
   int srcreg, dstreg;
@@ -1985,8 +1994,8 @@
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
   dstreg = translate_rreg (SD_, RN0);
-  store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
-  State.regs[dstreg] += 4;
+  store_word (State.regs[dstreg], State.regs[srcreg]);
+  State.regs[dstreg] += EXTEND8 (IMM8);
 }
 
 
@@ -2057,7 +2066,7 @@
 }
 
 // 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
-8.0xfb+8.0xea+4.RN2,4.RM0+8.IMM8:D2y:::movhu
+8.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu
 "movhu"
 *am33
 {
@@ -2066,12 +2075,12 @@
   PC = cia;
   srcreg = translate_rreg (SD_, RM0);
   dstreg = translate_rreg (SD_, RN2);
-  State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
-  State.regs[srcreg] += 2;
+  State.regs[dstreg] = load_half (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND8 (IMM8);
 }
 
 // 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
-8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
+8.0xfb+8.0xfa+4.RM2,4.RN0!RM2+8.IMM8:D2z:::movhu
 "movhu"
 {
   int srcreg, dstreg;
@@ -2079,8 +2088,8 @@
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
   dstreg = translate_rreg (SD_, RN0);
-  store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
-  State.regs[dstreg] += 2;
+  store_half (State.regs[dstreg], State.regs[srcreg]);
+  State.regs[dstreg] += EXTEND8 (IMM8);
 }
 
 
@@ -2593,7 +2602,7 @@
 }
 
 // 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
-8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mul
+8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul
 "mul"
 *am33
 {
@@ -2620,7 +2629,7 @@
 }
 
 // 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
-8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mulu
+8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu
 "mulu"
 *am33
 {
@@ -2803,7 +2812,7 @@
 }
 
 // 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2
-8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::mac
+8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac
 "mac"
 *am33
 {
@@ -2839,7 +2848,7 @@
 }
 
 // 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2
-8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::macu
+8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu
 "macu"
 *am33
 {
@@ -2930,26 +2939,28 @@
     }
 }
 
-// 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1
-8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::mach
+// 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1,Rd2
+8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach
 "mach"
 *am33
 {
-  int srcreg1, srcreg2, dstreg;
-  long temp, sum;
+  int srcreg1, srcreg2, dstreg1, dstreg2;
+  long long temp, sum;
   int v;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM2);
   srcreg2 = translate_rreg (SD_, RN0);
-  dstreg = translate_rreg (SD_, RD0);
+  dstreg1 = translate_rreg (SD_, RD0);
+  dstreg2 = translate_rreg (SD_, RD0);
 
   temp = ((signed32)(State.regs[srcreg2] & 0xffff)
           * (signed32)(State.regs[srcreg1] & 0xffff));
-  sum = State.regs[dstreg] + temp;
-  v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
+  State.regs[dstreg2] += (temp & 0xffffffff);
+  sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
+  v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
         && (temp & 0x80000000) != (sum & 0x80000000));
-  State.regs[dstreg] = sum;
+  State.regs[dstreg1] = sum;
   if (v)
     {
       State.regs[REG_MCVF] = 1;
@@ -2958,26 +2969,28 @@
     }
 }
 
-// 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1
-8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::machu
+// 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1,Rd2
+8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu
 "machu"
 *am33
 {
-  int srcreg1, srcreg2, dstreg;
-  long temp, sum;
+  int srcreg1, srcreg2, dstreg1, dstreg2;
+  long long temp, sum;
   int v;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM2);
   srcreg2 = translate_rreg (SD_, RN0);
-  dstreg = translate_rreg (SD_, RD0);
+  dstreg1 = translate_rreg (SD_, RD0);
+  dstreg2 = translate_rreg (SD_, RD0);
 
   temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
           * (unsigned32)(State.regs[srcreg1] & 0xffff));
-  sum = State.regs[dstreg] + temp;
-  v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
+  State.regs[dstreg2] += (temp & 0xffffffff);
+  sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
+  v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
         && (temp & 0x80000000) != (sum & 0x80000000));
-  State.regs[dstreg] = sum;
+  State.regs[dstreg1] = sum;
   if (v)
     {
       State.regs[REG_MCVF] = 1;
@@ -3047,7 +3060,7 @@
 }
 
 // 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2
-8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::dmulh
+8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh
 "dmulh"
 *am33
 {
@@ -3069,7 +3082,7 @@
 }
 
 // 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2
-8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2:D2c:::dmulhu
+8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu
 "dmulhu"
 *am33
 {
@@ -3274,14 +3287,12 @@
 "mov"
 *am33
 {
+  int dstreg;
+
   PC = cia;
+  dstreg = translate_xreg (SD_, XRN0);
 
-  if (XRN0 == 0)
-    {
-      State.regs[REG_SP] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
-    }
-  else
-    abort ();
+  State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
 }
 
 // 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
@@ -3542,7 +3553,7 @@
 }
 
 // 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn
-8.0xfd+8.0x6a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
+8.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
 "mov"
 *am33
 {
@@ -3551,14 +3562,12 @@
   PC = cia;
   srcreg = translate_rreg (SD_, RM0);
   dstreg = translate_rreg (SD_, RN2);
-  State.regs[dstreg] = load_word (State.regs[srcreg]
-                                 + EXTEND24 (FETCH24 (IMM24A,
-                                                      IMM24B, IMM24C)));
-  State.regs[srcreg] += 4;
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
 }
 
 // 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+)
-8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
+8.0xfd+8.0x7a+4.RM2,4.RN0!RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
 "mov"
 *am33
 {
@@ -3567,9 +3576,8 @@
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
   dstreg = translate_rreg (SD_, RN0);
-  store_word (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
-             State.regs[srcreg]);
-  State.regs[dstreg] += 4;
+  store_word (State.regs[dstreg], State.regs[srcreg]);
+  State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
 }
 
 
@@ -3655,7 +3663,7 @@
 }
 
 // 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn
-8.0xfd+8.0xea+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
+8.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
 "movhu"
 *am33
 {
@@ -3664,14 +3672,12 @@
   PC = cia;
   srcreg = translate_rreg (SD_, RM0);
   dstreg = translate_rreg (SD_, RN2);
-  State.regs[dstreg] = load_half (State.regs[srcreg]
-                                 + EXTEND24 (FETCH24 (IMM24A,
-                                             IMM24B, IMM24C)));
-  State.regs[dstreg] += 2;
+  State.regs[dstreg] = load_half (State.regs[srcreg]);
+  State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
 }
 
 // 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+)
-8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
+8.0xfd+8.0xfa+4.RM2,4.RN0!RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
 "movhu"
 *am33
 {
@@ -3680,9 +3686,8 @@
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
   dstreg = translate_rreg (SD_, RN0);
-  store_half (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
-             State.regs[srcreg]);
-  State.regs[srcreg] += 2;
+  store_half (State.regs[dstreg], State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
 }
 
 // 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn
@@ -4043,12 +4048,12 @@
 "mov"
 *am33
 {
+  int dstreg;
+
   PC = cia;
+  dstreg = translate_xreg (SD_, XRN0);
 
-  if (XRN0 == 0)
-    State.regs[REG_SP] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
-  else
-    abort ();
+  State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
 }
 
 // 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
@@ -4305,7 +4310,7 @@
 }
 
 // 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn
-8.0xfe+8.0x6a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
+8.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
 "mov"
 *am33
 {
@@ -4314,13 +4319,12 @@
   PC = cia;
   srcreg = translate_rreg (SD_, RM0);
   dstreg = translate_rreg (SD_, RN2);
-  State.regs[dstreg] = load_word (State.regs[srcreg]
-                                 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
-  State.regs[srcreg] += 4;
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 }
 
 // 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
-8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
+8.0xfe+8.0x7a+4.RM2,4.RN0!RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
 "mov"
 *am33
 {
@@ -4329,9 +4333,8 @@
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
   dstreg = translate_rreg (SD_, RN0);
-  store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
-             State.regs[srcreg]);
-  State.regs[dstreg] += 4;
+  store_word (State.regs[dstreg], State.regs[srcreg]);
+  State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 }
 
 
@@ -4415,7 +4418,7 @@
 
 
 // 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn
-8.0xfe+8.0xea+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
+8.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
 "movhu"
 *am33
 {
@@ -4424,13 +4427,12 @@
   PC = cia;
   srcreg = translate_rreg (SD_, RM0);
   dstreg = translate_rreg (SD_, RN2);
-  State.regs[dstreg] = load_half (State.regs[srcreg]
-                                 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
-  State.regs[srcreg] += 2;
+  State.regs[dstreg] = load_half (State.regs[srcreg]);
+  State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 }
 
 // 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+)
-8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
+8.0xfe+8.0xfa+4.RM2,4.RN0!RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
 "movhu"
 *am33
 {
@@ -4439,22 +4441,248 @@
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
   dstreg = translate_rreg (SD_, RN0);
-  store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
-             State.regs[srcreg]);
-  State.regs[dstreg] += 2;
+  store_half (State.regs[dstreg], State.regs[srcreg]);
+  State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+}
+
+
+// 1111 1110 0000 1011 Rn Rn IMM32; mac imm32,Rn
+8.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac
+"mac"
+*am33
+{
+  int srcreg, imm;
+  long long temp, sum;
+  int c, v;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+  temp = ((signed64)(signed32)State.regs[srcreg]
+          * (signed64)(signed32)imm);
+  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+  State.regs[REG_MCRL] = sum;
+  temp >>= 32;
+  temp &= 0xffffffff;
+  sum = State.regs[REG_MCRH] + temp + c;
+  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+        && (temp & 0x80000000) != (sum & 0x80000000));
+  State.regs[REG_MCRH] = sum;
+  if (v)
+    State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1110 0001 1011 Rn Rn IMM32; macu imm32,Rn
+8.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu
+"macu"
+*am33
+{
+  int srcreg, imm;
+  long long temp, sum;
+  int c, v;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+  temp = ((unsigned64)State.regs[srcreg]
+          * (unsigned64)imm);
+  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
+  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
+  State.regs[REG_MCRL] = sum;
+  temp >>= 32;
+  temp &= 0xffffffff;
+  sum = State.regs[REG_MCRH] + temp + c;
+  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
+        && (temp & 0x80000000) != (sum & 0x80000000));
+  State.regs[REG_MCRH] = sum;
+  if (v)
+    State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1110 0010 1011 Rn Rn IMM32; macb imm32,Rn
+8.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb
+"macb"
+*am33
+{
+  int srcreg, imm;
+  long temp, sum;
+  int v;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+  temp = ((signed32)(signed8)(State.regs[srcreg] & 0xff)
+          * (signed32)(signed8)(imm & 0xff));
+  sum = State.regs[REG_MCRL] + temp;
+  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+        && (temp & 0x80000000) != (sum & 0x80000000));
+  State.regs[REG_MCRL] = sum;
+  if (v)
+    State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1110 0011 1011 Rn Rn IMM32; macbu imm32,Rn
+8.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu
+"macbu"
+*am33
+{
+  int srcreg, imm;
+  long temp, sum;
+  int v;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+  temp = ((unsigned32)(State.regs[srcreg] & 0xff)
+          * (unsigned32)(imm & 0xff));
+  sum = State.regs[REG_MCRL] + temp;
+  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+        && (temp & 0x80000000) != (sum & 0x80000000));
+  State.regs[REG_MCRL] = sum;
+  if (v)
+    State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1110 0100 1011 Rn Rn IMM32; mach imm32,Rn
+8.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach
+"mach"
+*am33
+{
+  int srcreg, imm;
+  long temp, sum;
+  int v;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+  temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
+          * (signed32)(signed16)(imm & 0xffff));
+  sum = State.regs[REG_MCRL] + temp;
+  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+        && (temp & 0x80000000) != (sum & 0x80000000));
+  State.regs[REG_MCRL] = sum;
+  if (v)
+    State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1110 0101 1011 Rn Rn IMM32; machu imm32,Rn
+8.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu
+"machu"
+*am33
+{
+  int srcreg, imm;
+  long temp, sum;
+  int v;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+  temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
+          * (unsigned32)(imm & 0xffff));
+  sum = State.regs[REG_MCRL] + temp;
+  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+        && (temp & 0x80000000) != (sum & 0x80000000));
+  State.regs[REG_MCRL] = sum;
+  if (v)
+    State.regs[REG_MCVF] = 1;
+}
+
+// 1111 1110 0110 1011 Rn Rn IMM32; dmach imm32,Rn
+8.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach
+"dmach"
+*am33
+{
+  int srcreg, imm;
+  long temp, temp2, sum;
+  int v;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+  temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
+          * (signed32)(signed16)(imm & 0xffff));
+  temp2 = ((signed32)(signed16)((State.regs[srcreg] >> 16) & 0xffff)
+          * (signed32)(signed16)((imm >> 16) & 0xffff));
+  sum = temp + temp2 + State.regs[REG_MCRL];
+  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+        && (temp & 0x80000000) != (sum & 0x80000000));
+  State.regs[REG_MCRL] = sum;
+  if (v)
+    State.regs[REG_MCVF] = 1;
 }
 
+// 1111 1110 0111 1011 Rn Rn IMM32; dmachu imm32,Rn
+8.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu
+"dmachu"
+*am33
+{
+  int srcreg, imm;
+  long temp, temp2, sum;
+  int v;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+  temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
+          * (unsigned32)(imm & 0xffff));
+  temp2 = ((unsigned32)((State.regs[srcreg] >> 16) & 0xffff)
+          * (unsigned32)((imm >> 16) & 0xffff));
+  sum = temp + temp2 + State.regs[REG_MCRL];
+  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
+        && (temp & 0x80000000) != (sum & 0x80000000));
+  State.regs[REG_MCRL] = sum;
+  if (v)
+    State.regs[REG_MCVF] = 1;
+}
 
-// ??? mac
-// ??? macu
-// ??? macb
-// ??? macbu
-// ??? mach
-// ??? machu
-// ??? dmach
-// ??? dmachu
-// ??? dmulh
-// ??? dmulhu
+// 1111 1110 1000 1011 Rn Rn IMM32; dmulh imm32,Rn
+8.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh
+"dmulh"
+*am33
+{
+  int imm, dstreg;
+  long temp;
+
+  PC = cia;
+  dstreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+  temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
+          * (signed32)(signed16)(imm & 0xffff));
+  State.regs[REG_MDRQ] = temp;
+  temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
+          * (signed32)(signed16)((imm>>16) & 0xffff));
+  State.regs[dstreg] = temp;
+}
+
+// 1111 1110 1001 1011 Rn Rn IMM32; dmulhu imm32,Rn
+8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu
+"dmulhu"
+*am33
+{
+  int imm, dstreg;
+  long temp;
+
+  PC = cia;
+  dstreg = translate_rreg (SD_, RN0);
+  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+
+  temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
+          * (unsigned32)(imm & 0xffff));
+  State.regs[REG_MDRQ] = temp;
+  temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
+          * (unsigned32)((imm >>16) & 0xffff));
+  State.regs[dstreg] = temp;
+}
 
 // 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
 8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
@@ -7952,3 +8180,232 @@
   State.regs[dstreg2] <<= IMM4;
 }
 
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0000; mov_llt (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x0:D2:::mov_llt
+"mov_llt"
+*am33
+{
+  int srcreg, dstreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM);
+  dstreg = translate_rreg (SD_, RN);
+
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND4 (IMM4);
+
+  if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0001; mov_lgt (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x1:D2:::mov_lgt
+"mov_lgt"
+*am33
+{
+  int srcreg, dstreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM);
+  dstreg = translate_rreg (SD_, RN);
+
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND4 (IMM4);
+
+  if (!((PSW & PSW_Z)
+        || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0010; mov_lge (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x2:D2:::mov_lge
+"mov_lge"
+*am33
+{
+  int srcreg, dstreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM);
+  dstreg = translate_rreg (SD_, RN);
+
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND4 (IMM4);
+
+  if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0011; mov_lle (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x3:D2:::mov_lle
+"mov_lle"
+*am33
+{
+  int srcreg, dstreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM);
+  dstreg = translate_rreg (SD_, RN);
+
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND4 (IMM4);
+
+  if ((PSW & PSW_Z)
+      || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0100; mov_lcs (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x4:D2:::mov_lcs
+"mov_lcs"
+*am33
+{
+  int srcreg, dstreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM);
+  dstreg = translate_rreg (SD_, RN);
+
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND4 (IMM4);
+
+  if (PSW & PSW_C)
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0101; mov_lhi (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x5:D2:::mov_lhi
+"mov_lhi"
+*am33
+{
+  int srcreg, dstreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM);
+  dstreg = translate_rreg (SD_, RN);
+
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND4 (IMM4);
+
+  if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0110; mov_lcc (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x6:D2:::mov_lcc
+"mov_lcc"
+*am33
+{
+  int srcreg, dstreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM);
+  dstreg = translate_rreg (SD_, RN);
+
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND4 (IMM4);
+
+  if (!(PSW & PSW_C))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 0111; mov_lls (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x7:D2:::mov_lls
+"mov_lls"
+*am33
+{
+  int srcreg, dstreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM);
+  dstreg = translate_rreg (SD_, RN);
+
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND4 (IMM4);
+
+  if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 1000; mov_leq (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x8:D2:::mov_leq
+"mov_leq"
+*am33
+{
+  int srcreg, dstreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM);
+  dstreg = translate_rreg (SD_, RN);
+
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND4 (IMM4);
+
+  if (PSW & PSW_Z)
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 1001; mov_lne (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x9:D2:::mov_lne
+"mov_lne"
+*am33
+{
+  int srcreg, dstreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM);
+  dstreg = translate_rreg (SD_, RN);
+
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND4 (IMM4);
+
+  if (!(PSW & PSW_Z))
+    {
+      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+      nia = PC;
+    }
+}
+
+// 1111 0111 1110 0000 Rm1 Rn1 imm4 1010; mov_lra (Rm+,imm4),Rn
+8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0xa:D2:::mov_lra
+"mov_lra"
+*am33
+{
+  int srcreg, dstreg;
+
+  PC = cia;
+  srcreg = translate_rreg (SD_, RM);
+  dstreg = translate_rreg (SD_, RN);
+
+  State.regs[dstreg] = load_word (State.regs[srcreg]);
+  State.regs[srcreg] += EXTEND4 (IMM4);
+
+  State.regs[REG_PC] = State.regs[REG_LAR] - 4;
+  nia = PC;
+}