X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=gdb%2Fgdbserver%2Flinux-aarch64-low.c;h=961fd5b3cc41c708d7acfe3c03639e287330bbb7;hb=bb1183e25ae74ba21500fb4e39bc1ca9822e3086;hp=9682537728847850d824c7eac949c68ab09226ac;hpb=49bdb7ee48a10581e9f7254782f2eb953c4a164b;p=deliverable%2Fbinutils-gdb.git diff --git a/gdb/gdbserver/linux-aarch64-low.c b/gdb/gdbserver/linux-aarch64-low.c index 9682537728..961fd5b3cc 100644 --- a/gdb/gdbserver/linux-aarch64-low.c +++ b/gdb/gdbserver/linux-aarch64-low.c @@ -1,7 +1,7 @@ /* GNU/Linux/AArch64 specific low level interface, for the remote server for GDB. - Copyright (C) 2009-2017 Free Software Foundation, Inc. + Copyright (C) 2009-2020 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GDB. @@ -28,6 +28,7 @@ #include "elf/common.h" #include "ax.h" #include "tracepoint.h" +#include "debug.h" #include #include @@ -39,7 +40,10 @@ #include "gdb_proc_service.h" #include "arch/aarch64.h" +#include "linux-aarch32-tdesc.h" #include "linux-aarch64-tdesc.h" +#include "nat/aarch64-sve-linux-ptrace.h" +#include "tdesc.h" #ifdef HAVE_SYS_REG_H #include @@ -72,20 +76,14 @@ is_64bit_tdesc (void) return register_size (regcache->tdesc, 0) == 8; } -/* Implementation of linux_target_ops method "cannot_store_register". */ +/* Return true if the regcache contains the number of SVE registers. */ -static int -aarch64_cannot_store_register (int regno) +static bool +is_sve_tdesc (void) { - return regno >= AARCH64_NUM_REGS; -} - -/* Implementation of linux_target_ops method "cannot_fetch_register". */ + struct regcache *regcache = get_thread_regcache (current_thread, 0); -static int -aarch64_cannot_fetch_register (int regno) -{ - return regno >= AARCH64_NUM_REGS; + return tdesc_contains_feature (regcache->tdesc, "org.gnu.gdb.aarch64.sve"); } static void @@ -139,9 +137,22 @@ aarch64_store_fpregset (struct regcache *regcache, const void *buf) supply_register (regcache, AARCH64_FPCR_REGNUM, ®set->fpcr); } -/* Enable miscellaneous debugging output. The name is historical - it - was originally used to debug LinuxThreads support. */ -extern int debug_threads; +/* Store the pauth registers to regcache. */ + +static void +aarch64_store_pauthregset (struct regcache *regcache, const void *buf) +{ + uint64_t *pauth_regset = (uint64_t *) buf; + int pauth_base = find_regno (regcache->tdesc, "pauth_dmask"); + + if (pauth_base == 0) + return; + + supply_register (regcache, AARCH64_PAUTH_DMASK_REGNUM (pauth_base), + &pauth_regset[0]); + supply_register (regcache, AARCH64_PAUTH_CMASK_REGNUM (pauth_base), + &pauth_regset[1]); +} /* Implementation of linux_target_ops method "get_pc". */ @@ -360,14 +371,39 @@ aarch64_stopped_data_address (void) state = aarch64_get_debug_reg_state (pid_of (current_thread)); for (i = aarch64_num_wp_regs - 1; i >= 0; --i) { + const unsigned int offset + = aarch64_watchpoint_offset (state->dr_ctrl_wp[i]); const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]); const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr; - const CORE_ADDR addr_watch = state->dr_addr_wp[i]; + const CORE_ADDR addr_watch = state->dr_addr_wp[i] + offset; + const CORE_ADDR addr_watch_aligned = align_down (state->dr_addr_wp[i], 8); + const CORE_ADDR addr_orig = state->dr_addr_orig_wp[i]; + if (state->dr_ref_count_wp[i] && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i]) - && addr_trap >= addr_watch + && addr_trap >= addr_watch_aligned && addr_trap < addr_watch + len) - return addr_trap; + { + /* ADDR_TRAP reports the first address of the memory range + accessed by the CPU, regardless of what was the memory + range watched. Thus, a large CPU access that straddles + the ADDR_WATCH..ADDR_WATCH+LEN range may result in an + ADDR_TRAP that is lower than the + ADDR_WATCH..ADDR_WATCH+LEN range. E.g.: + + addr: | 4 | 5 | 6 | 7 | 8 | + |---- range watched ----| + |----------- range accessed ------------| + + In this case, ADDR_TRAP will be 4. + + To match a watchpoint known to GDB core, we must never + report *ADDR_P outside of any ADDR_WATCH..ADDR_WATCH+LEN + range. ADDR_WATCH <= ADDR_TRAP < ADDR_ORIG is a false + positive on kernels older than 4.10. See PR + external/20207. */ + return addr_orig; + } } return (CORE_ADDR) 0; @@ -464,6 +500,9 @@ aarch64_linux_new_fork (struct process_info *parent, *child->priv->arch_private = *parent->priv->arch_private; } +/* Matches HWCAP_PACA in kernel header arch/arm64/include/uapi/asm/hwcap.h. */ +#define AARCH64_HWCAP_PACA (1 << 30) + /* Implementation of linux_target_ops method "arch_setup". */ static void @@ -478,13 +517,35 @@ aarch64_arch_setup (void) is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine); if (is_elf64) - current_process ()->tdesc = aarch64_linux_read_description (); + { + uint64_t vq = aarch64_sve_get_vq (tid); + unsigned long hwcap = linux_get_hwcap (8); + bool pauth_p = hwcap & AARCH64_HWCAP_PACA; + + current_process ()->tdesc = aarch64_linux_read_description (vq, pauth_p); + } else - current_process ()->tdesc = tdesc_arm_with_neon; + current_process ()->tdesc = aarch32_linux_read_description (); aarch64_linux_get_debug_reg_capacity (lwpid_of (current_thread)); } +/* Wrapper for aarch64_sve_regs_copy_to_reg_buf. */ + +static void +aarch64_sve_regs_copy_to_regcache (struct regcache *regcache, const void *buf) +{ + return aarch64_sve_regs_copy_to_reg_buf (regcache, buf); +} + +/* Wrapper for aarch64_sve_regs_copy_from_reg_buf. */ + +static void +aarch64_sve_regs_copy_from_regcache (struct regcache *regcache, void *buf) +{ + return aarch64_sve_regs_copy_from_reg_buf (regcache, buf); +} + static struct regset_info aarch64_regsets[] = { { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS, @@ -494,6 +555,9 @@ static struct regset_info aarch64_regsets[] = sizeof (struct user_fpsimd_state), FP_REGS, aarch64_fill_fpregset, aarch64_store_fpregset }, + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_PAC_MASK, + AARCH64_PAUTH_REGS_SIZE, OPTIONAL_REGS, + NULL, aarch64_store_pauthregset }, NULL_REGSET }; @@ -511,15 +575,47 @@ static struct regs_info regs_info_aarch64 = &aarch64_regsets_info, }; +static struct regset_info aarch64_sve_regsets[] = +{ + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS, + sizeof (struct user_pt_regs), GENERAL_REGS, + aarch64_fill_gregset, aarch64_store_gregset }, + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_SVE, + SVE_PT_SIZE (AARCH64_MAX_SVE_VQ, SVE_PT_REGS_SVE), EXTENDED_REGS, + aarch64_sve_regs_copy_from_regcache, aarch64_sve_regs_copy_to_regcache + }, + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_PAC_MASK, + AARCH64_PAUTH_REGS_SIZE, OPTIONAL_REGS, + NULL, aarch64_store_pauthregset }, + NULL_REGSET +}; + +static struct regsets_info aarch64_sve_regsets_info = + { + aarch64_sve_regsets, /* regsets. */ + 0, /* num_regsets. */ + NULL, /* disabled_regsets. */ + }; + +static struct regs_info regs_info_aarch64_sve = + { + NULL, /* regset_bitmap. */ + NULL, /* usrregs. */ + &aarch64_sve_regsets_info, + }; + /* Implementation of linux_target_ops method "regs_info". */ static const struct regs_info * aarch64_regs_info (void) { - if (is_64bit_tdesc ()) - return ®s_info_aarch64; - else + if (!is_64bit_tdesc ()) return ®s_info_aarch32; + + if (is_sve_tdesc ()) + return ®s_info_aarch64_sve; + + return ®s_info_aarch64; } /* Implementation of linux_target_ops method "supports_tracepoints". */ @@ -1527,11 +1623,11 @@ append_insns (CORE_ADDR *to, size_t len, const uint32_t *buf) for (i = 0; i < len; i++) le_buf[i] = htole32 (buf[i]); - write_inferior_memory (*to, (const unsigned char *) le_buf, byte_len); + target_write_memory (*to, (const unsigned char *) le_buf, byte_len); xfree (le_buf); #else - write_inferior_memory (*to, (const unsigned char *) buf, byte_len); + target_write_memory (*to, (const unsigned char *) buf, byte_len); #endif *to += byte_len; @@ -1852,7 +1948,7 @@ aarch64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, for (i = 30; i >= 0; i -= 2) p += emit_stp_q_offset (p, i, i + 1, sp, i * 16); - /* Push general puspose registers on the stack. Note that we do not need + /* Push general purpose registers on the stack. Note that we do not need to push x31 as it represents the xzr register and not the stack pointer in a STR instruction. @@ -2020,7 +2116,7 @@ aarch64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, ; This instruction is a normal store with memory ordering ; constraints. Thanks to this we do not have to put a data ; barrier instruction to make sure all data read and writes are done - ; before this instruction is executed. Furthermore, this instrucion + ; before this instruction is executed. Furthermore, this instruction ; will trigger an event, letting other threads know they can grab ; the lock. STLR xzr, [x0] @@ -2215,7 +2311,7 @@ aarch64_emit_prologue (void) the current stack pointer in the frame pointer. This way, it is not clobbered when calling C functions. - Finally, throughtout every operation, we are using register x0 as the + Finally, throughout every operation, we are using register x0 as the top of the stack, and x1 as a scratch register. */ p += emit_stp (p, x0, x1, sp, preindex_memory_operand (-2 * 16)); @@ -2542,7 +2638,7 @@ aarch64_emit_goto (int *offset_p, int *size_p) /* Implementation of emit_ops method "write_goto_address". */ -void +static void aarch64_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size) { uint32_t insn; @@ -2956,8 +3052,8 @@ struct linux_target_ops the_low_target = { aarch64_arch_setup, aarch64_regs_info, - aarch64_cannot_fetch_register, - aarch64_cannot_store_register, + NULL, /* cannot_fetch_register */ + NULL, /* cannot_store_register */ NULL, /* fetch_register */ aarch64_get_pc, aarch64_set_pc, @@ -2998,4 +3094,5 @@ initialize_low_arch (void) initialize_low_arch_aarch32 (); initialize_regsets_info (&aarch64_regsets_info); + initialize_regsets_info (&aarch64_sve_regsets_info); }