dmaengine: dw: properly read DWC_PARAMS register
authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Mon, 28 Sep 2015 15:57:03 +0000 (18:57 +0300)
committerVinod Koul <vinod.koul@intel.com>
Wed, 30 Sep 2015 08:12:02 +0000 (13:42 +0530)
commit6bea0f6d1c47b07be88dfd93f013ae05fcb3d8bf
tree101b7803013771335da6245edffd0152d5b0ac81
parentee08b59d47d859ed0a11ab331a3fbc5ab3b56100
dmaengine: dw: properly read DWC_PARAMS register

In case we have less than maximum allowed channels (8) and autoconfiguration is
enabled the DWC_PARAMS read is wrong because it uses different arithmetic to
what is needed for channel priority setup.

Re-do the caclulations properly. This now works on AVR32 board well.

Fixes: fed2574b3c9f (dw_dmac: introduce software emulation of LLP transfers)
Cc: yitian.bu@tangramtek.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
drivers/dma/dw/core.c
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