[AArch64] Match instruction "STP with base register" in prologue

Nowadays, we only match pre-indexed STP in prologue.  Due to the change
in gcc, https://gcc.gnu.org/ml/gcc-patches/2016-07/msg01933.html, it
may generate "STP with base register" in prologue, which GDB doesn't
handle.  That is to say, previously GCC generates prologue like this,

 sub sp, sp, #490
 stp x29, x30, [sp, #-96]!
 mov x29, sp

with the gcc patch above, GCC generates prologue like like this,

 sub sp, sp, #4f0
 stp x29, x30, [sp]
 mov x29, sp

This patch is to teach GDB to recognize this instruction in prologue
analysis.

gdb:

2016-08-19  Yao Qi  <yao.qi@linaro.org>

	* aarch64-tdep.c (aarch64_analyze_prologue): Handle register
	based STP instruction.

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index 50fc8deb40937531809df45c83593952ce607349..db3527bf30219553a08220609f22ac06e6ae869e 100644 (file)
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,8 @@
+2016-08-19  Yao Qi  <yao.qi@linaro.org>
+
+       * aarch64-tdep.c (aarch64_analyze_prologue): Handle register
+       based STP instruction.
+
 2016-08-19  Yao Qi  <yao.qi@linaro.org>
 
        * completer.c (linespec_location_completer): Make file_to_match

diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index e97e2f41ddb0cc6b9d45a488527be7ade1d4dddd..3b7e954424e13df05c86c84c442501d719261f32 100644 (file)
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -322,10 +322,11 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
                         is64 ? 8 : 4, regs[rt]);
        }
       else if ((inst.opcode->iclass == ldstpair_off
-               || inst.opcode->iclass == ldstpair_indexed)
-              && inst.operands[2].addr.preind
+               || (inst.opcode->iclass == ldstpair_indexed
+                   && inst.operands[2].addr.preind))
               && strcmp ("stp", inst.opcode->name) == 0)
        {
+         /* STP with addressing mode Pre-indexed and Base register.  */
          unsigned rt1 = inst.operands[0].reg.regno;
          unsigned rt2 = inst.operands[1].reg.regno;
          unsigned rn = inst.operands[2].addr.base_regno;