Add support for the Cortex-A55 and Cortex-A75 versions of the AArch64 architecture.

	* config/tc-aarch64.c (aarch64_cpus): Add cortex-a55 and cortex-a75.
	* doc/c-aarch64.texi (-mcpu): Document cortex-a55 and cortex-a75.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 38ffc663396ae97042c1bb3dcf0af64601e77380..2e7e1852894186bc30d5523095f86fa1984353d1 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2017-06-21  James Greenhalgh  <james.greenhalgh@arm.com>
+
+       * config/tc-aarch64.c (aarch64_cpus): Add cortex-a55 and cortex-a75.
+       * doc/c-aarch64.texi (-mcpu): Document cortex-a55 and cortex-a75.
+
 2017-06-15  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR binutils/21594

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index be01bdd1432b9eda741b781dbd275aecc40144bc..fae29b4f47e064c444f659de57f6c3b0fbb69d05 100644 (file)
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -8395,6 +8395,12 @@ static const struct aarch64_cpu_option_table aarch64_cpus[] = {
                                  AARCH64_FEATURE_CRC), "Cortex-A72"},
   {"cortex-a73", AARCH64_FEATURE (AARCH64_ARCH_V8,
                                  AARCH64_FEATURE_CRC), "Cortex-A73"},
+  {"cortex-a55", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
+                                 AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16),
+                                 "Cortex-A55"},
+  {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
+                                 AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16),
+                                 "Cortex-A75"},
   {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8,
                                 AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO),
                                "Samsung Exynos M1"},

diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 2a01c3f5e7f3e7cf247d9328d53e3c0465da8de7..24775553cdafae7d68d13eab42bb5dac8eae5f14 100644 (file)
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -57,9 +57,11 @@ message if an attempt is made to assemble an instruction which will not execute
 on the target processor.  The following processor names are recognized:
 @code{cortex-a35},
 @code{cortex-a53},
+@code{cortex-a55},
 @code{cortex-a57},
 @code{cortex-a72},
 @code{cortex-a73},
+@code{cortex-a75},
 @code{exynos-m1},
 @code{falkor},
 @code{qdf24xx},