gas/

2007-09-17  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (baseindex): Removed.
	(build_modrm_byte): Check reg_num for RIP register instead of
	reg_type.
	(i386_index_check): Likewise.

opcodes/

2007-09-17  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.h (RegRip): New.

	* i386-reg.tbl (rip): Use RegRip for reg_num.
	* i386-tbl.h: Regenerated.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index c62639e9ead12ee1d83e074a4fa34fc7f2e0ee9e..81b5fdc4d21db3445396281e0310731a473dfaa7 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2007-09-17  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * config/tc-i386.c (baseindex): Removed.
+       (build_modrm_byte): Check reg_num for RIP register instead of
+       reg_type.
+       (i386_index_check): Likewise.
+
 2007-09-17  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR gas/5035

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 5453a00b31682f992db1da40c4193c7c0e5576c8..17bde043b0cad4347e15b9b123e8521689933af0 100644 (file)
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1098,7 +1098,6 @@ static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
 static const i386_operand_type anydisp
   = OPERAND_TYPE_ANYDISP;
-static const i386_operand_type baseindex = OPERAND_TYPE_BASEINDEX;
 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
@@ -4541,7 +4540,7 @@ build_modrm_byte (void)
                }
            }
          /* RIP addressing for 64bit mode.  */
-         else if (UINTS_EQUAL (i.base_reg->reg_type, baseindex))
+         else if (i.base_reg->reg_num == RegRip)
            {
              i.rm.regmem = NO_BASE_REGISTER;
              i.types[op].bitfield.disp8 = 0;
@@ -5977,7 +5976,7 @@ i386_index_check (const char *operand_string)
               || (i.prefix[ADDR_PREFIX]
                   && !i.base_reg->reg_type.bitfield.reg32))
           && (i.index_reg
-              || !UINTS_EQUAL (i.base_reg->reg_type, baseindex)))
+              || i.base_reg->reg_num != RegRip))
          || (i.index_reg
              && (!i.index_reg->reg_type.bitfield.baseindex
                  || (i.prefix[ADDR_PREFIX] == 0

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a4abe9539125439f1a21bc844e85db44fdb997ba..2fea362087a82fef7252c1e0af9a52fa558bc834 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2007-09-17  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-opc.h (RegRip): New.
+
+       * i386-reg.tbl (rip): Use RegRip for reg_num.
+       * i386-tbl.h: Regenerated.
+
 2007-09-17  Nick Clifton  <nickc@redhat.com>
 
        * po/es.po: Updated Spanish translation.

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 8a4f15b29427d840de81ff7ea2a3e115c09567fa..00fbe1c3ebaf8762c84a02ca2c3e6480b9fe973f 100644 (file)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -443,6 +443,7 @@ typedef struct
 #define RegRex     0x1  /* Extended register.  */
 #define RegRex64    0x2  /* Extended 8 bit register.  */
   unsigned int reg_num;
+#define RegRip ((unsigned int ) ~0)
 }
 reg_entry;
 

diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl
index a5103e167f4ff683c67420e140a48902f83e5df8..28debd7610ba9850ef9997dddc2beabb18a95706 100644 (file)
--- a/opcodes/i386-reg.tbl
+++ b/opcodes/i386-reg.tbl
@@ -189,7 +189,7 @@ xmm14, RegXMM, RegRex, 6
 xmm15, RegXMM, RegRex, 7
 // No type will make this register rejected for all purposes except
 // for addressing.  This saves creating one extra type for RIP.
-rip, BaseIndex, 0, 0
+rip, BaseIndex, 0, RegRip
 // fp regs.
 st(0), FloatReg|FloatAcc, 0, 0
 st(1), FloatReg, 0, 1

diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 792a18648293f730cdd9fd61f7ae389fb98260de..2f18422c9661b6bc45856f45b002dd76be9b1322 100644 (file)
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -13278,7 +13278,7 @@ const reg_entry i386_regtab[] =
   { "rip",
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    0, 0 },
+    0, RegRip },
   { "st(0)",
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 } },