opcodes/

	* mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
	for the single-operand forms of JALR and JALR.HB.
	* micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
	and JALRS.HB.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b021f906cd3f4d21dd16fe68053c477fb3041d3b..081c92445711c8283c65bc4178aec9e4fcb1816e 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
+
+       * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
+       for the single-operand forms of JALR and JALR.HB.
+       * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
+       and JALRS.HB.
+
 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 
        * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector

diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index d8e4c72198e1cf949eed5e316438cbb3596747ae..30dec8f26fd067390557baeeaed9408281d6fd5b 100644 (file)
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -707,15 +707,15 @@ const struct mips_opcode micromips_opcodes[] =
 {"j",                  "a",            0xd4000000, 0xfc000000, UBD,                    0,              I1,             0,      0 },
 {"jalr",               "mj",               0x45c0,     0xffe0, UBD|WR_31,              RD_mj|BD32,     I1,             0,      0 },
 {"jalr",               "my,mj",            0x45c0,     0xffe0, UBD|WR_31,              RD_mj|BD32,     I1,             0,      0 },
-{"jalr",               "s",            0x03e00f3c, 0xffe0ffff, UBD|RD_s|WR_t,          BD32,           I1,             0,      0 },
+{"jalr",               "s",            0x03e00f3c, 0xffe0ffff, UBD|RD_s|WR_31,         BD32,           I1,             0,      0 },
 {"jalr",               "t,s",          0x00000f3c, 0xfc00ffff, UBD|RD_s|WR_t,          BD32,           I1,             0,      0 },
-{"jalr.hb",            "s",            0x03e01f3c, 0xffe0ffff, UBD|RD_s|WR_t,          BD32,           I1,             0,      0 },
+{"jalr.hb",            "s",            0x03e01f3c, 0xffe0ffff, UBD|RD_s|WR_31,         BD32,           I1,             0,      0 },
 {"jalr.hb",            "t,s",          0x00001f3c, 0xfc00ffff, UBD|RD_s|WR_t,          BD32,           I1,             0,      0 },
 {"jalrs",              "mj",               0x45e0,     0xffe0, UBD|WR_31,              RD_mj|BD16,     I1,             0,      0 },
 {"jalrs",              "my,mj",            0x45e0,     0xffe0, UBD|WR_31,              RD_mj|BD16,     I1,             0,      0 },
-{"jalrs",              "s",            0x03e04f3c, 0xffe0ffff, UBD|RD_s|WR_t,          BD16,           I1,             0,      0 },
+{"jalrs",              "s",            0x03e04f3c, 0xffe0ffff, UBD|RD_s|WR_31,         BD16,           I1,             0,      0 },
 {"jalrs",              "t,s",          0x00004f3c, 0xfc00ffff, UBD|RD_s|WR_t,          BD16,           I1,             0,      0 },
-{"jalrs.hb",           "s",            0x03e05f3c, 0xffe0ffff, UBD|RD_s|WR_t,          BD16,           I1,             0,      0 },
+{"jalrs.hb",           "s",            0x03e05f3c, 0xffe0ffff, UBD|RD_s|WR_31,         BD16,           I1,             0,      0 },
 {"jalrs.hb",           "t,s",          0x00005f3c, 0xfc00ffff, UBD|RD_s|WR_t,          BD16,           I1,             0,      0 },
 /* SVR4 PIC code requires special handling for jal, so it must be a
    macro.  */

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 80b555baec5903b39cd7e9f89abe0426eaa00a22..ba817f518327bb7c3c9e2f45aa92e19c71d30f8e 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -942,11 +942,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
    assembler, but will never match user input (because the line above
    will match first).  */
 {"j",                  "a",            0x08000000, 0xfc000000, UBD,                    0,              I1,             0,      0 },
-{"jalr",               "s",            0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d,          0,              I1,             0,      0 },
+{"jalr",               "s",            0x0000f809, 0xfc1fffff, UBD|RD_s|WR_31,         0,              I1,             0,      0 },
 {"jalr",               "d,s",          0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d,          0,              I1,             0,      0 },
 /* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr
    with the same hazard barrier effect.  */
-{"jalr.hb",            "s",            0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d,          0,              I32,            0,      0 },
+{"jalr.hb",            "s",            0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_31,         0,              I32,            0,      0 },
 {"jalr.hb",            "d,s",          0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d,          0,              I32,            0,      0 },
 /* SVR4 PIC code requires special handling for jal, so it must be a
    macro.  */