opcodes: mark SPARC RETT instructions as v6notv9.

This prevents the disassembler to show `return' instructions as
`rett' in V9 and later architectures.

opcodes/ChangeLog:

2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 1c898b1656d1b08f1c7e607aae765a71ca135745..8595f2dc7ec262ffb56a8481067f6b929d69a4d7 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2017-04-21  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
+
 2017-04-21  Nick Clifton  <nickc@redhat.com>
 
        PR binutils/21380

diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c
index c302d835e291ad5b34daeed4cd9f65e4238988ca..021a5d8332e85e1b2f40256536c3a352cec5c296 100644 (file)
--- a/opcodes/sparc-opc.c
+++ b/opcodes/sparc-opc.c
@@ -788,13 +788,13 @@ ldtxa (0xEB), /* #ASI_TWINX_SL  */
 { "restore",   F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1),                              "1,i,d", 0, 0, 0, v6 },
 { "restore",   F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0),      "", 0, 0, 0, v6 }, /* restore %g0,0,%g0 */
 
-{ "rett",      F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0),        "1+2", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett rs1+rs2 */
-{ "rett",      F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0),    "1", F_UNBR|F_DELAYED, 0, 0, v6 },      /* rett rs1,%g0 */
-{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0,                "1+i", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett rs1+X */
-{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0,                "i+1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett X+rs1 */
-{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0,         "i", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett X+rs1 */
-{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0,         "i", F_UNBR|F_DELAYED, 0, 0, v6 },      /* rett X */
-{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0),     "1", F_UNBR|F_DELAYED, 0, 0, v6 },      /* rett rs1+0 */
+{ "rett",      F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0),        "1+2", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett rs1+rs2 */
+{ "rett",      F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0),    "1", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett rs1,%g0 */
+{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0,                "1+i", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett rs1+X */
+{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0,                "i+1", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett X+rs1 */
+{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0,         "i", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett X+rs1 */
+{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0,         "i", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett X */
+{ "rett",      F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0),     "1", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett rs1+0 */
 
 { "save",      F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0),      "1,2,d", 0, 0, 0, v6 },
 { "save",      F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1),              "1,i,d", 0, 0, 0, v6 },