X86: Remove the .s suffix from EVEX vpextrw

The .s suffix indicates that the instruction is encoded by swapping
2 register operands.  Since vpextrw takes an XMM register and an
integer register, the .s suffix should be ignored for EVEX vpextrw.

gas/

	PR binutils/20799
	* testsuite/gas/i386/opcode.s: Add a test for EVEX vpextrw.
	* testsuite/gas/i386/opcode-intel.d: Updated.
	* testsuite/gas/i386/opcode-suffix.d: Likewise.
	* testsuite/gas/i386/opcode.d: Likewise.
	* testsuite/gas/i386/x86-64-avx512bw-opts.s: Remove vpextrw
	tests.
	* testsuite/gas/i386/x86-64-avx512bw-opts-intel.d: Updated.
	* testsuite/gas/i386/x86-64-avx512bw-opts.d: Likewise.

opcodes/

	PR binutils/20799
	* i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
	* i386-dis.c (EdqwS): Removed.
	(dqw_swap_mode): Likewise.
	(intel_operand_size): Don't check dqw_swap_mode.
	(OP_E_register): Likewise.
	(OP_E_memory): Likewise.
	(OP_G): Likewise.
	(OP_EX): Likewise.
	* i386-opc.tbl: Remove "S" from EVEX vpextrw.
	* i386-tbl.h: Regerated.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 1685c862f3b43f68d8a43a74edcce9f0c7804105..2381ed7e9790c0b1556da8322e3b778b7a97db1b 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,15 @@
+2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR binutils/20799
+       * testsuite/gas/i386/opcode.s: Add a test for EVEX vpextrw.
+       * testsuite/gas/i386/opcode-intel.d: Updated.
+       * testsuite/gas/i386/opcode-suffix.d: Likewise.
+       * testsuite/gas/i386/opcode.d: Likewise.
+       * testsuite/gas/i386/x86-64-avx512bw-opts.s: Remove vpextrw
+       tests.
+       * testsuite/gas/i386/x86-64-avx512bw-opts-intel.d: Updated.
+       * testsuite/gas/i386/x86-64-avx512bw-opts.d: Likewise.
+
 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR binutils/20754

diff --git a/gas/testsuite/gas/i386/opcode-intel.d b/gas/testsuite/gas/i386/opcode-intel.d
index 6a6c86f7d4ef7684cff61adc85b8f86692e623bb..e924bf940ea859a96d752d2a8a04d25770bf5e2c 100644 (file)
--- a/gas/testsuite/gas/i386/opcode-intel.d
+++ b/gas/testsuite/gas/i386/opcode-intel.d
@@ -600,4 +600,5 @@ Disassembly of section .text:
  +[a-f0-9]+:   82 eb 01                sub    bl,0x1
  +[a-f0-9]+:   82 f3 01                xor    bl,0x1
  +[a-f0-9]+:   82 fb 01                cmp    bl,0x1
+ +[a-f0-9]+:   62 f3 7d 08 15 e8 ab    vpextrw eax,xmm5,0xab
 #pass

diff --git a/gas/testsuite/gas/i386/opcode-suffix.d b/gas/testsuite/gas/i386/opcode-suffix.d
index a5c76a3e227c4d2e1d977977be9fb1fe65f19b30..1fdd58fcfae9734054613218614c0d3bc3233300 100644 (file)
--- a/gas/testsuite/gas/i386/opcode-suffix.d
+++ b/gas/testsuite/gas/i386/opcode-suffix.d
@@ -600,4 +600,5 @@ Disassembly of section .text:
  +[a-f0-9]+:   82 eb 01                subb   \$0x1,%bl
  +[a-f0-9]+:   82 f3 01                xorb   \$0x1,%bl
  +[a-f0-9]+:   82 fb 01                cmpb   \$0x1,%bl
+ +[a-f0-9]+:   62 f3 7d 08 15 e8 ab    vpextrw \$0xab,%xmm5,%eax
 #pass

diff --git a/gas/testsuite/gas/i386/opcode.d b/gas/testsuite/gas/i386/opcode.d
index 2294f64ab1cc4d234adc8660fa8f7437808a7ad8..dd898281f44362fcc699c6267aab57a16be38227 100644 (file)
--- a/gas/testsuite/gas/i386/opcode.d
+++ b/gas/testsuite/gas/i386/opcode.d
@@ -599,4 +599,5 @@ Disassembly of section .text:
  +[a-f0-9]+:   82 eb 01                sub    \$0x1,%bl
  +[a-f0-9]+:   82 f3 01                xor    \$0x1,%bl
  +[a-f0-9]+:   82 fb 01                cmp    \$0x1,%bl
+ +[a-f0-9]+:   62 f3 7d 08 15 e8 ab    vpextrw \$0xab,%xmm5,%eax
 #pass

diff --git a/gas/testsuite/gas/i386/opcode.s b/gas/testsuite/gas/i386/opcode.s
index 001a1148179b3dcd322e5cee05caec2df2f3f0a7..101085a660e4ae05d3e0cd753ee516e74f63b5c2 100644 (file)
--- a/gas/testsuite/gas/i386/opcode.s
+++ b/gas/testsuite/gas/i386/opcode.s
@@ -598,3 +598,5 @@ foo:
        .byte 0x82, 0xeb, 0x01
        .byte 0x82, 0xf3, 0x01
        .byte 0x82, 0xfb, 0x01
+
+       .byte 0x62, 0xf3, 0x7d, 0x08, 0x15, 0xe8, 0xab

diff --git a/gas/testsuite/gas/i386/x86-64-avx512bw-opts-intel.d b/gas/testsuite/gas/i386/x86-64-avx512bw-opts-intel.d
index 9e1631125f87df30dcba2474da58f417bd098550..c4815af5abd981db2e1250dcd9accf9a36adf88d 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-avx512bw-opts-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-avx512bw-opts-intel.d
@@ -9,18 +9,6 @@
 Disassembly of section \.text:
 
 0+ <_start>:
-[      ]*[a-f0-9]+:[   ]*62 91 fd 08 c5 c5 ab[         ]*vpextrw rax,xmm29,0xab
-[      ]*[a-f0-9]+:[   ]*62 63 fd 08 15 e8 ab[         ]*vpextrw\.s rax,xmm29,0xab
-[      ]*[a-f0-9]+:[   ]*62 91 fd 08 c5 c5 7b[         ]*vpextrw rax,xmm29,0x7b
-[      ]*[a-f0-9]+:[   ]*62 63 fd 08 15 e8 7b[         ]*vpextrw\.s rax,xmm29,0x7b
-[      ]*[a-f0-9]+:[   ]*62 11 fd 08 c5 c5 7b[         ]*vpextrw r8,xmm29,0x7b
-[      ]*[a-f0-9]+:[   ]*62 43 fd 08 15 e8 7b[         ]*vpextrw\.s r8,xmm29,0x7b
-[      ]*[a-f0-9]+:[   ]*62 91 fd 08 c5 c5 ab[         ]*vpextrw rax,xmm29,0xab
-[      ]*[a-f0-9]+:[   ]*62 63 fd 08 15 e8 ab[         ]*vpextrw\.s rax,xmm29,0xab
-[      ]*[a-f0-9]+:[   ]*62 91 fd 08 c5 c5 7b[         ]*vpextrw rax,xmm29,0x7b
-[      ]*[a-f0-9]+:[   ]*62 63 fd 08 15 e8 7b[         ]*vpextrw\.s rax,xmm29,0x7b
-[      ]*[a-f0-9]+:[   ]*62 11 fd 08 c5 c5 7b[         ]*vpextrw r8,xmm29,0x7b
-[      ]*[a-f0-9]+:[   ]*62 43 fd 08 15 e8 7b[         ]*vpextrw\.s r8,xmm29,0x7b
 [      ]*[a-f0-9]+:[   ]*62 01 7f 48 6f f5[    ]*vmovdqu8 zmm30,zmm29
 [      ]*[a-f0-9]+:[   ]*62 01 7f 48 7f ee[    ]*vmovdqu8\.s zmm30,zmm29
 [      ]*[a-f0-9]+:[   ]*62 01 7f 4f 6f f5[    ]*vmovdqu8 zmm30\{k7\},zmm29
@@ -45,18 +33,6 @@ Disassembly of section \.text:
 [      ]*[a-f0-9]+:[   ]*62 01 ff 4f 7f ee[    ]*vmovdqu16\.s zmm30\{k7\},zmm29
 [      ]*[a-f0-9]+:[   ]*62 01 ff cf 6f f5[    ]*vmovdqu16 zmm30\{k7\}\{z\},zmm29
 [      ]*[a-f0-9]+:[   ]*62 01 ff cf 7f ee[    ]*vmovdqu16\.s zmm30\{k7\}\{z\},zmm29
-[      ]*[a-f0-9]+:[   ]*62 91 fd 08 c5 c5 ab[         ]*vpextrw rax,xmm29,0xab
-[      ]*[a-f0-9]+:[   ]*62 63 fd 08 15 e8 ab[         ]*vpextrw\.s rax,xmm29,0xab
-[      ]*[a-f0-9]+:[   ]*62 91 fd 08 c5 c5 7b[         ]*vpextrw rax,xmm29,0x7b
-[      ]*[a-f0-9]+:[   ]*62 63 fd 08 15 e8 7b[         ]*vpextrw\.s rax,xmm29,0x7b
-[      ]*[a-f0-9]+:[   ]*62 11 fd 08 c5 c5 7b[         ]*vpextrw r8,xmm29,0x7b
-[      ]*[a-f0-9]+:[   ]*62 43 fd 08 15 e8 7b[         ]*vpextrw\.s r8,xmm29,0x7b
-[      ]*[a-f0-9]+:[   ]*62 91 fd 08 c5 c5 ab[         ]*vpextrw rax,xmm29,0xab
-[      ]*[a-f0-9]+:[   ]*62 63 fd 08 15 e8 ab[         ]*vpextrw\.s rax,xmm29,0xab
-[      ]*[a-f0-9]+:[   ]*62 91 fd 08 c5 c5 7b[         ]*vpextrw rax,xmm29,0x7b
-[      ]*[a-f0-9]+:[   ]*62 63 fd 08 15 e8 7b[         ]*vpextrw\.s rax,xmm29,0x7b
-[      ]*[a-f0-9]+:[   ]*62 11 fd 08 c5 c5 7b[         ]*vpextrw r8,xmm29,0x7b
-[      ]*[a-f0-9]+:[   ]*62 43 fd 08 15 e8 7b[         ]*vpextrw\.s r8,xmm29,0x7b
 [      ]*[a-f0-9]+:[   ]*62 01 7f 48 6f f5[    ]*vmovdqu8 zmm30,zmm29
 [      ]*[a-f0-9]+:[   ]*62 01 7f 48 7f ee[    ]*vmovdqu8\.s zmm30,zmm29
 [      ]*[a-f0-9]+:[   ]*62 01 7f 4f 6f f5[    ]*vmovdqu8 zmm30\{k7\},zmm29

diff --git a/gas/testsuite/gas/i386/x86-64-avx512bw-opts.d b/gas/testsuite/gas/i386/x86-64-avx512bw-opts.d
index 9146337cb86cdcd4dce344e3d6c99de90a66bed7..8ddb25e21ffee42c8e1648d8bd588cf1ba46b849 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-avx512bw-opts.d
+++ b/gas/testsuite/gas/i386/x86-64-avx512bw-opts.d
@@ -9,18 +9,6 @@
 Disassembly of section \.text:
 
 0+ <_start>:
-[      ]*[a-f0-9]+:[   ]*62 91 fd 08 c5 c5 ab[         ]*vpextrw \$0xab,%xmm29,%rax
-[      ]*[a-f0-9]+:[   ]*62 63 fd 08 15 e8 ab[         ]*vpextrw\.s \$0xab,%xmm29,%rax
-[      ]*[a-f0-9]+:[   ]*62 91 fd 08 c5 c5 7b[         ]*vpextrw \$0x7b,%xmm29,%rax
-[      ]*[a-f0-9]+:[   ]*62 63 fd 08 15 e8 7b[         ]*vpextrw\.s \$0x7b,%xmm29,%rax
-[      ]*[a-f0-9]+:[   ]*62 11 fd 08 c5 c5 7b[         ]*vpextrw \$0x7b,%xmm29,%r8
-[      ]*[a-f0-9]+:[   ]*62 43 fd 08 15 e8 7b[         ]*vpextrw\.s \$0x7b,%xmm29,%r8
-[      ]*[a-f0-9]+:[   ]*62 91 fd 08 c5 c5 ab[         ]*vpextrw \$0xab,%xmm29,%rax
-[      ]*[a-f0-9]+:[   ]*62 63 fd 08 15 e8 ab[         ]*vpextrw\.s \$0xab,%xmm29,%rax
-[      ]*[a-f0-9]+:[   ]*62 91 fd 08 c5 c5 7b[         ]*vpextrw \$0x7b,%xmm29,%rax
-[      ]*[a-f0-9]+:[   ]*62 63 fd 08 15 e8 7b[         ]*vpextrw\.s \$0x7b,%xmm29,%rax
-[      ]*[a-f0-9]+:[   ]*62 11 fd 08 c5 c5 7b[         ]*vpextrw \$0x7b,%xmm29,%r8
-[      ]*[a-f0-9]+:[   ]*62 43 fd 08 15 e8 7b[         ]*vpextrw\.s \$0x7b,%xmm29,%r8
 [      ]*[a-f0-9]+:[   ]*62 01 7f 48 6f f5[    ]*vmovdqu8 %zmm29,%zmm30
 [      ]*[a-f0-9]+:[   ]*62 01 7f 48 7f ee[    ]*vmovdqu8\.s %zmm29,%zmm30
 [      ]*[a-f0-9]+:[   ]*62 01 7f 4f 6f f5[    ]*vmovdqu8 %zmm29,%zmm30\{%k7\}
@@ -45,18 +33,6 @@ Disassembly of section \.text:
 [      ]*[a-f0-9]+:[   ]*62 01 ff 4f 7f ee[    ]*vmovdqu16\.s %zmm29,%zmm30\{%k7\}
 [      ]*[a-f0-9]+:[   ]*62 01 ff cf 6f f5[    ]*vmovdqu16 %zmm29,%zmm30\{%k7\}\{z\}
 [      ]*[a-f0-9]+:[   ]*62 01 ff cf 7f ee[    ]*vmovdqu16\.s %zmm29,%zmm30\{%k7\}\{z\}
-[      ]*[a-f0-9]+:[   ]*62 91 fd 08 c5 c5 ab[         ]*vpextrw \$0xab,%xmm29,%rax
-[      ]*[a-f0-9]+:[   ]*62 63 fd 08 15 e8 ab[         ]*vpextrw\.s \$0xab,%xmm29,%rax
-[      ]*[a-f0-9]+:[   ]*62 91 fd 08 c5 c5 7b[         ]*vpextrw \$0x7b,%xmm29,%rax
-[      ]*[a-f0-9]+:[   ]*62 63 fd 08 15 e8 7b[         ]*vpextrw\.s \$0x7b,%xmm29,%rax
-[      ]*[a-f0-9]+:[   ]*62 11 fd 08 c5 c5 7b[         ]*vpextrw \$0x7b,%xmm29,%r8
-[      ]*[a-f0-9]+:[   ]*62 43 fd 08 15 e8 7b[         ]*vpextrw\.s \$0x7b,%xmm29,%r8
-[      ]*[a-f0-9]+:[   ]*62 91 fd 08 c5 c5 ab[         ]*vpextrw \$0xab,%xmm29,%rax
-[      ]*[a-f0-9]+:[   ]*62 63 fd 08 15 e8 ab[         ]*vpextrw\.s \$0xab,%xmm29,%rax
-[      ]*[a-f0-9]+:[   ]*62 91 fd 08 c5 c5 7b[         ]*vpextrw \$0x7b,%xmm29,%rax
-[      ]*[a-f0-9]+:[   ]*62 63 fd 08 15 e8 7b[         ]*vpextrw\.s \$0x7b,%xmm29,%rax
-[      ]*[a-f0-9]+:[   ]*62 11 fd 08 c5 c5 7b[         ]*vpextrw \$0x7b,%xmm29,%r8
-[      ]*[a-f0-9]+:[   ]*62 43 fd 08 15 e8 7b[         ]*vpextrw\.s \$0x7b,%xmm29,%r8
 [      ]*[a-f0-9]+:[   ]*62 01 7f 48 6f f5[    ]*vmovdqu8 %zmm29,%zmm30
 [      ]*[a-f0-9]+:[   ]*62 01 7f 48 7f ee[    ]*vmovdqu8\.s %zmm29,%zmm30
 [      ]*[a-f0-9]+:[   ]*62 01 7f 4f 6f f5[    ]*vmovdqu8 %zmm29,%zmm30\{%k7\}

diff --git a/gas/testsuite/gas/i386/x86-64-avx512bw-opts.s b/gas/testsuite/gas/i386/x86-64-avx512bw-opts.s
index 99ba78668ab352bcb63ab5ff259e0007fec7c6c8..c907c2ca0028c1636f721ad76e4519f8473124ed 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-avx512bw-opts.s
+++ b/gas/testsuite/gas/i386/x86-64-avx512bw-opts.s
@@ -3,18 +3,6 @@
        .allow_index_reg
        .text
 _start:
-       vpextrw $0xab, %xmm29, %rax      # AVX512BW
-       vpextrw.s       $0xab, %xmm29, %rax      # AVX512BW
-       vpextrw $123, %xmm29, %rax       # AVX512BW
-       vpextrw.s       $123, %xmm29, %rax       # AVX512BW
-       vpextrw $123, %xmm29, %r8        # AVX512BW
-       vpextrw.s       $123, %xmm29, %r8        # AVX512BW
-       vpextrw $0xab, %xmm29, %rax      # AVX512BW
-       vpextrw.s       $0xab, %xmm29, %rax      # AVX512BW
-       vpextrw $123, %xmm29, %rax       # AVX512BW
-       vpextrw.s       $123, %xmm29, %rax       # AVX512BW
-       vpextrw $123, %xmm29, %r8        # AVX512BW
-       vpextrw.s       $123, %xmm29, %r8        # AVX512BW
        vmovdqu8        %zmm29, %zmm30   # AVX512BW
        vmovdqu8.s      %zmm29, %zmm30   # AVX512BW
        vmovdqu8        %zmm29, %zmm30{%k7}      # AVX512BW
@@ -41,18 +29,6 @@ _start:
        vmovdqu16.s     %zmm29, %zmm30{%k7}{z}   # AVX512BW
 
        .intel_syntax noprefix
-       vpextrw rax, xmm29, 0xab         # AVX512BW
-       vpextrw.s       rax, xmm29, 0xab         # AVX512BW
-       vpextrw rax, xmm29, 123  # AVX512BW
-       vpextrw.s       rax, xmm29, 123  # AVX512BW
-       vpextrw r8, xmm29, 123   # AVX512BW
-       vpextrw.s       r8, xmm29, 123   # AVX512BW
-       vpextrw rax, xmm29, 0xab         # AVX512BW
-       vpextrw.s       rax, xmm29, 0xab         # AVX512BW
-       vpextrw rax, xmm29, 123  # AVX512BW
-       vpextrw.s       rax, xmm29, 123  # AVX512BW
-       vpextrw r8, xmm29, 123   # AVX512BW
-       vpextrw.s       r8, xmm29, 123   # AVX512BW
        vmovdqu8        zmm30, zmm29     # AVX512BW
        vmovdqu8.s      zmm30, zmm29     # AVX512BW
        vmovdqu8        zmm30{k7}, zmm29         # AVX512BW

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 1a5c49ba5cec466f915cd9a39d62828e3c6bae7b..53f2a94efb36df1f3debe582de56aaa425922469 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,17 @@
+2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR binutils/20799
+       * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
+       * i386-dis.c (EdqwS): Removed.
+       (dqw_swap_mode): Likewise.
+       (intel_operand_size): Don't check dqw_swap_mode.
+       (OP_E_register): Likewise.
+       (OP_E_memory): Likewise.
+       (OP_G): Likewise.
+       (OP_EX): Likewise.
+       * i386-opc.tbl: Remove "S" from EVEX vpextrw.
+       * i386-tbl.h: Regerated.
+
 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 
        * i386-opc.tbl: Merge AVX512F vmovq.

diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index 0f8327b0455c8a17f92119e60f9da061016f7b5f..267bad7ef772fdfb6aac189cb6627f611485d91e 100644 (file)
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -2561,7 +2561,7 @@ static const struct dis386 evex_table[][256] = {
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vpextrw",       { EdqwS, XM, Ib }, 0 },
+    { "vpextrw",       { Edqw, XM, Ib }, 0 },
   },
   /* PREFIX_EVEX_0F3A16 */
   {

diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index a15eabf038fc8801d6097622805a4e67f6c4a36f..5f49f919935ad61563c805337b6c79f49f37d18a 100644 (file)
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -252,7 +252,6 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
 #define Ed { OP_E, d_mode }
 #define Edq { OP_E, dq_mode }
 #define Edqw { OP_E, dqw_mode }
-#define EdqwS { OP_E, dqw_swap_mode }
 #define Edqb { OP_E, dqb_mode }
 #define Edb { OP_E, db_mode }
 #define Edw { OP_E, dw_mode }
@@ -556,7 +555,6 @@ enum
   dq_mode,
   /* registers like dq_mode, memory like w_mode.  */
   dqw_mode,
-  dqw_swap_mode,
   bnd_mode,
   /* 4- or 6-byte pointer operand */
   f_mode,
@@ -14552,7 +14550,6 @@ intel_operand_size (int bytemode, int sizeflag)
     case w_mode:
     case dw_mode:
     case dqw_mode:
-    case dqw_swap_mode:
       oappend ("WORD PTR ");
       break;
     case indir_v_mode:
@@ -14907,8 +14904,7 @@ OP_E_register (int bytemode, int sizeflag)
 
   if ((sizeflag & SUFFIX_ALWAYS)
       && (bytemode == b_swap_mode
-         || bytemode == v_swap_mode
-         || bytemode == dqw_swap_mode))
+         || bytemode == v_swap_mode))
     swap_operand ();
 
   switch (bytemode)
@@ -14960,7 +14956,6 @@ OP_E_register (int bytemode, int sizeflag)
     case dqb_mode:
     case dqd_mode:
     case dqw_mode:
-    case dqw_swap_mode:
       USED_REX (REX_W);
       if (rex & REX_W)
        names = names64;
@@ -15016,7 +15011,6 @@ OP_E_memory (int bytemode, int sizeflag)
        {
        case dqw_mode:
        case dw_mode:
-       case dqw_swap_mode:
          shift = 1;
          break;
        case dqb_mode:
@@ -15490,7 +15484,6 @@ OP_G (int bytemode, int sizeflag)
     case dqb_mode:
     case dqd_mode:
     case dqw_mode:
-    case dqw_swap_mode:
       USED_REX (REX_W);
       if (rex & REX_W)
        oappend (names64[modrm.reg + add]);
@@ -16345,7 +16338,6 @@ OP_EX (int bytemode, int sizeflag)
   if ((sizeflag & SUFFIX_ALWAYS)
       && (bytemode == x_swap_mode
          || bytemode == d_swap_mode
-         || bytemode == dqw_swap_mode
          || bytemode == d_scalar_swap_mode
          || bytemode == q_swap_mode
          || bytemode == q_scalar_swap_mode))

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 3b23194429a7440b59b4579ba5d403fe31ebbd9d..fba01b62cd0dd9b046cdfad929c74a27f15174a0 100644 (file)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -5577,7 +5577,7 @@ vpcmpeqw, 3, 0x6675, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|Ve
 vpcmpgtw, 3, 0x6665, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
 vpcmpgtw, 3, 0x6665, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
 vpcmpgtw, 3, 0x6665, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
-vpextrw, 3, 0x66C5, None, 1, CpuAVX512BW, Modrm|S|EVex=4|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 }
+vpextrw, 3, 0x66C5, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 }
 vpinsrw, 4, 0x66C4, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
 
 vpcmpuw, 4, 0x663E, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }

diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index fe087ba3c965f6c32dee4ce0ca52c6623ea77dbe..ed4860a7028a36851f43795405f61776a2d310b5 100644 (file)
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -45875,7 +45875,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
       1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0 },