RISC-V/bfd: Hook elf_backend_object_p to set the mach type.

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index ef7d68c2c4ae369d89edf64d0a083364b9953988..3fae9ddfc1e04711075af8309d40190e8ce000ba 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,7 @@
+2017-01-17  Kuan-Lin Chen  <kuanlinchentw@gmail.com>
+
+       * elfnn-riscv.c (riscv_elf_object_p): New function.
+
 2017-01-12  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR ld/21038

diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
index f414429ebe8420a3cf66e2c4d326c60740a888fa..320d318ce5b4f446d18f1ab845da0b1c987f1242 100644 (file)
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -3191,6 +3191,19 @@ riscv_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
   return TRUE;
 }
 
+/* Set the right mach type.  */
+static bfd_boolean
+riscv_elf_object_p (bfd *abfd)
+{
+  /* There are only two mach types in RISCV currently.  */
+  if (strcmp (abfd->xvec->name, "elf32-littleriscv") == 0)
+    bfd_default_set_arch_mach (abfd, bfd_arch_riscv, bfd_mach_riscv32);
+  else
+    bfd_default_set_arch_mach (abfd, bfd_arch_riscv, bfd_mach_riscv64);
+
+  return TRUE;
+}
+
 
 #define TARGET_LITTLE_SYM              riscv_elfNN_vec
 #define TARGET_LITTLE_NAME             "elfNN-littleriscv"
@@ -3216,6 +3229,7 @@ riscv_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
 #define elf_backend_plt_sym_val                     riscv_elf_plt_sym_val
 #define elf_backend_grok_prstatus            riscv_elf_grok_prstatus
 #define elf_backend_grok_psinfo              riscv_elf_grok_psinfo
+#define elf_backend_object_p                 riscv_elf_object_p
 #define elf_info_to_howto_rel               NULL
 #define elf_info_to_howto                   riscv_info_to_howto_rela
 #define bfd_elfNN_bfd_relax_section         _bfd_riscv_relax_section