x86: correct UDn

Make the assembler recognize UD0, supporting only the newer form
expecting a ModR/M byte.

Make assembler and disassembler properly emit / expect a ModR/M byte for
UD1.

For the testsuite, as arch-4 already tests all UDn, avoid producing a
huge delta for other tests using UD2B by making them use UD2 instead.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 8b6f8f9224fab9a277df4b379f4ae637e6f5a6b9..c00280754803983c1639db3bc095551e260c9e8a 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,12 @@
+2017-11-23  Jan Beulich  <jbeulich@suse.com>
+
+       * testsuite/gas/i386/arch-4.s: Correct ud1 and ud2b. Add ud0.
+       * testsuite/gas/i386/intel.s: Test ud2 instead of ud2b.
+       * testsuite/gas/i386/opcode.s: Likewise.
+       * testsuite/gas/i386/arch-4.d, testsuite/gas/i386/intel.d,
+       testsuite/gas/i386/opcode.d, testsuite/gas/i386/opcode-intel.d,
+       testsuite/gas/i386/opcode-suffix.d: Adjust expectations.
+
 2017-11-23  Jan Beulich  <jbeulich@suse.com>
 
        * config/tc-i386-intel.c (i386_intel_operand): Don't call

diff --git a/gas/testsuite/gas/i386/arch-4.d b/gas/testsuite/gas/i386/arch-4.d
index 05375d74ae344d80faf066d37a8d33cf331937e6..dc2c05dfdcdf3a7c057aaf758b050da438c5272c 100644 (file)
--- a/gas/testsuite/gas/i386/arch-4.d
+++ b/gas/testsuite/gas/i386/arch-4.d
@@ -1,4 +1,3 @@
-#as: -march=generic32
 #objdump: -dw
 #name: i386 arch 4
 
@@ -7,8 +6,9 @@
 Disassembly of section .text:
 
 0+ <.text>:
-[      ]*[a-f0-9]+:    0f b9                   ud1    
+[      ]*[a-f0-9]+:    0f ff 07 [      ]*ud0    \(%edi\),%eax
+[      ]*[a-f0-9]+:    0f b9 07 [      ]*ud1    \(%edi\),%eax
 [      ]*[a-f0-9]+:    0f 0b                   ud2    
 [      ]*[a-f0-9]+:    0f 0b                   ud2    
-[      ]*[a-f0-9]+:    0f b9                   ud1    
+[      ]*[a-f0-9]+:    0f b9 07 [      ]*ud1    \(%edi\),%eax
 #pass

diff --git a/gas/testsuite/gas/i386/arch-4.s b/gas/testsuite/gas/i386/arch-4.s
index 75d53bb4a1d2e9f52964885b04c0bc6f3a7f5b68..cf14d736b3614fa4fe93b1d4b7ce9673a81869f6 100644 (file)
--- a/gas/testsuite/gas/i386/arch-4.s
+++ b/gas/testsuite/gas/i386/arch-4.s
@@ -1,5 +1,6 @@
        .text
-       ud1
+       ud0     (%edi),%eax
+       ud1     (%edi),%eax
        ud2
        ud2a
-       ud2b
+       ud2b    (%edi),%eax

diff --git a/gas/testsuite/gas/i386/intel.d b/gas/testsuite/gas/i386/intel.d
index 836acd601dc5cfe969d6e106e34281af1bb94902..8401d10906f97a5f6f500323cda8468ba8e1a6eb 100644 (file)
--- a/gas/testsuite/gas/i386/intel.d
+++ b/gas/testsuite/gas/i386/intel.d
@@ -360,7 +360,7 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    0f b5 90 90 90 90 90 [  ]*lgs    -0x6f6f6f70\(%eax\),%edx
 [      ]*[a-f0-9]+:    0f b6 90 90 90 90 90 [  ]*movzbl -0x6f6f6f70\(%eax\),%edx
 [      ]*[a-f0-9]+:    0f b7 90 90 90 90 90 [  ]*movzwl -0x6f6f6f70\(%eax\),%edx
-[      ]*[a-f0-9]+:    0f b9 [         ]*ud1    
+[      ]*[a-f0-9]+:    0f 0b [         ]*ud2[  ]*
 [      ]*[a-f0-9]+:    0f bb 90 90 90 90 90 [  ]*btc    %edx,-0x6f6f6f70\(%eax\)
 [      ]*[a-f0-9]+:    0f bc 90 90 90 90 90 [  ]*bsf    -0x6f6f6f70\(%eax\),%edx
 [      ]*[a-f0-9]+:    0f bd 90 90 90 90 90 [  ]*bsr    -0x6f6f6f70\(%eax\),%edx

diff --git a/gas/testsuite/gas/i386/intel.s b/gas/testsuite/gas/i386/intel.s
index 813daaa60df87ac705578eb3281d96925439a8f2..54249d35b6b0659f4c638541a8cef339a7d4e38c 100644 (file)
--- a/gas/testsuite/gas/i386/intel.s
+++ b/gas/testsuite/gas/i386/intel.s
@@ -353,7 +353,7 @@ foo:
  lgs    edx, 0x90909090[eax]
  movzx  edx, byte ptr 0x90909090[eax]
  movzx  edx, word ptr 0x90909090[eax]
- ud2b
+ ud2
  btc    0x90909090[eax], edx
  bsf    edx, 0x90909090[eax]
  bsr    edx, 0x90909090[eax]

diff --git a/gas/testsuite/gas/i386/opcode-intel.d b/gas/testsuite/gas/i386/opcode-intel.d
index 404758c2bfce01265285b52d7c08a0ae61d30bbd..434b0e39701abd8bd29dbe470c36f5a6a93a0f25 100644 (file)
--- a/gas/testsuite/gas/i386/opcode-intel.d
+++ b/gas/testsuite/gas/i386/opcode-intel.d
@@ -358,7 +358,7 @@ Disassembly of section .text:
  *[0-9a-f]+:   0f b5 90 90 90 90 90[   ]+lgs[  ]+edx,(FWORD PTR )?\[eax-0x6f6f6f70\]
  *[0-9a-f]+:   0f b6 90 90 90 90 90[   ]+movzx[        ]+edx,BYTE PTR \[eax-0x6f6f6f70\]
  *[0-9a-f]+:   0f b7 90 90 90 90 90[   ]+movzx[        ]+edx,WORD PTR \[eax-0x6f6f6f70\]
- *[0-9a-f]+:   0f b9[  ]+ud1[  ]*
+ *[0-9a-f]+:   0f 0b[  ]+ud2[  ]*
  *[0-9a-f]+:   0f bb 90 90 90 90 90[   ]+btc[  ]+(DWORD PTR )?\[eax-0x6f6f6f70\],edx
  *[0-9a-f]+:   0f bc 90 90 90 90 90[   ]+bsf[  ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]
  *[0-9a-f]+:   0f bd 90 90 90 90 90[   ]+bsr[  ]+edx,(DWORD PTR )?\[eax-0x6f6f6f70\]

diff --git a/gas/testsuite/gas/i386/opcode-suffix.d b/gas/testsuite/gas/i386/opcode-suffix.d
index 1fdd58fcfae9734054613218614c0d3bc3233300..059a10cd47077898a53be6caca87e62fb0e0e5d2 100644 (file)
--- a/gas/testsuite/gas/i386/opcode-suffix.d
+++ b/gas/testsuite/gas/i386/opcode-suffix.d
@@ -358,7 +358,7 @@ Disassembly of section .text:
  *[0-9a-f]+:   0f b5 90 90 90 90 90[   ]+lgsl[         ]+-0x6f6f6f70\(%eax\),%edx
  *[0-9a-f]+:   0f b6 90 90 90 90 90[   ]+movzbl -0x6f6f6f70\(%eax\),%edx
  *[0-9a-f]+:   0f b7 90 90 90 90 90[   ]+movzwl -0x6f6f6f70\(%eax\),%edx
- *[0-9a-f]+:   0f b9[  ]+ud1[  ]+
+ *[0-9a-f]+:   0f 0b[  ]+ud2[  ]*
  *[0-9a-f]+:   0f bb 90 90 90 90 90[   ]+btcl[         ]+%edx,-0x6f6f6f70\(%eax\)
  *[0-9a-f]+:   0f bc 90 90 90 90 90[   ]+bsfl[         ]+-0x6f6f6f70\(%eax\),%edx
  *[0-9a-f]+:   0f bd 90 90 90 90 90[   ]+bsrl[         ]+-0x6f6f6f70\(%eax\),%edx

diff --git a/gas/testsuite/gas/i386/opcode.d b/gas/testsuite/gas/i386/opcode.d
index b80a78cd4b60a10b4a1f25c857a97de75283602e..f2897ff38d877eabf11fab5013767456e8f51a46 100644 (file)
--- a/gas/testsuite/gas/i386/opcode.d
+++ b/gas/testsuite/gas/i386/opcode.d
@@ -357,7 +357,7 @@ Disassembly of section .text:
  57e:  0f b5 90 90 90 90 90 [  ]*lgs    -0x6f6f6f70\(%eax\),%edx
  585:  0f b6 90 90 90 90 90 [  ]*movzbl -0x6f6f6f70\(%eax\),%edx
  58c:  0f b7 90 90 90 90 90 [  ]*movzwl -0x6f6f6f70\(%eax\),%edx
- 593:  0f b9 [         ]*ud1    
+ 593:  0f 0b [         ]*ud2[  ]*
  595:  0f bb 90 90 90 90 90 [  ]*btc    %edx,-0x6f6f6f70\(%eax\)
  59c:  0f bc 90 90 90 90 90 [  ]*bsf    -0x6f6f6f70\(%eax\),%edx
  5a3:  0f bd 90 90 90 90 90 [  ]*bsr    -0x6f6f6f70\(%eax\),%edx

diff --git a/gas/testsuite/gas/i386/opcode.s b/gas/testsuite/gas/i386/opcode.s
index db47446dfa9211c3188c60907c50933a38c73f17..ca521116f744d6fb810ee4b4130c04a24fc5b67a 100644 (file)
--- a/gas/testsuite/gas/i386/opcode.s
+++ b/gas/testsuite/gas/i386/opcode.s
@@ -350,7 +350,7 @@ foo:
  lgs    0x90909090(%eax),%edx
  movzbl 0x90909090(%eax),%edx
  movzwl 0x90909090(%eax),%edx
- ud2b
+ ud2
  btc    %edx,0x90909090(%eax)
  bsf    0x90909090(%eax),%edx
  bsr    0x90909090(%eax),%edx

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 9ca089c27f661debdc9fd0514bd34cd0ce50bf59..57624662036ce889021ab69b4ee9cc89e678934e 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,11 @@
+2017-11-23  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.
+       (twobyte_has_modrm): Set flag for index 0xb9 and 0xff.
+       * i386-opc.tbl (ud1, ud2b): Add operands.
+       (ud0): New.
+       * i386-tbl.h: Re-generate.
+
 2017-11-22  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 
        * i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.

diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 64b47028fd4e34d68cc78de529847b1057fa5535..12b723a40566521ee6872b883244f9baf6585701 100644 (file)
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -3067,7 +3067,7 @@ static const struct dis386 dis386_twobyte[] = {
   { "movz{wR|x}",      { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
   /* b8 */
   { PREFIX_TABLE (PREFIX_0FB8) },
-  { "ud1",             { XX }, 0 },
+  { "ud1S",            { Gv, Ev }, 0 },
   { REG_TABLE (REG_0FBA) },
   { "btcS",            { Evh1, Gv }, 0 },
   { PREFIX_TABLE (PREFIX_0FBC) },
@@ -3145,7 +3145,7 @@ static const struct dis386 dis386_twobyte[] = {
   { "paddb",           { MX, EM }, PREFIX_OPCODE },
   { "paddw",           { MX, EM }, PREFIX_OPCODE },
   { "paddd",           { MX, EM }, PREFIX_OPCODE },
-  { Bad_Opcode },
+  { "ud0S",            { Gv, Ev }, 0 },
 };
 
 static const unsigned char onebyte_has_modrm[256] = {
@@ -3185,11 +3185,11 @@ static const unsigned char twobyte_has_modrm[256] = {
   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
-  /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
+  /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
-  /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
+  /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
   /*       -------------------------------        */
   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
 };

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index ec478d7e8259e4880db8a6f017a373f710d6c122..eb4d62f008f8a31b63272f95f22ab45851bf0e3b 100644 (file)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -861,9 +861,11 @@ ud2, 0, 0xf0b, None, 2, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf
 // alias for ud2
 ud2a, 0, 0xf0b, None, 2, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 // 2nd. official undefined instr.
-ud1, 0, 0xfb9, None, 2, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+ud1, 2, 0xfb9, None, 2, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
 // alias for ud1
-ud2b, 0, 0xfb9, None, 2, Cpu186, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+ud2b, 2, 0xfb9, None, 2, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
+// 3rd official undefined instr (older CPUs don't take a ModR/M byte)
+ud0, 2, 0xfff, None, 2, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
 
 cmovo, 2, 0xf40, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
 cmovno, 2, 0xf41, None, 2, Cpu686, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }

diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index da12e2837ad625c09c58bb81cbb0a59268cd1e3c..33a885088b6a43f96c7b5da1ffe67d8f0dd8b955 100644 (file)
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -9579,32 +9579,55 @@ const insn_template i386_optab[] =
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
-  { "ud1", 0, 0xfb9, None, 2,
+  { "ud1", 2, 0xfb9, None, 2,
     { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0 } },
-    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,
-      1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0 },
-    { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+         0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0,
+         1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } },
+      { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
-  { "ud2b", 0, 0xfb9, None, 2,
+  { "ud2b", 2, 0xfb9, None, 2,
     { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0 } },
-    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,
-      1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0 },
-    { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+         0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0,
+         1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } },
+      { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
+  { "ud0", 2, 0xfff, None, 2,
+    { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0 } },
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+      0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 0 },
+    { { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+         0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0,
+         1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } },
+      { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
   { "cmovo", 2, 0xf40, None, 2,