Correct wclr encoding.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index c267d2c3755589bebeea66a3a4e21d79cfcd19e9..0f36e6f4c0aab0b3ae5ea837153dff541ca1e586 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2010-05-13  Alan Modra  <amodra@gmail.com>
+
+       * gas/ppc/a2.d: Correct wclr encoding.
+
 2010-05-11  Andrew Stubbs  <ams@codesourcery.com>
 
        * gas/arm/attr-cpu-directive.d: Add Tag_DIV_use.

diff --git a/gas/testsuite/gas/ppc/a2.d b/gas/testsuite/gas/ppc/a2.d
index 02414b9b17bcf6f9bc75b4df9ed3ec79be450e12..d4be915fd20ae5bf92f686f71b8377bb5bc50e04 100644 (file)
--- a/gas/testsuite/gas/ppc/a2.d
+++ b/gas/testsuite/gas/ppc/a2.d
@@ -573,9 +573,9 @@ Disassembly of section \.text:
  884:  7c 00 01 6c     wchkall 
  888:  7c 00 01 6c     wchkall 
  88c:  7d 80 01 6c     wchkall cr3
- 890:  7c 2a 5d 6c     wclr    1,r10,r11
- 894:  7c 20 05 6c     wclrall 1
- 898:  7c 4a 5d 6c     wclrone r10,r11
+ 890:  7c 2a 5f 4c     wclr    1,r10,r11
+ 894:  7c 20 07 4c     wclrall 1
+ 898:  7c 4a 5f 4c     wclrone r10,r11
  89c:  7d 40 01 06     wrtee   r10
  8a0:  7c 00 81 46     wrteei  1
  8a4:  7d 6a 62 79     xor\.    r10,r11,r12

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index feea13533762d4ab9d639c497f4c1b4776fdef3a..b59dc1361e644702acd79c6d57114bc8ec3f34bf 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2010-05-13  Alan Modra  <amodra@gmail.com>
+
+       * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
+
 2010-05-11  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 
        * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 3cad93947db9bef2d91535b79b8c96370e591cfb..b51da53411840de60f7dcac6bac3ff54cb9e36b8 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -4530,10 +4530,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"stvrx",      X(31,679),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
 {"sthfcmux",   APU(31,679,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
 
-{"wclrone",    XOPL2(31,694,2),XRT_MASK,    PPCA2,     PPCNONE,        {RA0, RB}},
-{"wclrall",    X(31,694),      XRARB_MASK,  PPCA2,     PPCNONE,        {L}},
-{"wclr",       X(31,694),      X_MASK,      PPCA2,     PPCNONE,        {L, RA0, RB}},
-
 {"stbcx.",     XRC(31,694,1),  X_MASK,      POWER7,    PPCNONE,        {RS, RA0, RB}},
 
 {"stfsux",     X(31,695),      X_MASK,      COM,       PPCNONE,        {FRS, RAS, RB}},
@@ -4717,6 +4713,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"stfddx",     X(31,931),      X_MASK,      E500MC,    PPCNONE,        {FRS, RA, RB}},
 
+{"wclrone",    XOPL2(31,934,2),XRT_MASK,    PPCA2,     PPCNONE,        {RA0, RB}},
+{"wclrall",    X(31,934),      XRARB_MASK,  PPCA2,     PPCNONE,        {L}},
+{"wclr",       X(31,934),      X_MASK,      PPCA2,     PPCNONE,        {L, RA0, RB}},
+
 {"stvrxl",     X(31,935),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
 
 {"divdeo",     XO(31,425,1,0), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},