sim: bfin: fix typo in BF54x SIC init

The current code triggers a warning:
dv-bfin_sic.c: In function 'bfin_sic_finish':
dv-bfin_sic.c:930:41: warning: operation on 'sic-><U78e8>.bf54x.iwr1'
	may be undefined [-Wsequence-point]

This points out the IWR2 register was not being setup because of a typo.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

diff --git a/sim/bfin/ChangeLog b/sim/bfin/ChangeLog
index cdaf5bad3a74b6b6f82c7e25fa173dfe8b402924..973b7883681070e00a885e77b42605b63acb9a4f 100644 (file)
--- a/sim/bfin/ChangeLog
+++ b/sim/bfin/ChangeLog
@@ -1,3 +1,7 @@
+2012-03-31  Mike Frysinger  <vapier@gentoo.org>
+
+       * dv-bfin_sic.c (bfin_sic_finish): Change iwr1 to iwr2.
+
 2012-03-31  Mike Frysinger  <vapier@gentoo.org>
 
        * devices.c: Include devices.h.

diff --git a/sim/bfin/dv-bfin_sic.c b/sim/bfin/dv-bfin_sic.c
index 277e4e1b0cf167f4d310b50127bf2cc8fa7c28f6..a565575869736378c6ba6588dacbdcf4f6d3edf1 100644 (file)
--- a/sim/bfin/dv-bfin_sic.c
+++ b/sim/bfin/dv-bfin_sic.c
@@ -926,7 +926,7 @@ bfin_sic_finish (struct hw *me)
       /* Initialize the SIC.  */
       sic->bf54x.imask0 = sic->bf54x.imask1 = sic->bf54x.imask2 = 0;
       sic->bf54x.isr0 = sic->bf54x.isr1 = sic->bf54x.isr2 = 0;
-      sic->bf54x.iwr0 = sic->bf54x.iwr1 = sic->bf54x.iwr1 = 0xFFFFFFFF;
+      sic->bf54x.iwr0 = sic->bf54x.iwr1 = sic->bf54x.iwr2 = 0xFFFFFFFF;
       sic->bf54x.iar0 = 0x10000000;
       sic->bf54x.iar1 = 0x33322221;
       sic->bf54x.iar2 = 0x66655444;