sim: bfin: update VIT_MAX behavior to match hardware when Acc.X bits are set

The Blackfin PRM says that the top 8 bits of the accumulator must be
cleared when using the VIT_MAX insn, so the sim has followed this spec.
Matching the hardware behavior though when the high bits are not cleared
is easy to do and doesn't break existing behavior, so go for it.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

diff --git a/sim/bfin/ChangeLog b/sim/bfin/ChangeLog
index 0e37dddc148253666bafddc30236daec344c810b..62d14bb4fc3cd436f8a9ccfbcd1214f427bae31f 100644 (file)
--- a/sim/bfin/ChangeLog
+++ b/sim/bfin/ChangeLog
@@ -1,3 +1,8 @@
+2011-03-23  Robin Getz  <robin.getz@analog.com>
+
+       * bfin-sim.c (decode_dsp32shift_0): Set acc0 to the unextended
+       value for the VIT_MAX insn, and mask off the result when done.
+
 2011-03-23  Robin Getz  <robin.getz@analog.com>
 
        * bfin-sim.c (decode_dsp32alu_0): Set A1 to a1_lo when up_hi is false,

diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c
index 85e281a9d1d36442b64826584b9817866eedde15..467d74230705b9a937312fcc182bcea99a93d139 100644 (file)
--- a/sim/bfin/bfin-sim.c
+++ b/sim/bfin/bfin-sim.c
@@ -5425,7 +5425,7 @@ decode_dsp32shift_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
     }
   else if ((sop == 0 || sop == 1) && sopcde == 9)
     {
-      bs40 acc0 = get_extended_acc (cpu, 0);
+      bs40 acc0 = get_unextended_acc (cpu, 0);
       bs16 sL, sH, out;
 
       TRACE_INSN (cpu, "R%i.L = VIT_MAX (R%i) (AS%c);",
@@ -5435,7 +5435,7 @@ decode_dsp32shift_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
       sH = DREG (src1) >> 16;
 
       if (sop & 1)
-       acc0 >>= 1;
+       acc0 = (acc0 & 0xfeffffffffull) >> 1;
       else
        acc0 <<= 1;