PM / devfreq: exynos: Add the detailed correlation for Exynos5422 bus

This patch adds the detailed corrleation between sub-blocks and power line
for Exynos5422.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com>

diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
index 7dbd4abfca3396f77faae3054c36753a27941566..d3ec8e676b6bf306309b42bdd4678403a1682c82 100644 (file)
--- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
+++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
@@ -104,6 +104,25 @@ Detailed correlation between sub-blocks and power line according to Exynos SoC:
                |--- LCD0
                |--- ISP
 
+- In case of Exynos5422, there are two power line as following:
+       VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller)
+               |--- DREX 1
+
+       VDD_INT |--- NoC_Core (parent device)
+               |--- G2D
+               |--- G3D
+               |--- DISP1
+               |--- NoC_WCORE
+               |--- GSCL
+               |--- MSCL
+               |--- ISP
+               |--- MFC
+               |--- GEN
+               |--- PERIS
+               |--- PERIC
+               |--- FSYS
+               |--- FSYS2
+
 Example1:
        Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
        power line (regulator). The MIF (Memory Interface) AXI bus is used to