x86: improve handling of insns with ambiguous operand sizes

Commit b76bc5d54e ("x86: don't default variable shift count insns to
8-bit operand size") pointed out a very bad case, but the underlying
problem is, as mentioned on various occasions, much larger: Silently
selecting a (nowhere documented afaict) certain default operand size
when there's no "sizing" suffix and no suitable register operand(s) is
simply dangerous (for the programmer to make mistakes).

While in Intel syntax mode such mistakes already lead to an error (which
is going to remain that way), AT&T syntax mode now gains warnings in
such cases by default, which can be suppressed or promoted to an error
if so desired by the programmer. Furthermore at least general purpose
insns now consistently have a default applied (alongside the warning
emission), rather than accepting some and refusing others.

No warnings are (as before) to be generated for "DefaultSize" insns as
well as ones acting on selector and other fixed-width values. For
SYSRET, however, the DefaultSize needs to be dropped - it had been
wrongly put there in the first place, as it's unrelated to .code16gcc
(no stack accesses involved).

As set forth as a prereq when I first mentioned this intended change a
few years back, Linux as well as gcc have meanwhile been patched to
avoid (emission of) ambiguous operands (and hence triggering of the new
warning).

Note that I think that in 64-bit mode IRET and far RET would better get
a diagnostic too, as it's reasonably likely that a suffix-less instance
really is meant to be a 64-bit one. But I guess I better make this a
separate follow-on patch.

Note further that floating point operations with integer operands are an
exception for now: They continue to use short (16-bit) operands by
default even in 32- and 64-bit modes.

Finally note that while {,V}PCMPESTR{I,M} would, strictly speaking, also
need to be diagnosed, with their 64-bit forms not being very useful I
think it is better to continue to avoid warning about them (by way of
them carrying IgnoreSize attributes).

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 798d7cff5214340c3e53a85527bb6d155f4570f4..c5528ed6e86234fada3905f4e814f0113c984f8c 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,48 @@
+2020-01-21  Jan Beulich  <jbeulich@suse.com>
+
+       * config/tc-i386.c (process_suffix): Drop SYSRET special case
+       and an intel_syntax check. Re-write lack-of-suffix processing
+       logic.
+       * doc/c-i386.texi: Document operand size defaults for suffix-
+       less AT&T syntax insns.
+       * testsuite/gas/i386/bundle.s, testsuite/gas/i386/lock-1.s,
+       testsuite/gas/i386/opcode.s, testsuite/gas/i386/sse3.s,
+       testsuite/gas/i386/x86-64-avx-scalar.s,
+       testsuite/gas/i386/x86-64-avx.s,
+       testsuite/gas/i386/x86-64-bundle.s,
+       testsuite/gas/i386/x86-64-intel64.s,
+       testsuite/gas/i386/x86-64-lock-1.s,
+       testsuite/gas/i386/x86-64-opcode.s,
+       testsuite/gas/i386/x86-64-sse2avx.s,
+       testsuite/gas/i386/x86-64-sse3.s: Add missing suffixes.
+       * testsuite/gas/i386/nops.s, testsuite/gas/i386/sse-noavx.s,
+       testsuite/gas/i386/x86-64-nops.s,
+       testsuite/gas/i386/x86-64-ptwrite.s,
+       testsuite/gas/i386/x86-64-simd.s,
+       testsuite/gas/i386/x86-64-sse-noavx.s,
+       testsuite/gas/i386/x86-64-suffix.s: Drop bogus suffix-less
+       insns.
+       * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s,
+       testsuite/gas/i386/noreg64.s: Add further tests.
+       * testsuite/gas/i386/ilp32/x86-64-nops.d,
+       testsuite/gas/i386/nops.d, testsuite/gas/i386/noreg16.d,
+       testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg64.d,
+       testsuite/gas/i386/sse-noavx.d,
+       testsuite/gas/i386/x86-64-intel64.d,
+       testsuite/gas/i386/x86-64-nops.d,
+       testsuite/gas/i386/x86-64-opcode.d,
+       testsuite/gas/i386/x86-64-ptwrite-intel.d,
+       testsuite/gas/i386/x86-64-ptwrite.d,
+       testsuite/gas/i386/x86-64-simd-intel.d,
+       testsuite/gas/i386/x86-64-simd-suffix.d,
+       testsuite/gas/i386/x86-64-simd.d,
+       testsuite/gas/i386/x86-64-sse-noavx.d
+       testsuite/gas/i386/x86-64-suffix.d,
+       testsuite/gas/i386/x86-64-suffix-intel.d: Adjust expectations.
+       * testsuite/gas/i386/noreg16.l, testsuite/gas/i386/noreg32.l,
+       testsuite/gas/i386/noreg64.l: New.
+       * testsuite/gas/i386/i386.exp: Run new tests.
+
 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 
        * testsuite/gas/i386/avx512_bf16_vl.s,

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 87ab43bbce017ed338a388b3e6e8ca7331d0dfa4..0b7542f99dc0ad87811fbeeb29149e3d58c7f047 100644 (file)
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -6395,9 +6395,7 @@ process_suffix (void)
   else if (i.tm.opcode_modifier.defaultsize
           && !i.suffix
           /* exclude fldenv/frstor/fsave/fstenv */
-          && i.tm.opcode_modifier.no_ssuf
-          /* exclude sysret */
-          && i.tm.base_opcode != 0x0f07)
+          && i.tm.opcode_modifier.no_ssuf)
     {
       i.suffix = stackop_size;
       if (stackop_size == LONG_MNEM_SUFFIX)
@@ -6418,8 +6416,7 @@ process_suffix (void)
                     i.tm.name);
        }
     }
-  else if (intel_syntax
-          && !i.suffix
+  else if (!i.suffix
           && (i.tm.opcode_modifier.jump == JUMP_ABSOLUTE
               || i.tm.opcode_modifier.jump == JUMP_BYTE
               || i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT
@@ -6446,42 +6443,49 @@ process_suffix (void)
        }
     }
 
-  if (!i.suffix)
+  if (!i.suffix
+      && !i.tm.opcode_modifier.defaultsize
+      && !i.tm.opcode_modifier.ignoresize)
     {
-      if (!intel_syntax)
+      unsigned int suffixes;
+
+      suffixes = !i.tm.opcode_modifier.no_bsuf;
+      if (!i.tm.opcode_modifier.no_wsuf)
+       suffixes |= 1 << 1;
+      if (!i.tm.opcode_modifier.no_lsuf)
+       suffixes |= 1 << 2;
+      if (!i.tm.opcode_modifier.no_ldsuf)
+       suffixes |= 1 << 3;
+      if (!i.tm.opcode_modifier.no_ssuf)
+       suffixes |= 1 << 4;
+      if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
+       suffixes |= 1 << 5;
+
+      /* Are multiple suffixes allowed?  */
+      if (suffixes & (suffixes - 1))
        {
-         if (i.tm.opcode_modifier.w)
+         if (intel_syntax)
            {
-             as_bad (_("no instruction mnemonic suffix given and "
-                       "no register operands; can't size instruction"));
+             as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
              return 0;
            }
-       }
-      else
-       {
-         unsigned int suffixes;
-
-         suffixes = !i.tm.opcode_modifier.no_bsuf;
-         if (!i.tm.opcode_modifier.no_wsuf)
-           suffixes |= 1 << 1;
-         if (!i.tm.opcode_modifier.no_lsuf)
-           suffixes |= 1 << 2;
-         if (!i.tm.opcode_modifier.no_ldsuf)
-           suffixes |= 1 << 3;
-         if (!i.tm.opcode_modifier.no_ssuf)
-           suffixes |= 1 << 4;
-         if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
-           suffixes |= 1 << 5;
-
-         /* There are more than suffix matches.  */
-         if (i.tm.opcode_modifier.w
-             || ((suffixes & (suffixes - 1))
-                 && !i.tm.opcode_modifier.defaultsize
-                 && !i.tm.opcode_modifier.ignoresize))
+         if (operand_check == check_error)
            {
-             as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
+             as_bad (_("no instruction mnemonic suffix given and "
+                       "no register operands; can't size `%s'"), i.tm.name);
              return 0;
            }
+         if (operand_check == check_warning)
+           as_warn (_("no instruction mnemonic suffix given and "
+                      "no register operands; using default for `%s'"),
+                    i.tm.name);
+
+         if (i.tm.opcode_modifier.floatmf)
+           i.suffix = SHORT_MNEM_SUFFIX;
+         else if (flag_code == CODE_16BIT)
+           i.suffix = WORD_MNEM_SUFFIX;
+         else
+           i.suffix = LONG_MNEM_SUFFIX;
        }
     }
 

diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index e8685dd046ff74fe1d21a32773bed3aab855e958..6d556a01a10ab6f50d601d25529cd19495ad10fa 100644 (file)
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -723,6 +723,31 @@ assembler which assumes that a missing mnemonic suffix implies long
 operand size.  (This incompatibility does not affect compiler output
 since compilers always explicitly specify the mnemonic suffix.)
 
+When there is no sizing suffix and no (suitable) register operands to
+deduce the size of memory operands, with a few exceptions and where long
+operand size is possible in the first place, operand size will default
+to long in 32- and 64-bit modes.  Similarly it will default to short in
+16-bit mode. Noteworthy exceptions are
+
+@itemize @bullet
+@item
+Instructions with an implicit on-stack operand as well as branches,
+which default to quad in 64-bit mode.
+
+@item
+Sign- and zero-extending moves, which default to byte size source
+operands.
+
+@item
+Floating point insns with integer operands, which default to short (for
+perhaps historical reasons).
+
+@item
+CRC32 with a 64-bit destination, which defaults to a quad source
+operand.
+
+@end itemize
+
 Almost all instructions have the same names in AT&T and Intel format.
 There are a few exceptions.  The sign extend and zero extend
 instructions need two sizes to specify them.  They need a size to

diff --git a/gas/testsuite/gas/i386/bundle.s b/gas/testsuite/gas/i386/bundle.s
index 3932f637e0ef1be1bd6cdab5b024bf35fd46c9dc..60d9fc5d7321c56c2e91d4293d545dce3b3e8d20 100644 (file)
--- a/gas/testsuite/gas/i386/bundle.s
+++ b/gas/testsuite/gas/i386/bundle.s
@@ -58,7 +58,7 @@
        and $3,%eax
 .endm
 .macro test_4
-       lock and $3,(%eax)
+       lock andl $3,(%eax)
 .endm
 .macro test_5
        mov $0xaabbccdd,%eax

diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 9be9c1a22ebe9bb80d705f50d0bec257061ecde3..aedcf147380ae1400bfbd88ccdcb2a27d0ef806e 100644 (file)
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -129,7 +129,9 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_dump_test "nops-6"
     run_dump_test "nops-7"
     run_dump_test "noreg16"
+    run_list_test "noreg16"
     run_dump_test "noreg32"
+    run_list_test "noreg32"
     run_dump_test "addr16"
     run_dump_test "addr32"
     run_dump_test "code16"
@@ -730,6 +732,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_dump_test "x86-64-sysenter-amd"
     run_list_test "x86-64-sysenter-amd"
     run_dump_test "noreg64"
+    run_list_test "noreg64"
     run_list_test "cvtsi2sX"
     run_dump_test "x86-64-sse4_1"
     run_dump_test "x86-64-sse4_1-intel"

diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-nops.d b/gas/testsuite/gas/i386/ilp32/x86-64-nops.d
index a497115b4ec0707251a9e53ea01c9afa96c9fdcd..3a47e6cb994a71611939506ec4b0e5db3b0a3d63 100644 (file)
--- a/gas/testsuite/gas/i386/ilp32/x86-64-nops.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-nops.d
@@ -42,7 +42,6 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    0f 1d 04 59             nopl   \(%rcx,%rbx,2\)
 [      ]*[a-f0-9]+:    0f 1e 04 59             nopl   \(%rcx,%rbx,2\)
 [      ]*[a-f0-9]+:    0f 1f 04 59             nopl   \(%rcx,%rbx,2\)
-[      ]*[a-f0-9]+:    0f 1f 00                nopl   \(%rax\)
 [      ]*[a-f0-9]+:    48 0f 1f c0             nop    %rax
 [      ]*[a-f0-9]+:    0f 1f c0                nop    %eax
 [      ]*[a-f0-9]+:    66 0f 1f c0             nop    %ax
@@ -52,7 +51,6 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    48 0f 1f c0             nop    %rax
 [      ]*[a-f0-9]+:    0f 1f c0                nop    %eax
 [      ]*[a-f0-9]+:    66 0f 1f c0             nop    %ax
-[      ]*[a-f0-9]+:    41 0f 1f 02             nopl   \(%r10\)
 [      ]*[a-f0-9]+:    49 0f 1f c2             nop    %r10
 [      ]*[a-f0-9]+:    41 0f 1f c2             nop    %r10d
 [      ]*[a-f0-9]+:    66 41 0f 1f c2          nop    %r10w

diff --git a/gas/testsuite/gas/i386/lock-1.s b/gas/testsuite/gas/i386/lock-1.s
index 4a2a90e6a454d4968588bdf4c5885996373be531..936b8ba67cb220bcb438eacdb71b08669b6bf8e5 100644 (file)
--- a/gas/testsuite/gas/i386/lock-1.s
+++ b/gas/testsuite/gas/i386/lock-1.s
@@ -3,17 +3,17 @@
        .text
 foo:
        lock add %eax, (%ebx)
-       lock add $0x64, (%ebx)
+       lock addl $0x64, (%ebx)
        lock adc %eax, (%ebx)
-       lock adc $0x64, (%ebx)
+       lock adcl $0x64, (%ebx)
        lock and %eax, (%ebx)
-       lock and $0x64, (%ebx)
+       lock andl $0x64, (%ebx)
        lock btc %eax, (%ebx)
-       lock btc $0x64, (%ebx)
+       lock btcl $0x64, (%ebx)
        lock btr %eax, (%ebx)
-       lock btr $0x64, (%ebx)
+       lock btrl $0x64, (%ebx)
        lock bts %eax, (%ebx)
-       lock bts $0x64, (%ebx)
+       lock btsl $0x64, (%ebx)
        lock cmpxchg %eax,(%ebx)
        lock cmpxchg8b (%ebx)
        lock decl (%ebx)
@@ -21,16 +21,16 @@ foo:
        lock negl (%ebx)
        lock notl (%ebx)
        lock or %eax, (%ebx)
-       lock or $0x64, (%ebx)
+       lock orl $0x64, (%ebx)
        lock sbb %eax, (%ebx)
-       lock sbb $0x64, (%ebx)
+       lock sbbl $0x64, (%ebx)
        lock sub %eax, (%ebx)
-       lock sub $0x64, (%ebx)
+       lock subl $0x64, (%ebx)
        lock xadd %eax, (%ebx)
        lock xchg (%ebx), %eax
        lock xchg %eax, (%ebx)
        lock xor %eax, (%ebx)
-       lock xor $0x64, (%ebx)
+       lock xorl $0x64, (%ebx)
 
        .intel_syntax noprefix
        lock add DWORD PTR [ebx],eax

diff --git a/gas/testsuite/gas/i386/nops.d b/gas/testsuite/gas/i386/nops.d
index 5275973bc3c61f2550a53a69006e89e97ef87fdf..4e4c75fc28a3bab26455b6ab615bd0088b907857 100644 (file)
--- a/gas/testsuite/gas/i386/nops.d
+++ b/gas/testsuite/gas/i386/nops.d
@@ -41,7 +41,6 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    0f 1d 04 59             nopl   \(%ecx,%ebx,2\)
 [      ]*[a-f0-9]+:    0f 1e 04 59             nopl   \(%ecx,%ebx,2\)
 [      ]*[a-f0-9]+:    0f 1f 04 59             nopl   \(%ecx,%ebx,2\)
-[      ]*[a-f0-9]+:    0f 1f 00                nopl   \(%eax\)
 [      ]*[a-f0-9]+:    0f 1f c0                nop    %eax
 [      ]*[a-f0-9]+:    66 0f 1f c0             nop    %ax
 [      ]*[a-f0-9]+:    0f 1f 00                nopl   \(%eax\)

diff --git a/gas/testsuite/gas/i386/nops.s b/gas/testsuite/gas/i386/nops.s
index a6177cc01fdaf36bb2a1b8e3aab7febb8c18e05b..df5396bc6716eab0c49fb7fa95fa6d1098bc1276 100644 (file)
--- a/gas/testsuite/gas/i386/nops.s
+++ b/gas/testsuite/gas/i386/nops.s
@@ -44,7 +44,6 @@
        .byte 0x0f, 0x1e, 0x04, 0x59
        .byte 0x0f, 0x1f, 0x04, 0x59
 
-       nop (%eax) 
        nop %eax
        nop %ax
        nopl (%eax) 

diff --git a/gas/testsuite/gas/i386/noreg16.d b/gas/testsuite/gas/i386/noreg16.d
index 66f0df6fe427c52b71ad9f6fe49f1457fd03d798..fd7336fac5d9f352b5b22bb47461768ce9246944 100644 (file)
--- a/gas/testsuite/gas/i386/noreg16.d
+++ b/gas/testsuite/gas/i386/noreg16.d
@@ -1,3 +1,4 @@
+#as: -moperand-check=none
 #objdump: -dwMi8086
 #name: 16-bit insns not sizeable through register operands
 
@@ -7,16 +8,28 @@ Disassembly of section .text:
 
 0+ <noreg>:
  *[a-f0-9]+:   83 17 01                adcw   \$0x1,\(%bx\)
+ *[a-f0-9]+:   81 17 89 00             adcw   \$0x89,\(%bx\)
+ *[a-f0-9]+:   81 17 34 12             adcw   \$0x1234,\(%bx\)
  *[a-f0-9]+:   83 07 01                addw   \$0x1,\(%bx\)
+ *[a-f0-9]+:   81 07 89 00             addw   \$0x89,\(%bx\)
+ *[a-f0-9]+:   81 07 34 12             addw   \$0x1234,\(%bx\)
  *[a-f0-9]+:   83 27 01                andw   \$0x1,\(%bx\)
+ *[a-f0-9]+:   81 27 89 00             andw   \$0x89,\(%bx\)
+ *[a-f0-9]+:   81 27 34 12             andw   \$0x1234,\(%bx\)
  *[a-f0-9]+:   0f ba 27 01             btw    \$0x1,\(%bx\)
  *[a-f0-9]+:   0f ba 3f 01             btcw   \$0x1,\(%bx\)
  *[a-f0-9]+:   0f ba 37 01             btrw   \$0x1,\(%bx\)
  *[a-f0-9]+:   0f ba 2f 01             btsw   \$0x1,\(%bx\)
  *[a-f0-9]+:   ff 17                   call   \*\(%bx\)
  *[a-f0-9]+:   83 3f 01                cmpw   \$0x1,\(%bx\)
+ *[a-f0-9]+:   81 3f 89 00             cmpw   \$0x89,\(%bx\)
+ *[a-f0-9]+:   81 3f 34 12             cmpw   \$0x1234,\(%bx\)
+ *[a-f0-9]+:   a7                      cmpsw  %es:\(%di\),%ds:\(%si\)
+ *[a-f0-9]+:   67 a7                   cmpsw  %es:\(%edi\),%ds:\(%esi\)
  *[a-f0-9]+:   f2 0f 2a 07             cvtsi2sdl \(%bx\),%xmm0
  *[a-f0-9]+:   f3 0f 2a 07             cvtsi2ssl \(%bx\),%xmm0
+ *[a-f0-9]+:   ff 0f                   decw   \(%bx\)
+ *[a-f0-9]+:   f7 37                   divw   \(%bx\)
  *[a-f0-9]+:   d8 07                   fadds  \(%bx\)
  *[a-f0-9]+:   d8 17                   fcoms  \(%bx\)
  *[a-f0-9]+:   d8 1f                   fcomps \(%bx\)
@@ -40,23 +53,87 @@ Disassembly of section .text:
  *[a-f0-9]+:   d9 1f                   fstps  \(%bx\)
  *[a-f0-9]+:   d8 27                   fsubs  \(%bx\)
  *[a-f0-9]+:   d8 2f                   fsubrs \(%bx\)
+ *[a-f0-9]+:   f7 3f                   idivw  \(%bx\)
+ *[a-f0-9]+:   f7 2f                   imulw  \(%bx\)
+ *[a-f0-9]+:   e5 00                   in     \$0x0,%ax
+ *[a-f0-9]+:   ed                      in     \(%dx\),%ax
+ *[a-f0-9]+:   ff 07                   incw   \(%bx\)
+ *[a-f0-9]+:   6d                      insw   \(%dx\),%es:\(%di\)
+ *[a-f0-9]+:   67 6d                   insw   \(%dx\),%es:\(%edi\)
  *[a-f0-9]+:   ff 27                   jmp    \*\(%bx\)
  *[a-f0-9]+:   0f 01 17                lgdtw  \(%bx\)
  *[a-f0-9]+:   0f 01 1f                lidtw  \(%bx\)
  *[a-f0-9]+:   0f 00 17                lldt   \(%bx\)
  *[a-f0-9]+:   0f 01 37                lmsw   \(%bx\)
+ *[a-f0-9]+:   ad                      lods   %ds:\(%si\),%ax
+ *[a-f0-9]+:   67 ad                   lods   %ds:\(%esi\),%ax
  *[a-f0-9]+:   0f 00 1f                ltr    \(%bx\)
+ *[a-f0-9]+:   c7 07 12 00             movw   \$0x12,\(%bx\)
+ *[a-f0-9]+:   c7 07 34 12             movw   \$0x1234,\(%bx\)
  *[a-f0-9]+:   8c 07                   mov    %es,\(%bx\)
  *[a-f0-9]+:   8e 07                   mov    \(%bx\),%es
+ *[a-f0-9]+:   a5                      movsw  %ds:\(%si\),%es:\(%di\)
+ *[a-f0-9]+:   67 a5                   movsw  %ds:\(%esi\),%es:\(%edi\)
+ *[a-f0-9]+:   f7 27                   mulw   \(%bx\)
+ *[a-f0-9]+:   f7 1f                   negw   \(%bx\)
  *[a-f0-9]+:   0f 1f 07                nopw   \(%bx\)
+ *[a-f0-9]+:   f7 17                   notw   \(%bx\)
  *[a-f0-9]+:   83 0f 01                orw    \$0x1,\(%bx\)
+ *[a-f0-9]+:   81 0f 89 00             orw    \$0x89,\(%bx\)
+ *[a-f0-9]+:   81 0f 34 12             orw    \$0x1234,\(%bx\)
+ *[a-f0-9]+:   e7 00                   out    %ax,\$0x0
+ *[a-f0-9]+:   ef                      out    %ax,\(%dx\)
+ *[a-f0-9]+:   6f                      outsw  %ds:\(%si\),\(%dx\)
+ *[a-f0-9]+:   67 6f                   outsw  %ds:\(%esi\),\(%dx\)
  *[a-f0-9]+:   8f 07                   popw   \(%bx\)
  *[a-f0-9]+:   07                      pop    %es
  *[a-f0-9]+:   f3 0f ae 27             ptwritel \(%bx\)
  *[a-f0-9]+:   ff 37                   pushw  \(%bx\)
  *[a-f0-9]+:   06                      push   %es
+ *[a-f0-9]+:   d1 17                   rclw   \(%bx\)
+ *[a-f0-9]+:   c1 17 02                rclw   \$0x2,\(%bx\)
+ *[a-f0-9]+:   d3 17                   rclw   %cl,\(%bx\)
+ *[a-f0-9]+:   d1 17                   rclw   \(%bx\)
+ *[a-f0-9]+:   d1 1f                   rcrw   \(%bx\)
+ *[a-f0-9]+:   c1 1f 02                rcrw   \$0x2,\(%bx\)
+ *[a-f0-9]+:   d3 1f                   rcrw   %cl,\(%bx\)
+ *[a-f0-9]+:   d1 1f                   rcrw   \(%bx\)
+ *[a-f0-9]+:   d1 07                   rolw   \(%bx\)
+ *[a-f0-9]+:   c1 07 02                rolw   \$0x2,\(%bx\)
+ *[a-f0-9]+:   d3 07                   rolw   %cl,\(%bx\)
+ *[a-f0-9]+:   d1 07                   rolw   \(%bx\)
+ *[a-f0-9]+:   d1 0f                   rorw   \(%bx\)
+ *[a-f0-9]+:   c1 0f 02                rorw   \$0x2,\(%bx\)
+ *[a-f0-9]+:   d3 0f                   rorw   %cl,\(%bx\)
+ *[a-f0-9]+:   d1 0f                   rorw   \(%bx\)
  *[a-f0-9]+:   83 1f 01                sbbw   \$0x1,\(%bx\)
+ *[a-f0-9]+:   81 1f 89 00             sbbw   \$0x89,\(%bx\)
+ *[a-f0-9]+:   81 1f 34 12             sbbw   \$0x1234,\(%bx\)
+ *[a-f0-9]+:   af                      scas   %es:\(%di\),%ax
+ *[a-f0-9]+:   67 af                   scas   %es:\(%edi\),%ax
+ *[a-f0-9]+:   d1 27                   shlw   \(%bx\)
+ *[a-f0-9]+:   c1 27 02                shlw   \$0x2,\(%bx\)
+ *[a-f0-9]+:   d3 27                   shlw   %cl,\(%bx\)
+ *[a-f0-9]+:   d1 27                   shlw   \(%bx\)
+ *[a-f0-9]+:   d1 3f                   sarw   \(%bx\)
+ *[a-f0-9]+:   c1 3f 02                sarw   \$0x2,\(%bx\)
+ *[a-f0-9]+:   d3 3f                   sarw   %cl,\(%bx\)
+ *[a-f0-9]+:   d1 3f                   sarw   \(%bx\)
+ *[a-f0-9]+:   d1 27                   shlw   \(%bx\)
+ *[a-f0-9]+:   c1 27 02                shlw   \$0x2,\(%bx\)
+ *[a-f0-9]+:   d3 27                   shlw   %cl,\(%bx\)
+ *[a-f0-9]+:   d1 27                   shlw   \(%bx\)
+ *[a-f0-9]+:   d1 2f                   shrw   \(%bx\)
+ *[a-f0-9]+:   c1 2f 02                shrw   \$0x2,\(%bx\)
+ *[a-f0-9]+:   d3 2f                   shrw   %cl,\(%bx\)
+ *[a-f0-9]+:   d1 2f                   shrw   \(%bx\)
+ *[a-f0-9]+:   ab                      stos   %ax,%es:\(%di\)
+ *[a-f0-9]+:   67 ab                   stos   %ax,%es:\(%edi\)
  *[a-f0-9]+:   83 2f 01                subw   \$0x1,\(%bx\)
+ *[a-f0-9]+:   81 2f 89 00             subw   \$0x89,\(%bx\)
+ *[a-f0-9]+:   81 2f 34 12             subw   \$0x1234,\(%bx\)
+ *[a-f0-9]+:   f7 07 89 00             testw  \$0x89,\(%bx\)
+ *[a-f0-9]+:   f7 07 34 12             testw  \$0x1234,\(%bx\)
  *[a-f0-9]+:   c5 fb 2a 07             vcvtsi2sdl \(%bx\),%xmm0,%xmm0
  *[a-f0-9]+:   62 f1 7f 08 2a 07       vcvtsi2sdl \(%bx\),%xmm0,%xmm0
  *[a-f0-9]+:   c5 fa 2a 07             vcvtsi2ssl \(%bx\),%xmm0,%xmm0
@@ -64,4 +141,6 @@ Disassembly of section .text:
  *[a-f0-9]+:   62 f1 7f 08 7b 07       vcvtusi2sdl \(%bx\),%xmm0,%xmm0
  *[a-f0-9]+:   62 f1 7e 08 7b 07       vcvtusi2ssl \(%bx\),%xmm0,%xmm0
  *[a-f0-9]+:   83 37 01                xorw   \$0x1,\(%bx\)
+ *[a-f0-9]+:   81 37 89 00             xorw   \$0x89,\(%bx\)
+ *[a-f0-9]+:   81 37 34 12             xorw   \$0x1234,\(%bx\)
 #pass

diff --git a/gas/testsuite/gas/i386/noreg16.l b/gas/testsuite/gas/i386/noreg16.l
new file mode 100644 (file)
index 0000000..2861431
--- /dev/null
+++ b/gas/testsuite/gas/i386/noreg16.l
@@ -0,0 +1,115 @@
+.*: Assembler messages:
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `bt'
+.*:[1-9][0-9]*: Warning: .* `btc'
+.*:[1-9][0-9]*: Warning: .* `btr'
+.*:[1-9][0-9]*: Warning: .* `bts'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `dec'
+.*:[1-9][0-9]*: Warning: .* `div'
+.*:[1-9][0-9]*: Warning: .* `fadd'
+.*:[1-9][0-9]*: Warning: .* `fcom'
+.*:[1-9][0-9]*: Warning: .* `fcomp'
+.*:[1-9][0-9]*: Warning: .* `fdiv'
+.*:[1-9][0-9]*: Warning: .* `fdivr'
+.*:[1-9][0-9]*: Warning: .* `fiadd'
+.*:[1-9][0-9]*: Warning: .* `ficom'
+.*:[1-9][0-9]*: Warning: .* `ficomp'
+.*:[1-9][0-9]*: Warning: .* `fidiv'
+.*:[1-9][0-9]*: Warning: .* `fidivr'
+.*:[1-9][0-9]*: Warning: .* `fild'
+.*:[1-9][0-9]*: Warning: .* `fimul'
+.*:[1-9][0-9]*: Warning: .* `fist'
+.*:[1-9][0-9]*: Warning: .* `fistp'
+.*:[1-9][0-9]*: Warning: .* `fisttp'
+.*:[1-9][0-9]*: Warning: .* `fisub'
+.*:[1-9][0-9]*: Warning: .* `fisubr'
+.*:[1-9][0-9]*: Warning: .* `fld'
+.*:[1-9][0-9]*: Warning: .* `fmul'
+.*:[1-9][0-9]*: Warning: .* `fst'
+.*:[1-9][0-9]*: Warning: .* `fstp'
+.*:[1-9][0-9]*: Warning: .* `fsub'
+.*:[1-9][0-9]*: Warning: .* `fsubr'
+.*:[1-9][0-9]*: Warning: .* `idiv'
+.*:[1-9][0-9]*: Warning: .* `imul'
+.*:[1-9][0-9]*: Warning: .* `in'
+.*:[1-9][0-9]*: Warning: .* `in'
+.*:[1-9][0-9]*: Warning: .* `inc'
+.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Warning: .* `mul'
+.*:[1-9][0-9]*: Warning: .* `neg'
+.*:[1-9][0-9]*: Warning: .* `nop'
+.*:[1-9][0-9]*: Warning: .* `not'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `out'
+.*:[1-9][0-9]*: Warning: .* `out'
+.*:[1-9][0-9]*: Warning: .* `outs'
+.*:[1-9][0-9]*: Warning: .* `outs'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `scas'
+.*:[1-9][0-9]*: Warning: .* `scas'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `stos'
+.*:[1-9][0-9]*: Warning: .* `stos'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Warning: .* `xor'

diff --git a/gas/testsuite/gas/i386/noreg16.s b/gas/testsuite/gas/i386/noreg16.s
index aff96d9a561934a7e4bb2fe777a97be48a13a272..0d64e326f089e00189052a3b14849115a2c382ee 100644 (file)
--- a/gas/testsuite/gas/i386/noreg16.s
+++ b/gas/testsuite/gas/i386/noreg16.s
@@ -2,16 +2,28 @@
        .code16
 noreg:
        adc     $1, (%bx)
+       adc     $0x89, (%bx)
+       adc     $0x1234, (%bx)
        add     $1, (%bx)
+       add     $0x89, (%bx)
+       add     $0x1234, (%bx)
        and     $1, (%bx)
+       and     $0x89, (%bx)
+       and     $0x1234, (%bx)
        bt      $1, (%bx)
        btc     $1, (%bx)
        btr     $1, (%bx)
        bts     $1, (%bx)
        call    *(%bx)
        cmp     $1, (%bx)
+       cmp     $0x89, (%bx)
+       cmp     $0x1234, (%bx)
+       cmps
+       cmps    %es:(%edi), (%esi)
        cvtsi2sd (%bx), %xmm0
        cvtsi2ss (%bx), %xmm0
+       dec     (%bx)
+       div     (%bx)
        fadd    (%bx)
        fcom    (%bx)
        fcomp   (%bx)
@@ -35,23 +47,87 @@ noreg:
        fstp    (%bx)
        fsub    (%bx)
        fsubr   (%bx)
+       idiv    (%bx)
+       imul    (%bx)
+       in      $0
+       in      %dx
+       inc     (%bx)
+       ins
+       ins     %dx, %es:(%edi)
        jmp     *(%bx)
        lgdt    (%bx)
        lidt    (%bx)
        lldt    (%bx)
        lmsw    (%bx)
+       lods
+       lods    (%esi)
        ltr     (%bx)
+       mov     $0x12, (%bx)
+       mov     $0x1234, (%bx)
        mov     %es, (%bx)
        mov     (%bx), %es
+       movs
+       movs    (%esi), %es:(%edi)
+       mul     (%bx)
+       neg     (%bx)
        nop     (%bx)
+       not     (%bx)
        or      $1, (%bx)
+       or      $0x89, (%bx)
+       or      $0x1234, (%bx)
+       out     $0
+       out     %dx
+       outs
+       outs    (%esi), %dx
        pop     (%bx)
        pop     %es
        ptwrite (%bx)
        push    (%bx)
        push    %es
+       rcl     $1, (%bx)
+       rcl     $2, (%bx)
+       rcl     %cl, (%bx)
+       rcl     (%bx)
+       rcr     $1, (%bx)
+       rcr     $2, (%bx)
+       rcr     %cl, (%bx)
+       rcr     (%bx)
+       rol     $1, (%bx)
+       rol     $2, (%bx)
+       rol     %cl, (%bx)
+       rol     (%bx)
+       ror     $1, (%bx)
+       ror     $2, (%bx)
+       ror     %cl, (%bx)
+       ror     (%bx)
        sbb     $1, (%bx)
+       sbb     $0x89, (%bx)
+       sbb     $0x1234, (%bx)
+       scas
+       scas    %es:(%edi)
+       sal     $1, (%bx)
+       sal     $2, (%bx)
+       sal     %cl, (%bx)
+       sal     (%bx)
+       sar     $1, (%bx)
+       sar     $2, (%bx)
+       sar     %cl, (%bx)
+       sar     (%bx)
+       shl     $1, (%bx)
+       shl     $2, (%bx)
+       shl     %cl, (%bx)
+       shl     (%bx)
+       shr     $1, (%bx)
+       shr     $2, (%bx)
+       shr     %cl, (%bx)
+       shr     (%bx)
+       stos
+       stos    %es:(%edi)
        sub     $1, (%bx)
+       sub     $0x89, (%bx)
+       sub     $0x1234, (%bx)
+       test    $0x89, (%bx)
+       test    $0x1234, (%bx)
        vcvtsi2sd (%bx), %xmm0, %xmm0
        {evex} vcvtsi2sd (%bx), %xmm0, %xmm0
        vcvtsi2ss (%bx), %xmm0, %xmm0
@@ -59,3 +135,5 @@ noreg:
        vcvtusi2sd (%bx), %xmm0, %xmm0
        vcvtusi2ss (%bx), %xmm0, %xmm0
        xor     $1, (%bx)
+       xor     $0x89, (%bx)
+       xor     $0x1234, (%bx)

diff --git a/gas/testsuite/gas/i386/noreg32.d b/gas/testsuite/gas/i386/noreg32.d
index 0cdd5fa50c4f169ca4311fcee8e93a02635a4ddd..b0f8c248b1d4af67b8264609f2cb12ab5fc0e7dc 100644 (file)
--- a/gas/testsuite/gas/i386/noreg32.d
+++ b/gas/testsuite/gas/i386/noreg32.d
@@ -1,3 +1,4 @@
+#as: -moperand-check=none
 #objdump: -dw
 #name: 32-bit insns not sizeable through register operands
 
@@ -7,16 +8,32 @@ Disassembly of section .text:
 
 0+ <noreg>:
  *[a-f0-9]+:   83 10 01                adcl   \$0x1,\(%eax\)
+ *[a-f0-9]+:   81 10 89 00 00 00       adcl   \$0x89,\(%eax\)
+ *[a-f0-9]+:   81 10 34 12 00 00       adcl   \$0x1234,\(%eax\)
+ *[a-f0-9]+:   81 10 78 56 34 12       adcl   \$0x12345678,\(%eax\)
  *[a-f0-9]+:   83 00 01                addl   \$0x1,\(%eax\)
+ *[a-f0-9]+:   81 00 89 00 00 00       addl   \$0x89,\(%eax\)
+ *[a-f0-9]+:   81 00 34 12 00 00       addl   \$0x1234,\(%eax\)
+ *[a-f0-9]+:   81 00 78 56 34 12       addl   \$0x12345678,\(%eax\)
  *[a-f0-9]+:   83 20 01                andl   \$0x1,\(%eax\)
+ *[a-f0-9]+:   81 20 89 00 00 00       andl   \$0x89,\(%eax\)
+ *[a-f0-9]+:   81 20 34 12 00 00       andl   \$0x1234,\(%eax\)
+ *[a-f0-9]+:   81 20 78 56 34 12       andl   \$0x12345678,\(%eax\)
  *[a-f0-9]+:   0f ba 20 01             btl    \$0x1,\(%eax\)
  *[a-f0-9]+:   0f ba 38 01             btcl   \$0x1,\(%eax\)
  *[a-f0-9]+:   0f ba 30 01             btrl   \$0x1,\(%eax\)
  *[a-f0-9]+:   0f ba 28 01             btsl   \$0x1,\(%eax\)
  *[a-f0-9]+:   ff 10                   call   \*\(%eax\)
  *[a-f0-9]+:   83 38 01                cmpl   \$0x1,\(%eax\)
+ *[a-f0-9]+:   81 38 89 00 00 00       cmpl   \$0x89,\(%eax\)
+ *[a-f0-9]+:   81 38 34 12 00 00       cmpl   \$0x1234,\(%eax\)
+ *[a-f0-9]+:   81 38 78 56 34 12       cmpl   \$0x12345678,\(%eax\)
+ *[a-f0-9]+:   a7                      cmpsl  %es:\(%edi\),%ds:\(%esi\)
+ *[a-f0-9]+:   a7                      cmpsl  %es:\(%edi\),%ds:\(%esi\)
  *[a-f0-9]+:   f2 0f 2a 00             cvtsi2sdl \(%eax\),%xmm0
  *[a-f0-9]+:   f3 0f 2a 00             cvtsi2ssl \(%eax\),%xmm0
+ *[a-f0-9]+:   ff 08                   decl   \(%eax\)
+ *[a-f0-9]+:   f7 30                   divl   \(%eax\)
  *[a-f0-9]+:   d8 00                   fadds  \(%eax\)
  *[a-f0-9]+:   d8 10                   fcoms  \(%eax\)
  *[a-f0-9]+:   d8 18                   fcomps \(%eax\)
@@ -40,23 +57,92 @@ Disassembly of section .text:
  *[a-f0-9]+:   d9 18                   fstps  \(%eax\)
  *[a-f0-9]+:   d8 20                   fsubs  \(%eax\)
  *[a-f0-9]+:   d8 28                   fsubrs \(%eax\)
+ *[a-f0-9]+:   f7 38                   idivl  \(%eax\)
+ *[a-f0-9]+:   f7 28                   imull  \(%eax\)
+ *[a-f0-9]+:   e5 00                   in     \$0x0,%eax
+ *[a-f0-9]+:   ed                      in     \(%dx\),%eax
+ *[a-f0-9]+:   ff 00                   incl   \(%eax\)
+ *[a-f0-9]+:   6d                      insl   \(%dx\),%es:\(%edi\)
+ *[a-f0-9]+:   6d                      insl   \(%dx\),%es:\(%edi\)
  *[a-f0-9]+:   ff 20                   jmp    \*\(%eax\)
  *[a-f0-9]+:   0f 01 10                lgdtl  \(%eax\)
  *[a-f0-9]+:   0f 01 18                lidtl  \(%eax\)
  *[a-f0-9]+:   0f 00 10                lldt   \(%eax\)
  *[a-f0-9]+:   0f 01 30                lmsw   \(%eax\)
+ *[a-f0-9]+:   ad                      lods   %ds:\(%esi\),%eax
+ *[a-f0-9]+:   ad                      lods   %ds:\(%esi\),%eax
  *[a-f0-9]+:   0f 00 18                ltr    \(%eax\)
+ *[a-f0-9]+:   c7 00 12 00 00 00       movl   \$0x12,\(%eax\)
+ *[a-f0-9]+:   c7 00 34 12 00 00       movl   \$0x1234,\(%eax\)
+ *[a-f0-9]+:   c7 00 78 56 34 12       movl   \$0x12345678,\(%eax\)
  *[a-f0-9]+:   8c 00                   mov    %es,\(%eax\)
  *[a-f0-9]+:   8e 00                   mov    \(%eax\),%es
+ *[a-f0-9]+:   a5                      movsl  %ds:\(%esi\),%es:\(%edi\)
+ *[a-f0-9]+:   a5                      movsl  %ds:\(%esi\),%es:\(%edi\)
+ *[a-f0-9]+:   f7 20                   mull   \(%eax\)
+ *[a-f0-9]+:   f7 18                   negl   \(%eax\)
  *[a-f0-9]+:   0f 1f 00                nopl   \(%eax\)
+ *[a-f0-9]+:   f7 10                   notl   \(%eax\)
  *[a-f0-9]+:   83 08 01                orl    \$0x1,\(%eax\)
+ *[a-f0-9]+:   81 08 89 00 00 00       orl    \$0x89,\(%eax\)
+ *[a-f0-9]+:   81 08 34 12 00 00       orl    \$0x1234,\(%eax\)
+ *[a-f0-9]+:   81 08 78 56 34 12       orl    \$0x12345678,\(%eax\)
+ *[a-f0-9]+:   e7 00                   out    %eax,\$0x0
+ *[a-f0-9]+:   ef                      out    %eax,\(%dx\)
+ *[a-f0-9]+:   6f                      outsl  %ds:\(%esi\),\(%dx\)
+ *[a-f0-9]+:   6f                      outsl  %ds:\(%esi\),\(%dx\)
  *[a-f0-9]+:   8f 00                   popl   \(%eax\)
  *[a-f0-9]+:   07                      pop    %es
  *[a-f0-9]+:   f3 0f ae 20             ptwritel \(%eax\)
  *[a-f0-9]+:   ff 30                   pushl  \(%eax\)
  *[a-f0-9]+:   06                      push   %es
+ *[a-f0-9]+:   d1 10                   rcll   \(%eax\)
+ *[a-f0-9]+:   c1 10 02                rcll   \$0x2,\(%eax\)
+ *[a-f0-9]+:   d3 10                   rcll   %cl,\(%eax\)
+ *[a-f0-9]+:   d1 10                   rcll   \(%eax\)
+ *[a-f0-9]+:   d1 18                   rcrl   \(%eax\)
+ *[a-f0-9]+:   c1 18 02                rcrl   \$0x2,\(%eax\)
+ *[a-f0-9]+:   d3 18                   rcrl   %cl,\(%eax\)
+ *[a-f0-9]+:   d1 18                   rcrl   \(%eax\)
+ *[a-f0-9]+:   d1 00                   roll   \(%eax\)
+ *[a-f0-9]+:   c1 00 02                roll   \$0x2,\(%eax\)
+ *[a-f0-9]+:   d3 00                   roll   %cl,\(%eax\)
+ *[a-f0-9]+:   d1 00                   roll   \(%eax\)
+ *[a-f0-9]+:   d1 08                   rorl   \(%eax\)
+ *[a-f0-9]+:   c1 08 02                rorl   \$0x2,\(%eax\)
+ *[a-f0-9]+:   d3 08                   rorl   %cl,\(%eax\)
+ *[a-f0-9]+:   d1 08                   rorl   \(%eax\)
  *[a-f0-9]+:   83 18 01                sbbl   \$0x1,\(%eax\)
+ *[a-f0-9]+:   81 18 89 00 00 00       sbbl   \$0x89,\(%eax\)
+ *[a-f0-9]+:   81 18 34 12 00 00       sbbl   \$0x1234,\(%eax\)
+ *[a-f0-9]+:   81 18 78 56 34 12       sbbl   \$0x12345678,\(%eax\)
+ *[a-f0-9]+:   af                      scas   %es:\(%edi\),%eax
+ *[a-f0-9]+:   af                      scas   %es:\(%edi\),%eax
+ *[a-f0-9]+:   d1 20                   shll   \(%eax\)
+ *[a-f0-9]+:   c1 20 02                shll   \$0x2,\(%eax\)
+ *[a-f0-9]+:   d3 20                   shll   %cl,\(%eax\)
+ *[a-f0-9]+:   d1 20                   shll   \(%eax\)
+ *[a-f0-9]+:   d1 38                   sarl   \(%eax\)
+ *[a-f0-9]+:   c1 38 02                sarl   \$0x2,\(%eax\)
+ *[a-f0-9]+:   d3 38                   sarl   %cl,\(%eax\)
+ *[a-f0-9]+:   d1 38                   sarl   \(%eax\)
+ *[a-f0-9]+:   d1 20                   shll   \(%eax\)
+ *[a-f0-9]+:   c1 20 02                shll   \$0x2,\(%eax\)
+ *[a-f0-9]+:   d3 20                   shll   %cl,\(%eax\)
+ *[a-f0-9]+:   d1 20                   shll   \(%eax\)
+ *[a-f0-9]+:   d1 28                   shrl   \(%eax\)
+ *[a-f0-9]+:   c1 28 02                shrl   \$0x2,\(%eax\)
+ *[a-f0-9]+:   d3 28                   shrl   %cl,\(%eax\)
+ *[a-f0-9]+:   d1 28                   shrl   \(%eax\)
+ *[a-f0-9]+:   ab                      stos   %eax,%es:\(%edi\)
+ *[a-f0-9]+:   ab                      stos   %eax,%es:\(%edi\)
  *[a-f0-9]+:   83 28 01                subl   \$0x1,\(%eax\)
+ *[a-f0-9]+:   81 28 89 00 00 00       subl   \$0x89,\(%eax\)
+ *[a-f0-9]+:   81 28 34 12 00 00       subl   \$0x1234,\(%eax\)
+ *[a-f0-9]+:   81 28 78 56 34 12       subl   \$0x12345678,\(%eax\)
+ *[a-f0-9]+:   f7 00 89 00 00 00       testl  \$0x89,\(%eax\)
+ *[a-f0-9]+:   f7 00 34 12 00 00       testl  \$0x1234,\(%eax\)
+ *[a-f0-9]+:   f7 00 78 56 34 12       testl  \$0x12345678,\(%eax\)
  *[a-f0-9]+:   c5 fb 2a 00             vcvtsi2sdl \(%eax\),%xmm0,%xmm0
  *[a-f0-9]+:   62 f1 7f 08 2a 00       vcvtsi2sdl \(%eax\),%xmm0,%xmm0
  *[a-f0-9]+:   c5 fa 2a 00             vcvtsi2ssl \(%eax\),%xmm0,%xmm0
@@ -64,4 +150,7 @@ Disassembly of section .text:
  *[a-f0-9]+:   62 f1 7f 08 7b 00       vcvtusi2sdl \(%eax\),%xmm0,%xmm0
  *[a-f0-9]+:   62 f1 7e 08 7b 00       vcvtusi2ssl \(%eax\),%xmm0,%xmm0
  *[a-f0-9]+:   83 30 01                xorl   \$0x1,\(%eax\)
+ *[a-f0-9]+:   81 30 89 00 00 00       xorl   \$0x89,\(%eax\)
+ *[a-f0-9]+:   81 30 34 12 00 00       xorl   \$0x1234,\(%eax\)
+ *[a-f0-9]+:   81 30 78 56 34 12       xorl   \$0x12345678,\(%eax\)
 #pass

diff --git a/gas/testsuite/gas/i386/noreg32.l b/gas/testsuite/gas/i386/noreg32.l
new file mode 100644 (file)
index 0000000..842774e
--- /dev/null
+++ b/gas/testsuite/gas/i386/noreg32.l
@@ -0,0 +1,125 @@
+.*: Assembler messages:
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `bt'
+.*:[1-9][0-9]*: Warning: .* `btc'
+.*:[1-9][0-9]*: Warning: .* `btr'
+.*:[1-9][0-9]*: Warning: .* `bts'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `dec'
+.*:[1-9][0-9]*: Warning: .* `div'
+.*:[1-9][0-9]*: Warning: .* `fadd'
+.*:[1-9][0-9]*: Warning: .* `fcom'
+.*:[1-9][0-9]*: Warning: .* `fcomp'
+.*:[1-9][0-9]*: Warning: .* `fdiv'
+.*:[1-9][0-9]*: Warning: .* `fdivr'
+.*:[1-9][0-9]*: Warning: .* `fiadd'
+.*:[1-9][0-9]*: Warning: .* `ficom'
+.*:[1-9][0-9]*: Warning: .* `ficomp'
+.*:[1-9][0-9]*: Warning: .* `fidiv'
+.*:[1-9][0-9]*: Warning: .* `fidivr'
+.*:[1-9][0-9]*: Warning: .* `fild'
+.*:[1-9][0-9]*: Warning: .* `fimul'
+.*:[1-9][0-9]*: Warning: .* `fist'
+.*:[1-9][0-9]*: Warning: .* `fistp'
+.*:[1-9][0-9]*: Warning: .* `fisttp'
+.*:[1-9][0-9]*: Warning: .* `fisub'
+.*:[1-9][0-9]*: Warning: .* `fisubr'
+.*:[1-9][0-9]*: Warning: .* `fld'
+.*:[1-9][0-9]*: Warning: .* `fmul'
+.*:[1-9][0-9]*: Warning: .* `fst'
+.*:[1-9][0-9]*: Warning: .* `fstp'
+.*:[1-9][0-9]*: Warning: .* `fsub'
+.*:[1-9][0-9]*: Warning: .* `fsubr'
+.*:[1-9][0-9]*: Warning: .* `idiv'
+.*:[1-9][0-9]*: Warning: .* `imul'
+.*:[1-9][0-9]*: Warning: .* `in'
+.*:[1-9][0-9]*: Warning: .* `in'
+.*:[1-9][0-9]*: Warning: .* `inc'
+.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Warning: .* `mul'
+.*:[1-9][0-9]*: Warning: .* `neg'
+.*:[1-9][0-9]*: Warning: .* `nop'
+.*:[1-9][0-9]*: Warning: .* `not'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `out'
+.*:[1-9][0-9]*: Warning: .* `out'
+.*:[1-9][0-9]*: Warning: .* `outs'
+.*:[1-9][0-9]*: Warning: .* `outs'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `scas'
+.*:[1-9][0-9]*: Warning: .* `scas'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `stos'
+.*:[1-9][0-9]*: Warning: .* `stos'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Warning: .* `xor'

diff --git a/gas/testsuite/gas/i386/noreg32.s b/gas/testsuite/gas/i386/noreg32.s
index d6a4cad29e9865701cc90b2de46e88941562e6cc..7876e963147a9f5761ba13fbf7dfabbfe3f0b429 100644 (file)
--- a/gas/testsuite/gas/i386/noreg32.s
+++ b/gas/testsuite/gas/i386/noreg32.s
@@ -1,16 +1,32 @@
        .text
 noreg:
        adc     $1, (%eax)
+       adc     $0x89, (%eax)
+       adc     $0x1234, (%eax)
+       adc     $0x12345678, (%eax)
        add     $1, (%eax)
+       add     $0x89, (%eax)
+       add     $0x1234, (%eax)
+       add     $0x12345678, (%eax)
        and     $1, (%eax)
+       and     $0x89, (%eax)
+       and     $0x1234, (%eax)
+       and     $0x12345678, (%eax)
        bt      $1, (%eax)
        btc     $1, (%eax)
        btr     $1, (%eax)
        bts     $1, (%eax)
        call    *(%eax)
        cmp     $1, (%eax)
+       cmp     $0x89, (%eax)
+       cmp     $0x1234, (%eax)
+       cmp     $0x12345678, (%eax)
+       cmps
+       cmps    %es:(%edi), (%esi)
        cvtsi2sd (%eax), %xmm0
        cvtsi2ss (%eax), %xmm0
+       dec     (%eax)
+       div     (%eax)
        fadd    (%eax)
        fcom    (%eax)
        fcomp   (%eax)
@@ -34,23 +50,92 @@ noreg:
        fstp    (%eax)
        fsub    (%eax)
        fsubr   (%eax)
+       idiv    (%eax)
+       imul    (%eax)
+       in      $0
+       in      %dx
+       inc     (%eax)
+       ins
+       ins     %dx, %es:(%edi)
        jmp     *(%eax)
        lgdt    (%eax)
        lidt    (%eax)
        lldt    (%eax)
        lmsw    (%eax)
+       lods
+       lods    (%esi)
        ltr     (%eax)
+       mov     $0x12, (%eax)
+       mov     $0x1234, (%eax)
+       mov     $0x12345678, (%eax)
        mov     %es, (%eax)
        mov     (%eax), %es
+       movs
+       movs    (%esi), %es:(%edi)
+       mul     (%eax)
+       neg     (%eax)
        nop     (%eax)
+       not     (%eax)
        or      $1, (%eax)
+       or      $0x89, (%eax)
+       or      $0x1234, (%eax)
+       or      $0x12345678, (%eax)
+       out     $0
+       out     %dx
+       outs
+       outs    (%esi), %dx
        pop     (%eax)
        pop     %es
        ptwrite (%eax)
        push    (%eax)
        push    %es
+       rcl     $1, (%eax)
+       rcl     $2, (%eax)
+       rcl     %cl, (%eax)
+       rcl     (%eax)
+       rcr     $1, (%eax)
+       rcr     $2, (%eax)
+       rcr     %cl, (%eax)
+       rcr     (%eax)
+       rol     $1, (%eax)
+       rol     $2, (%eax)
+       rol     %cl, (%eax)
+       rol     (%eax)
+       ror     $1, (%eax)
+       ror     $2, (%eax)
+       ror     %cl, (%eax)
+       ror     (%eax)
        sbb     $1, (%eax)
+       sbb     $0x89, (%eax)
+       sbb     $0x1234, (%eax)
+       sbb     $0x12345678, (%eax)
+       scas
+       scas    %es:(%edi)
+       sal     $1, (%eax)
+       sal     $2, (%eax)
+       sal     %cl, (%eax)
+       sal     (%eax)
+       sar     $1, (%eax)
+       sar     $2, (%eax)
+       sar     %cl, (%eax)
+       sar     (%eax)
+       shl     $1, (%eax)
+       shl     $2, (%eax)
+       shl     %cl, (%eax)
+       shl     (%eax)
+       shr     $1, (%eax)
+       shr     $2, (%eax)
+       shr     %cl, (%eax)
+       shr     (%eax)
+       stos
+       stos    %es:(%edi)
        sub     $1, (%eax)
+       sub     $0x89, (%eax)
+       sub     $0x1234, (%eax)
+       sub     $0x12345678, (%eax)
+       test    $0x89, (%eax)
+       test    $0x1234, (%eax)
+       test    $0x12345678, (%eax)
        vcvtsi2sd (%eax), %xmm0, %xmm0
        {evex} vcvtsi2sd (%eax), %xmm0, %xmm0
        vcvtsi2ss (%eax), %xmm0, %xmm0
@@ -58,3 +143,6 @@ noreg:
        vcvtusi2sd (%eax), %xmm0, %xmm0
        vcvtusi2ss (%eax), %xmm0, %xmm0
        xor     $1, (%eax)
+       xor     $0x89, (%eax)
+       xor     $0x1234, (%eax)
+       xor     $0x12345678, (%eax)

diff --git a/gas/testsuite/gas/i386/noreg64.d b/gas/testsuite/gas/i386/noreg64.d
index fd4fca7182fb43cd240dfd155b6a5774c587635e..d058da486fd0322b029887497d4516b64d881058 100644 (file)
--- a/gas/testsuite/gas/i386/noreg64.d
+++ b/gas/testsuite/gas/i386/noreg64.d
@@ -1,3 +1,4 @@
+#as: -moperand-check=none
 #objdump: -dw
 #name: 64-bit insns not sizeable through register operands
 
@@ -7,16 +8,32 @@ Disassembly of section .text:
 
 0+ <noreg>:
  *[a-f0-9]+:   83 10 01                adcl   \$0x1,\(%rax\)
+ *[a-f0-9]+:   81 10 89 00 00 00       adcl   \$0x89,\(%rax\)
+ *[a-f0-9]+:   81 10 34 12 00 00       adcl   \$0x1234,\(%rax\)
+ *[a-f0-9]+:   81 10 78 56 34 12       adcl   \$0x12345678,\(%rax\)
  *[a-f0-9]+:   83 00 01                addl   \$0x1,\(%rax\)
+ *[a-f0-9]+:   81 00 89 00 00 00       addl   \$0x89,\(%rax\)
+ *[a-f0-9]+:   81 00 34 12 00 00       addl   \$0x1234,\(%rax\)
+ *[a-f0-9]+:   81 00 78 56 34 12       addl   \$0x12345678,\(%rax\)
  *[a-f0-9]+:   83 20 01                andl   \$0x1,\(%rax\)
+ *[a-f0-9]+:   81 20 89 00 00 00       andl   \$0x89,\(%rax\)
+ *[a-f0-9]+:   81 20 34 12 00 00       andl   \$0x1234,\(%rax\)
+ *[a-f0-9]+:   81 20 78 56 34 12       andl   \$0x12345678,\(%rax\)
  *[a-f0-9]+:   0f ba 20 01             btl    \$0x1,\(%rax\)
  *[a-f0-9]+:   0f ba 38 01             btcl   \$0x1,\(%rax\)
  *[a-f0-9]+:   0f ba 30 01             btrl   \$0x1,\(%rax\)
  *[a-f0-9]+:   0f ba 28 01             btsl   \$0x1,\(%rax\)
  *[a-f0-9]+:   ff 10                   callq  \*\(%rax\)
  *[a-f0-9]+:   83 38 01                cmpl   \$0x1,\(%rax\)
+ *[a-f0-9]+:   81 38 89 00 00 00       cmpl   \$0x89,\(%rax\)
+ *[a-f0-9]+:   81 38 34 12 00 00       cmpl   \$0x1234,\(%rax\)
+ *[a-f0-9]+:   81 38 78 56 34 12       cmpl   \$0x12345678,\(%rax\)
+ *[a-f0-9]+:   a7                      cmpsl  %es:\(%rdi\),%ds:\(%rsi\)
+ *[a-f0-9]+:   a7                      cmpsl  %es:\(%rdi\),%ds:\(%rsi\)
  *[a-f0-9]+:   f2 0f 2a 00             cvtsi2sdl \(%rax\),%xmm0
  *[a-f0-9]+:   f3 0f 2a 00             cvtsi2ssl \(%rax\),%xmm0
+ *[a-f0-9]+:   ff 08                   decl   \(%rax\)
+ *[a-f0-9]+:   f7 30                   divl   \(%rax\)
  *[a-f0-9]+:   d8 00                   fadds  \(%rax\)
  *[a-f0-9]+:   d8 10                   fcoms  \(%rax\)
  *[a-f0-9]+:   d8 18                   fcomps \(%rax\)
@@ -40,23 +57,93 @@ Disassembly of section .text:
  *[a-f0-9]+:   d9 18                   fstps  \(%rax\)
  *[a-f0-9]+:   d8 20                   fsubs  \(%rax\)
  *[a-f0-9]+:   d8 28                   fsubrs \(%rax\)
+ *[a-f0-9]+:   f7 38                   idivl  \(%rax\)
+ *[a-f0-9]+:   f7 28                   imull  \(%rax\)
+ *[a-f0-9]+:   e5 00                   in     \$0x0,%eax
+ *[a-f0-9]+:   ed                      in     \(%dx\),%eax
+ *[a-f0-9]+:   ff 00                   incl   \(%rax\)
+ *[a-f0-9]+:   6d                      insl   \(%dx\),%es:\(%rdi\)
+ *[a-f0-9]+:   6d                      insl   \(%dx\),%es:\(%rdi\)
  *[a-f0-9]+:   ff 20                   jmpq   \*\(%rax\)
  *[a-f0-9]+:   0f 01 10                lgdt   \(%rax\)
  *[a-f0-9]+:   0f 01 18                lidt   \(%rax\)
  *[a-f0-9]+:   0f 00 10                lldt   \(%rax\)
  *[a-f0-9]+:   0f 01 30                lmsw   \(%rax\)
+ *[a-f0-9]+:   ad                      lods   %ds:\(%rsi\),%eax
+ *[a-f0-9]+:   ad                      lods   %ds:\(%rsi\),%eax
  *[a-f0-9]+:   0f 00 18                ltr    \(%rax\)
+ *[a-f0-9]+:   c7 00 12 00 00 00       movl   \$0x12,\(%rax\)
+ *[a-f0-9]+:   c7 00 34 12 00 00       movl   \$0x1234,\(%rax\)
+ *[a-f0-9]+:   c7 00 78 56 34 12       movl   \$0x12345678,\(%rax\)
  *[a-f0-9]+:   8c 00                   mov    %es,\(%rax\)
  *[a-f0-9]+:   8e 00                   mov    \(%rax\),%es
+ *[a-f0-9]+:   a5                      movsl  %ds:\(%rsi\),%es:\(%rdi\)
+ *[a-f0-9]+:   a5                      movsl  %ds:\(%rsi\),%es:\(%rdi\)
+ *[a-f0-9]+:   f7 20                   mull   \(%rax\)
+ *[a-f0-9]+:   f7 18                   negl   \(%rax\)
  *[a-f0-9]+:   0f 1f 00                nopl   \(%rax\)
+ *[a-f0-9]+:   f7 10                   notl   \(%rax\)
  *[a-f0-9]+:   83 08 01                orl    \$0x1,\(%rax\)
+ *[a-f0-9]+:   81 08 89 00 00 00       orl    \$0x89,\(%rax\)
+ *[a-f0-9]+:   81 08 34 12 00 00       orl    \$0x1234,\(%rax\)
+ *[a-f0-9]+:   81 08 78 56 34 12       orl    \$0x12345678,\(%rax\)
+ *[a-f0-9]+:   e7 00                   out    %eax,\$0x0
+ *[a-f0-9]+:   ef                      out    %eax,\(%dx\)
+ *[a-f0-9]+:   6f                      outsl  %ds:\(%rsi\),\(%dx\)
+ *[a-f0-9]+:   6f                      outsl  %ds:\(%rsi\),\(%dx\)
  *[a-f0-9]+:   8f 00                   popq   \(%rax\)
  *[a-f0-9]+:   0f a1                   popq   %fs
  *[a-f0-9]+:   f3 0f ae 20             ptwritel \(%rax\)
  *[a-f0-9]+:   ff 30                   pushq  \(%rax\)
  *[a-f0-9]+:   0f a0                   pushq  %fs
+ *[a-f0-9]+:   d1 10                   rcll   \(%rax\)
+ *[a-f0-9]+:   c1 10 02                rcll   \$0x2,\(%rax\)
+ *[a-f0-9]+:   d3 10                   rcll   %cl,\(%rax\)
+ *[a-f0-9]+:   d1 10                   rcll   \(%rax\)
+ *[a-f0-9]+:   d1 18                   rcrl   \(%rax\)
+ *[a-f0-9]+:   c1 18 02                rcrl   \$0x2,\(%rax\)
+ *[a-f0-9]+:   d3 18                   rcrl   %cl,\(%rax\)
+ *[a-f0-9]+:   d1 18                   rcrl   \(%rax\)
+ *[a-f0-9]+:   d1 00                   roll   \(%rax\)
+ *[a-f0-9]+:   c1 00 02                roll   \$0x2,\(%rax\)
+ *[a-f0-9]+:   d3 00                   roll   %cl,\(%rax\)
+ *[a-f0-9]+:   d1 00                   roll   \(%rax\)
+ *[a-f0-9]+:   d1 08                   rorl   \(%rax\)
+ *[a-f0-9]+:   c1 08 02                rorl   \$0x2,\(%rax\)
+ *[a-f0-9]+:   d3 08                   rorl   %cl,\(%rax\)
+ *[a-f0-9]+:   d1 08                   rorl   \(%rax\)
  *[a-f0-9]+:   83 18 01                sbbl   \$0x1,\(%rax\)
+ *[a-f0-9]+:   81 18 89 00 00 00       sbbl   \$0x89,\(%rax\)
+ *[a-f0-9]+:   81 18 34 12 00 00       sbbl   \$0x1234,\(%rax\)
+ *[a-f0-9]+:   81 18 78 56 34 12       sbbl   \$0x12345678,\(%rax\)
+ *[a-f0-9]+:   af                      scas   %es:\(%rdi\),%eax
+ *[a-f0-9]+:   af                      scas   %es:\(%rdi\),%eax
+ *[a-f0-9]+:   d1 20                   shll   \(%rax\)
+ *[a-f0-9]+:   c1 20 02                shll   \$0x2,\(%rax\)
+ *[a-f0-9]+:   d3 20                   shll   %cl,\(%rax\)
+ *[a-f0-9]+:   d1 20                   shll   \(%rax\)
+ *[a-f0-9]+:   d1 38                   sarl   \(%rax\)
+ *[a-f0-9]+:   c1 38 02                sarl   \$0x2,\(%rax\)
+ *[a-f0-9]+:   d3 38                   sarl   %cl,\(%rax\)
+ *[a-f0-9]+:   d1 38                   sarl   \(%rax\)
+ *[a-f0-9]+:   d1 20                   shll   \(%rax\)
+ *[a-f0-9]+:   c1 20 02                shll   \$0x2,\(%rax\)
+ *[a-f0-9]+:   d3 20                   shll   %cl,\(%rax\)
+ *[a-f0-9]+:   d1 20                   shll   \(%rax\)
+ *[a-f0-9]+:   d1 28                   shrl   \(%rax\)
+ *[a-f0-9]+:   c1 28 02                shrl   \$0x2,\(%rax\)
+ *[a-f0-9]+:   d3 28                   shrl   %cl,\(%rax\)
+ *[a-f0-9]+:   d1 28                   shrl   \(%rax\)
+ *[a-f0-9]+:   ab                      stos   %eax,%es:\(%rdi\)
+ *[a-f0-9]+:   ab                      stos   %eax,%es:\(%rdi\)
  *[a-f0-9]+:   83 28 01                subl   \$0x1,\(%rax\)
+ *[a-f0-9]+:   81 28 89 00 00 00       subl   \$0x89,\(%rax\)
+ *[a-f0-9]+:   81 28 34 12 00 00       subl   \$0x1234,\(%rax\)
+ *[a-f0-9]+:   81 28 78 56 34 12       subl   \$0x12345678,\(%rax\)
+ *[a-f0-9]+:   0f 07                   sysret *
+ *[a-f0-9]+:   f7 00 89 00 00 00       testl  \$0x89,\(%rax\)
+ *[a-f0-9]+:   f7 00 34 12 00 00       testl  \$0x1234,\(%rax\)
+ *[a-f0-9]+:   f7 00 78 56 34 12       testl  \$0x12345678,\(%rax\)
  *[a-f0-9]+:   c5 fb 2a 00             vcvtsi2sdl \(%rax\),%xmm0,%xmm0
  *[a-f0-9]+:   62 61 7f 08 2a 38       vcvtsi2sdl \(%rax\),%xmm0,%xmm31
  *[a-f0-9]+:   c5 fa 2a 00             vcvtsi2ssl \(%rax\),%xmm0,%xmm0
@@ -64,4 +151,7 @@ Disassembly of section .text:
  *[a-f0-9]+:   62 f1 7f 08 7b 00       vcvtusi2sdl \(%rax\),%xmm0,%xmm0
  *[a-f0-9]+:   62 f1 7e 08 7b 00       vcvtusi2ssl \(%rax\),%xmm0,%xmm0
  *[a-f0-9]+:   83 30 01                xorl   \$0x1,\(%rax\)
+ *[a-f0-9]+:   81 30 89 00 00 00       xorl   \$0x89,\(%rax\)
+ *[a-f0-9]+:   81 30 34 12 00 00       xorl   \$0x1234,\(%rax\)
+ *[a-f0-9]+:   81 30 78 56 34 12       xorl   \$0x12345678,\(%rax\)
 #pass

diff --git a/gas/testsuite/gas/i386/noreg64.l b/gas/testsuite/gas/i386/noreg64.l
new file mode 100644 (file)
index 0000000..9ec8093
--- /dev/null
+++ b/gas/testsuite/gas/i386/noreg64.l
@@ -0,0 +1,135 @@
+.*: Assembler messages:
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `adc'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `add'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `and'
+.*:[1-9][0-9]*: Warning: .* `bt'
+.*:[1-9][0-9]*: Warning: .* `btc'
+.*:[1-9][0-9]*: Warning: .* `btr'
+.*:[1-9][0-9]*: Warning: .* `bts'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmp'
+.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `cmps'
+.*:[1-9][0-9]*: Warning: .* `cvtsi2sd'
+.*:[1-9][0-9]*: Warning: .* `cvtsi2ss'
+.*:[1-9][0-9]*: Warning: .* `dec'
+.*:[1-9][0-9]*: Warning: .* `div'
+.*:[1-9][0-9]*: Warning: .* `fadd'
+.*:[1-9][0-9]*: Warning: .* `fcom'
+.*:[1-9][0-9]*: Warning: .* `fcomp'
+.*:[1-9][0-9]*: Warning: .* `fdiv'
+.*:[1-9][0-9]*: Warning: .* `fdivr'
+.*:[1-9][0-9]*: Warning: .* `fiadd'
+.*:[1-9][0-9]*: Warning: .* `ficom'
+.*:[1-9][0-9]*: Warning: .* `ficomp'
+.*:[1-9][0-9]*: Warning: .* `fidiv'
+.*:[1-9][0-9]*: Warning: .* `fidivr'
+.*:[1-9][0-9]*: Warning: .* `fild'
+.*:[1-9][0-9]*: Warning: .* `fimul'
+.*:[1-9][0-9]*: Warning: .* `fist'
+.*:[1-9][0-9]*: Warning: .* `fistp'
+.*:[1-9][0-9]*: Warning: .* `fisttp'
+.*:[1-9][0-9]*: Warning: .* `fisub'
+.*:[1-9][0-9]*: Warning: .* `fisubr'
+.*:[1-9][0-9]*: Warning: .* `fld'
+.*:[1-9][0-9]*: Warning: .* `fmul'
+.*:[1-9][0-9]*: Warning: .* `fst'
+.*:[1-9][0-9]*: Warning: .* `fstp'
+.*:[1-9][0-9]*: Warning: .* `fsub'
+.*:[1-9][0-9]*: Warning: .* `fsubr'
+.*:[1-9][0-9]*: Warning: .* `idiv'
+.*:[1-9][0-9]*: Warning: .* `imul'
+.*:[1-9][0-9]*: Warning: .* `in'
+.*:[1-9][0-9]*: Warning: .* `in'
+.*:[1-9][0-9]*: Warning: .* `inc'
+.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Warning: .* `ins'
+.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Warning: .* `lods'
+.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Warning: .* `mov'
+.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Warning: .* `movs'
+.*:[1-9][0-9]*: Warning: .* `mul'
+.*:[1-9][0-9]*: Warning: .* `neg'
+.*:[1-9][0-9]*: Warning: .* `nop'
+.*:[1-9][0-9]*: Warning: .* `not'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `or'
+.*:[1-9][0-9]*: Warning: .* `out'
+.*:[1-9][0-9]*: Warning: .* `out'
+.*:[1-9][0-9]*: Warning: .* `outs'
+.*:[1-9][0-9]*: Warning: .* `outs'
+.*:[1-9][0-9]*: Warning: .* `ptwrite'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcl'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rcr'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `rol'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `ror'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `sbb'
+.*:[1-9][0-9]*: Warning: .* `scas'
+.*:[1-9][0-9]*: Warning: .* `scas'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sal'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `sar'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shl'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `shr'
+.*:[1-9][0-9]*: Warning: .* `stos'
+.*:[1-9][0-9]*: Warning: .* `stos'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `sub'
+.*:[1-9][0-9]*: Warning: .* `sysret'
+.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `test'
+.*:[1-9][0-9]*: Warning: .* `vcvtsi2sd'
+.*:[1-9][0-9]*: Warning: .* `vcvtsi2sd'
+.*:[1-9][0-9]*: Warning: .* `vcvtsi2ss'
+.*:[1-9][0-9]*: Warning: .* `vcvtsi2ss'
+.*:[1-9][0-9]*: Warning: .* `vcvtusi2sd'
+.*:[1-9][0-9]*: Warning: .* `vcvtusi2ss'
+.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Warning: .* `xor'
+.*:[1-9][0-9]*: Warning: .* `xor'

diff --git a/gas/testsuite/gas/i386/noreg64.s b/gas/testsuite/gas/i386/noreg64.s
index c50d76a180d89868ad8b4de1cf0843b267dd83b9..7418ccb2204dea83a2ea3a678c6646e6b4546024 100644 (file)
--- a/gas/testsuite/gas/i386/noreg64.s
+++ b/gas/testsuite/gas/i386/noreg64.s
@@ -1,16 +1,32 @@
        .text
 noreg:
        adc     $1, (%rax)
+       adc     $0x89, (%rax)
+       adc     $0x1234, (%rax)
+       adc     $0x12345678, (%rax)
        add     $1, (%rax)
+       add     $0x89, (%rax)
+       add     $0x1234, (%rax)
+       add     $0x12345678, (%rax)
        and     $1, (%rax)
+       and     $0x89, (%rax)
+       and     $0x1234, (%rax)
+       and     $0x12345678, (%rax)
        bt      $1, (%rax)
        btc     $1, (%rax)
        btr     $1, (%rax)
        bts     $1, (%rax)
        call    *(%rax)
        cmp     $1, (%rax)
+       cmp     $0x89, (%rax)
+       cmp     $0x1234, (%rax)
+       cmp     $0x12345678, (%rax)
+       cmps
+       cmps    %es:(%rdi), (%rsi)
        cvtsi2sd (%rax), %xmm0
        cvtsi2ss (%rax), %xmm0
+       dec     (%rax)
+       div     (%rax)
        fadd    (%rax)
        fcom    (%rax)
        fcomp   (%rax)
@@ -34,23 +50,93 @@ noreg:
        fstp    (%rax)
        fsub    (%rax)
        fsubr   (%rax)
+       idiv    (%rax)
+       imul    (%rax)
+       in      $0
+       in      %dx
+       inc     (%rax)
+       ins
+       ins     %dx, %es:(%rdi)
        jmp     *(%rax)
        lgdt    (%rax)
        lidt    (%rax)
        lldt    (%rax)
        lmsw    (%rax)
+       lods
+       lods    (%rsi)
        ltr     (%rax)
+       mov     $0x12, (%rax)
+       mov     $0x1234, (%rax)
+       mov     $0x12345678, (%rax)
        mov     %es, (%rax)
        mov     (%rax), %es
+       movs
+       movs    (%rsi), %es:(%rdi)
+       mul     (%rax)
+       neg     (%rax)
        nop     (%rax)
+       not     (%rax)
        or      $1, (%rax)
+       or      $0x89, (%rax)
+       or      $0x1234, (%rax)
+       or      $0x12345678, (%rax)
+       out     $0
+       out     %dx
+       outs
+       outs    (%rsi), %dx
        pop     (%rax)
        pop     %fs
        ptwrite (%rax)
        push    (%rax)
        push    %fs
+       rcl     $1, (%rax)
+       rcl     $2, (%rax)
+       rcl     %cl, (%rax)
+       rcl     (%rax)
+       rcr     $1, (%rax)
+       rcr     $2, (%rax)
+       rcr     %cl, (%rax)
+       rcr     (%rax)
+       rol     $1, (%rax)
+       rol     $2, (%rax)
+       rol     %cl, (%rax)
+       rol     (%rax)
+       ror     $1, (%rax)
+       ror     $2, (%rax)
+       ror     %cl, (%rax)
+       ror     (%rax)
        sbb     $1, (%rax)
+       sbb     $0x89, (%rax)
+       sbb     $0x1234, (%rax)
+       sbb     $0x12345678, (%rax)
+       scas
+       scas    %es:(%rdi)
+       sal     $1, (%rax)
+       sal     $2, (%rax)
+       sal     %cl, (%rax)
+       sal     (%rax)
+       sar     $1, (%rax)
+       sar     $2, (%rax)
+       sar     %cl, (%rax)
+       sar     (%rax)
+       shl     $1, (%rax)
+       shl     $2, (%rax)
+       shl     %cl, (%rax)
+       shl     (%rax)
+       shr     $1, (%rax)
+       shr     $2, (%rax)
+       shr     %cl, (%rax)
+       shr     (%rax)
+       stos
+       stos    %es:(%rdi)
        sub     $1, (%rax)
+       sub     $0x89, (%rax)
+       sub     $0x1234, (%rax)
+       sub     $0x12345678, (%rax)
+       sysret
+       test    $0x89, (%rax)
+       test    $0x1234, (%rax)
+       test    $0x12345678, (%rax)
        vcvtsi2sd (%rax), %xmm0, %xmm0
        vcvtsi2sd (%rax), %xmm0, %xmm31
        vcvtsi2ss (%rax), %xmm0, %xmm0
@@ -58,3 +144,6 @@ noreg:
        vcvtusi2sd (%rax), %xmm0, %xmm0
        vcvtusi2ss (%rax), %xmm0, %xmm0
        xor     $1, (%rax)
+       xor     $0x89, (%rax)
+       xor     $0x1234, (%rax)
+       xor     $0x12345678, (%rax)

diff --git a/gas/testsuite/gas/i386/opcode.s b/gas/testsuite/gas/i386/opcode.s
index ca521116f744d6fb810ee4b4130c04a24fc5b67a..1f803c38e5d506d9a4713d2e8078fbe002ccd552 100644 (file)
--- a/gas/testsuite/gas/i386/opcode.s
+++ b/gas/testsuite/gas/i386/opcode.s
@@ -211,8 +211,8 @@ foo:
  fistl  0x90909090(%eax)
  fcoml  0x90909090(%eax)
  fstl   0x90909090(%eax)
- ficom  0x90909090(%eax)
- fist   0x90909090(%eax)
+ ficoms 0x90909090(%eax)
+ fists  0x90909090(%eax)
  loopne .+2-0x70
  loope  .+2-0x70
  loop   .+2-0x70

diff --git a/gas/testsuite/gas/i386/sse-noavx.d b/gas/testsuite/gas/i386/sse-noavx.d
index 0fbb874ccadd642d068e9bae8237f54c37d559cd..d42290915096c1ddcd0546cbecac96f443041e26 100644 (file)
--- a/gas/testsuite/gas/i386/sse-noavx.d
+++ b/gas/testsuite/gas/i386/sse-noavx.d
@@ -15,7 +15,6 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    66 0f 2c dc             cvttpd2pi %xmm4,%mm3
 [      ]*[a-f0-9]+:    0f 2c dc                cvttps2pi %xmm4,%mm3
 [      ]*[a-f0-9]+:    df 08                   fisttps \(%eax\)
-[      ]*[a-f0-9]+:    df 08                   fisttps \(%eax\)
 [      ]*[a-f0-9]+:    db 08                   fisttpl \(%eax\)
 [      ]*[a-f0-9]+:    dd 08                   fisttpll \(%eax\)
 [      ]*[a-f0-9]+:    0f ae e8                lfence 

diff --git a/gas/testsuite/gas/i386/sse-noavx.s b/gas/testsuite/gas/i386/sse-noavx.s
index 42d1c3dd365a073270ebdfb5aa77860636fc1a60..5316351b9dd7905095b6c81bf718e9b011a61a79 100644 (file)
--- a/gas/testsuite/gas/i386/sse-noavx.s
+++ b/gas/testsuite/gas/i386/sse-noavx.s
@@ -9,7 +9,6 @@ _start:
  cvtps2pi      %xmm7,%mm6
  cvttpd2pi     %xmm4,%mm3
  cvttps2pi     %xmm4,%mm3
- fisttp (%eax)
  fisttps (%eax)
  fisttpl (%eax)
  fisttpll (%eax)

diff --git a/gas/testsuite/gas/i386/sse3.s b/gas/testsuite/gas/i386/sse3.s
index 051dfb08237fe0eda29dad4f9da0d5e49ac3b778..de0f31637a5f29d42304deabd329948fb54086ec 100644 (file)
--- a/gas/testsuite/gas/i386/sse3.s
+++ b/gas/testsuite/gas/i386/sse3.s
@@ -6,7 +6,7 @@ foo:
        addsubpd        %xmm2,%xmm1
        addsubps        (%ebx),%xmm2
        addsubps        %xmm4,%xmm3
-       fisttp          0x90909090(%eax)
+       fisttps         0x90909090(%eax)
        fisttpl         0x90909090(%eax)
        fisttpll        0x90909090(%eax)
        haddpd          0x0(%ebp),%xmm4

diff --git a/gas/testsuite/gas/i386/x86-64-avx-scalar.s b/gas/testsuite/gas/i386/x86-64-avx-scalar.s
index 0f8800fc6da4a8c98184b7330f30f65557d5fc09..aa3f2773b2ddd023893b8ff3206d216df56ec88b 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-avx-scalar.s
+++ b/gas/testsuite/gas/i386/x86-64-avx-scalar.s
@@ -234,9 +234,9 @@ _start:
 
 # Tests for op regl/mem32, xmm, xmm
        vcvtsi2sd %ecx,%xmm4,%xmm6
-       vcvtsi2sd (%rcx),%xmm4,%xmm6
+       vcvtsi2sdl (%rcx),%xmm4,%xmm6
        vcvtsi2ss %ecx,%xmm4,%xmm6
-       vcvtsi2ss (%rcx),%xmm4,%xmm6
+       vcvtsi2ssl (%rcx),%xmm4,%xmm6
 
 # Tests for op imm8, xmm/mem32, xmm, xmm
        vcmpss $7,%xmm4,%xmm6,%xmm2

diff --git a/gas/testsuite/gas/i386/x86-64-avx.s b/gas/testsuite/gas/i386/x86-64-avx.s
index b5f011ec45e4a4f79aa80e9ece4e073a56a369a8..c7355dcaa8bca55ecf4700d76587b8c2fc77f1a5 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-avx.s
+++ b/gas/testsuite/gas/i386/x86-64-avx.s
@@ -1222,9 +1222,9 @@ _start:
 
 # Tests for op regl/mem32, xmm, xmm
        vcvtsi2sd %ecx,%xmm4,%xmm6
-       vcvtsi2sd (%rcx),%xmm4,%xmm6
+       vcvtsi2sdl (%rcx),%xmm4,%xmm6
        vcvtsi2ss %ecx,%xmm4,%xmm6
-       vcvtsi2ss (%rcx),%xmm4,%xmm6
+       vcvtsi2ssl (%rcx),%xmm4,%xmm6
 
 # Tests for op imm8, xmm/mem32, xmm, xmm
        vcmpss $7,%xmm4,%xmm6,%xmm2

diff --git a/gas/testsuite/gas/i386/x86-64-bundle.s b/gas/testsuite/gas/i386/x86-64-bundle.s
index 8272f046fe055b91483111b37db3a1c5b296f480..f8381abbaa659d23bf870a39f90e7cdc873b602b 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-bundle.s
+++ b/gas/testsuite/gas/i386/x86-64-bundle.s
@@ -58,7 +58,7 @@
        and $3,%eax
 .endm
 .macro test_4
-       lock and $3,(%rax)
+       lock andl $3,(%rax)
 .endm
 .macro test_5
        mov $0x11223344,%eax

diff --git a/gas/testsuite/gas/i386/x86-64-intel64.d b/gas/testsuite/gas/i386/x86-64-intel64.d
index 545fcdcfc5408a445ed0443e9036101871e4a421..cae797bacd9e12abbbcd0ae500d9516d0a7a5dbd 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-intel64.d
+++ b/gas/testsuite/gas/i386/x86-64-intel64.d
@@ -14,6 +14,7 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    48 0f b2 1a             lss    \(%rdx\),%rbx
 [      ]*[a-f0-9]+:    0f 05                   syscall 
 [      ]*[a-f0-9]+:    0f 07                   sysret 
+[      ]*[a-f0-9]+:    48 0f 07                sysretq *
 [      ]*[a-f0-9]+:    48 0f b4 01             lfs    \(%rcx\),%rax
 [      ]*[a-f0-9]+:    48 0f b4 01             lfs    \(%rcx\),%rax
 [      ]*[a-f0-9]+:    48 0f b5 0a             lgs    \(%rdx\),%rcx

diff --git a/gas/testsuite/gas/i386/x86-64-intel64.s b/gas/testsuite/gas/i386/x86-64-intel64.s
index 233f6b72a6086d471844126011d1aac14fec1346..d7852ab8ff4c6013b6fb3d0e1c0b40580b585197 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-intel64.s
+++ b/gas/testsuite/gas/i386/x86-64-intel64.s
@@ -11,7 +11,8 @@ _start:
        lssq    (%rdx), %rbx
 
        syscall
-       sysret
+       sysretl
+       sysretq
 
        .intel_syntax noprefix
        lfs     rax, [rcx]

diff --git a/gas/testsuite/gas/i386/x86-64-lock-1.s b/gas/testsuite/gas/i386/x86-64-lock-1.s
index bbd71c8d3620962100e4dc56165bfb6269caf05b..ac1f8ee6f147640f21b9ab6fe28f872b9ac16d05 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-lock-1.s
+++ b/gas/testsuite/gas/i386/x86-64-lock-1.s
@@ -3,17 +3,17 @@
        .text
 foo:
        lock add %eax, (%rbx)
-       lock add $0x64, (%rbx)
+       lock addl $0x64, (%rbx)
        lock adc %eax, (%rbx)
-       lock adc $0x64, (%rbx)
+       lock adcl $0x64, (%rbx)
        lock and %eax, (%rbx)
-       lock and $0x64, (%rbx)
+       lock andl $0x64, (%rbx)
        lock btc %eax, (%rbx)
-       lock btc $0x64, (%rbx)
+       lock btcl $0x64, (%rbx)
        lock btr %eax, (%rbx)
-       lock btr $0x64, (%rbx)
+       lock btrl $0x64, (%rbx)
        lock bts %eax, (%rbx)
-       lock bts $0x64, (%rbx)
+       lock btsl $0x64, (%rbx)
        lock cmpxchg %eax,(%rbx)
        lock cmpxchg8b (%rbx)
        lock cmpxchg16b (%rbx)
@@ -22,16 +22,16 @@ foo:
        lock negl (%rbx)
        lock notl (%rbx)
        lock or %eax, (%rbx)
-       lock or $0x64, (%rbx)
+       lock orl $0x64, (%rbx)
        lock sbb %eax, (%rbx)
-       lock sbb $0x64, (%rbx)
+       lock sbbl $0x64, (%rbx)
        lock sub %eax, (%rbx)
-       lock sub $0x64, (%rbx)
+       lock subl $0x64, (%rbx)
        lock xadd %eax, (%rbx)
        lock xchg (%rbx), %eax
        lock xchg %eax, (%rbx)
        lock xor %eax, (%rbx)
-       lock xor $0x64, (%rbx)
+       lock xorl $0x64, (%rbx)
 
        .intel_syntax noprefix
        lock add DWORD PTR [rbx],eax

diff --git a/gas/testsuite/gas/i386/x86-64-nops.d b/gas/testsuite/gas/i386/x86-64-nops.d
index 8c6312d08af7217304bfa3acb0d7a66b0a5ad4c0..faf2dc9b5f4b48b03320435e2c32a7aac64c1b74 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-nops.d
+++ b/gas/testsuite/gas/i386/x86-64-nops.d
@@ -41,7 +41,6 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    0f 1d 04 59             nopl   \(%rcx,%rbx,2\)
 [      ]*[a-f0-9]+:    0f 1e 04 59             nopl   \(%rcx,%rbx,2\)
 [      ]*[a-f0-9]+:    0f 1f 04 59             nopl   \(%rcx,%rbx,2\)
-[      ]*[a-f0-9]+:    0f 1f 00                nopl   \(%rax\)
 [      ]*[a-f0-9]+:    48 0f 1f c0             nop    %rax
 [      ]*[a-f0-9]+:    0f 1f c0                nop    %eax
 [      ]*[a-f0-9]+:    66 0f 1f c0             nop    %ax
@@ -51,7 +50,6 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    48 0f 1f c0             nop    %rax
 [      ]*[a-f0-9]+:    0f 1f c0                nop    %eax
 [      ]*[a-f0-9]+:    66 0f 1f c0             nop    %ax
-[      ]*[a-f0-9]+:    41 0f 1f 02             nopl   \(%r10\)
 [      ]*[a-f0-9]+:    49 0f 1f c2             nop    %r10
 [      ]*[a-f0-9]+:    41 0f 1f c2             nop    %r10d
 [      ]*[a-f0-9]+:    66 41 0f 1f c2          nop    %r10w

diff --git a/gas/testsuite/gas/i386/x86-64-nops.s b/gas/testsuite/gas/i386/x86-64-nops.s
index d954ed1894a51455428ffc3072de8907857612bb..8bbd7e3a5be189f1fff8ad3216804255a9199173 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-nops.s
+++ b/gas/testsuite/gas/i386/x86-64-nops.s
@@ -44,7 +44,6 @@
        .byte 0x0f, 0x1e, 0x04, 0x59
        .byte 0x0f, 0x1f, 0x04, 0x59
 
-       nop (%rax) 
        nop %rax
        nop %eax
        nop %ax
@@ -54,7 +53,6 @@
        nopq %rax
        nopl %eax
        nopw %ax
-       nop (%r10) 
        nop %r10
        nop %r10d
        nop %r10w

diff --git a/gas/testsuite/gas/i386/x86-64-opcode.d b/gas/testsuite/gas/i386/x86-64-opcode.d
index 70e40307f0b5c9489ea98722ed0234ba41b5ca10..8ff12a5ff58f6c6dc259548a51396554b5d85f56 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-opcode.d
+++ b/gas/testsuite/gas/i386/x86-64-opcode.d
@@ -321,6 +321,7 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    0f 00 08                str    \(%rax\)
 [      ]*[a-f0-9]+:    0f 05                   syscall 
 [      ]*[a-f0-9]+:    0f 07                   sysret 
+[      ]*[a-f0-9]+:    48 0f 07                sysretq *
 [      ]*[a-f0-9]+:    0f 01 f8                swapgs 
 [      ]*[a-f0-9]+:    66 68 22 22             pushw  \$0x2222
 [      ]*[a-f0-9]+:    f6 c9 01                test   \$(0x)?0*1,%cl

diff --git a/gas/testsuite/gas/i386/x86-64-opcode.s b/gas/testsuite/gas/i386/x86-64-opcode.s
index f066e613bd3c9e71a18f97c20b666d6a20c4b183..fb322e2b70122dd98382a06bc1bae8f27fa367cf 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-opcode.s
+++ b/gas/testsuite/gas/i386/x86-64-opcode.s
@@ -189,48 +189,48 @@
        CVTTSS2SIq %xmm0,%r8          #  --  --  F3 4C   0f 2c c0                        ; OVR 128-bit media instruction override Result is sign extended                          REX for 64-bit operand size                 REX to access upper reg.
 
         # CVTSI2SS
-       CVTSI2SS  (%r8),%xmm0         #  --  --  F3 41   0f 2a 00                        ; OVR 128-bit media instruction override REX to access upper reg.
-       CVTSI2SS  (%rax),%xmm0        #  --  --  F3 --   0f 2a 00        ; OVR 128-bit media instruction override
-       CVTSI2SS  (%r8),%xmm15        #  --  --  F3 45   0f 2a 38                        ; OVR 128-bit media instruction override REX to access upper XMM reg            REX to access upper reg.
-       CVTSI2SS  (%rax),%xmm15       #  --  --  F3 44   0f 2a 38                        ; OVR 128-bit media instruction override REX to access upper XMM reg
-       CVTSI2SS  (%r8),%xmm8         #  --  --  F3 45   0f 2a 00                        ; OVR 128-bit media instruction override REX to access upper XMM reg            REX to access upper reg.
-       CVTSI2SS  (%rax),%xmm8        #  --  --  F3 44   0f 2a 00                        ; OVR 128-bit media instruction override REX to access upper XMM reg
-       CVTSI2SS  (%r8),%xmm7         #  --  --  F3 41   0f 2a 38                        ; OVR 128-bit media instruction override REX to access upper reg.
-       CVTSI2SS  (%rax),%xmm7        #  --  --  F3 --   0f 2a 38                        ; OVR 128-bit media instruction override
+       CVTSI2SSl (%r8),%xmm0         #  --  --  F3 41   0f 2a 00                        ; OVR 128-bit media instruction override REX to access upper reg.
+       CVTSI2SSl (%rax),%xmm0        #  --  --  F3 --   0f 2a 00        ; OVR 128-bit media instruction override
+       CVTSI2SSl (%r8),%xmm15        #  --  --  F3 45   0f 2a 38                        ; OVR 128-bit media instruction override REX to access upper XMM reg            REX to access upper reg.
+       CVTSI2SSl (%rax),%xmm15       #  --  --  F3 44   0f 2a 38                        ; OVR 128-bit media instruction override REX to access upper XMM reg
+       CVTSI2SSl (%r8),%xmm8         #  --  --  F3 45   0f 2a 00                        ; OVR 128-bit media instruction override REX to access upper XMM reg            REX to access upper reg.
+       CVTSI2SSl (%rax),%xmm8        #  --  --  F3 44   0f 2a 00                        ; OVR 128-bit media instruction override REX to access upper XMM reg
+       CVTSI2SSl (%r8),%xmm7         #  --  --  F3 41   0f 2a 38                        ; OVR 128-bit media instruction override REX to access upper reg.
+       CVTSI2SSl (%rax),%xmm7        #  --  --  F3 --   0f 2a 38                        ; OVR 128-bit media instruction override
        CVTSI2SS  %eax,%xmm0          #  --  --  F3 --   0f 2a c0                        ; OVR 128-bit media instruction override
        CVTSI2SS  %eax,%xmm15         #  --  --  F3 44   0f 2a f8                        ; OVR 128-bit media instruction override REX to access upper XMM reg
        CVTSI2SS  %eax,%xmm8          #  --  --  F3 44   0f 2a c0                        ; OVR 128-bit media instruction override REX to access upper XMM reg
        CVTSI2SS  %eax,%xmm7          #  --  --  F3 --   0f 2a f8                        ; OVR 128-bit media instruction override
-       CVTSI2SS  (%r8),%xmm0         #  --  --  F3 41   0f 2a 00                        ; OVR 128-bit media instruction override REX to access upper reg.
-       CVTSI2SS  (%rax),%xmm0        #  --  --  F3 --   0f 2a 00                        ; OVR 128-bit media instruction override
-       CVTSI2SS  (%r8),%xmm15        #  --  --  F3 45   0f 2a 38                        ; OVR 128-bit media instruction override REX to access upper XMM reg            REX to access upper reg.
-       CVTSI2SS  (%rax),%xmm15       #  --  --  F3 44   0f 2a 38                        ; OVR 128-bit media instruction override REX to access upper XMM reg
-       CVTSI2SS  (%r8),%xmm8         #  --  --  F3 45   0f 2a 00                        ; OVR 128-bit media instruction override REX to access upper XMM reg            REX to access upper reg.
-       CVTSI2SS  (%rax),%xmm8        #  --  --  F3 44   0f 2a 00                        ; OVR 128-bit media instruction override REX to access upper XMM reg
-       CVTSI2SS  (%r8),%xmm7         #  --  --  F3 41   0f 2a 38                        ; OVR 128-bit media instruction override REX to access upper reg.
-       CVTSI2SS  (%rax),%xmm7        #  --  --  F3 --   0f 2a 38                        ; OVR 128-bit media instruction override
+       CVTSI2SSl (%r8),%xmm0         #  --  --  F3 41   0f 2a 00                        ; OVR 128-bit media instruction override REX to access upper reg.
+       CVTSI2SSl (%rax),%xmm0        #  --  --  F3 --   0f 2a 00                        ; OVR 128-bit media instruction override
+       CVTSI2SSl (%r8),%xmm15        #  --  --  F3 45   0f 2a 38                        ; OVR 128-bit media instruction override REX to access upper XMM reg            REX to access upper reg.
+       CVTSI2SSl (%rax),%xmm15       #  --  --  F3 44   0f 2a 38                        ; OVR 128-bit media instruction override REX to access upper XMM reg
+       CVTSI2SSl (%r8),%xmm8         #  --  --  F3 45   0f 2a 00                        ; OVR 128-bit media instruction override REX to access upper XMM reg            REX to access upper reg.
+       CVTSI2SSl (%rax),%xmm8        #  --  --  F3 44   0f 2a 00                        ; OVR 128-bit media instruction override REX to access upper XMM reg
+       CVTSI2SSl (%r8),%xmm7         #  --  --  F3 41   0f 2a 38                        ; OVR 128-bit media instruction override REX to access upper reg.
+       CVTSI2SSl (%rax),%xmm7        #  --  --  F3 --   0f 2a 38                        ; OVR 128-bit media instruction override
 
         # CVTSI2SD
-       CVTSI2SD  (%r8),%xmm0         #  --  --  F2 41   0F 2A 00                        ; REX to access upper reg. OVR 128bit MMinstr.
-       CVTSI2SD  (%rax),%xmm0        #  --  --  F2 --   0F 2A 00                        ; OVR 128bit MMinstr.
-       CVTSI2SD  (%r8),%xmm15        #  --  --  F2 45   0F 2A 38                        ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
-       CVTSI2SD  (%rax),%xmm15       #  --  --  F2 44   0F 2A 38                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
-       CVTSI2SD  (%r8),%xmm8         #  --  --  F2 45   0F 2A 00                        ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
-       CVTSI2SD  (%rax),%xmm8        #  --  --  F2 44   0F 2A 00                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
-       CVTSI2SD  (%r8),%xmm7         #  --  --  F2 41   0F 2A 38                        ; REX to access upper reg. OVR 128bit MMinstr.
-       CVTSI2SD  (%rax),%xmm7        #  --  --  F2 --   0F 2A 38                        ; OVR 128bit MMinstr.
+       CVTSI2SDl (%r8),%xmm0         #  --  --  F2 41   0F 2A 00                        ; REX to access upper reg. OVR 128bit MMinstr.
+       CVTSI2SDl (%rax),%xmm0        #  --  --  F2 --   0F 2A 00                        ; OVR 128bit MMinstr.
+       CVTSI2SDl (%r8),%xmm15        #  --  --  F2 45   0F 2A 38                        ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
+       CVTSI2SDl (%rax),%xmm15       #  --  --  F2 44   0F 2A 38                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       CVTSI2SDl (%r8),%xmm8         #  --  --  F2 45   0F 2A 00                        ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
+       CVTSI2SDl (%rax),%xmm8        #  --  --  F2 44   0F 2A 00                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       CVTSI2SDl (%r8),%xmm7         #  --  --  F2 41   0F 2A 38                        ; REX to access upper reg. OVR 128bit MMinstr.
+       CVTSI2SDl (%rax),%xmm7        #  --  --  F2 --   0F 2A 38                        ; OVR 128bit MMinstr.
        CVTSI2SD  %eax,%xmm0          #  --  --  F2 --   0F 2A C0                        ; OVR 128bit MMinstr.
        CVTSI2SD  %eax,%xmm15         #  --  --  F2 44   0F 2A F8                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
        CVTSI2SD  %eax,%xmm8          #  --  --  F2 44   0F 2A C0                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
        CVTSI2SD  %eax,%xmm7          #  --  --  F2 --   0F 2A F8                        ; OVR 128bit MMinstr.
-       CVTSI2SD  (%r8),%xmm0         #  --  --  F2 41   0F 2A 00                        ; REX to access upper reg. OVR 128bit MMinstr.
-       CVTSI2SD  (%rax),%xmm0        #  --  --  F2 --   0F 2A 00                        ; OVR 128bit MMinstr.
-       CVTSI2SD  (%r8),%xmm15        #  --  --  F2 45   0F 2A 38                        ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
-       CVTSI2SD  (%rax),%xmm15       #  --  --  F2 44   0F 2A 38                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
-       CVTSI2SD  (%r8),%xmm8         #  --  --  F2 45   0F 2A 00                        ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
-       CVTSI2SD  (%rax),%xmm8        #  --  --  F2 44   0F 2A 00                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
-       CVTSI2SD  (%r8),%xmm7         #  --  --  F2 41   0F 2A 38                        ; REX to access upper reg. OVR 128bit MMinstr.
-       CVTSI2SD  (%rax),%xmm7        #  --  --  F2 --   0F 2A 38                        ; OVR 128bit MMinstr.
+       CVTSI2SDl (%r8),%xmm0         #  --  --  F2 41   0F 2A 00                        ; REX to access upper reg. OVR 128bit MMinstr.
+       CVTSI2SDl (%rax),%xmm0        #  --  --  F2 --   0F 2A 00                        ; OVR 128bit MMinstr.
+       CVTSI2SDl (%r8),%xmm15        #  --  --  F2 45   0F 2A 38                        ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
+       CVTSI2SDl (%rax),%xmm15       #  --  --  F2 44   0F 2A 38                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       CVTSI2SDl (%r8),%xmm8         #  --  --  F2 45   0F 2A 00                        ; REX to access upper XMM reg. REX to access upper reg. OVR 128bit MMinstr.
+       CVTSI2SDl (%rax),%xmm8        #  --  --  F2 44   0F 2A 00                        ; REX to access upper XMM reg. OVR 128bit MMinstr.
+       CVTSI2SDl (%r8),%xmm7         #  --  --  F2 41   0F 2A 38                        ; REX to access upper reg. OVR 128bit MMinstr.
+       CVTSI2SDl (%rax),%xmm7        #  --  --  F2 --   0F 2A 38                        ; OVR 128bit MMinstr.
 
        # MOVD
        MOVD (%r8),%xmm0              #  --  --  66 41   0F 6E 00                        ; REX to access upper reg. Data128 = ZEXT(Data32). OVR 128bit MMinstr.
@@ -446,7 +446,8 @@
         str (%rax)                   #  --  --  -- --   0F 00 08
 
         syscall                              #  --  --  -- --   0F 05
-        sysret                       #  --  --  -- --   0F 07
+        sysretl                              #  --  --  -- --   0F 07
+        sysretq                              #  --  --  -- 48   0F 07
 
         swapgs                       #  --  --  -- --   0F 01 f8
 

diff --git a/gas/testsuite/gas/i386/x86-64-ptwrite-intel.d b/gas/testsuite/gas/i386/x86-64-ptwrite-intel.d
index 37e79459f71780709c558529a29d43de8097e079..74d5a4c12db49abc0539d9b74ed6198eff15870b 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-ptwrite-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-ptwrite-intel.d
@@ -14,7 +14,6 @@ Disassembly of section \.text:
  +[a-f0-9]+:   f3 48 0f ae e1          ptwrite rcx
  +[a-f0-9]+:   f3 48 0f ae e1          ptwrite rcx
  +[a-f0-9]+:   f3 0f ae 21             ptwrite DWORD PTR \[rcx\]
- +[a-f0-9]+:   f3 0f ae 21             ptwrite DWORD PTR \[rcx\]
  +[a-f0-9]+:   f3 48 0f ae 21          ptwrite QWORD PTR \[rcx\]
  +[a-f0-9]+:   f3 0f ae e1             ptwrite ecx
  +[a-f0-9]+:   f3 48 0f ae e1          ptwrite rcx

diff --git a/gas/testsuite/gas/i386/x86-64-ptwrite.d b/gas/testsuite/gas/i386/x86-64-ptwrite.d
index 75183b0f9eb736f53956105dc6c0916bffbba8a7..fd5ce7d002d5ce6699f2d53d6ce8a9af6f01aa24 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-ptwrite.d
+++ b/gas/testsuite/gas/i386/x86-64-ptwrite.d
@@ -14,7 +14,6 @@ Disassembly of section \.text:
  +[a-f0-9]+:   f3 48 0f ae e1          ptwrite %rcx
  +[a-f0-9]+:   f3 48 0f ae e1          ptwrite %rcx
  +[a-f0-9]+:   f3 0f ae 21             ptwritel \(%rcx\)
- +[a-f0-9]+:   f3 0f ae 21             ptwritel \(%rcx\)
  +[a-f0-9]+:   f3 48 0f ae 21          ptwriteq \(%rcx\)
  +[a-f0-9]+:   f3 0f ae e1             ptwrite %ecx
  +[a-f0-9]+:   f3 48 0f ae e1          ptwrite %rcx

diff --git a/gas/testsuite/gas/i386/x86-64-ptwrite.s b/gas/testsuite/gas/i386/x86-64-ptwrite.s
index 2e62b3b3fcabccfc0d5fb7d4d77b9daca8cf5ddd..b516f3054a2a268174a6ca069466f121126fc73f 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-ptwrite.s
+++ b/gas/testsuite/gas/i386/x86-64-ptwrite.s
@@ -6,7 +6,6 @@ _start:
        ptwritel %ecx
        ptwrite %rcx
        ptwriteq %rcx
-       ptwrite (%rcx)
        ptwritel (%rcx)
        ptwriteq (%rcx)
 

diff --git a/gas/testsuite/gas/i386/x86-64-simd-intel.d b/gas/testsuite/gas/i386/x86-64-simd-intel.d
index 9522e3d8b2ed12d83a996823ce018bd45ce2205e..9ec34ed4620cd0890c8b4865342104d6a6ffa817 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-simd-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-simd-intel.d
@@ -25,8 +25,6 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    f2 48 0f 2a c8          cvtsi2sd xmm1,rax
 [      ]*[a-f0-9]+:    f3 0f 2a 08             cvtsi2ss xmm1,DWORD PTR \[rax\]
 [      ]*[a-f0-9]+:    f2 0f 2a 08             cvtsi2sd xmm1,DWORD PTR \[rax\]
-[      ]*[a-f0-9]+:    f3 0f 2a 08             cvtsi2ss xmm1,DWORD PTR \[rax\]
-[      ]*[a-f0-9]+:    f2 0f 2a 08             cvtsi2sd xmm1,DWORD PTR \[rax\]
 [      ]*[a-f0-9]+:    f3 48 0f 2a 08          cvtsi2ss xmm1,QWORD PTR \[rax\]
 [      ]*[a-f0-9]+:    f2 48 0f 2a 08          cvtsi2sd xmm1,QWORD PTR \[rax\]
 [      ]*[a-f0-9]+:    f2 0f 7c 0d 78 56 34 12         haddps xmm1,XMMWORD PTR \[rip\+0x12345678\]        # [0-9a-f]+ <_start\+0x[0-9a-f]+>

diff --git a/gas/testsuite/gas/i386/x86-64-simd-suffix.d b/gas/testsuite/gas/i386/x86-64-simd-suffix.d
index 9841b32d846c6c4ea626b59ecf752a46d31f49f2..e52de1be5951c9ef108b80d3ec22302303843394 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-simd-suffix.d
+++ b/gas/testsuite/gas/i386/x86-64-simd-suffix.d
@@ -25,8 +25,6 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    f2 48 0f 2a c8          cvtsi2sdq %rax,%xmm1
 [      ]*[a-f0-9]+:    f3 0f 2a 08             cvtsi2ssl \(%rax\),%xmm1
 [      ]*[a-f0-9]+:    f2 0f 2a 08             cvtsi2sdl \(%rax\),%xmm1
-[      ]*[a-f0-9]+:    f3 0f 2a 08             cvtsi2ssl \(%rax\),%xmm1
-[      ]*[a-f0-9]+:    f2 0f 2a 08             cvtsi2sdl \(%rax\),%xmm1
 [      ]*[a-f0-9]+:    f3 48 0f 2a 08          cvtsi2ssq \(%rax\),%xmm1
 [      ]*[a-f0-9]+:    f2 48 0f 2a 08          cvtsi2sdq \(%rax\),%xmm1
 [      ]*[a-f0-9]+:    f2 0f 7c 0d 78 56 34 12         haddps 0x12345678\(%rip\),%xmm1        # [0-9a-f]+ <_start\+0x[0-9a-f]+>

diff --git a/gas/testsuite/gas/i386/x86-64-simd.d b/gas/testsuite/gas/i386/x86-64-simd.d
index 3b8781bc8f2dad2d67175590893c2497581f8a5a..e93950a7d7357f8077e983faf4d5c81181d10238 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-simd.d
+++ b/gas/testsuite/gas/i386/x86-64-simd.d
@@ -24,8 +24,6 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    f2 48 0f 2a c8          cvtsi2sd %rax,%xmm1
 [      ]*[a-f0-9]+:    f3 0f 2a 08             cvtsi2ssl \(%rax\),%xmm1
 [      ]*[a-f0-9]+:    f2 0f 2a 08             cvtsi2sdl \(%rax\),%xmm1
-[      ]*[a-f0-9]+:    f3 0f 2a 08             cvtsi2ssl \(%rax\),%xmm1
-[      ]*[a-f0-9]+:    f2 0f 2a 08             cvtsi2sdl \(%rax\),%xmm1
 [      ]*[a-f0-9]+:    f3 48 0f 2a 08          cvtsi2ssq \(%rax\),%xmm1
 [      ]*[a-f0-9]+:    f2 48 0f 2a 08          cvtsi2sdq \(%rax\),%xmm1
 [      ]*[a-f0-9]+:    f2 0f 7c 0d 78 56 34 12         haddps 0x12345678\(%rip\),%xmm1        # [0-9a-f]+ <_start\+0x[0-9a-f]+>

diff --git a/gas/testsuite/gas/i386/x86-64-simd.s b/gas/testsuite/gas/i386/x86-64-simd.s
index 2b44a4e636d37fe26fff92fc45d696b46c0ffadd..d74cb119ae92403a76b08e62adc13d3fb52b8952 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-simd.s
+++ b/gas/testsuite/gas/i386/x86-64-simd.s
@@ -15,8 +15,6 @@ _start:
        cvtsi2sd %rax, %xmm1
        cvtsi2ssq %rax, %xmm1
        cvtsi2sdq %rax, %xmm1
-       cvtsi2ss (%rax), %xmm1
-       cvtsi2sd (%rax), %xmm1
        cvtsi2ssl (%rax), %xmm1
        cvtsi2sdl (%rax), %xmm1
        cvtsi2ssq (%rax), %xmm1

diff --git a/gas/testsuite/gas/i386/x86-64-sse-noavx.d b/gas/testsuite/gas/i386/x86-64-sse-noavx.d
index e15791642a7f940ffedde70889114a1632e3941b..c83dae5a4ae59ad282490395893c058a0ff8448e 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-sse-noavx.d
+++ b/gas/testsuite/gas/i386/x86-64-sse-noavx.d
@@ -16,7 +16,6 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    66 0f 2c dc             cvttpd2pi %xmm4,%mm3
 [      ]*[a-f0-9]+:    0f 2c dc                cvttps2pi %xmm4,%mm3
 [      ]*[a-f0-9]+:    df 08                   fisttps \(%rax\)
-[      ]*[a-f0-9]+:    df 08                   fisttps \(%rax\)
 [      ]*[a-f0-9]+:    db 08                   fisttpl \(%rax\)
 [      ]*[a-f0-9]+:    dd 08                   fisttpll \(%rax\)
 [      ]*[a-f0-9]+:    0f ae e8                lfence 

diff --git a/gas/testsuite/gas/i386/x86-64-sse-noavx.s b/gas/testsuite/gas/i386/x86-64-sse-noavx.s
index f1795ea5c165a6341b5bd60977cdadf1dc88fb8d..3e0c31a2098d33f354b544c27d4b3891ba2afe87 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-sse-noavx.s
+++ b/gas/testsuite/gas/i386/x86-64-sse-noavx.s
@@ -10,7 +10,6 @@ _start:
  cvtps2pi      %xmm7,%mm6
  cvttpd2pi     %xmm4,%mm3
  cvttps2pi     %xmm4,%mm3
- fisttp (%rax)
  fisttps (%rax)
  fisttpl (%rax)
  fisttpll (%rax)

diff --git a/gas/testsuite/gas/i386/x86-64-sse2avx.s b/gas/testsuite/gas/i386/x86-64-sse2avx.s
index 92da305f190cc4ba97fe632aeb949df2902cef41..08d1b250f3622abf008927a8f7c1990935b92c2e 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-sse2avx.s
+++ b/gas/testsuite/gas/i386/x86-64-sse2avx.s
@@ -720,9 +720,9 @@ _start:
 
 # Tests for op regl/mem32, xmm[, xmm]
        cvtsi2sd %ecx,%xmm4
-       cvtsi2sd (%rcx),%xmm4
+       cvtsi2sdl (%rcx),%xmm4
        cvtsi2ss %ecx,%xmm4
-       cvtsi2ss (%rcx),%xmm4
+       cvtsi2ssl (%rcx),%xmm4
 
 # Tests for op imm8, xmm/mem32, xmm[, xmm]
        cmpss $100,%xmm4,%xmm6

diff --git a/gas/testsuite/gas/i386/x86-64-sse3.s b/gas/testsuite/gas/i386/x86-64-sse3.s
index 60122832f54a3395048c5aa4a4471c2d4aabf636..2b9ecf52bebc3ebfdff60f4963aec58b0f80e9b0 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-sse3.s
+++ b/gas/testsuite/gas/i386/x86-64-sse3.s
@@ -6,7 +6,7 @@ foo:
        addsubpd        %xmm2,%xmm1
        addsubps        (%rbx),%xmm2
        addsubps        %xmm4,%xmm3
-       fisttp          0x909090(%rax)
+       fisttps         0x909090(%rax)
        fisttpl         0x909090(%rax)
        fisttpll        0x909090(%rax)
        haddpd          0x0(%rbp),%xmm4

diff --git a/gas/testsuite/gas/i386/x86-64-suffix-intel.d b/gas/testsuite/gas/i386/x86-64-suffix-intel.d
index 32fcb19f46caefef8d10e30859049b3b997811f3..358777ec20660a9407af2d558dcbf3e89628d6cb 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-suffix-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-suffix-intel.d
@@ -18,13 +18,11 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    cf                      iretd  
 [      ]*[a-f0-9]+:    48 cf                   iretq  
 [      ]*[a-f0-9]+:    0f 07                   sysretd 
-[      ]*[a-f0-9]+:    0f 07                   sysretd 
 [      ]*[a-f0-9]+:    48 0f 07                sysretq 
 [      ]*[a-f0-9]+:    66 cf                   iretw  
 [      ]*[a-f0-9]+:    cf                      iretd  
 [      ]*[a-f0-9]+:    cf                      iretd  
 [      ]*[a-f0-9]+:    48 cf                   iretq  
 [      ]*[a-f0-9]+:    0f 07                   sysretd 
-[      ]*[a-f0-9]+:    0f 07                   sysretd 
 [      ]*[a-f0-9]+:    48 0f 07                sysretq 
 #pass

diff --git a/gas/testsuite/gas/i386/x86-64-suffix.d b/gas/testsuite/gas/i386/x86-64-suffix.d
index 749a300ff9ae7b8bbc1ce66a08c21028b5aad6f6..60dd5517335466afde60e3f3af2163d3825eab5a 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-suffix.d
+++ b/gas/testsuite/gas/i386/x86-64-suffix.d
@@ -17,13 +17,11 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    cf                      iretl  
 [      ]*[a-f0-9]+:    48 cf                   iretq  
 [      ]*[a-f0-9]+:    0f 07                   sysretl 
-[      ]*[a-f0-9]+:    0f 07                   sysretl 
 [      ]*[a-f0-9]+:    48 0f 07                sysretq 
 [      ]*[a-f0-9]+:    66 cf                   iretw  
 [      ]*[a-f0-9]+:    cf                      iretl  
 [      ]*[a-f0-9]+:    cf                      iretl  
 [      ]*[a-f0-9]+:    48 cf                   iretq  
 [      ]*[a-f0-9]+:    0f 07                   sysretl 
-[      ]*[a-f0-9]+:    0f 07                   sysretl 
 [      ]*[a-f0-9]+:    48 0f 07                sysretq 
 #pass

diff --git a/gas/testsuite/gas/i386/x86-64-suffix.s b/gas/testsuite/gas/i386/x86-64-suffix.s
index d5838217146695bfe8657dab07b4b6143d7f25ee..818edf59e987a73591730800891b88ea701d7f3b 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-suffix.s
+++ b/gas/testsuite/gas/i386/x86-64-suffix.s
@@ -15,7 +15,6 @@ foo:
        iret
        iretq
        sysretl
-       sysret
        sysretq
 
        .intel_syntax noprefix
@@ -24,5 +23,4 @@ foo:
        iret
        iretq
        sysretd
-       sysret
        sysretq

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index d02f133eac56ff9c527bc2c6bae707e326c6c3eb..49977e74009c9d464835acda402afd3ba2294e5a 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2020-01-21  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-opc.tbl (sysret): Drop DefaultSize.
+       * i386-tbl.h: Re-generate.
+
 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 
        * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 2396955a910468fc1a5f414617a5e737c5774185..2acb76bfa151d6d2e0905b10af5fe033c9eb09b7 100644 (file)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2809,7 +2809,7 @@ pswapd, 2, 0xf0f, 0xbb, 2, Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|N
 
 // AMD extensions.
 syscall, 0, 0xf05, None, 2, CpuSYSCALL, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
-sysret, 0, 0xf07, None, 2, CpuSYSCALL, DefaultSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 }
+sysret, 0, 0xf07, None, 2, CpuSYSCALL, No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { 0 }
 swapgs, 0, 0xf01f8, None, 3, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 rdtscp, 0, 0xf01f9, None, 3, CpuRdtscp, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 

diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 3bdfb415ac530f7eef18892de6da2e85cad4cb7d..c8fa7e95a0063854c3b34c7fb807309080522850 100644 (file)
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -46661,7 +46661,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0,
+    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,