config SPI_OMAP24XX
tristate "McSPI driver for OMAP"
depends on HAS_DMA
----- depends on ARM || ARM64 || AVR32 || HEXAGON || MIPS || SUPERH
depends on ARCH_OMAP2PLUS || COMPILE_TEST
help
SPI master controller for OMAP24XX and later Multichannel SPI
config SPI_ORION
tristate "Orion SPI master"
----- depends on PLAT_ORION || COMPILE_TEST
+++++ depends on PLAT_ORION || ARCH_MVEBU || COMPILE_TEST
help
This enables using the SPI master controller on the Orion chips.
+++++config SPI_PIC32
+++++ tristate "Microchip PIC32 series SPI"
+++++ depends on MACH_PIC32 || COMPILE_TEST
+++++ help
+++++ SPI driver for Microchip PIC32 SPI master controller.
+++++
+++++config SPI_PIC32_SQI
+++++ tristate "Microchip PIC32 Quad SPI driver"
+++++ depends on MACH_PIC32 || COMPILE_TEST
+++++ depends on HAS_DMA
+++++ help
+++++ SPI driver for PIC32 Quad SPI controller.
+++++
config SPI_PL022
tristate "ARM AMBA PL022 SSP controller"
depends on ARM_AMBA
config SPI_ROCKCHIP
tristate "Rockchip SPI controller driver"
----- depends on ARM || ARM64 || AVR32 || HEXAGON || MIPS || SUPERH
help
This selects a driver for Rockchip SPI controller.
config SPI_ST_SSC4
tristate "STMicroelectronics SPI SSC-based driver"
---- - depends on ARCH_STI
++++ + depends on ARCH_STI || COMPILE_TEST
help
STMicroelectronics SoCs support for SPI. If you say yes to
this option, support will be included for the SSC driven SPI.
config SPI_XLP
tristate "Netlogic XLP SPI controller driver"
----- depends on CPU_XLP || COMPILE_TEST
+++++ depends on CPU_XLP || ARCH_VULCAN || COMPILE_TEST
help
Enable support for the SPI controller on the Netlogic XLP SoCs.
Currently supported XLP variants are XLP8XX, XLP3XX, XLP2XX, XLP9XX
.reg_general = -1,
.reg_ssp = 0x20,
.reg_cs_ctrl = 0x24,
----- .reg_capabilities = 0xfc,
+++++ .reg_capabilities = -1,
.rx_threshold = 1,
.tx_threshold_lo = 32,
.tx_threshold_hi = 56,
/* see if the next and current messages point
* to the same chip
*/
- ---- if (next_msg && next_msg->spi != msg->spi)
- ---- next_msg = NULL;
- ---- if (!next_msg || msg->state == ERROR_STATE)
+ ++++ if ((next_msg && next_msg->spi != msg->spi) ||
+ ++++ msg->state == ERROR_STATE)
cs_deassert(drv_data);
}
u32 dma_thresh = drv_data->cur_chip->dma_threshold;
u32 dma_burst = drv_data->cur_chip->dma_burst_size;
u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
+ ++++ int err;
/* Get current state information */
message = drv_data->cur_msg;
/* Ensure we have the correct interrupt handler */
drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
- ---- pxa2xx_spi_dma_prepare(drv_data, dma_burst);
+ ++++ err = pxa2xx_spi_dma_prepare(drv_data, dma_burst);
+ ++++ if (err) {
+ ++++ message->status = err;
+ ++++ giveback(drv_data);
+ ++++ return;
+ ++++ }
/* Clear status and start DMA engine */
cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
drv_data->pdev = pdev;
drv_data->ssp = ssp;
----- master->dev.parent = &pdev->dev;
master->dev.of_node = pdev->dev.of_node;
/* the spi->mode bits understood by this driver: */
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
master->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
master->auto_runtime_pm = true;
+ ++++ master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
drv_data->ssp_type = ssp->type;