/* BFD back-end for Renesas H8/300 COFF binaries.
Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
- 2000, 2001, 2002, 2003
+ 2000, 2001, 2002, 2003, 2004
Free Software Foundation, Inc.
Written by Steve Chamberlain, <sac@cygnus.com>.
bfd_vma value;
bfd_vma dot;
int gap, tmp;
+ unsigned char temp_code;
switch (reloc->howto->type)
{
if (data[dst_address - 2] != 0x6a)
abort ();
+ temp_code = data[src_address - 1];
+ if ((temp_code & 0x10) != 0x10)
+ temp_code &= 0xf0;
+
/* Fix up the opcode. */
- switch (data[src_address - 1] & 0xf0)
+ switch (temp_code)
{
case 0x00:
data[dst_address - 2] = (data[src_address - 1] & 0xf) | 0x20;
case 0x80:
data[dst_address - 2] = (data[src_address - 1] & 0xf) | 0x30;
break;
+ case 0x18:
+ data[dst_address - 2] = 0x7f;
+ break;
+ case 0x10:
+ data[dst_address - 2] = 0x7e;
+ break;
default:
abort ();
}
if (data[dst_address - 2] != 0x6a)
abort ();
+ temp_code = data[src_address - 1];
+ if ((temp_code & 0x30) != 0x30)
+ temp_code &= 0xf0;
+
/* Fix up the opcode. */
- switch (data[src_address - 1] & 0xf0)
+ switch (temp_code)
{
case 0x20:
data[dst_address - 2] = (data[src_address - 1] & 0xf) | 0x20;
case 0xa0:
data[dst_address - 2] = (data[src_address - 1] & 0xf) | 0x30;
break;
+ case 0x38:
+ data[dst_address - 2] = 0x7f;
+ break;
+ case 0x30:
+ data[dst_address - 2] = 0x7e;
+ break;
default:
abort ();
}
if (value >= 0xffffff00u)
{
unsigned char code;
+ unsigned char temp_code;
/* Note that we've changed the relocs, section contents,
etc. */
if (code != 0x6a)
abort ();
- code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
+ temp_code = code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
+ if ((temp_code & 0x10) != 0x10)
+ temp_code &= 0xf0;
- if ((code & 0xf0) == 0x00)
- bfd_put_8 (abfd,
- (code & 0xf) | 0x20,
- contents + irel->r_offset - 2);
- else if ((code & 0xf0) == 0x80)
- bfd_put_8 (abfd,
- (code & 0xf) | 0x30,
- contents + irel->r_offset - 2);
- else
- abort ();
+ switch (temp_code)
+ {
+ case 0x00:
+ bfd_put_8 (abfd, (code & 0xf) | 0x20,
+ contents + irel->r_offset - 2);
+ break;
+ case 0x80:
+ bfd_put_8 (abfd, (code & 0xf) | 0x30,
+ contents + irel->r_offset - 2);
+ break;
+ case 0x18:
+ bfd_put_8 (abfd, 0x7f, contents + irel->r_offset - 2);
+ break;
+ case 0x10:
+ bfd_put_8 (abfd, 0x7e, contents + irel->r_offset - 2);
+ break;
+ default:
+ abort ();
+ }
/* Fix the relocation's type. */
irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
if (value >= 0xffffff00u)
{
unsigned char code;
+ unsigned char temp_code;
/* Note that we've changed the relocs, section contents,
etc. */
if (code != 0x6a)
abort ();
- code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
+ temp_code = code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
+
+ if ((temp_code & 0x30) != 0x30)
+ temp_code &= 0xf0;
- switch (code & 0xf0)
+ switch (temp_code)
{
case 0x20:
bfd_put_8 (abfd, (code & 0xf) | 0x20,
bfd_put_8 (abfd, (code & 0xf) | 0x30,
contents + irel->r_offset - 2);
break;
+ case 0x38:
+ bfd_put_8 (abfd, 0x7f, contents + irel->r_offset - 2);
+ break;
+ case 0x30:
+ bfd_put_8 (abfd, 0x7e, contents + irel->r_offset - 2);
+ break;
default:
- abort ();
+ abort();
}
/* Fix the relocation's type. */
}
}
- /* FALLTHRU */
+ /* Fall through. */
/* This is a 24/32bit absolute address in a "mov" insn, which may
become a 16-bit absolute address if it is in the right range. */
+2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
+
+ * config/tc-h8300.c (build_bytes): Apply relaxation to bit
+ manipulation insns.
+
2004-01-12 Richard Sandiford <rsandifo@redhat.com>
* config/tc-mips.c (macro_build_jalr): When adding an R_MIPS_JALR
/* tc-h8300.c -- Assemble code for the Renesas H8/300
Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000,
- 2001, 2002, 2003 Free Software Foundation, Inc.
+ 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
for (i = 0; i < this_try->length; i++)
output[i] = (asnibbles[i * 2] << 4) | asnibbles[i * 2 + 1];
- /* Note if this is a movb instruction -- there's a special relaxation
- which only applies to them. */
- if (this_try->opcode->how == O (O_MOV, SB))
+ /* Note if this is a movb or a bit manipulation instruction
+ there is a special relaxation which only applies. */
+ if ( this_try->opcode->how == O (O_MOV, SB)
+ || this_try->opcode->how == O (O_BCLR, SB)
+ || this_try->opcode->how == O (O_BAND, SB)
+ || this_try->opcode->how == O (O_BIAND, SB)
+ || this_try->opcode->how == O (O_BILD, SB)
+ || this_try->opcode->how == O (O_BIOR, SB)
+ || this_try->opcode->how == O (O_BIST, SB)
+ || this_try->opcode->how == O (O_BIXOR, SB)
+ || this_try->opcode->how == O (O_BLD, SB)
+ || this_try->opcode->how == O (O_BNOT, SB)
+ || this_try->opcode->how == O (O_BOR, SB)
+ || this_try->opcode->how == O (O_BSET, SB)
+ || this_try->opcode->how == O (O_BST, SB)
+ || this_try->opcode->how == O (O_BTST, SB)
+ || this_try->opcode->how == O (O_BXOR, SB))
movb = 1;
/* Output any fixes. */
+2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
+
+ * h8300.h (BITOP): Pass MEMRELAX flag.
+
2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
* h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
{code, AV_H8, 2, name, {{imm, RD8, E}}, {{op00, op01, imm, RD8, E}}}, \
{code, AV_H8, 6, name, {{imm, RDIND, E}}, {{op10, op11, B30 | RDIND, 0, op00, op01, imm, 0, E}}}, \
{code, AV_H8, 6, name, {{imm, ABS8DST, E}}, {{op20, op21, DSTABS8LIST, op00, op01, imm, 0, E}}}, \
- {code, AV_H8S, 6, name, {{imm, ABS16DST, E}}, {{0x6, 0xa, 0x1, op30, DST | ABS16LIST, op00, op01, imm, op4, E}}}, \
- {code, AV_H8S, 6, name, {{imm, ABS32DST, E}}, {{0x6, 0xa, 0x3, op30, DST | ABS32LIST, op00, op01, imm, op4, E}}}
+ {code, AV_H8S, 6, name, {{imm, ABS16DST, E}}, {{0x6, 0xa, 0x1, op30, DST | MEMRELAX | ABS16LIST , op00, op01, imm, op4, E}}}, \
+ {code, AV_H8S, 6, name, {{imm, ABS32DST, E}}, {{0x6, 0xa, 0x3, op30, DST | MEMRELAX | ABS32LIST , op00, op01, imm, op4, E}}}
#define BITOP_B(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \
{code, AV_H8SX, 0, name, {{imm, RDIND, E}}, {{op10, op11, B30 | RDIND, 0, op00, op01, imm, op4, E}}}, \
+2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
+
+ * ld-h8300/h8300-exp: Run the relax-4 test.
+ * ld-h8300/relax-4.s: New file: Source for relax-4 test.
+ * ld-h8300/relax-4.d: New file: Expected output and commands for
+ assembling and linking the relax-4 test.
+ * ld-h8300/relax-4-coff.d: New file: Variant for the COFF based
+ toolchain.
+
2004-01-09 H.J. Lu <hongjiu.lu@intel.com>
* ld-selective/selective.exp: Skip ia64-*-*.
# Expect script for ld-h8300 tests
-# Copyright 2002, 2003 Free Software Foundation, Inc.
+# Copyright 2002, 2003, 2004 Free Software Foundation, Inc.
#
# This file is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
if {[istarget *-elf]} {
run_dump_test relax-2
run_dump_test relax-3
+ run_dump_test relax-4
} else {
run_dump_test relax-3-coff
+ run_dump_test relax-4-coff
}
--- /dev/null
+# name: H8300 Relaxation Test 4
+# source: relax-4.s
+# ld: --relax -m h8300s
+# objdump: -d --no-show-raw-insn
+
+.*: file format .*-h8300
+
+Disassembly of section .text:
+
+00000100 <_start>:
+ 100: f8 03 mov.b #0x3,r0l
+ 102: fa 05 mov.b #0x5,r2l
+ 104: 7f ff 60 80 bset r0l,@0xff:8
+ 108: 7f 00 60 a0 bset r2l,@0x0:8
+ 10c: 7e ff 63 a0 btst r2l,@0xff:8
+ 110: 7e 00 63 80 btst r0l,@0x0:8
+ 114: 6a 18 00 00 70 50 bset #0x5,@0x0:16
+ 11a: 6a 18 7f ff 70 50 bset #0x5,@0x7fff:16
+ 120: 6a 18 80 00 70 50 bset #0x5,@0x8000:16
+ 126: 6a 18 fe ff 70 50 bset #0x5,@0xfeff:16
+ 12c: 7f 00 70 50 bset #0x5,@0x0:8
+ 130: 7f ff 70 50 bset #0x5,@0xff:8
+ 134: 6a 10 00 00 76 50 band #0x5,@0x0:16
+ 13a: 6a 10 7f ff 76 50 band #0x5,@0x7fff:16
+ 140: 6a 10 80 00 76 50 band #0x5,@0x8000:16
+ 146: 6a 10 fe ff 76 50 band #0x5,@0xfeff:16
+ 14c: 7e 00 76 50 band #0x5,@0x0:8
+ 150: 7e ff 76 50 band #0x5,@0xff:8
+ 154: 7f ff 60 a0 bset r2l,@0xff:8
+ 158: 7f 00 60 80 bset r0l,@0x0:8
+ 15c: 7e ff 63 80 btst r0l,@0xff:8
+ 160: 7e 00 63 a0 btst r2l,@0x0:8
+ 164: 6a 18 00 00 70 60 bset #0x6,@0x0:16
+ 16a: 6a 18 7f ff 70 60 bset #0x6,@0x7fff:16
+ 170: 6a 38 00 00 80 00 70 60 bset #0x6,@0x8000:32
+ 178: 6a 38 00 00 ff 00 70 60 bset #0x6,@0xff00:32
+ 180: 6a 38 00 ff ff 00 70 60 bset #0x6,@0xffff00:32
+ 188: 6a 38 ff ff 7f ff 70 60 bset #0x6,@0xffff7fff:32
+ 190: 6a 18 80 00 70 60 bset #0x6,@0x8000:16
+ 196: 6a 18 fe ff 70 60 bset #0x6,@0xfeff:16
+ 19c: 7f 00 70 60 bset #0x6,@0x0:8
+ 1a0: 7f ff 70 60 bset #0x6,@0xff:8
+ 1a4: 6a 10 00 00 76 60 band #0x6,@0x0:16
+ 1aa: 6a 10 7f ff 76 60 band #0x6,@0x7fff:16
+ 1b0: 6a 30 00 00 80 00 76 60 band #0x6,@0x8000:32
+ 1b8: 6a 30 00 00 ff 00 76 60 band #0x6,@0xff00:32
+ 1c0: 6a 30 00 ff ff 00 76 60 band #0x6,@0xffff00:32
+ 1c8: 6a 30 ff ff 7f ff 76 60 band #0x6,@0xffff7fff:32
+ 1d0: 6a 10 80 00 76 60 band #0x6,@0x8000:16
+ 1d6: 6a 10 fe ff 76 60 band #0x6,@0xfeff:16
+ 1dc: 7e 00 76 60 band #0x6,@0x0:8
+ 1e0: 7e ff 76 60 band #0x6,@0xff:8
--- /dev/null
+# name: H8300 Relaxation Test 4
+# ld: --relax -m h8300self
+# objdump: -d --no-show-raw-insn
+
+.*: file format .*-h8300
+
+Disassembly of section .text:
+
+00000100 <_start>:
+ 100: f8 03 mov.b #0x3,r0l
+ 102: fa 05 mov.b #0x5,r2l
+ 104: 7f ff 60 80 bset r0l,@0xff:8
+ 108: 7f 00 60 a0 bset r2l,@0x0:8
+ 10c: 7e ff 63 a0 btst r2l,@0xff:8
+ 110: 7e 00 63 80 btst r0l,@0x0:8
+ 114: 6a 18 00 00 70 50 bset #0x5,@0x0:16
+ 11a: 6a 18 7f ff 70 50 bset #0x5,@0x7fff:16
+ 120: 6a 18 80 00 70 50 bset #0x5,@0x8000:16
+ 126: 6a 18 fe ff 70 50 bset #0x5,@0xfeff:16
+ 12c: 7f 00 70 50 bset #0x5,@0x0:8
+ 130: 7f ff 70 50 bset #0x5,@0xff:8
+ 134: 6a 10 00 00 76 50 band #0x5,@0x0:16
+ 13a: 6a 10 7f ff 76 50 band #0x5,@0x7fff:16
+ 140: 6a 10 80 00 76 50 band #0x5,@0x8000:16
+ 146: 6a 10 fe ff 76 50 band #0x5,@0xfeff:16
+ 14c: 7e 00 76 50 band #0x5,@0x0:8
+ 150: 7e ff 76 50 band #0x5,@0xff:8
+ 154: 7f ff 60 a0 bset r2l,@0xff:8
+ 158: 7f 00 60 80 bset r0l,@0x0:8
+ 15c: 7e ff 63 80 btst r0l,@0xff:8
+ 160: 7e 00 63 a0 btst r2l,@0x0:8
+ 164: 6a 18 00 00 70 60 bset #0x6,@0x0:16
+ 16a: 6a 18 7f ff 70 60 bset #0x6,@0x7fff:16
+ 170: 6a 38 00 00 80 00 70 60 bset #0x6,@0x8000:32
+ 178: 6a 38 00 00 ff 00 70 60 bset #0x6,@0xff00:32
+ 180: 6a 38 00 ff ff 00 70 60 bset #0x6,@0xffff00:32
+ 188: 6a 38 ff ff 7f ff 70 60 bset #0x6,@0xffff7fff:32
+ 190: 6a 18 80 00 70 60 bset #0x6,@0x8000:16
+ 196: 6a 18 fe ff 70 60 bset #0x6,@0xfeff:16
+ 19c: 7f 00 70 60 bset #0x6,@0x0:8
+ 1a0: 7f ff 70 60 bset #0x6,@0xff:8
+ 1a4: 6a 10 00 00 76 60 band #0x6,@0x0:16
+ 1aa: 6a 10 7f ff 76 60 band #0x6,@0x7fff:16
+ 1b0: 6a 30 00 00 80 00 76 60 band #0x6,@0x8000:32
+ 1b8: 6a 30 00 00 ff 00 76 60 band #0x6,@0xff00:32
+ 1c0: 6a 30 00 ff ff 00 76 60 band #0x6,@0xffff00:32
+ 1c8: 6a 30 ff ff 7f ff 76 60 band #0x6,@0xffff7fff:32
+ 1d0: 6a 10 80 00 76 60 band #0x6,@0x8000:16
+ 1d6: 6a 10 fe ff 76 60 band #0x6,@0xfeff:16
+ 1dc: 7e 00 76 60 band #0x6,@0x0:8
+ 1e0: 7e ff 76 60 band #0x6,@0xff:8
--- /dev/null
+; Relaxation is possible for following bit manipulation instructions\r
+; BAND, BCLR, BIAND, BILD, BIOR, BIST, BIXOR, BLD, BNOT, BOR, BSET, BST, BTST, BXOR\r
+ .h8300s\r
+ .globl _start\r
+ _start:\r
+ # s3-s6 aren't valid 16-bit addresses.\r
+ mov.b #0x3,r0l\r
+ mov.b #0x5,r2l\r
+;\r
+; Relaxation of aa:16\r
+; \r
+ bset r0l,@s10:16\r
+ bset r2l,@s9:16\r
+ btst r2l,@s10:16\r
+ btst r0l,@s9:16\r
+ \r
+ bset #5,@s1:16\r
+ bset #5,@s2:16\r
+ bset #5,@s7:16\r
+ bset #5,@s8:16\r
+ bset #5,@s9:16\r
+ bset #5,@s10:16 \r
+ \r
+ band #5,@s1:16\r
+ band #5,@s2:16\r
+ band #5,@s7:16\r
+ band #5,@s8:16\r
+ band #5,@s9:16\r
+ band #5,@s10:16\r
+;\r
+; Relaxation of aa:32\r
+;\r
+ bset r2l,@s10:32\r
+ bset r0l,@s9:32\r
+ btst r0l,@s10:32\r
+ btst r2l,@s9:32\r
+ \r
+ bset #6,@s1:32\r
+ bset #6,@s2:32\r
+ bset #6,@s3:32\r
+ bset #6,@s4:32\r
+ bset #6,@s5:32\r
+ bset #6,@s6:32\r
+ bset #6,@s7:32\r
+ bset #6,@s8:32\r
+ bset #6,@s9:32\r
+ bset #6,@s10:32\r
+ \r
+ band #6,@s1:32\r
+ band #6,@s2:32\r
+ band #6,@s3:32\r
+ band #6,@s4:32\r
+ band #6,@s5:32\r
+ band #6,@s6:32\r
+ band #6,@s7:32\r
+ band #6,@s8:32\r
+ band #6,@s9:32\r
+ band #6,@s10:32\r
+ \r
+ .equ s1,0\r
+ .equ s2,0x7fff\r
+ .equ s3,0x8000\r
+ .equ s4,0xff00\r
+ .equ s5,0xffff00\r
+ .equ s6,0xffff7fff\r
+ .equ s7,0xffff8000\r
+ .equ s8,0xfffffeff\r
+ .equ s9,0xffffff00\r
+ .equ s10,0xffffffff\r
+ \r
+ .end\r
+ \r
projects / deliverable / binutils-gdb.git / commitdiff
