2004-06-17 Alexandre Oliva <aoliva@redhat.com>

* band.s, biand.s: imm3_abs16 is not available on h8300h.
* bset.s: Likewise.  Ditto for rn_abs32.

diff --git a/sim/testsuite/sim/h8300/ChangeLog b/sim/testsuite/sim/h8300/ChangeLog
index 4dc65595ebe48f0251b1f46c44982f9400096dfa..a90793a9ee212454c8c711d96797822f857a6863 100644 (file)
--- a/sim/testsuite/sim/h8300/ChangeLog
+++ b/sim/testsuite/sim/h8300/ChangeLog
@@ -1,3 +1,9 @@
+2004-06-24  Alexandre Oliva  <aoliva@redhat.com>
+
+       2004-06-17  Alexandre Oliva  <aoliva@redhat.com>
+       * band.s, biand.s: imm3_abs16 is not available on h8300h.
+       * bset.s: Likewise.  Ditto for rn_abs32.
+
 2003-07-22  Michael Snyder  <msnyder@redhat.com>
 
        * cmpw.s: Add test for less-than-zero immediate.

diff --git a/sim/testsuite/sim/h8300/band.s b/sim/testsuite/sim/h8300/band.s
index f3455ad4cb848f1681e16bfb191a5c7394b1f187..3c7e5a3aa4ecc550dc8f1041ba59b272c4f2e353 100644 (file)
--- a/sim/testsuite/sim/h8300/band.s
+++ b/sim/testsuite/sim/h8300/band.s
@@ -104,7 +104,7 @@ band_imm3_abs8:
 
        test_grs_a5a5           ; general registers should not be changed.
 
-.if (sim_cpu)                  ; non-zero means not h8300
+.if (sim_cpu > h8300h)
 band_imm3_abs16:
        set_grs_a5a5
        set_ccr_zero
@@ -314,7 +314,7 @@ bld_imm3_abs8:
 
        test_grs_a5a5           ; general registers should not be changed.
 
-.if (sim_cpu)                  ; non-zero means not h8300
+.if (sim_cpu > h8300h)
 bld_imm3_abs16:
        set_grs_a5a5
        set_ccr_zero
@@ -491,7 +491,7 @@ btst_imm3_abs8:
 
        test_grs_a5a5           ; general registers should not be changed.
 
-.if (sim_cpu)                  ; non-zero means not h8300
+.if (sim_cpu > h8300h)
 btst_imm3_abs16:
        set_grs_a5a5
        set_ccr_zero

diff --git a/sim/testsuite/sim/h8300/biand.s b/sim/testsuite/sim/h8300/biand.s
index 07d3ecfe04456908a98bbca2848e304b87b6cf0f..c4cf285dbd0d7d749191a516b74a60b2a110357f 100644 (file)
--- a/sim/testsuite/sim/h8300/biand.s
+++ b/sim/testsuite/sim/h8300/biand.s
@@ -104,7 +104,7 @@ biand_imm3_abs8:
 
        test_grs_a5a5           ; general registers should not be changed.
 
-.if (sim_cpu)                  ; non-zero means not h8300
+.if (sim_cpu > h8300h)
 biand_imm3_abs16:
        set_grs_a5a5
        set_ccr_zero
@@ -314,7 +314,7 @@ bild_imm3_abs8:
 
        test_grs_a5a5           ; general registers should not be changed.
 
-.if (sim_cpu)                  ; non-zero means not h8300
+.if (sim_cpu > h8300h)
 bild_imm3_abs16:
        set_grs_a5a5
        set_ccr_zero

diff --git a/sim/testsuite/sim/h8300/bset.s b/sim/testsuite/sim/h8300/bset.s
index a94e916b26c240c7a32fdeaf063a45a4928db169..0e16fc1f9d2355d979af432326870f162e970199 100644 (file)
--- a/sim/testsuite/sim/h8300/bset.s
+++ b/sim/testsuite/sim/h8300/bset.s
@@ -263,6 +263,7 @@ bclr_imm3_ind:
        test_gr_a5a5 6
        test_gr_a5a5 7
 
+.if (sim_cpu > h8300h)
 bset_imm3_abs16:
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
 
@@ -383,6 +384,7 @@ bclr_imm3_abs16:
        test_gr_a5a5 6
        test_gr_a5a5 7
 .endif
+.endif
 
 bset_rs8_rd8:
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
@@ -644,6 +646,7 @@ bclr_rs8_ind:
        test_gr_a5a5 6
        test_gr_a5a5 7
 
+.if (sim_cpu > h8300h)
 bset_rs8_abs32:
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
 
@@ -780,6 +783,7 @@ bclr_rs8_abs32:
        test_gr_a5a5 6
        test_gr_a5a5 7
 .endif
+.endif
 
 .if (sim_cpu == h8sx)
 bset_eq_imm3_abs16: