Merge remote-tracking branch 'drm/drm-next'
authorStephen Rothwell <sfr@canb.auug.org.au>
Tue, 13 Sep 2016 00:31:55 +0000 (10:31 +1000)
committerStephen Rothwell <sfr@canb.auug.org.au>
Tue, 13 Sep 2016 00:31:55 +0000 (10:31 +1000)
29 files changed:
1  2 
Documentation/gpu/index.rst
MAINTAINERS
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
drivers/gpu/drm/amd/amdgpu/cik_sdma.c
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
drivers/gpu/drm/drm_atomic.c
drivers/gpu/drm/drm_crtc.c
drivers/gpu/drm/drm_dp_helper.c
drivers/gpu/drm/drm_fb_helper.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_gem_gtt.c
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/i915_vgpu.c
drivers/gpu/drm/i915/intel_csr.c
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_drv.h
drivers/gpu/drm/i915/intel_pm.c
drivers/gpu/drm/imx/imx-drm-core.c
drivers/gpu/drm/imx/ipuv3-crtc.c
drivers/gpu/drm/radeon/atombios_crtc.c
drivers/gpu/drm/radeon/radeon_ttm.c
drivers/gpu/drm/vc4/vc4_drv.c
drivers/gpu/drm/vc4/vc4_gem.c

index 5ff3d2b236afa04c171375e9223def9d339d2db9,ba92f45abb76e59f6c8324c3bd01db13b53003e9..be0dafcf5556df17509a9d376e29e2800c14ca61
@@@ -12,10 -12,4 +12,11 @@@ Linux GPU Driver Developer's Guid
     drm-uapi
     i915
     vga-switcheroo
+    vgaarbiter
 +
 +.. only::  subproject
 +
 +   Indices
 +   =======
 +
 +   * :ref:`genindex`
diff --cc MAINTAINERS
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index ddebe54cd5ca673dd6ba213efcc18664b8278916,631691bae01d7f914844e2eac5b83d26e7e7da64..d84a0ead81005c31abb77f7ec723b35e6726fa15
@@@ -5402,13 -1915,19 +1915,22 @@@ int drm_mode_page_flip_ioctl(struct drm
        struct drm_crtc *crtc;
        struct drm_framebuffer *fb = NULL;
        struct drm_pending_vblank_event *e = NULL;
+       u32 target_vblank = page_flip->sequence;
        int ret = -EINVAL;
  
-       if (page_flip->flags & ~DRM_MODE_PAGE_FLIP_FLAGS ||
-           page_flip->reserved != 0)
 +      if (!drm_core_check_feature(dev, DRIVER_MODESET))
 +              return -EINVAL;
 +
+       if (page_flip->flags & ~DRM_MODE_PAGE_FLIP_FLAGS)
+               return -EINVAL;
+       if (page_flip->sequence != 0 && !(page_flip->flags & DRM_MODE_PAGE_FLIP_TARGET))
+               return -EINVAL;
+       /* Only one of the DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE/RELATIVE flags
+        * can be specified
+        */
+       if ((page_flip->flags & DRM_MODE_PAGE_FLIP_TARGET) == DRM_MODE_PAGE_FLIP_TARGET)
                return -EINVAL;
  
        if ((page_flip->flags & DRM_MODE_PAGE_FLIP_ASYNC) && !dev->mode_config.async_page_flip)
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index c3b33a10c15cd8a6f74bcec4b7d442b786cce969,fb27d187876cedb845c08ac1bf9d75e40a697161..1ea0e1f433971ea201debcff43e36d6cd75a35f4
   * onwards to drive newly added DMC (Display microcontroller) in display
   * engine to save and restore the state of display engine when it enter into
   * low-power state and comes back to normal.
-  *
-  * Firmware loading status will be one of the below states: FW_UNINITIALIZED,
-  * FW_LOADED, FW_FAILED.
-  *
-  * Once the firmware is written into the registers status will be moved from
-  * FW_UNINITIALIZED to FW_LOADED and for any erroneous condition status will
-  * be moved to FW_FAILED.
   */
  
 -#define I915_CSR_KBL "i915/kbl_dmc_ver1.bin"
 +#define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin"
  MODULE_FIRMWARE(I915_CSR_KBL);
  #define KBL_CSR_VERSION_REQUIRED      CSR_VERSION(1, 1)
  
index 175595fc3e45d239ce528662696167bac4c73327,d224f64836c53d42bf37efe938b95ae1a28e0ea3..d65f0136b73ec66a282fe937af1dc50ddded1746
@@@ -3204,24 -3587,26 +3587,28 @@@ void intel_finish_reset(struct drm_i915
         */
        intel_complete_page_flips(dev_priv);
  
-       /* no reset support for gen2 */
-       if (IS_GEN2(dev_priv))
-               return;
+       dev_priv->modeset_restore_state = NULL;
  
 +      dev_priv->modeset_restore_state = NULL;
 +
        /* reset doesn't touch the display */
-       if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
-               /*
-                * Flips in the rings have been nuked by the reset,
-                * so update the base address of all primary
-                * planes to the the last fb to make sure we're
-                * showing the correct fb after a reset.
-                *
-                * FIXME: Atomic will make this obsolete since we won't schedule
-                * CS-based flips (which might get lost in gpu resets) any more.
-                */
-               intel_update_primary_planes(dev);
+       if (!gpu_reset_clobbers_display(dev_priv)) {
+               if (!state) {
+                       /*
+                        * Flips in the rings have been nuked by the reset,
+                        * so update the base address of all primary
+                        * planes to the the last fb to make sure we're
+                        * showing the correct fb after a reset.
+                        *
+                        * FIXME: Atomic will make this obsolete since we won't schedule
+                        * CS-based flips (which might get lost in gpu resets) any more.
+                        */
+                       intel_update_primary_planes(dev);
+               } else {
+                       ret = __intel_display_resume(dev, state);
+                       if (ret)
+                               DRM_ERROR("Restoring old state failed with %i\n", ret);
+               }
        } else {
                /*
                 * The display has been reset as well,
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