+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/tc-arm.c (struct arm_it): Make immisreg field larger to hold
+ type of register.
+ (enum shift_kind): Add SHIFT_UXTW shift kind.
+ (enum parse_shift_mode): Add SHIFT_UXTW_IMMEDIATE shift mode.
+ (parse_shift): Handle new shift type.
+ (parse_address_main): Accept new addressing modes.
+ (M_MNEM_vstrb, M_MNEM_vstrh, M_MNEM_vstrw, M_MNEM_vstrd,
+ M_MNEM_vldrb, M_MNEM_vldrh, M_MNEM_vldrw, M_MNEM_vldrd): New
+ instruction encodings.
+ (do_mve_vstr_vldr_QI): New encoding functions.
+ (do_mve_vstr_vldr_RQ): Likewise.
+ (do_mve_vstr_vldr_RI): Likewise.
+ (do_mve_vstr_vldr): Likewise.
+ * testsuite/gas/arm/mve-vldr-bad-1.d: New test.
+ * testsuite/gas/arm/mve-vldr-bad-1.l: New test.
+ * testsuite/gas/arm/mve-vldr-bad-1.s: New test.
+ * testsuite/gas/arm/mve-vldr-bad-2.d: New test.
+ * testsuite/gas/arm/mve-vldr-bad-2.l: New test.
+ * testsuite/gas/arm/mve-vldr-bad-2.s: New test.
+ * testsuite/gas/arm/mve-vldr-bad-3.d: New test.
+ * testsuite/gas/arm/mve-vldr-bad-3.l: New test.
+ * testsuite/gas/arm/mve-vldr-bad-3.s: New test.
+ * testsuite/gas/arm/mve-vstr-bad-1.d: New test.
+ * testsuite/gas/arm/mve-vstr-bad-1.l: New test.
+ * testsuite/gas/arm/mve-vstr-bad-1.s: New test.
+ * testsuite/gas/arm/mve-vstr-bad-2.d: New test.
+ * testsuite/gas/arm/mve-vstr-bad-2.l: New test.
+ * testsuite/gas/arm/mve-vstr-bad-2.s: New test.
+ * testsuite/gas/arm/mve-vstr-bad-3.d: New test.
+ * testsuite/gas/arm/mve-vstr-bad-3.l: New test.
+ * testsuite/gas/arm/mve-vstr-bad-3.s: New test.
+
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum it_instruction_type): Add MVE_UNPREDICABLE_INSN.
struct neon_type_el vectype;
unsigned present : 1; /* Operand present. */
unsigned isreg : 1; /* Operand was a register. */
- unsigned immisreg : 1; /* .imm field is a second register. */
+ unsigned immisreg : 2; /* .imm field is a second register.
+ 0: imm, 1: gpr, 2: MVE Q-register. */
unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
unsigned immisalign : 1; /* Immediate is an alignment specifier. */
unsigned immisfloat : 1; /* Immediate was parsed as a float. */
/* Shift operands. */
enum shift_kind
{
- SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
+ SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX, SHIFT_UXTW
};
struct asm_shift_name
SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
+ SHIFT_UXTW_IMMEDIATE /* Shift must be UXTW immediate. */
};
/* Parse a <shift> specifier on an ARM data processing instruction.
switch (mode)
{
case NO_SHIFT_RESTRICT:
- case SHIFT_IMMEDIATE: break;
+ case SHIFT_IMMEDIATE:
+ if (shift == SHIFT_UXTW)
+ {
+ inst.error = _("'UXTW' not allowed here");
+ return FAIL;
+ }
+ break;
case SHIFT_LSL_OR_ASR_IMMEDIATE:
if (shift != SHIFT_LSL && shift != SHIFT_ASR)
return FAIL;
}
break;
+ case SHIFT_UXTW_IMMEDIATE:
+ if (shift != SHIFT_UXTW)
+ {
+ inst.error = _("'UXTW' required");
+ return FAIL;
+ }
+ break;
default: abort ();
}
/* PR gas/14887: Allow for whitespace after the opening bracket. */
skip_whitespace (p);
- if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
+ if (group_type == GROUP_MVE)
+ {
+ enum arm_reg_type rtype = REG_TYPE_MQ;
+ struct neon_type_el et;
+ if ((reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
+ {
+ inst.operands[i].isquad = 1;
+ }
+ else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
+ {
+ inst.error = BAD_ADDR_MODE;
+ return PARSE_OPERAND_FAIL;
+ }
+ }
+ else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
{
if (group_type == GROUP_MVE)
inst.error = BAD_ADDR_MODE;
if (*p == '+') p++;
else if (*p == '-') p++, inst.operands[i].negative = 1;
- if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
+ enum arm_reg_type rtype = REG_TYPE_MQ;
+ struct neon_type_el et;
+ if (group_type == GROUP_MVE
+ && (reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
+ {
+ inst.operands[i].immisreg = 2;
+ inst.operands[i].imm = reg;
+
+ if (skip_past_comma (&p) == SUCCESS)
+ {
+ if (parse_shift (&p, i, SHIFT_UXTW_IMMEDIATE) == SUCCESS)
+ {
+ inst.operands[i].imm |= inst.relocs[0].exp.X_add_number << 5;
+ inst.relocs[0].exp.X_add_number = 0;
+ }
+ else
+ return PARSE_OPERAND_FAIL;
+ }
+ }
+ else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
{
inst.operands[i].imm = reg;
inst.operands[i].immisreg = 1;
if (*p == '+') p++;
else if (*p == '-') p++, inst.operands[i].negative = 1;
- if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
+ enum arm_reg_type rtype = REG_TYPE_MQ;
+ struct neon_type_el et;
+ if (group_type == GROUP_MVE
+ && (reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
+ {
+ inst.operands[i].immisreg = 2;
+ inst.operands[i].imm = reg;
+ }
+ else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
{
/* We might be using the immediate for alignment already. If we
are, OR the register number into the low-order bits. */
#define M_MNEM_vld41 0xfc901e21
#define M_MNEM_vld42 0xfc901e41
#define M_MNEM_vld43 0xfc901e61
+#define M_MNEM_vstrb 0xec000e00
+#define M_MNEM_vstrh 0xec000e10
+#define M_MNEM_vstrw 0xec000e40
+#define M_MNEM_vstrd 0xec000e50
+#define M_MNEM_vldrb 0xec100e00
+#define M_MNEM_vldrh 0xec100e10
+#define M_MNEM_vldrw 0xec100e40
+#define M_MNEM_vldrd 0xec100e50
/* Neon instruction encoder helpers. */
return 0;
}
+static void
+do_mve_vstr_vldr_QI (int size, int elsize, int load)
+{
+ constraint (size < 32, BAD_ADDR_MODE);
+ constraint (size != elsize, BAD_EL_TYPE);
+ constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
+ constraint (!inst.operands[1].preind, BAD_ADDR_MODE);
+ constraint (load && inst.operands[0].reg == inst.operands[1].reg,
+ _("destination register and offset register may not be the"
+ " same"));
+
+ int imm = inst.relocs[0].exp.X_add_number;
+ int add = 1;
+ if (imm < 0)
+ {
+ add = 0;
+ imm = -imm;
+ }
+ constraint ((imm % (size / 8) != 0)
+ || imm > (0x7f << neon_logbits (size)),
+ (size == 32) ? _("immediate must be a multiple of 4 in the"
+ " range of +/-[0,508]")
+ : _("immediate must be a multiple of 8 in the"
+ " range of +/-[0,1016]"));
+ inst.instruction |= 0x11 << 24;
+ inst.instruction |= add << 23;
+ inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+ inst.instruction |= inst.operands[1].writeback << 21;
+ inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
+ inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+ inst.instruction |= 1 << 12;
+ inst.instruction |= (size == 64) << 8;
+ inst.instruction &= 0xffffff00;
+ inst.instruction |= HI1 (inst.operands[1].reg) << 7;
+ inst.instruction |= imm >> neon_logbits (size);
+}
+
+static void
+do_mve_vstr_vldr_RQ (int size, int elsize, int load)
+{
+ unsigned os = inst.operands[1].imm >> 5;
+ constraint (os != 0 && size == 8,
+ _("can not shift offsets when accessing less than half-word"));
+ constraint (os && os != neon_logbits (size),
+ _("shift immediate must be 1, 2 or 3 for half-word, word"
+ " or double-word accesses respectively"));
+ if (inst.operands[1].reg == REG_PC)
+ as_tsktsk (MVE_BAD_PC);
+
+ switch (size)
+ {
+ case 8:
+ constraint (elsize >= 64, BAD_EL_TYPE);
+ break;
+ case 16:
+ constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE);
+ break;
+ case 32:
+ case 64:
+ constraint (elsize != size, BAD_EL_TYPE);
+ break;
+ default:
+ break;
+ }
+ constraint (inst.operands[1].writeback || !inst.operands[1].preind,
+ BAD_ADDR_MODE);
+ if (load)
+ {
+ constraint (inst.operands[0].reg == (inst.operands[1].imm & 0x1f),
+ _("destination register and offset register may not be"
+ " the same"));
+ constraint (size == elsize && inst.vectype.el[0].type != NT_unsigned,
+ BAD_EL_TYPE);
+ constraint (inst.vectype.el[0].type != NT_unsigned
+ && inst.vectype.el[0].type != NT_signed, BAD_EL_TYPE);
+ inst.instruction |= (inst.vectype.el[0].type == NT_unsigned) << 28;
+ }
+ else
+ {
+ constraint (inst.vectype.el[0].type != NT_untyped, BAD_EL_TYPE);
+ }
+
+ inst.instruction |= 1 << 23;
+ inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+ inst.instruction |= inst.operands[1].reg << 16;
+ inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+ inst.instruction |= neon_logbits (elsize) << 7;
+ inst.instruction |= HI1 (inst.operands[1].imm) << 5;
+ inst.instruction |= LOW4 (inst.operands[1].imm);
+ inst.instruction |= !!os;
+}
+
+static void
+do_mve_vstr_vldr_RI (int size, int elsize, int load)
+{
+ enum neon_el_type type = inst.vectype.el[0].type;
+
+ constraint (size >= 64, BAD_ADDR_MODE);
+ switch (size)
+ {
+ case 16:
+ constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE);
+ break;
+ case 32:
+ constraint (elsize != size, BAD_EL_TYPE);
+ break;
+ default:
+ break;
+ }
+ if (load)
+ {
+ constraint (elsize != size && type != NT_unsigned
+ && type != NT_signed, BAD_EL_TYPE);
+ }
+ else
+ {
+ constraint (elsize != size && type != NT_untyped, BAD_EL_TYPE);
+ }
+
+ int imm = inst.relocs[0].exp.X_add_number;
+ int add = 1;
+ if (imm < 0)
+ {
+ add = 0;
+ imm = -imm;
+ }
+
+ if ((imm % (size / 8) != 0) || imm > (0x7f << neon_logbits (size)))
+ {
+ switch (size)
+ {
+ case 8:
+ constraint (1, _("immediate must be in the range of +/-[0,127]"));
+ break;
+ case 16:
+ constraint (1, _("immediate must be a multiple of 2 in the"
+ " range of +/-[0,254]"));
+ break;
+ case 32:
+ constraint (1, _("immediate must be a multiple of 4 in the"
+ " range of +/-[0,508]"));
+ break;
+ }
+ }
+
+ if (size != elsize)
+ {
+ constraint (inst.operands[1].reg > 7, BAD_HIREG);
+ constraint (inst.operands[0].reg > 14,
+ _("MVE vector register in the range [Q0..Q7] expected"));
+ inst.instruction |= (load && type == NT_unsigned) << 28;
+ inst.instruction |= (size == 16) << 19;
+ inst.instruction |= neon_logbits (elsize) << 7;
+ }
+ else
+ {
+ if (inst.operands[1].reg == REG_PC)
+ as_tsktsk (MVE_BAD_PC);
+ else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback)
+ as_tsktsk (MVE_BAD_SP);
+ inst.instruction |= 1 << 12;
+ inst.instruction |= neon_logbits (size) << 7;
+ }
+ inst.instruction |= inst.operands[1].preind << 24;
+ inst.instruction |= add << 23;
+ inst.instruction |= HI1 (inst.operands[0].reg) << 22;
+ inst.instruction |= inst.operands[1].writeback << 21;
+ inst.instruction |= inst.operands[1].reg << 16;
+ inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
+ inst.instruction &= 0xffffff80;
+ inst.instruction |= imm >> neon_logbits (size);
+
+}
+
+static void
+do_mve_vstr_vldr (void)
+{
+ unsigned size;
+ int load = 0;
+
+ if (inst.cond > COND_ALWAYS)
+ inst.pred_insn_type = INSIDE_VPT_INSN;
+ else
+ inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
+
+ switch (inst.instruction)
+ {
+ default:
+ gas_assert (0);
+ break;
+ case M_MNEM_vldrb:
+ load = 1;
+ /* fall through. */
+ case M_MNEM_vstrb:
+ size = 8;
+ break;
+ case M_MNEM_vldrh:
+ load = 1;
+ /* fall through. */
+ case M_MNEM_vstrh:
+ size = 16;
+ break;
+ case M_MNEM_vldrw:
+ load = 1;
+ /* fall through. */
+ case M_MNEM_vstrw:
+ size = 32;
+ break;
+ case M_MNEM_vldrd:
+ load = 1;
+ /* fall through. */
+ case M_MNEM_vstrd:
+ size = 64;
+ break;
+ }
+ unsigned elsize = inst.vectype.el[0].size;
+
+ if (inst.operands[1].isquad)
+ {
+ /* We are dealing with [Q, imm]{!} cases. */
+ do_mve_vstr_vldr_QI (size, elsize, load);
+ }
+ else
+ {
+ if (inst.operands[1].immisreg == 2)
+ {
+ /* We are dealing with [R, Q, {UXTW #os}] cases. */
+ do_mve_vstr_vldr_RQ (size, elsize, load);
+ }
+ else if (!inst.operands[1].immisreg)
+ {
+ /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
+ do_mve_vstr_vldr_RI (size, elsize, load);
+ }
+ else
+ constraint (1, BAD_ADDR_MODE);
+ }
+
+ inst.is_neon = 1;
+}
+
static void
do_mve_vst_vld (void)
{
{ "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
{ "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
{ "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
- { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
+ { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX },
+ { "uxtw", SHIFT_UXTW}, { "UXTW", SHIFT_UXTW}
};
/* Table of all explicit relocation names. */
mCEF(vld41, _vld41, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
mCEF(vld42, _vld42, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
mCEF(vld43, _vld43, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
+ mCEF(vstrb, _vstrb, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
+ mCEF(vstrh, _vstrh, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
+ mCEF(vstrw, _vstrw, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
+ mCEF(vstrd, _vstrd, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
+ mCEF(vldrb, _vldrb, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
+ mCEF(vldrh, _vldrh, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
+ mCEF(vldrw, _vldrw, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
+ mCEF(vldrd, _vldrd, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
#undef ARM_VARIANT
#define ARM_VARIANT & fpu_vfp_ext_v1xd
--- /dev/null
+#name: bad MVE VLDR with [R, Q] addressing mode
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vldr-bad-1.l
+
+.*: +file format .*arm.*
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:10: Error: bad element type for instruction -- `vldrb.16 q0,\[r0,q1\]'
+[^:]*:11: Error: bad element type for instruction -- `vldrb.p16 q0,\[r0,q1\]'
+[^:]*:12: Error: bad element type for instruction -- `vldrb.f16 q0,\[r0,q1\]'
+[^:]*:13: Error: bad element type for instruction -- `vldrb.32 q0,\[r0,q1\]'
+[^:]*:14: Error: bad element type for instruction -- `vldrb.f32 q0,\[r0,q1\]'
+[^:]*:15: Error: bad element type for instruction -- `vldrb.64 q0,\[r0,q1\]'
+[^:]*:16: Error: bad element type for instruction -- `vldrb.u64 q0,\[r0,q1\]'
+[^:]*:17: Error: bad element type for instruction -- `vldrb.s64 q0,\[r0,q1\]'
+[^:]*:18: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:19: Error: destination register and offset register may not be the same -- `vldrb.u32 q0,\[r0,q0\]'
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: Error: syntax error -- `vldrbeq.u32 q0,\[r0,q1\]'
+[^:]*:23: Error: syntax error -- `vldrbeq.u32 q0,\[r0,q1\]'
+[^:]*:25: Error: syntax error -- `vldrbeq.u32 q0,\[r0,q1\]'
+[^:]*:26: Error: vector predicated instruction should be in VPT/VPST block -- `vldrbt.u32 q0,\[r0,q1\]'
+[^:]*:28: Error: instruction missing MVE vector predication code -- `vldrb.u32 q0,\[r0,q1\]'
+[^:]*:30: Error: bad element type for instruction -- `vldrh.32 q0,\[r0,q1\]'
+[^:]*:31: Error: bad element type for instruction -- `vldrh.f32 q0,\[r0,q1\]'
+[^:]*:32: Error: bad element type for instruction -- `vldrh.64 q0,\[r0,q1\]'
+[^:]*:33: Error: bad element type for instruction -- `vldrh.u64 q0,\[r0,q1\]'
+[^:]*:34: Error: bad element type for instruction -- `vldrh.s64 q0,\[r0,q1\]'
+[^:]*:35: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:36: Error: destination register and offset register may not be the same -- `vldrh.u32 q0,\[r0,q0\]'
+[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:37: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:39: Error: syntax error -- `vldrheq.u32 q0,\[r0,q1\]'
+[^:]*:40: Error: syntax error -- `vldrheq.u32 q0,\[r0,q1\]'
+[^:]*:42: Error: syntax error -- `vldrheq.u32 q0,\[r0,q1\]'
+[^:]*:43: Error: vector predicated instruction should be in VPT/VPST block -- `vldrht.u32 q0,\[r0,q1\]'
+[^:]*:45: Error: instruction missing MVE vector predication code -- `vldrh.u32 q0,\[r0,q1\]'
+[^:]*:47: Error: bad element type for instruction -- `vldrw.64 q0,\[r0,q1\]'
+[^:]*:48: Error: bad element type for instruction -- `vldrw.u64 q0,\[r0,q1\]'
+[^:]*:49: Error: bad element type for instruction -- `vldrw.s64 q0,\[r0,q1\]'
+[^:]*:50: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:51: Error: destination register and offset register may not be the same -- `vldrw.u32 q0,\[r0,q0\]'
+[^:]*:52: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:52: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:52: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:52: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:52: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:52: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:54: Error: syntax error -- `vldrweq.u32 q0,\[r0,q1\]'
+[^:]*:55: Error: syntax error -- `vldrweq.u32 q0,\[r0,q1\]'
+[^:]*:57: Error: syntax error -- `vldrweq.u32 q0,\[r0,q1\]'
+[^:]*:58: Error: vector predicated instruction should be in VPT/VPST block -- `vldrwt.u32 q0,\[r0,q1\]'
+[^:]*:60: Error: instruction missing MVE vector predication code -- `vldrw.u32 q0,\[r0,q1\]'
+[^:]*:69: Error: bad element type for instruction -- `vldrd.8 q0,\[r0,q1\]'
+[^:]*:70: Error: bad element type for instruction -- `vldrd.u8 q0,\[r0,q1\]'
+[^:]*:71: Error: bad element type for instruction -- `vldrd.s8 q0,\[r0,q1\]'
+[^:]*:72: Error: bad element type for instruction -- `vldrd.p8 q0,\[r0,q1\]'
+[^:]*:73: Error: bad element type for instruction -- `vldrd.16 q0,\[r0,q1\]'
+[^:]*:74: Error: bad element type for instruction -- `vldrd.u16 q0,\[r0,q1\]'
+[^:]*:75: Error: bad element type for instruction -- `vldrd.s16 q0,\[r0,q1\]'
+[^:]*:76: Error: bad element type for instruction -- `vldrd.p16 q0,\[r0,q1\]'
+[^:]*:77: Error: bad element type for instruction -- `vldrd.f16 q0,\[r0,q1\]'
+[^:]*:78: Error: bad element type for instruction -- `vldrd.32 q0,\[r0,q1\]'
+[^:]*:79: Error: bad element type for instruction -- `vldrd.u32 q0,\[r0,q1\]'
+[^:]*:80: Error: bad element type for instruction -- `vldrd.s32 q0,\[r0,q1\]'
+[^:]*:81: Error: bad element type for instruction -- `vldrd.f32 q0,\[r0,q1\]'
+[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:82: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:84: Error: syntax error -- `vldrdeq.u64 q0,\[r0,q1\]'
+[^:]*:85: Error: syntax error -- `vldrdeq.u64 q0,\[r0,q1\]'
+[^:]*:87: Error: syntax error -- `vldrdeq.u64 q0,\[r0,q1\]'
+[^:]*:88: Error: vector predicated instruction should be in VPT/VPST block -- `vldrdt.u64 q0,\[r0,q1\]'
+[^:]*:90: Error: instruction missing MVE vector predication code -- `vldrd.u64 q0,\[r0,q1\]'
+[^:]*:92: Error: shift expression expected -- `vldrb.u8 q0,\[r0,q1,#0\]'
+[^:]*:93: Error: can not shift offsets when accessing less than half-word -- `vldrb.u8 q0,\[r0,q1,UXTW#1\]'
+[^:]*:94: Error: can not shift offsets when accessing less than half-word -- `vldrb.u16 q0,\[r0,q1,UXTW#1\]'
+[^:]*:95: Error: can not shift offsets when accessing less than half-word -- `vldrb.u32 q0,\[r0,q1,UXTW#1\]'
+[^:]*:96: Error: shift expression expected -- `vldrh.u16 q0,\[r0,q1,#1\]'
+[^:]*:97: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrh.u16 q0,\[r0,q1,UXTW#2\]'
+[^:]*:98: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrh.u32 q0,\[r0,q1,UXTW#2\]'
+[^:]*:99: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrh.u16 q0,\[r0,q1,UXTW#3\]'
+[^:]*:100: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrh.u32 q0,\[r0,q1,UXTW#3\]'
+[^:]*:101: Error: shift expression expected -- `vldrw.u32 q0,\[r0,q1,#2\]'
+[^:]*:102: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrw.u32 q0,\[r0,q1,UXTW#1\]'
+[^:]*:103: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrw.u32 q0,\[r0,q1,UXTW#3\]'
+[^:]*:104: Error: shift expression expected -- `vldrd.u64 q0,\[r0,q1,#3\]'
+[^:]*:105: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrd.u64 q0,\[r0,q1,UXTW#1\]'
+[^:]*:106: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrd.u64 q0,\[r0,q1,UXTW#2\]'
+[^:]*:107: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vldrd.u64 q0,\[r0,q1,UXTW#4\]'
+
+
--- /dev/null
+.macro cond mnem
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\mnem\().u32 q0, [r0, q1]
+.endr
+.endm
+
+.syntax unified
+.thumb
+vldrb.16 q0, [r0, q1]
+vldrb.p16 q0, [r0, q1]
+vldrb.f16 q0, [r0, q1]
+vldrb.32 q0, [r0, q1]
+vldrb.f32 q0, [r0, q1]
+vldrb.64 q0, [r0, q1]
+vldrb.u64 q0, [r0, q1]
+vldrb.s64 q0, [r0, q1]
+vldrb.u32 q0, [pc, q1]
+vldrb.u32 q0, [r0, q0]
+cond vldrb
+it eq
+vldrbeq.u32 q0, [r0, q1]
+vldrbeq.u32 q0, [r0, q1]
+vpst
+vldrbeq.u32 q0, [r0, q1]
+vldrbt.u32 q0, [r0, q1]
+vpst
+vldrb.u32 q0, [r0, q1]
+
+vldrh.32 q0, [r0, q1]
+vldrh.f32 q0, [r0, q1]
+vldrh.64 q0, [r0, q1]
+vldrh.u64 q0, [r0, q1]
+vldrh.s64 q0, [r0, q1]
+vldrh.u32 q0, [pc, q1]
+vldrh.u32 q0, [r0, q0]
+cond vldrh
+it eq
+vldrheq.u32 q0, [r0, q1]
+vldrheq.u32 q0, [r0, q1]
+vpst
+vldrheq.u32 q0, [r0, q1]
+vldrht.u32 q0, [r0, q1]
+vpst
+vldrh.u32 q0, [r0, q1]
+
+vldrw.64 q0, [r0, q1]
+vldrw.u64 q0, [r0, q1]
+vldrw.s64 q0, [r0, q1]
+vldrw.u32 q0, [pc, q1]
+vldrw.u32 q0, [r0, q0]
+cond vldrw
+it eq
+vldrweq.u32 q0, [r0, q1]
+vldrweq.u32 q0, [r0, q1]
+vpst
+vldrweq.u32 q0, [r0, q1]
+vldrwt.u32 q0, [r0, q1]
+vpst
+vldrw.u32 q0, [r0, q1]
+
+.macro cond64
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vldrd.u64 q0, [r0, q1]
+.endr
+.endm
+
+vldrd.8 q0, [r0, q1]
+vldrd.u8 q0, [r0, q1]
+vldrd.s8 q0, [r0, q1]
+vldrd.p8 q0, [r0, q1]
+vldrd.16 q0, [r0, q1]
+vldrd.u16 q0, [r0, q1]
+vldrd.s16 q0, [r0, q1]
+vldrd.p16 q0, [r0, q1]
+vldrd.f16 q0, [r0, q1]
+vldrd.32 q0, [r0, q1]
+vldrd.u32 q0, [r0, q1]
+vldrd.s32 q0, [r0, q1]
+vldrd.f32 q0, [r0, q1]
+cond64
+it eq
+vldrdeq.u64 q0, [r0, q1]
+vldrdeq.u64 q0, [r0, q1]
+vpst
+vldrdeq.u64 q0, [r0, q1]
+vldrdt.u64 q0, [r0, q1]
+vpst
+vldrd.u64 q0, [r0, q1]
+
+vldrb.u8 q0, [r0, q1, #0]
+vldrb.u8 q0, [r0, q1, UXTW #1]
+vldrb.u16 q0, [r0, q1, UXTW #1]
+vldrb.u32 q0, [r0, q1, UXTW #1]
+vldrh.u16 q0, [r0, q1, #1]
+vldrh.u16 q0, [r0, q1, UXTW #2]
+vldrh.u32 q0, [r0, q1, UXTW #2]
+vldrh.u16 q0, [r0, q1, UXTW #3]
+vldrh.u32 q0, [r0, q1, UXTW #3]
+vldrw.u32 q0, [r0, q1, #2]
+vldrw.u32 q0, [r0, q1, UXTW #1]
+vldrw.u32 q0, [r0, q1, UXTW #3]
+vldrd.u64 q0, [r0, q1, #3]
+vldrd.u64 q0, [r0, q1, UXTW #1]
+vldrd.u64 q0, [r0, q1, UXTW #2]
+vldrd.u64 q0, [r0, q1, UXTW #4]
--- /dev/null
+#name: bad MVE VLDR with [Q, #imm] addressing mode
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vldr-bad-2.l
+
+.*: +file format .*arm.*
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:10: Error: bad element type for instruction -- `vldrw.u16 q0,\[q1,#4\]'
+[^:]*:11: Error: bad element type for instruction -- `vldrw.u64 q0,\[q1,#-4\]'
+[^:]*:12: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.u32 q0,\[q1,#1\]'
+[^:]*:13: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.u32 q0,\[q1,#2\]'
+[^:]*:14: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.u32 q0,\[q1,#231\]'
+[^:]*:15: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.u32 q0,\[q1,#516\]'
+[^:]*:16: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.u32 q0,\[q1,#-516\]'
+[^:]*:17: Error: destination register and offset register may not be the same -- `vldrw.u32 q0,\[q0,#4\]'
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:18: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:20: Error: syntax error -- `vldrweq.u32 q0,\[q1\]'
+[^:]*:21: Error: syntax error -- `vldrweq.u32 q0,\[q1\]'
+[^:]*:23: Error: syntax error -- `vldrweq.u32 q0,\[q1\]'
+[^:]*:24: Error: vector predicated instruction should be in VPT/VPST block -- `vldrwt.u32 q0,\[q1\]'
+[^:]*:26: Error: instruction missing MVE vector predication code -- `vldrw.u32 q0,\[q1\]'
+[^:]*:27: Error: bad element type for instruction -- `vldrd.u16 q0,\[q1,#8\]'
+[^:]*:28: Error: bad element type for instruction -- `vldrd.u32 q0,\[q1,#-8\]'
+[^:]*:29: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vldrd.u64 q0,\[q1,#1\]'
+[^:]*:30: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vldrd.u64 q0,\[q1,#4\]'
+[^:]*:31: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vldrd.u64 q0,\[q1,#7\]'
+[^:]*:32: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vldrd.u64 q0,\[q1,#228\]'
+[^:]*:33: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vldrd.u64 q0,\[q1,#1024\]'
+[^:]*:34: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vldrd.u64 q0,\[q1,#-1024\]'
+[^:]*:35: Error: destination register and offset register may not be the same -- `vldrd.u64 q0,\[q0,#8\]'
+[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:38: Error: syntax error -- `vldrdeq.u64 q0,\[q1\]'
+[^:]*:39: Error: syntax error -- `vldrdeq.u64 q0,\[q1\]'
+[^:]*:41: Error: syntax error -- `vldrdeq.u64 q0,\[q1\]'
+[^:]*:42: Error: vector predicated instruction should be in VPT/VPST block -- `vldrdt.u64 q0,\[q1\]'
+[^:]*:44: Error: instruction missing MVE vector predication code -- `vldrd.u64 q0,\[q1\]'
+
--- /dev/null
+.macro cond mnem, size
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\mnem\().u\size q0, [q1, #8]
+.endr
+.endm
+
+.syntax unified
+.thumb
+vldrw.u16 q0, [q1, #4]
+vldrw.u64 q0, [q1, #-4]
+vldrw.u32 q0, [q1, #1]
+vldrw.u32 q0, [q1, #2]
+vldrw.u32 q0, [q1, #231]
+vldrw.u32 q0, [q1, #516]
+vldrw.u32 q0, [q1, #-516]
+vldrw.u32 q0, [q0, #4]
+cond vldrw, 32
+it eq
+vldrweq.u32 q0, [q1]
+vldrweq.u32 q0, [q1]
+vpst
+vldrweq.u32 q0, [q1]
+vldrwt.u32 q0, [q1]
+vpst
+vldrw.u32 q0, [q1]
+vldrd.u16 q0, [q1, #8]
+vldrd.u32 q0, [q1, #-8]
+vldrd.u64 q0, [q1, #1]
+vldrd.u64 q0, [q1, #4]
+vldrd.u64 q0, [q1, #7]
+vldrd.u64 q0, [q1, #228]
+vldrd.u64 q0, [q1, #1024]
+vldrd.u64 q0, [q1, #-1024]
+vldrd.u64 q0, [q0, #8]
+cond vldrd, 64
+it eq
+vldrdeq.u64 q0, [q1]
+vldrdeq.u64 q0, [q1]
+vpst
+vldrdeq.u64 q0, [q1]
+vldrdt.u64 q0, [q1]
+vpst
+vldrd.u64 q0, [q1]
--- /dev/null
+#name: bad MVE VLDR with [R, #imm] addressing mode
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vldr-bad-3.l
+
+.*: +file format .*arm.*
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:10: Error: immediate must be in the range of \+/-\[0,127\] -- `vldrb.8 q0,\[r0,#128\]'
+[^:]*:11: Error: immediate must be in the range of \+/-\[0,127\] -- `vldrb.8 q0,\[r0,#-128\]'
+[^:]*:12: Error: immediate must be in the range of \+/-\[0,127\] -- `vldrb.u16 q0,\[r0,#128\]'
+[^:]*:13: Error: immediate must be in the range of \+/-\[0,127\] -- `vldrb.u16 q0,\[r0,#-128\]'
+[^:]*:14: Error: immediate must be in the range of \+/-\[0,127\] -- `vldrb.u32 q0,\[r0,#128\]'
+[^:]*:15: Error: immediate must be in the range of \+/-\[0,127\] -- `vldrb.u32 q0,\[r0,#-128\]'
+[^:]*:16: Error: immediate must be in the range of \+/-\[0,127\] -- `vldrb.8 q0,\[r0,#128\]!'
+[^:]*:17: Error: immediate must be in the range of \+/-\[0,127\] -- `vldrb.8 q0,\[r0,#-128\]!'
+[^:]*:18: Error: immediate must be in the range of \+/-\[0,127\] -- `vldrb.u16 q0,\[r0,#128\]!'
+[^:]*:19: Error: immediate must be in the range of \+/-\[0,127\] -- `vldrb.u16 q0,\[r0,#-128\]!'
+[^:]*:20: Error: immediate must be in the range of \+/-\[0,127\] -- `vldrb.u32 q0,\[r0,#128\]!'
+[^:]*:21: Error: immediate must be in the range of \+/-\[0,127\] -- `vldrb.u32 q0,\[r0,#-128\]!'
+[^:]*:22: Error: immediate must be in the range of \+/-\[0,127\] -- `vldrb.8 q0,\[r0\],#128'
+[^:]*:23: Error: immediate must be in the range of \+/-\[0,127\] -- `vldrb.8 q0,\[r0\],#-128'
+[^:]*:24: Error: immediate must be in the range of \+/-\[0,127\] -- `vldrb.u16 q0,\[r0\],#128'
+[^:]*:25: Error: immediate must be in the range of \+/-\[0,127\] -- `vldrb.u16 q0,\[r0\],#-128'
+[^:]*:26: Error: immediate must be in the range of \+/-\[0,127\] -- `vldrb.u32 q0,\[r0\],#128'
+[^:]*:27: Error: immediate must be in the range of \+/-\[0,127\] -- `vldrb.u32 q0,\[r0\],#-128'
+[^:]*:28: Error: lo register required -- `vldrb.u16 q0,\[r10,#2\]'
+[^:]*:29: Error: lo register required -- `vldrb.u16 q0,\[r10,#2\]!'
+[^:]*:30: Error: lo register required -- `vldrb.u16 q0,\[r10\],#2'
+[^:]*:31: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:32: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:33: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: Error: bad element type for instruction -- `vldrb.16 q0,\[r0\]'
+[^:]*:36: Error: bad element type for instruction -- `vldrb.f16 q0,\[r0\]'
+[^:]*:37: Error: bad element type for instruction -- `vldrb.p16 q0,\[r0\]'
+[^:]*:38: Error: bad element type for instruction -- `vldrb.32 q0,\[r0\]'
+[^:]*:39: Error: bad element type for instruction -- `vldrb.f32 q0,\[r0\]'
+[^:]*:40: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.16 q0,\[r0,#1\]'
+[^:]*:41: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.16 q0,\[r0,#17\]'
+[^:]*:42: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.16 q0,\[r0,#-17\]'
+[^:]*:43: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.16 q0,\[r0,#256\]'
+[^:]*:44: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.16 q0,\[r0,#-256\]'
+[^:]*:45: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.u32 q0,\[r0,#1\]'
+[^:]*:46: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.u32 q0,\[r0,#17\]'
+[^:]*:47: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.u32 q0,\[r0,#-17\]'
+[^:]*:48: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.u32 q0,\[r0,#256\]'
+[^:]*:49: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.u32 q0,\[r0,#-256\]'
+[^:]*:50: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.16 q0,\[r0,#1\]!'
+[^:]*:51: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.16 q0,\[r0,#17\]!'
+[^:]*:52: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.16 q0,\[r0,#-17\]!'
+[^:]*:53: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.16 q0,\[r0,#256\]!'
+[^:]*:54: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.16 q0,\[r0,#-256\]!'
+[^:]*:55: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.s32 q0,\[r0,#1\]!'
+[^:]*:56: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.s32 q0,\[r0,#17\]!'
+[^:]*:57: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.s32 q0,\[r0,#-17\]!'
+[^:]*:58: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.s32 q0,\[r0,#256\]!'
+[^:]*:59: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.s32 q0,\[r0,#-256\]!'
+[^:]*:60: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.16 q0,\[r0\],#1'
+[^:]*:61: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.16 q0,\[r0\],#17'
+[^:]*:62: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.16 q0,\[r0\],#-17'
+[^:]*:63: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.16 q0,\[r0\],#256'
+[^:]*:64: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.16 q0,\[r0\],#-256'
+[^:]*:65: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.u32 q0,\[r0\],#1'
+[^:]*:66: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.u32 q0,\[r0\],#17'
+[^:]*:67: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.u32 q0,\[r0\],#-17'
+[^:]*:68: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.u32 q0,\[r0\],#256'
+[^:]*:69: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vldrh.u32 q0,\[r0\],#-256'
+[^:]*:70: Error: lo register required -- `vldrh.u32 q0,\[r10,#4\]'
+[^:]*:71: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:72: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:73: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:74: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:75: Error: bad element type for instruction -- `vldrh.8 q0,\[r0\]'
+[^:]*:76: Error: bad element type for instruction -- `vldrh.u8 q0,\[r0\]'
+[^:]*:77: Error: bad element type for instruction -- `vldrh.s8 q0,\[r0\]'
+[^:]*:78: Error: bad element type for instruction -- `vldrh.p8 q0,\[r0\]'
+[^:]*:79: Error: bad element type for instruction -- `vldrh.32 q0,\[r0\]'
+[^:]*:80: Error: bad element type for instruction -- `vldrh.f32 q0,\[r0\]'
+[^:]*:81: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.32 q0,\[r0,#3\]'
+[^:]*:82: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.32 q0,\[r0,#-3\]'
+[^:]*:83: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.32 q0,\[r0,#514\]'
+[^:]*:84: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.32 q0,\[r0,#-258\]'
+[^:]*:85: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.32 q0,\[r0,#258\]'
+[^:]*:86: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.32 q0,\[r0,#516\]'
+[^:]*:87: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.32 q0,\[r0,#-516\]'
+[^:]*:88: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.32 q0,\[r0,#3\]!'
+[^:]*:89: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.32 q0,\[r0,#-3\]!'
+[^:]*:90: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.32 q0,\[r0,#514\]!'
+[^:]*:91: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.32 q0,\[r0,#-258\]!'
+[^:]*:92: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.32 q0,\[r0,#258\]!'
+[^:]*:93: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.32 q0,\[r0,#516\]!'
+[^:]*:94: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.32 q0,\[r0,#-516\]!'
+[^:]*:95: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.32 q0,\[r0\],#3'
+[^:]*:96: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.32 q0,\[r0\],#-3'
+[^:]*:97: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.32 q0,\[r0\],#514'
+[^:]*:98: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.32 q0,\[r0\],#-258'
+[^:]*:99: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.32 q0,\[r0\],#258'
+[^:]*:100: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.32 q0,\[r0\],#516'
+[^:]*:101: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vldrw.32 q0,\[r0\],#-516'
+[^:]*:102: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:103: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:104: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:104: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:104: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:104: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:104: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:104: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:105: Error: bad element type for instruction -- `vldrw.8 q0,\[r0\]'
+[^:]*:106: Error: bad element type for instruction -- `vldrw.u8 q0,\[r0\]'
+[^:]*:107: Error: bad element type for instruction -- `vldrw.s8 q0,\[r0\]'
+[^:]*:108: Error: bad element type for instruction -- `vldrw.p8 q0,\[r0\]'
+[^:]*:109: Error: bad element type for instruction -- `vldrw.16 q0,\[r0\]'
+[^:]*:110: Error: bad element type for instruction -- `vldrw.u16 q0,\[r0\]'
+[^:]*:111: Error: bad element type for instruction -- `vldrw.s16 q0,\[r0\]'
+[^:]*:112: Error: bad element type for instruction -- `vldrw.f16 q0,\[r0\]'
+[^:]*:113: Error: bad element type for instruction -- `vldrw.p16 q0,\[r0\]'
+[^:]*:115: Error: syntax error -- `vldrbeq.8 q0,\[r0\]'
+[^:]*:116: Error: syntax error -- `vldrbeq.8 q0,\[r0\]'
+[^:]*:118: Error: syntax error -- `vldrbeq.8 q0,\[r0\]'
+[^:]*:119: Error: vector predicated instruction should be in VPT/VPST block -- `vldrbt.8 q0,\[r0\]'
+[^:]*:121: Error: instruction missing MVE vector predication code -- `vldrb.8 q0,\[r0\]'
+[^:]*:123: Error: syntax error -- `vldrheq.16 q0,\[r0\]'
+[^:]*:124: Error: syntax error -- `vldrheq.16 q0,\[r0\]'
+[^:]*:126: Error: syntax error -- `vldrheq.16 q0,\[r0\]'
+[^:]*:127: Error: vector predicated instruction should be in VPT/VPST block -- `vldrht.16 q0,\[r0\]'
+[^:]*:129: Error: instruction missing MVE vector predication code -- `vldrh.16 q0,\[r0\]'
+[^:]*:131: Error: syntax error -- `vldrweq.32 q0,\[r0\]'
+[^:]*:132: Error: syntax error -- `vldrweq.32 q0,\[r0\]'
+[^:]*:134: Error: syntax error -- `vldrweq.32 q0,\[r0\]'
+[^:]*:135: Error: vector predicated instruction should be in VPT/VPST block -- `vldrwt.32 q0,\[r0\]'
+[^:]*:137: Error: instruction missing MVE vector predication code -- `vldrw.32 q0,\[r0\]'
--- /dev/null
+.macro cond mnem
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\mnem\().u32 q0, [r0]
+.endr
+.endm
+
+.syntax unified
+.thumb
+vldrb.8 q0, [r0, #128]
+vldrb.8 q0, [r0, #-128]
+vldrb.u16 q0, [r0, #128]
+vldrb.u16 q0, [r0, #-128]
+vldrb.u32 q0, [r0, #128]
+vldrb.u32 q0, [r0, #-128]
+vldrb.8 q0, [r0, #128]!
+vldrb.8 q0, [r0, #-128]!
+vldrb.u16 q0, [r0, #128]!
+vldrb.u16 q0, [r0, #-128]!
+vldrb.u32 q0, [r0, #128]!
+vldrb.u32 q0, [r0, #-128]!
+vldrb.8 q0, [r0], #128
+vldrb.8 q0, [r0], #-128
+vldrb.u16 q0, [r0], #128
+vldrb.u16 q0, [r0], #-128
+vldrb.u32 q0, [r0], #128
+vldrb.u32 q0, [r0], #-128
+vldrb.u16 q0, [r10, #2]
+vldrb.u16 q0, [r10, #2]!
+vldrb.u16 q0, [r10], #2
+vldrb.8 q0, [sp, #2]!
+vldrb.8 q0, [sp], #2
+vldrb.8 q0, [pc, #2]
+cond vldrb
+vldrb.16 q0, [r0]
+vldrb.f16 q0, [r0]
+vldrb.p16 q0, [r0]
+vldrb.32 q0, [r0]
+vldrb.f32 q0, [r0]
+vldrh.16 q0, [r0, #1]
+vldrh.16 q0, [r0, #17]
+vldrh.16 q0, [r0, #-17]
+vldrh.16 q0, [r0, #256]
+vldrh.16 q0, [r0, #-256]
+vldrh.u32 q0, [r0, #1]
+vldrh.u32 q0, [r0, #17]
+vldrh.u32 q0, [r0, #-17]
+vldrh.u32 q0, [r0, #256]
+vldrh.u32 q0, [r0, #-256]
+vldrh.16 q0, [r0, #1]!
+vldrh.16 q0, [r0, #17]!
+vldrh.16 q0, [r0, #-17]!
+vldrh.16 q0, [r0, #256]!
+vldrh.16 q0, [r0, #-256]!
+vldrh.s32 q0, [r0, #1]!
+vldrh.s32 q0, [r0, #17]!
+vldrh.s32 q0, [r0, #-17]!
+vldrh.s32 q0, [r0, #256]!
+vldrh.s32 q0, [r0, #-256]!
+vldrh.16 q0, [r0], #1
+vldrh.16 q0, [r0], #17
+vldrh.16 q0, [r0], #-17
+vldrh.16 q0, [r0], #256
+vldrh.16 q0, [r0], #-256
+vldrh.u32 q0, [r0], #1
+vldrh.u32 q0, [r0], #17
+vldrh.u32 q0, [r0], #-17
+vldrh.u32 q0, [r0], #256
+vldrh.u32 q0, [r0], #-256
+vldrh.u32 q0, [r10, #4]
+vldrh.16 q0, [sp, #2]!
+vldrh.16 q0, [sp], #2
+vldrh.16 q0, [pc, #2]
+cond vldrh
+vldrh.8 q0, [r0]
+vldrh.u8 q0, [r0]
+vldrh.s8 q0, [r0]
+vldrh.p8 q0, [r0]
+vldrh.32 q0, [r0]
+vldrh.f32 q0, [r0]
+vldrw.32 q0, [r0, #3]
+vldrw.32 q0, [r0, #-3]
+vldrw.32 q0, [r0, #514]
+vldrw.32 q0, [r0, #-258]
+vldrw.32 q0, [r0, #258]
+vldrw.32 q0, [r0, #516]
+vldrw.32 q0, [r0, #-516]
+vldrw.32 q0, [r0, #3]!
+vldrw.32 q0, [r0, #-3]!
+vldrw.32 q0, [r0, #514]!
+vldrw.32 q0, [r0, #-258]!
+vldrw.32 q0, [r0, #258]!
+vldrw.32 q0, [r0, #516]!
+vldrw.32 q0, [r0, #-516]!
+vldrw.32 q0, [r0], #3
+vldrw.32 q0, [r0], #-3
+vldrw.32 q0, [r0], #514
+vldrw.32 q0, [r0], #-258
+vldrw.32 q0, [r0], #258
+vldrw.32 q0, [r0], #516
+vldrw.32 q0, [r0], #-516
+vldrw.32 q0, [sp, #4]!
+vldrw.32 q0, [pc, #4]
+cond vldrw
+vldrw.8 q0, [r0]
+vldrw.u8 q0, [r0]
+vldrw.s8 q0, [r0]
+vldrw.p8 q0, [r0]
+vldrw.16 q0, [r0]
+vldrw.u16 q0, [r0]
+vldrw.s16 q0, [r0]
+vldrw.f16 q0, [r0]
+vldrw.p16 q0, [r0]
+it eq
+vldrbeq.8 q0, [r0]
+vldrbeq.8 q0, [r0]
+vpst
+vldrbeq.8 q0, [r0]
+vldrbt.8 q0, [r0]
+vpst
+vldrb.8 q0, [r0]
+it eq
+vldrheq.16 q0, [r0]
+vldrheq.16 q0, [r0]
+vpst
+vldrheq.16 q0, [r0]
+vldrht.16 q0, [r0]
+vpst
+vldrh.16 q0, [r0]
+it eq
+vldrweq.32 q0, [r0]
+vldrweq.32 q0, [r0]
+vpst
+vldrweq.32 q0, [r0]
+vldrwt.32 q0, [r0]
+vpst
+vldrw.32 q0, [r0]
+
--- /dev/null
+#name: bad MVE VSTR with [R, Q] addressing mode
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vstr-bad-1.l
+
+.*: +file format .*arm.*
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:12: Error: bad element type for instruction -- `vstrb.s8 q0,\[r0,q1\]'
+[^:]*:13: Error: bad element type for instruction -- `vstrb.u8 q0,\[r0,q1\]'
+[^:]*:14: Error: bad element type for instruction -- `vstrb.s16 q0,\[r0,q1\]'
+[^:]*:15: Error: bad element type for instruction -- `vstrb.u16 q0,\[r0,q1\]'
+[^:]*:16: Error: bad element type for instruction -- `vstrb.f16 q0,\[r0,q1\]'
+[^:]*:17: Error: bad element type for instruction -- `vstrb.u32 q0,\[r0,q1\]'
+[^:]*:18: Error: bad element type for instruction -- `vstrb.s32 q0,\[r0,q1\]'
+[^:]*:19: Error: bad element type for instruction -- `vstrb.f32 q0,\[r0,q1\]'
+[^:]*:20: Error: bad element type for instruction -- `vstrb.64 q0,\[r0,q1\]'
+[^:]*:21: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:22: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:25: Error: bad element type for instruction -- `vstrh.8 q0,\[r0,q1\]'
+[^:]*:26: Error: bad element type for instruction -- `vstrh.s8 q0,\[r0,q1\]'
+[^:]*:27: Error: bad element type for instruction -- `vstrh.u8 q0,\[r0,q1\]'
+[^:]*:28: Error: bad element type for instruction -- `vstrh.s16 q0,\[r0,q1\]'
+[^:]*:29: Error: bad element type for instruction -- `vstrh.u16 q0,\[r0,q1\]'
+[^:]*:30: Error: bad element type for instruction -- `vstrh.f16 q0,\[r0,q1\]'
+[^:]*:31: Error: bad element type for instruction -- `vstrh.u32 q0,\[r0,q1\]'
+[^:]*:32: Error: bad element type for instruction -- `vstrh.s32 q0,\[r0,q1\]'
+[^:]*:33: Error: bad element type for instruction -- `vstrh.f32 q0,\[r0,q1\]'
+[^:]*:34: Error: bad element type for instruction -- `vstrh.64 q0,\[r0,q1\]'
+[^:]*:35: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:39: Error: shift expression expected -- `vstrh.16 q0,\[r0,q1,#1\]'
+[^:]*:40: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrh.16 q0,\[r0,q1,UXTW#2\]'
+[^:]*:41: Error: bad element type for instruction -- `vstrw.8 q0,\[r0,q1\]'
+[^:]*:42: Error: bad element type for instruction -- `vstrw.u8 q0,\[r0,q1\]'
+[^:]*:43: Error: bad element type for instruction -- `vstrw.s8 q0,\[r0,q1\]'
+[^:]*:44: Error: bad element type for instruction -- `vstrw.16 q0,\[r0,q1\]'
+[^:]*:45: Error: bad element type for instruction -- `vstrw.f16 q0,\[r0,q1\]'
+[^:]*:46: Error: bad element type for instruction -- `vstrw.u16 q0,\[r0,q1\]'
+[^:]*:47: Error: bad element type for instruction -- `vstrw.s16 q0,\[r0,q1\]'
+[^:]*:48: Error: bad element type for instruction -- `vstrw.u32 q0,\[r0,q1\]'
+[^:]*:49: Error: bad element type for instruction -- `vstrw.s32 q0,\[r0,q1\]'
+[^:]*:50: Error: bad element type for instruction -- `vstrw.f32 q0,\[r0,q1\]'
+[^:]*:51: Error: bad element type for instruction -- `vstrw.64 q0,\[r0,q1\]'
+[^:]*:52: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:53: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:53: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:53: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:53: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:53: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:53: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:56: Error: shift expression expected -- `vstrw.32 q0,\[r0,q1,#2\]'
+[^:]*:57: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrw.32 q0,\[r0,q1,UXTW#1\]'
+[^:]*:58: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrw.32 q0,\[r0,q1,UXTW#3\]'
+[^:]*:59: Error: bad element type for instruction -- `vstrd.8 q0,\[r0,q1\]'
+[^:]*:60: Error: bad element type for instruction -- `vstrd.u8 q0,\[r0,q1\]'
+[^:]*:61: Error: bad element type for instruction -- `vstrd.s8 q0,\[r0,q1\]'
+[^:]*:62: Error: bad element type for instruction -- `vstrd.16 q0,\[r0,q1\]'
+[^:]*:63: Error: bad element type for instruction -- `vstrd.u16 q0,\[r0,q1\]'
+[^:]*:64: Error: bad element type for instruction -- `vstrd.s16 q0,\[r0,q1\]'
+[^:]*:65: Error: bad element type for instruction -- `vstrd.f16 q0,\[r0,q1\]'
+[^:]*:66: Error: bad element type for instruction -- `vstrd.32 q0,\[r0,q1\]'
+[^:]*:67: Error: bad element type for instruction -- `vstrd.u32 q0,\[r0,q1\]'
+[^:]*:68: Error: bad element type for instruction -- `vstrd.s32 q0,\[r0,q1\]'
+[^:]*:69: Error: bad element type for instruction -- `vstrd.f32 q0,\[r0,q1\]'
+[^:]*:70: Error: bad element type for instruction -- `vstrd.f64 q0,\[r0,q1\]'
+[^:]*:71: Error: bad element type for instruction -- `vstrd.u64 q0,\[r0,q1\]'
+[^:]*:72: Error: bad element type for instruction -- `vstrd.s64 q0,\[r0,q1\]'
+[^:]*:83: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:83: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:83: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:83: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:83: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:83: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:84: Error: shift expression expected -- `vstrd.64 q0,\[r0,q1,#3\]'
+[^:]*:85: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrd.64 q0,\[r0,q1,UXTW#1\]'
+[^:]*:86: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrd.64 q0,\[r0,q1,UXTW#2\]'
+[^:]*:87: Error: shift immediate must be 1, 2 or 3 for half-word, word or double-word accesses respectively -- `vstrd.64 q0,\[r0,q1,UXTW#4\]'
+[^:]*:90: Error: syntax error -- `vstrbeq.32 q0,\[r0,q1\]'
+[^:]*:91: Error: syntax error -- `vstrbeq.32 q0,\[r0,q1\]'
+[^:]*:93: Error: syntax error -- `vstrbeq.32 q0,\[r0,q1\]'
+[^:]*:95: Error: instruction missing MVE vector predication code -- `vstrb.32 q0,\[r0,q1\]'
+[^:]*:96: Error: vector predicated instruction should be in VPT/VPST block -- `vstrbt.32 q0,\[r0,q1\]'
+[^:]*:97: Error: vector predicated instruction should be in VPT/VPST block -- `vstrbe.32 q0,\[r0,q1\]'
+[^:]*:99: Error: syntax error -- `vstrheq.32 q0,\[r0,q1\]'
+[^:]*:100: Error: syntax error -- `vstrheq.32 q0,\[r0,q1\]'
+[^:]*:102: Error: syntax error -- `vstrheq.32 q0,\[r0,q1\]'
+[^:]*:104: Error: instruction missing MVE vector predication code -- `vstrh.32 q0,\[r0,q1\]'
+[^:]*:105: Error: vector predicated instruction should be in VPT/VPST block -- `vstrht.32 q0,\[r0,q1\]'
+[^:]*:106: Error: vector predicated instruction should be in VPT/VPST block -- `vstrhe.32 q0,\[r0,q1\]'
+[^:]*:108: Error: syntax error -- `vstrweq.32 q0,\[r0,q1\]'
+[^:]*:109: Error: syntax error -- `vstrweq.32 q0,\[r0,q1\]'
+[^:]*:111: Error: syntax error -- `vstrweq.32 q0,\[r0,q1\]'
+[^:]*:113: Error: instruction missing MVE vector predication code -- `vstrw.32 q0,\[r0,q1\]'
+[^:]*:114: Error: vector predicated instruction should be in VPT/VPST block -- `vstrwt.32 q0,\[r0,q1\]'
+[^:]*:115: Error: vector predicated instruction should be in VPT/VPST block -- `vstrwe.32 q0,\[r0,q1\]'
+[^:]*:117: Error: syntax error -- `vstrdeq.64 q0,\[r0,q1\]'
+[^:]*:118: Error: syntax error -- `vstrdeq.64 q0,\[r0,q1\]'
+[^:]*:120: Error: syntax error -- `vstrdeq.64 q0,\[r0,q1\]'
+[^:]*:122: Error: instruction missing MVE vector predication code -- `vstrd.64 q0,\[r0,q1\]'
+[^:]*:123: Error: vector predicated instruction should be in VPT/VPST block -- `vstrdt.64 q0,\[r0,q1\]'
+[^:]*:124: Error: vector predicated instruction should be in VPT/VPST block -- `vstrde.64 q0,\[r0,q1\]'
--- /dev/null
+.macro cond mnem
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\mnem\().32 q0, [r0, q1]
+.endr
+.endm
+
+
+
+.syntax unified
+.thumb
+vstrb.s8 q0, [r0, q1]
+vstrb.u8 q0, [r0, q1]
+vstrb.s16 q0, [r0, q1]
+vstrb.u16 q0, [r0, q1]
+vstrb.f16 q0, [r0, q1]
+vstrb.u32 q0, [r0, q1]
+vstrb.s32 q0, [r0, q1]
+vstrb.f32 q0, [r0, q1]
+vstrb.64 q0, [r0, q1]
+vstrb.16 q0, [pc, q1]
+cond vstrb
+
+
+vstrh.8 q0, [r0, q1]
+vstrh.s8 q0, [r0, q1]
+vstrh.u8 q0, [r0, q1]
+vstrh.s16 q0, [r0, q1]
+vstrh.u16 q0, [r0, q1]
+vstrh.f16 q0, [r0, q1]
+vstrh.u32 q0, [r0, q1]
+vstrh.s32 q0, [r0, q1]
+vstrh.f32 q0, [r0, q1]
+vstrh.64 q0, [r0, q1]
+vstrh.16 q0, [pc, q1]
+cond vstrh
+
+
+vstrh.16 q0, [r0, q1, #1]
+vstrh.16 q0, [r0, q1, UXTW #2]
+vstrw.8 q0, [r0, q1]
+vstrw.u8 q0, [r0, q1]
+vstrw.s8 q0, [r0, q1]
+vstrw.16 q0, [r0, q1]
+vstrw.f16 q0, [r0, q1]
+vstrw.u16 q0, [r0, q1]
+vstrw.s16 q0, [r0, q1]
+vstrw.u32 q0, [r0, q1]
+vstrw.s32 q0, [r0, q1]
+vstrw.f32 q0, [r0, q1]
+vstrw.64 q0, [r0, q1]
+vstrw.32 q0, [pc, q1]
+cond vstrw
+
+
+vstrw.32 q0, [r0, q1, #2]
+vstrw.32 q0, [r0, q1, UXTW #1]
+vstrw.32 q0, [r0, q1, UXTW #3]
+vstrd.8 q0, [r0, q1]
+vstrd.u8 q0, [r0, q1]
+vstrd.s8 q0, [r0, q1]
+vstrd.16 q0, [r0, q1]
+vstrd.u16 q0, [r0, q1]
+vstrd.s16 q0, [r0, q1]
+vstrd.f16 q0, [r0, q1]
+vstrd.32 q0, [r0, q1]
+vstrd.u32 q0, [r0, q1]
+vstrd.s32 q0, [r0, q1]
+vstrd.f32 q0, [r0, q1]
+vstrd.f64 q0, [r0, q1]
+vstrd.u64 q0, [r0, q1]
+vstrd.s64 q0, [r0, q1]
+
+.macro cond64
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+vstrd\().64 q0, [r0, q1]
+.endr
+.endm
+
+
+
+cond64
+vstrd.64 q0, [r0, q1, #3]
+vstrd.64 q0, [r0, q1, UXTW #1]
+vstrd.64 q0, [r0, q1, UXTW #2]
+vstrd.64 q0, [r0, q1, UXTW #4]
+
+it eq
+vstrbeq.32 q0, [r0, q1]
+vstrbeq.32 q0, [r0, q1]
+vpst
+vstrbeq.32 q0, [r0, q1]
+vpst
+vstrb.32 q0, [r0, q1]
+vstrbt.32 q0, [r0, q1]
+vstrbe.32 q0, [r0, q1]
+it eq
+vstrheq.32 q0, [r0, q1]
+vstrheq.32 q0, [r0, q1]
+vpst
+vstrheq.32 q0, [r0, q1]
+vpst
+vstrh.32 q0, [r0, q1]
+vstrht.32 q0, [r0, q1]
+vstrhe.32 q0, [r0, q1]
+it eq
+vstrweq.32 q0, [r0, q1]
+vstrweq.32 q0, [r0, q1]
+vpst
+vstrweq.32 q0, [r0, q1]
+vpst
+vstrw.32 q0, [r0, q1]
+vstrwt.32 q0, [r0, q1]
+vstrwe.32 q0, [r0, q1]
+it eq
+vstrdeq.64 q0, [r0, q1]
+vstrdeq.64 q0, [r0, q1]
+vpst
+vstrdeq.64 q0, [r0, q1]
+vpst
+vstrd.64 q0, [r0, q1]
+vstrdt.64 q0, [r0, q1]
+vstrde.64 q0, [r0, q1]
--- /dev/null
+#name: bad MVE VSTR with [Q, #imm] addressing mode
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vstr-bad-2.l
+
+.*: +file format .*arm.*
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:10: Error: bad element type for instruction -- `vstrw.u16 q0,\[q1,#4\]'
+[^:]*:11: Error: bad element type for instruction -- `vstrw.u64 q0,\[q1,#-4\]'
+[^:]*:12: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.u32 q0,\[q1,#1\]'
+[^:]*:13: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.u32 q0,\[q1,#2\]'
+[^:]*:14: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.u32 q0,\[q1,#231\]'
+[^:]*:15: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.u32 q0,\[q1,#516\]'
+[^:]*:16: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.u32 q0,\[q1,#-516\]'
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:17: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:19: Error: syntax error -- `vstrweq.u32 q0,\[q1\]'
+[^:]*:20: Error: syntax error -- `vstrweq.u32 q0,\[q1\]'
+[^:]*:22: Error: syntax error -- `vstrweq.u32 q0,\[q1\]'
+[^:]*:23: Error: vector predicated instruction should be in VPT/VPST block -- `vstrwt.u32 q0,\[q1\]'
+[^:]*:25: Error: instruction missing MVE vector predication code -- `vstrw.u32 q0,\[q1\]'
+[^:]*:26: Error: bad element type for instruction -- `vstrd.u16 q0,\[q1,#8\]'
+[^:]*:27: Error: bad element type for instruction -- `vstrd.u32 q0,\[q1,#-8\]'
+[^:]*:28: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vstrd.u64 q0,\[q1,#1\]'
+[^:]*:29: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vstrd.u64 q0,\[q1,#4\]'
+[^:]*:30: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vstrd.u64 q0,\[q1,#7\]'
+[^:]*:31: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vstrd.u64 q0,\[q1,#228\]'
+[^:]*:32: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vstrd.u64 q0,\[q1,#1024\]'
+[^:]*:33: Error: immediate must be a multiple of 8 in the range of \+/-\[0,1016\] -- `vstrd.u64 q0,\[q1,#-1024\]'
+[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:36: Error: syntax error -- `vstrdeq.u64 q0,\[q1\]'
+[^:]*:37: Error: syntax error -- `vstrdeq.u64 q0,\[q1\]'
+[^:]*:39: Error: syntax error -- `vstrdeq.u64 q0,\[q1\]'
+[^:]*:40: Error: vector predicated instruction should be in VPT/VPST block -- `vstrdt.u64 q0,\[q1\]'
+[^:]*:42: Error: instruction missing MVE vector predication code -- `vstrd.u64 q0,\[q1\]'
--- /dev/null
+.macro cond mnem, size
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\mnem\().u\size q0, [q1, #8]
+.endr
+.endm
+
+.syntax unified
+.thumb
+vstrw.u16 q0, [q1, #4]
+vstrw.u64 q0, [q1, #-4]
+vstrw.u32 q0, [q1, #1]
+vstrw.u32 q0, [q1, #2]
+vstrw.u32 q0, [q1, #231]
+vstrw.u32 q0, [q1, #516]
+vstrw.u32 q0, [q1, #-516]
+cond vstrw, 32
+it eq
+vstrweq.u32 q0, [q1]
+vstrweq.u32 q0, [q1]
+vpst
+vstrweq.u32 q0, [q1]
+vstrwt.u32 q0, [q1]
+vpst
+vstrw.u32 q0, [q1]
+vstrd.u16 q0, [q1, #8]
+vstrd.u32 q0, [q1, #-8]
+vstrd.u64 q0, [q1, #1]
+vstrd.u64 q0, [q1, #4]
+vstrd.u64 q0, [q1, #7]
+vstrd.u64 q0, [q1, #228]
+vstrd.u64 q0, [q1, #1024]
+vstrd.u64 q0, [q1, #-1024]
+cond vstrd, 64
+it eq
+vstrdeq.u64 q0, [q1]
+vstrdeq.u64 q0, [q1]
+vpst
+vstrdeq.u64 q0, [q1]
+vstrdt.u64 q0, [q1]
+vpst
+vstrd.u64 q0, [q1]
+
--- /dev/null
+#name: bad MVE VSTR with [R, #imm] addressing mode
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vstr-bad-3.l
+
+.*: +file format .*arm.*
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:10: Error: immediate must be in the range of \+/-\[0,127\] -- `vstrb.8 q0,\[r0,#128\]'
+[^:]*:11: Error: immediate must be in the range of \+/-\[0,127\] -- `vstrb.8 q0,\[r0,#-128\]'
+[^:]*:12: Error: immediate must be in the range of \+/-\[0,127\] -- `vstrb.16 q0,\[r0,#128\]'
+[^:]*:13: Error: immediate must be in the range of \+/-\[0,127\] -- `vstrb.16 q0,\[r0,#-128\]'
+[^:]*:14: Error: immediate must be in the range of \+/-\[0,127\] -- `vstrb.32 q0,\[r0,#128\]'
+[^:]*:15: Error: immediate must be in the range of \+/-\[0,127\] -- `vstrb.32 q0,\[r0,#-128\]'
+[^:]*:16: Error: immediate must be in the range of \+/-\[0,127\] -- `vstrb.8 q0,\[r0,#128\]!'
+[^:]*:17: Error: immediate must be in the range of \+/-\[0,127\] -- `vstrb.8 q0,\[r0,#-128\]!'
+[^:]*:18: Error: immediate must be in the range of \+/-\[0,127\] -- `vstrb.16 q0,\[r0,#128\]!'
+[^:]*:19: Error: immediate must be in the range of \+/-\[0,127\] -- `vstrb.16 q0,\[r0,#-128\]!'
+[^:]*:20: Error: immediate must be in the range of \+/-\[0,127\] -- `vstrb.32 q0,\[r0,#128\]!'
+[^:]*:21: Error: immediate must be in the range of \+/-\[0,127\] -- `vstrb.32 q0,\[r0,#-128\]!'
+[^:]*:22: Error: immediate must be in the range of \+/-\[0,127\] -- `vstrb.8 q0,\[r0\],#128'
+[^:]*:23: Error: immediate must be in the range of \+/-\[0,127\] -- `vstrb.8 q0,\[r0\],#-128'
+[^:]*:24: Error: immediate must be in the range of \+/-\[0,127\] -- `vstrb.16 q0,\[r0\],#128'
+[^:]*:25: Error: immediate must be in the range of \+/-\[0,127\] -- `vstrb.16 q0,\[r0\],#-128'
+[^:]*:26: Error: immediate must be in the range of \+/-\[0,127\] -- `vstrb.32 q0,\[r0\],#128'
+[^:]*:27: Error: immediate must be in the range of \+/-\[0,127\] -- `vstrb.32 q0,\[r0\],#-128'
+[^:]*:28: Error: lo register required -- `vstrb.16 q0,\[r10,#2\]'
+[^:]*:29: Error: lo register required -- `vstrb.16 q0,\[r10,#2\]!'
+[^:]*:30: Error: lo register required -- `vstrb.16 q0,\[r10\],#2'
+[^:]*:31: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:32: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:33: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:34: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:35: Error: bad element type for instruction -- `vstrb.u16 q0,\[r0\]'
+[^:]*:36: Error: bad element type for instruction -- `vstrb.s16 q0,\[r0\]'
+[^:]*:37: Error: bad element type for instruction -- `vstrb.f16 q0,\[r0\]'
+[^:]*:38: Error: bad element type for instruction -- `vstrb.p16 q0,\[r0\]'
+[^:]*:39: Error: bad element type for instruction -- `vstrb.u32 q0,\[r0\]'
+[^:]*:40: Error: bad element type for instruction -- `vstrb.s32 q0,\[r0\]'
+[^:]*:41: Error: bad element type for instruction -- `vstrb.f32 q0,\[r0\]'
+[^:]*:42: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.16 q0,\[r0,#1\]'
+[^:]*:43: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.16 q0,\[r0,#17\]'
+[^:]*:44: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.16 q0,\[r0,#-17\]'
+[^:]*:45: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.16 q0,\[r0,#256\]'
+[^:]*:46: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.16 q0,\[r0,#-256\]'
+[^:]*:47: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.32 q0,\[r0,#1\]'
+[^:]*:48: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.32 q0,\[r0,#17\]'
+[^:]*:49: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.32 q0,\[r0,#-17\]'
+[^:]*:50: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.32 q0,\[r0,#256\]'
+[^:]*:51: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.32 q0,\[r0,#-256\]'
+[^:]*:52: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.16 q0,\[r0,#1\]!'
+[^:]*:53: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.16 q0,\[r0,#17\]!'
+[^:]*:54: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.16 q0,\[r0,#-17\]!'
+[^:]*:55: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.16 q0,\[r0,#256\]!'
+[^:]*:56: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.16 q0,\[r0,#-256\]!'
+[^:]*:57: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.32 q0,\[r0,#1\]!'
+[^:]*:58: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.32 q0,\[r0,#17\]!'
+[^:]*:59: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.32 q0,\[r0,#-17\]!'
+[^:]*:60: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.32 q0,\[r0,#256\]!'
+[^:]*:61: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.32 q0,\[r0,#-256\]!'
+[^:]*:62: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.16 q0,\[r0\],#1'
+[^:]*:63: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.16 q0,\[r0\],#17'
+[^:]*:64: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.16 q0,\[r0\],#-17'
+[^:]*:65: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.16 q0,\[r0\],#256'
+[^:]*:66: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.16 q0,\[r0\],#-256'
+[^:]*:67: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.32 q0,\[r0\],#1'
+[^:]*:68: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.32 q0,\[r0\],#17'
+[^:]*:69: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.32 q0,\[r0\],#-17'
+[^:]*:70: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.32 q0,\[r0\],#256'
+[^:]*:71: Error: immediate must be a multiple of 2 in the range of \+/-\[0,254\] -- `vstrh.32 q0,\[r0\],#-256'
+[^:]*:72: Error: lo register required -- `vstrh.32 q0,\[r10,#4\]'
+[^:]*:73: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:74: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:75: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:76: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:77: Error: bad element type for instruction -- `vstrh.8 q0,\[r0\]'
+[^:]*:78: Error: bad element type for instruction -- `vstrh.u8 q0,\[r0\]'
+[^:]*:79: Error: bad element type for instruction -- `vstrh.s8 q0,\[r0\]'
+[^:]*:80: Error: bad element type for instruction -- `vstrh.p8 q0,\[r0\]'
+[^:]*:81: Error: bad element type for instruction -- `vstrh.u32 q0,\[r0\]'
+[^:]*:82: Error: bad element type for instruction -- `vstrh.s32 q0,\[r0\]'
+[^:]*:83: Error: bad element type for instruction -- `vstrh.f32 q0,\[r0\]'
+[^:]*:84: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.32 q0,\[r0,#3\]'
+[^:]*:85: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.32 q0,\[r0,#-3\]'
+[^:]*:86: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.32 q0,\[r0,#514\]'
+[^:]*:87: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.32 q0,\[r0,#-258\]'
+[^:]*:88: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.32 q0,\[r0,#258\]'
+[^:]*:89: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.32 q0,\[r0,#516\]'
+[^:]*:90: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.32 q0,\[r0,#-516\]'
+[^:]*:91: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.32 q0,\[r0,#3\]!'
+[^:]*:92: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.32 q0,\[r0,#-3\]!'
+[^:]*:93: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.32 q0,\[r0,#514\]!'
+[^:]*:94: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.32 q0,\[r0,#-258\]!'
+[^:]*:95: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.32 q0,\[r0,#258\]!'
+[^:]*:96: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.32 q0,\[r0,#516\]!'
+[^:]*:97: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.32 q0,\[r0,#-516\]!'
+[^:]*:98: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.32 q0,\[r0\],#3'
+[^:]*:99: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.32 q0,\[r0\],#-3'
+[^:]*:100: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.32 q0,\[r0\],#514'
+[^:]*:101: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.32 q0,\[r0\],#-258'
+[^:]*:102: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.32 q0,\[r0\],#258'
+[^:]*:103: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.32 q0,\[r0\],#516'
+[^:]*:104: Error: immediate must be a multiple of 4 in the range of \+/-\[0,508\] -- `vstrw.32 q0,\[r0\],#-516'
+[^:]*:105: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:106: Warning: instruction is UNPREDICTABLE with PC operand
+[^:]*:107: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:107: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:107: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:107: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:107: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:107: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:108: Error: bad element type for instruction -- `vstrw.8 q0,\[r0\]'
+[^:]*:109: Error: bad element type for instruction -- `vstrw.u8 q0,\[r0\]'
+[^:]*:110: Error: bad element type for instruction -- `vstrw.s8 q0,\[r0\]'
+[^:]*:111: Error: bad element type for instruction -- `vstrw.p8 q0,\[r0\]'
+[^:]*:112: Error: bad element type for instruction -- `vstrw.16 q0,\[r0\]'
+[^:]*:113: Error: bad element type for instruction -- `vstrw.u16 q0,\[r0\]'
+[^:]*:114: Error: bad element type for instruction -- `vstrw.s16 q0,\[r0\]'
+[^:]*:115: Error: bad element type for instruction -- `vstrw.f16 q0,\[r0\]'
+[^:]*:116: Error: bad element type for instruction -- `vstrw.p16 q0,\[r0\]'
+[^:]*:118: Error: syntax error -- `vstrbeq.8 q0,\[r0\]'
+[^:]*:119: Error: syntax error -- `vstrbeq.8 q0,\[r0\]'
+[^:]*:121: Error: syntax error -- `vstrbeq.8 q0,\[r0\]'
+[^:]*:122: Error: vector predicated instruction should be in VPT/VPST block -- `vstrbt.8 q0,\[r0\]'
+[^:]*:124: Error: instruction missing MVE vector predication code -- `vstrb.8 q0,\[r0\]'
+[^:]*:126: Error: syntax error -- `vstrheq.16 q0,\[r0\]'
+[^:]*:127: Error: syntax error -- `vstrheq.16 q0,\[r0\]'
+[^:]*:129: Error: syntax error -- `vstrheq.16 q0,\[r0\]'
+[^:]*:130: Error: vector predicated instruction should be in VPT/VPST block -- `vstrht.16 q0,\[r0\]'
+[^:]*:132: Error: instruction missing MVE vector predication code -- `vstrh.16 q0,\[r0\]'
+[^:]*:134: Error: syntax error -- `vstrweq.32 q0,\[r0\]'
+[^:]*:135: Error: syntax error -- `vstrweq.32 q0,\[r0\]'
+[^:]*:137: Error: syntax error -- `vstrweq.32 q0,\[r0\]'
+[^:]*:138: Error: vector predicated instruction should be in VPT/VPST block -- `vstrwt.32 q0,\[r0\]'
+[^:]*:140: Error: instruction missing MVE vector predication code -- `vstrw.32 q0,\[r0\]'
--- /dev/null
+.macro cond mnem
+.irp cond, eq, ne, gt, ge, lt, le
+it \cond
+\mnem\().32 q0, [r0]
+.endr
+.endm
+
+.syntax unified
+.thumb
+vstrb.8 q0, [r0, #128]
+vstrb.8 q0, [r0, #-128]
+vstrb.16 q0, [r0, #128]
+vstrb.16 q0, [r0, #-128]
+vstrb.32 q0, [r0, #128]
+vstrb.32 q0, [r0, #-128]
+vstrb.8 q0, [r0, #128]!
+vstrb.8 q0, [r0, #-128]!
+vstrb.16 q0, [r0, #128]!
+vstrb.16 q0, [r0, #-128]!
+vstrb.32 q0, [r0, #128]!
+vstrb.32 q0, [r0, #-128]!
+vstrb.8 q0, [r0], #128
+vstrb.8 q0, [r0], #-128
+vstrb.16 q0, [r0], #128
+vstrb.16 q0, [r0], #-128
+vstrb.32 q0, [r0], #128
+vstrb.32 q0, [r0], #-128
+vstrb.16 q0, [r10, #2]
+vstrb.16 q0, [r10, #2]!
+vstrb.16 q0, [r10], #2
+vstrb.8 q0, [sp, #2]!
+vstrb.8 q0, [sp], #2
+vstrb.8 q0, [pc, #2]
+cond vstrb
+vstrb.u16 q0, [r0]
+vstrb.s16 q0, [r0]
+vstrb.f16 q0, [r0]
+vstrb.p16 q0, [r0]
+vstrb.u32 q0, [r0]
+vstrb.s32 q0, [r0]
+vstrb.f32 q0, [r0]
+vstrh.16 q0, [r0, #1]
+vstrh.16 q0, [r0, #17]
+vstrh.16 q0, [r0, #-17]
+vstrh.16 q0, [r0, #256]
+vstrh.16 q0, [r0, #-256]
+vstrh.32 q0, [r0, #1]
+vstrh.32 q0, [r0, #17]
+vstrh.32 q0, [r0, #-17]
+vstrh.32 q0, [r0, #256]
+vstrh.32 q0, [r0, #-256]
+vstrh.16 q0, [r0, #1]!
+vstrh.16 q0, [r0, #17]!
+vstrh.16 q0, [r0, #-17]!
+vstrh.16 q0, [r0, #256]!
+vstrh.16 q0, [r0, #-256]!
+vstrh.32 q0, [r0, #1]!
+vstrh.32 q0, [r0, #17]!
+vstrh.32 q0, [r0, #-17]!
+vstrh.32 q0, [r0, #256]!
+vstrh.32 q0, [r0, #-256]!
+vstrh.16 q0, [r0], #1
+vstrh.16 q0, [r0], #17
+vstrh.16 q0, [r0], #-17
+vstrh.16 q0, [r0], #256
+vstrh.16 q0, [r0], #-256
+vstrh.32 q0, [r0], #1
+vstrh.32 q0, [r0], #17
+vstrh.32 q0, [r0], #-17
+vstrh.32 q0, [r0], #256
+vstrh.32 q0, [r0], #-256
+vstrh.32 q0, [r10, #4]
+vstrh.16 q0, [sp, #2]!
+vstrh.16 q0, [sp], #2
+vstrh.16 q0, [pc, #2]
+cond vstrh
+vstrh.8 q0, [r0]
+vstrh.u8 q0, [r0]
+vstrh.s8 q0, [r0]
+vstrh.p8 q0, [r0]
+vstrh.u32 q0, [r0]
+vstrh.s32 q0, [r0]
+vstrh.f32 q0, [r0]
+vstrw.32 q0, [r0, #3]
+vstrw.32 q0, [r0, #-3]
+vstrw.32 q0, [r0, #514]
+vstrw.32 q0, [r0, #-258]
+vstrw.32 q0, [r0, #258]
+vstrw.32 q0, [r0, #516]
+vstrw.32 q0, [r0, #-516]
+vstrw.32 q0, [r0, #3]!
+vstrw.32 q0, [r0, #-3]!
+vstrw.32 q0, [r0, #514]!
+vstrw.32 q0, [r0, #-258]!
+vstrw.32 q0, [r0, #258]!
+vstrw.32 q0, [r0, #516]!
+vstrw.32 q0, [r0, #-516]!
+vstrw.32 q0, [r0], #3
+vstrw.32 q0, [r0], #-3
+vstrw.32 q0, [r0], #514
+vstrw.32 q0, [r0], #-258
+vstrw.32 q0, [r0], #258
+vstrw.32 q0, [r0], #516
+vstrw.32 q0, [r0], #-516
+vstrw.32 q0, [sp, #4]!
+vstrw.32 q0, [pc, #4]
+cond vstrw
+vstrw.8 q0, [r0]
+vstrw.u8 q0, [r0]
+vstrw.s8 q0, [r0]
+vstrw.p8 q0, [r0]
+vstrw.16 q0, [r0]
+vstrw.u16 q0, [r0]
+vstrw.s16 q0, [r0]
+vstrw.f16 q0, [r0]
+vstrw.p16 q0, [r0]
+it eq
+vstrbeq.8 q0, [r0]
+vstrbeq.8 q0, [r0]
+vpst
+vstrbeq.8 q0, [r0]
+vstrbt.8 q0, [r0]
+vpst
+vstrb.8 q0, [r0]
+it eq
+vstrheq.16 q0, [r0]
+vstrheq.16 q0, [r0]
+vpst
+vstrheq.16 q0, [r0]
+vstrht.16 q0, [r0]
+vpst
+vstrh.16 q0, [r0]
+it eq
+vstrweq.32 q0, [r0]
+vstrweq.32 q0, [r0]
+vpst
+vstrweq.32 q0, [r0]
+vstrwt.32 q0, [r0]
+vpst
+vstrw.32 q0, [r0]
projects / deliverable / binutils-gdb.git / commitdiff
