including CRIS v32, CGEN-based.
* configure.ac: Add corresponding configury.
* configure: Regenerate.
+2005-01-28 Hans-Peter Nilsson <hp@axis.com>
+
+ * cris: New directory, simulator for Axis Communications CRIS
+ including CRIS v32, CGEN-based.
+ * configure.ac: Add corresponding configury.
+ * configure: Regenerate.
+
2005-01-17 Andrew Cagney <cagney@gnu.org>
* configure.ac: For mips*-*-* and mn10300*-*-* configure the
ac_unique_file="Makefile.in"
ac_subdirs_all="$ac_subdirs_all arm"
+ac_subdirs_all="$ac_subdirs_all cris"
ac_subdirs_all="$ac_subdirs_all d10v"
ac_subdirs_all="$ac_subdirs_all frv"
ac_subdirs_all="$ac_subdirs_all h8300"
subdirs="$subdirs arm"
+ testsuite=yes
+ common=yes
+ ;;
+ cris-*-* | crisv32-*-*)
+
+
+subdirs="$subdirs cris"
+
testsuite=yes
common=yes
;;
testsuite=yes
common=yes
;;
+ cris-*-* | crisv32-*-*)
+ AC_CONFIG_SUBDIRS(cris)
+ testsuite=yes
+ common=yes
+ ;;
d10v-*-*)
AC_CONFIG_SUBDIRS(d10v)
;;
--- /dev/null
+# Makefile template for Configure for the CRIS simulator, based on a mix
+# of the ones for m32r and i960.
+#
+# Copyright (C) 2004, 2005 Free Software Foundation, Inc.
+# Contributed by Axis Communications.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+## COMMON_PRE_CONFIG_FRAG
+
+CRISV10F_OBJS = crisv10f.o cpuv10.o decodev10.o semcrisv10f-switch.o modelv10.o mloopv10f.o
+CRISV32F_OBJS = crisv32f.o cpuv32.o decodev32.o semcrisv32f-switch.o modelv32.o mloopv32f.o
+
+CONFIG_DEVICES = dv-sockser.o
+CONFIG_DEVICES =
+
+SIM_OBJS = \
+ $(SIM_NEW_COMMON_OBJS) \
+ sim-cpu.o \
+ sim-hload.o \
+ sim-hrw.o \
+ sim-model.o \
+ sim-reg.o \
+ cgen-utils.o cgen-trace.o cgen-scache.o \
+ cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
+ sim-if.o arch.o \
+ $(CRISV10F_OBJS) \
+ $(CRISV32F_OBJS) \
+ traps.o devices.o \
+ $(CONFIG_DEVICES) \
+ cris-desc.o
+
+# Extra headers included by sim-main.h.
+# FIXME: $(srccom)/cgen-ops.h should be in CGEN_INCLUDE_DEPS.
+SIM_EXTRA_DEPS = \
+ $(CGEN_INCLUDE_DEPS) $(srccom)/cgen-ops.h \
+ arch.h cpuall.h cris-sim.h cris-desc.h
+
+SIM_RUN_OBJS = nrun.o
+SIM_EXTRA_CLEAN = cris-clean
+
+# This selects the cris newlib/libgloss syscall definitions.
+NL_TARGET = -DNL_TARGET_cris
+
+## COMMON_POST_CONFIG_FRAG
+
+CGEN_CPU_DIR = $(CGENDIR)/../cpu
+
+arch = cris
+
+sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(sim-core_h) $(sim-options_h)
+
+arch.o: arch.c $(SIM_MAIN_DEPS)
+
+traps.o: traps.c targ-vals.h $(SIM_MAIN_DEPS) $(sim-options_h)
+devices.o: devices.c $(SIM_MAIN_DEPS)
+
+# CRISV10 objs
+
+CRISV10F_INCLUDE_DEPS = \
+ $(CGEN_MAIN_CPU_DEPS) \
+ cpuv10.h decodev10.h engv10.h
+
+crisv10f.o: crisv10f.c cris-tmpl.c $(CRISV10F_INCLUDE_DEPS)
+
+# FIXME: What is mono and what does "Use of `mono' is wip" mean (other
+# than the apparent; some "mono" feature is work in progress)?
+mloopv10f.c engv10.h: stamp-v10fmloop
+stamp-v10fmloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
+ $(SHELL) $(srccom)/genmloop.sh \
+ -mono -no-fast -pbb -switch semcrisv10f-switch.c \
+ -cpu crisv10f -infile $(srcdir)/mloop.in
+ $(SHELL) $(srcroot)/move-if-change eng.hin engv10.h
+ $(SHELL) $(srcroot)/move-if-change mloop.cin mloopv10f.c
+ touch stamp-v10fmloop
+mloopv10f.o: mloopv10f.c semcrisv10f-switch.c $(CRISV10F_INCLUDE_DEPS)
+
+cpuv10.o: cpuv10.c $(CRISV10F_INCLUDE_DEPS)
+decodev10.o: decodev10.c $(CRISV10F_INCLUDE_DEPS)
+semcrisv10f-switch.o: semcrisv10f-switch.c $(CRISV10F_INCLUDE_DEPS)
+modelv10.o: modelv10.c $(CRISV10F_INCLUDE_DEPS)
+
+# CRISV32 objs
+
+CRISV32F_INCLUDE_DEPS = \
+ $(CGEN_MAIN_CPU_DEPS) \
+ cpuv32.h decodev32.h engv32.h
+
+crisv32f.o: crisv32f.c cris-tmpl.c $(CRISV32F_INCLUDE_DEPS)
+
+# FIXME: What is mono and what does "Use of `mono' is wip" mean (other
+# than the apparent; some "mono" feature is work in progress)?
+mloopv32f.c engv32.h: stamp-v32fmloop
+stamp-v32fmloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
+ $(SHELL) $(srccom)/genmloop.sh \
+ -mono -no-fast -pbb -switch semcrisv32f-switch.c \
+ -cpu crisv32f -infile $(srcdir)/mloop.in
+ $(SHELL) $(srcroot)/move-if-change eng.hin engv32.h
+ $(SHELL) $(srcroot)/move-if-change mloop.cin mloopv32f.c
+ touch stamp-v32fmloop
+mloopv32f.o: mloopv32f.c semcrisv32f-switch.c $(CRISV32F_INCLUDE_DEPS)
+
+cpuv32.o: cpuv32.c $(CRISV32F_INCLUDE_DEPS)
+decodev32.o: decodev32.c $(CRISV32F_INCLUDE_DEPS)
+semcrisv32f-switch.o: semcrisv32f-switch.c $(CRISV32F_INCLUDE_DEPS)
+modelv32.o: modelv32.c $(CRISV32F_INCLUDE_DEPS)
+
+cris-clean:
+ for v in 10 32; do \
+ rm -f mloopv$${v}f.c engv$${v}.h stamp-v$${v}fmloop; \
+ rm -f stamp-v$${v}fcpu; \
+ done
+ -rm -f stamp-arch stamp-desc
+ -rm -f tmp-*
+
+# cgen support, enable with --enable-cgen-maint
+CGEN_MAINT = ; @true
+# The following line is commented in or out depending upon --enable-cgen-maint.
+@CGEN_MAINT@CGEN_MAINT =
+
+# Useful when making CGEN-generated files manually, without --enable-cgen-maint.
+stamps: stamp-v10fmloop stamp-v32fmloop stamp-arch stamp-v10fcpu stamp-v32fcpu stamp-desc
+
+stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CGEN_CPU_DIR)/cris.cpu Makefile
+ $(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=crisv10,crisv32 \
+ archfile=$(CGEN_CPU_DIR)/cris.cpu \
+ FLAGS="with-scache with-profile=fn"
+ touch stamp-arch
+arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
+
+stamp-v10fcpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/cris.cpu Makefile
+ $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
+ archfile=$(CGEN_CPU_DIR)/cris.cpu \
+ cpu=crisv10f mach=crisv10 SUFFIX=v10 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"
+ $(SHELL) $(srcroot)/move-if-change $(srcdir)/semv10-switch.c $(srcdir)/semcrisv10f-switch.c
+ touch stamp-v10fcpu
+cpuv10.h cpuv10.c semcrisv10f-switch.c modelv10.c decodev10.c decodev10.h: $(CGEN_MAINT) stamp-v10fcpu
+
+stamp-v32fcpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/cris.cpu Makefile
+ $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
+ archfile=$(CGEN_CPU_DIR)/cris.cpu \
+ cpu=crisv32f mach=crisv32 SUFFIX=v32 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"
+ $(SHELL) $(srcroot)/move-if-change $(srcdir)/semv32-switch.c $(srcdir)/semcrisv32f-switch.c
+ touch stamp-v32fcpu
+cpuv32.h cpuv32.c semcrisv32f-switch.c modelv32.c decodev32.c decodev32.h: $(CGEN_MAINT) stamp-v32fcpu
+
+stamp-desc: $(CGEN_READ_SCM) $(CGEN_DESC_SCM) $(CGEN_CPU_DIR)/cris.cpu Makefile
+ $(MAKE) cgen-desc $(CGEN_FLAGS_TO_PASS) \
+ archfile=$(CGEN_CPU_DIR)/cris.cpu \
+ cpu=cris mach=all
+ touch stamp-desc
+cris-desc.c cris-desc.h cris-opc.h: $(CGEN_MAINT) stamp-desc
--- /dev/null
+/* Simulator support for cris.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2004 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#include "sim-main.h"
+#include "bfd.h"
+
+const MACH *sim_machs[] =
+{
+#ifdef HAVE_CPU_CRISV10F
+ & crisv10_mach,
+#endif
+#ifdef HAVE_CPU_CRISV32F
+ & crisv32_mach,
+#endif
+ 0
+};
+
--- /dev/null
+/* Simulator header for cris.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2004 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef CRIS_ARCH_H
+#define CRIS_ARCH_H
+
+#define TARGET_BIG_ENDIAN 1
+
+/* Enum declaration for model types. */
+typedef enum model_type {
+ MODEL_CRISV10, MODEL_CRISV32, MODEL_MAX
+} MODEL_TYPE;
+
+#define MAX_MODELS ((int) MODEL_MAX)
+
+/* Enum declaration for unit types. */
+typedef enum unit_type {
+ UNIT_NONE, UNIT_CRISV10_U_MOVEM, UNIT_CRISV10_U_MULTIPLY, UNIT_CRISV10_U_SKIP4
+ , UNIT_CRISV10_U_STALL, UNIT_CRISV10_U_CONST32, UNIT_CRISV10_U_CONST16, UNIT_CRISV10_U_MEM
+ , UNIT_CRISV10_U_EXEC, UNIT_CRISV32_U_EXEC_TO_SR, UNIT_CRISV32_U_EXEC_MOVEM, UNIT_CRISV32_U_EXEC
+ , UNIT_CRISV32_U_SKIP4, UNIT_CRISV32_U_CONST32, UNIT_CRISV32_U_CONST16, UNIT_CRISV32_U_JUMP
+ , UNIT_CRISV32_U_JUMP_SR, UNIT_CRISV32_U_JUMP_R, UNIT_CRISV32_U_BRANCH, UNIT_CRISV32_U_MULTIPLY
+ , UNIT_CRISV32_U_MOVEM_MTOR, UNIT_CRISV32_U_MOVEM_RTOM, UNIT_CRISV32_U_MEM_W, UNIT_CRISV32_U_MEM_R
+ , UNIT_CRISV32_U_MEM, UNIT_MAX
+} UNIT_TYPE;
+
+#define MAX_UNITS (4)
+
+#endif /* CRIS_ARCH_H */
--- /dev/null
+#! /bin/sh
+# Guess values for system-dependent variables and create Makefiles.
+# Generated by GNU Autoconf 2.59.
+#
+# Copyright (C) 2003 Free Software Foundation, Inc.
+# This configure script is free software; the Free Software Foundation
+# gives unlimited permission to copy, distribute and modify it.
+## --------------------- ##
+## M4sh Initialization. ##
+## --------------------- ##
+
+# Be Bourne compatible
+if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then
+ emulate sh
+ NULLCMD=:
+ # Zsh 3.x and 4.x performs word splitting on ${1+"$@"}, which
+ # is contrary to our usage. Disable this feature.
+ alias -g '${1+"$@"}'='"$@"'
+elif test -n "${BASH_VERSION+set}" && (set -o posix) >/dev/null 2>&1; then
+ set -o posix
+fi
+DUALCASE=1; export DUALCASE # for MKS sh
+
+# Support unset when possible.
+if ( (MAIL=60; unset MAIL) || exit) >/dev/null 2>&1; then
+ as_unset=unset
+else
+ as_unset=false
+fi
+
+
+# Work around bugs in pre-3.0 UWIN ksh.
+$as_unset ENV MAIL MAILPATH
+PS1='$ '
+PS2='> '
+PS4='+ '
+
+# NLS nuisances.
+for as_var in \
+ LANG LANGUAGE LC_ADDRESS LC_ALL LC_COLLATE LC_CTYPE LC_IDENTIFICATION \
+ LC_MEASUREMENT LC_MESSAGES LC_MONETARY LC_NAME LC_NUMERIC LC_PAPER \
+ LC_TELEPHONE LC_TIME
+do
+ if (set +x; test -z "`(eval $as_var=C; export $as_var) 2>&1`"); then
+ eval $as_var=C; export $as_var
+ else
+ $as_unset $as_var
+ fi
+done
+
+# Required to use basename.
+if expr a : '\(a\)' >/dev/null 2>&1; then
+ as_expr=expr
+else
+ as_expr=false
+fi
+
+if (basename /) >/dev/null 2>&1 && test "X`basename / 2>&1`" = "X/"; then
+ as_basename=basename
+else
+ as_basename=false
+fi
+
+
+# Name of the executable.
+as_me=`$as_basename "$0" ||
+$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
+ X"$0" : 'X\(//\)$' \| \
+ X"$0" : 'X\(/\)$' \| \
+ . : '\(.\)' 2>/dev/null ||
+echo X/"$0" |
+ sed '/^.*\/\([^/][^/]*\)\/*$/{ s//\1/; q; }
+ /^X\/\(\/\/\)$/{ s//\1/; q; }
+ /^X\/\(\/\).*/{ s//\1/; q; }
+ s/.*/./; q'`
+
+
+# PATH needs CR, and LINENO needs CR and PATH.
+# Avoid depending upon Character Ranges.
+as_cr_letters='abcdefghijklmnopqrstuvwxyz'
+as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
+as_cr_Letters=$as_cr_letters$as_cr_LETTERS
+as_cr_digits='0123456789'
+as_cr_alnum=$as_cr_Letters$as_cr_digits
+
+# The user is always right.
+if test "${PATH_SEPARATOR+set}" != set; then
+ echo "#! /bin/sh" >conf$$.sh
+ echo "exit 0" >>conf$$.sh
+ chmod +x conf$$.sh
+ if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then
+ PATH_SEPARATOR=';'
+ else
+ PATH_SEPARATOR=:
+ fi
+ rm -f conf$$.sh
+fi
+
+
+ as_lineno_1=$LINENO
+ as_lineno_2=$LINENO
+ as_lineno_3=`(expr $as_lineno_1 + 1) 2>/dev/null`
+ test "x$as_lineno_1" != "x$as_lineno_2" &&
+ test "x$as_lineno_3" = "x$as_lineno_2" || {
+ # Find who we are. Look in the path if we contain no path at all
+ # relative or not.
+ case $0 in
+ *[\\/]* ) as_myself=$0 ;;
+ *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
+done
+
+ ;;
+ esac
+ # We did not find ourselves, most probably we were run as `sh COMMAND'
+ # in which case we are not to be found in the path.
+ if test "x$as_myself" = x; then
+ as_myself=$0
+ fi
+ if test ! -f "$as_myself"; then
+ { echo "$as_me: error: cannot find myself; rerun with an absolute path" >&2
+ { (exit 1); exit 1; }; }
+ fi
+ case $CONFIG_SHELL in
+ '')
+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for as_base in sh bash ksh sh5; do
+ case $as_dir in
+ /*)
+ if ("$as_dir/$as_base" -c '
+ as_lineno_1=$LINENO
+ as_lineno_2=$LINENO
+ as_lineno_3=`(expr $as_lineno_1 + 1) 2>/dev/null`
+ test "x$as_lineno_1" != "x$as_lineno_2" &&
+ test "x$as_lineno_3" = "x$as_lineno_2" ') 2>/dev/null; then
+ $as_unset BASH_ENV || test "${BASH_ENV+set}" != set || { BASH_ENV=; export BASH_ENV; }
+ $as_unset ENV || test "${ENV+set}" != set || { ENV=; export ENV; }
+ CONFIG_SHELL=$as_dir/$as_base
+ export CONFIG_SHELL
+ exec "$CONFIG_SHELL" "$0" ${1+"$@"}
+ fi;;
+ esac
+ done
+done
+;;
+ esac
+
+ # Create $as_me.lineno as a copy of $as_myself, but with $LINENO
+ # uniformly replaced by the line number. The first 'sed' inserts a
+ # line-number line before each line; the second 'sed' does the real
+ # work. The second script uses 'N' to pair each line-number line
+ # with the numbered line, and appends trailing '-' during
+ # substitution so that $LINENO is not a special case at line end.
+ # (Raja R Harinath suggested sed '=', and Paul Eggert wrote the
+ # second 'sed' script. Blame Lee E. McMahon for sed's syntax. :-)
+ sed '=' <$as_myself |
+ sed '
+ N
+ s,$,-,
+ : loop
+ s,^\(['$as_cr_digits']*\)\(.*\)[$]LINENO\([^'$as_cr_alnum'_]\),\1\2\1\3,
+ t loop
+ s,-$,,
+ s,^['$as_cr_digits']*\n,,
+ ' >$as_me.lineno &&
+ chmod +x $as_me.lineno ||
+ { echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2
+ { (exit 1); exit 1; }; }
+
+ # Don't try to exec as it changes $[0], causing all sort of problems
+ # (the dirname of $[0] is not the place where we might find the
+ # original and so on. Autoconf is especially sensible to this).
+ . ./$as_me.lineno
+ # Exit status is that of the last command.
+ exit
+}
+
+
+case `echo "testing\c"; echo 1,2,3`,`echo -n testing; echo 1,2,3` in
+ *c*,-n*) ECHO_N= ECHO_C='
+' ECHO_T=' ' ;;
+ *c*,* ) ECHO_N=-n ECHO_C= ECHO_T= ;;
+ *) ECHO_N= ECHO_C='\c' ECHO_T= ;;
+esac
+
+if expr a : '\(a\)' >/dev/null 2>&1; then
+ as_expr=expr
+else
+ as_expr=false
+fi
+
+rm -f conf$$ conf$$.exe conf$$.file
+echo >conf$$.file
+if ln -s conf$$.file conf$$ 2>/dev/null; then
+ # We could just check for DJGPP; but this test a) works b) is more generic
+ # and c) will remain valid once DJGPP supports symlinks (DJGPP 2.04).
+ if test -f conf$$.exe; then
+ # Don't use ln at all; we don't have any links
+ as_ln_s='cp -p'
+ else
+ as_ln_s='ln -s'
+ fi
+elif ln conf$$.file conf$$ 2>/dev/null; then
+ as_ln_s=ln
+else
+ as_ln_s='cp -p'
+fi
+rm -f conf$$ conf$$.exe conf$$.file
+
+if mkdir -p . 2>/dev/null; then
+ as_mkdir_p=:
+else
+ test -d ./-p && rmdir ./-p
+ as_mkdir_p=false
+fi
+
+as_executable_p="test -f"
+
+# Sed expression to map a string onto a valid CPP name.
+as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'"
+
+# Sed expression to map a string onto a valid variable name.
+as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'"
+
+
+# IFS
+# We need space, tab and new line, in precisely that order.
+as_nl='
+'
+IFS=" $as_nl"
+
+# CDPATH.
+$as_unset CDPATH
+
+
+# Name of the host.
+# hostname on some systems (SVR3.2, Linux) returns a bogus exit status,
+# so uname gets run too.
+ac_hostname=`(hostname || uname -n) 2>/dev/null | sed 1q`
+
+exec 6>&1
+
+#
+# Initializations.
+#
+ac_default_prefix=/usr/local
+ac_config_libobj_dir=.
+cross_compiling=no
+subdirs=
+MFLAGS=
+MAKEFLAGS=
+SHELL=${CONFIG_SHELL-/bin/sh}
+
+# Maximum number of lines to put in a shell here document.
+# This variable seems obsolete. It should probably be removed, and
+# only ac_max_sed_lines should be used.
+: ${ac_max_here_lines=38}
+
+# Identity of this package.
+PACKAGE_NAME=
+PACKAGE_TARNAME=
+PACKAGE_VERSION=
+PACKAGE_STRING=
+PACKAGE_BUGREPORT=
+
+ac_unique_file="Makefile.in"
+# Factoring default headers for most tests.
+ac_includes_default="\
+#include <stdio.h>
+#if HAVE_SYS_TYPES_H
+# include <sys/types.h>
+#endif
+#if HAVE_SYS_STAT_H
+# include <sys/stat.h>
+#endif
+#if STDC_HEADERS
+# include <stdlib.h>
+# include <stddef.h>
+#else
+# if HAVE_STDLIB_H
+# include <stdlib.h>
+# endif
+#endif
+#if HAVE_STRING_H
+# if !STDC_HEADERS && HAVE_MEMORY_H
+# include <memory.h>
+# endif
+# include <string.h>
+#endif
+#if HAVE_STRINGS_H
+# include <strings.h>
+#endif
+#if HAVE_INTTYPES_H
+# include <inttypes.h>
+#else
+# if HAVE_STDINT_H
+# include <stdint.h>
+# endif
+#endif
+#if HAVE_UNISTD_H
+# include <unistd.h>
+#endif"
+
+ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS sim_environment sim_alignment sim_assert sim_bitsize sim_endian sim_hostendian sim_float sim_scache sim_default_model sim_hw_cflags sim_hw_objs sim_hw sim_inline sim_packages sim_regparm sim_reserved_bits sim_smp sim_stdcall sim_xor_endian WARN_CFLAGS WERROR_CFLAGS build build_cpu build_vendor build_os host host_cpu host_vendor host_os target target_cpu target_vendor target_os CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA CC_FOR_BUILD HDEFINES AR RANLIB ac_ct_RANLIB SET_MAKE CPP EGREP ALLOCA USE_NLS MSGFMT GMSGFMT XGETTEXT USE_INCLUDED_LIBINTL CATALOGS CATOBJEXT DATADIRNAME GMOFILES INSTOBJEXT INTLDEPS INTLLIBS INTLOBJS POFILES POSUB INCLUDE_LOCALE_H GT_NO GT_YES MKINSTALLDIRS l MAINT sim_bswap sim_cflags sim_debug sim_stdio sim_trace sim_profile CGEN_MAINT cgendir cgen cgen_breaks LIBOBJS LTLIBOBJS'
+ac_subst_files=''
+
+# Initialize some variables set by options.
+ac_init_help=
+ac_init_version=false
+# The variables have the same names as the options, with
+# dashes changed to underlines.
+cache_file=/dev/null
+exec_prefix=NONE
+no_create=
+no_recursion=
+prefix=NONE
+program_prefix=NONE
+program_suffix=NONE
+program_transform_name=s,x,x,
+silent=
+site=
+srcdir=
+verbose=
+x_includes=NONE
+x_libraries=NONE
+
+# Installation directory options.
+# These are left unexpanded so users can "make install exec_prefix=/foo"
+# and all the variables that are supposed to be based on exec_prefix
+# by default will actually change.
+# Use braces instead of parens because sh, perl, etc. also accept them.
+bindir='${exec_prefix}/bin'
+sbindir='${exec_prefix}/sbin'
+libexecdir='${exec_prefix}/libexec'
+datadir='${prefix}/share'
+sysconfdir='${prefix}/etc'
+sharedstatedir='${prefix}/com'
+localstatedir='${prefix}/var'
+libdir='${exec_prefix}/lib'
+includedir='${prefix}/include'
+oldincludedir='/usr/include'
+infodir='${prefix}/info'
+mandir='${prefix}/man'
+
+ac_prev=
+for ac_option
+do
+ # If the previous option needs an argument, assign it.
+ if test -n "$ac_prev"; then
+ eval "$ac_prev=\$ac_option"
+ ac_prev=
+ continue
+ fi
+
+ ac_optarg=`expr "x$ac_option" : 'x[^=]*=\(.*\)'`
+
+ # Accept the important Cygnus configure options, so we can diagnose typos.
+
+ case $ac_option in
+
+ -bindir | --bindir | --bindi | --bind | --bin | --bi)
+ ac_prev=bindir ;;
+ -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*)
+ bindir=$ac_optarg ;;
+
+ -build | --build | --buil | --bui | --bu)
+ ac_prev=build_alias ;;
+ -build=* | --build=* | --buil=* | --bui=* | --bu=*)
+ build_alias=$ac_optarg ;;
+
+ -cache-file | --cache-file | --cache-fil | --cache-fi \
+ | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c)
+ ac_prev=cache_file ;;
+ -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \
+ | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*)
+ cache_file=$ac_optarg ;;
+
+ --config-cache | -C)
+ cache_file=config.cache ;;
+
+ -datadir | --datadir | --datadi | --datad | --data | --dat | --da)
+ ac_prev=datadir ;;
+ -datadir=* | --datadir=* | --datadi=* | --datad=* | --data=* | --dat=* \
+ | --da=*)
+ datadir=$ac_optarg ;;
+
+ -disable-* | --disable-*)
+ ac_feature=`expr "x$ac_option" : 'x-*disable-\(.*\)'`
+ # Reject names that are not valid shell variable names.
+ expr "x$ac_feature" : ".*[^-_$as_cr_alnum]" >/dev/null &&
+ { echo "$as_me: error: invalid feature name: $ac_feature" >&2
+ { (exit 1); exit 1; }; }
+ ac_feature=`echo $ac_feature | sed 's/-/_/g'`
+ eval "enable_$ac_feature=no" ;;
+
+ -enable-* | --enable-*)
+ ac_feature=`expr "x$ac_option" : 'x-*enable-\([^=]*\)'`
+ # Reject names that are not valid shell variable names.
+ expr "x$ac_feature" : ".*[^-_$as_cr_alnum]" >/dev/null &&
+ { echo "$as_me: error: invalid feature name: $ac_feature" >&2
+ { (exit 1); exit 1; }; }
+ ac_feature=`echo $ac_feature | sed 's/-/_/g'`
+ case $ac_option in
+ *=*) ac_optarg=`echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"`;;
+ *) ac_optarg=yes ;;
+ esac
+ eval "enable_$ac_feature='$ac_optarg'" ;;
+
+ -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \
+ | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \
+ | --exec | --exe | --ex)
+ ac_prev=exec_prefix ;;
+ -exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \
+ | --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \
+ | --exec=* | --exe=* | --ex=*)
+ exec_prefix=$ac_optarg ;;
+
+ -gas | --gas | --ga | --g)
+ # Obsolete; use --with-gas.
+ with_gas=yes ;;
+
+ -help | --help | --hel | --he | -h)
+ ac_init_help=long ;;
+ -help=r* | --help=r* | --hel=r* | --he=r* | -hr*)
+ ac_init_help=recursive ;;
+ -help=s* | --help=s* | --hel=s* | --he=s* | -hs*)
+ ac_init_help=short ;;
+
+ -host | --host | --hos | --ho)
+ ac_prev=host_alias ;;
+ -host=* | --host=* | --hos=* | --ho=*)
+ host_alias=$ac_optarg ;;
+
+ -includedir | --includedir | --includedi | --included | --include \
+ | --includ | --inclu | --incl | --inc)
+ ac_prev=includedir ;;
+ -includedir=* | --includedir=* | --includedi=* | --included=* | --include=* \
+ | --includ=* | --inclu=* | --incl=* | --inc=*)
+ includedir=$ac_optarg ;;
+
+ -infodir | --infodir | --infodi | --infod | --info | --inf)
+ ac_prev=infodir ;;
+ -infodir=* | --infodir=* | --infodi=* | --infod=* | --info=* | --inf=*)
+ infodir=$ac_optarg ;;
+
+ -libdir | --libdir | --libdi | --libd)
+ ac_prev=libdir ;;
+ -libdir=* | --libdir=* | --libdi=* | --libd=*)
+ libdir=$ac_optarg ;;
+
+ -libexecdir | --libexecdir | --libexecdi | --libexecd | --libexec \
+ | --libexe | --libex | --libe)
+ ac_prev=libexecdir ;;
+ -libexecdir=* | --libexecdir=* | --libexecdi=* | --libexecd=* | --libexec=* \
+ | --libexe=* | --libex=* | --libe=*)
+ libexecdir=$ac_optarg ;;
+
+ -localstatedir | --localstatedir | --localstatedi | --localstated \
+ | --localstate | --localstat | --localsta | --localst \
+ | --locals | --local | --loca | --loc | --lo)
+ ac_prev=localstatedir ;;
+ -localstatedir=* | --localstatedir=* | --localstatedi=* | --localstated=* \
+ | --localstate=* | --localstat=* | --localsta=* | --localst=* \
+ | --locals=* | --local=* | --loca=* | --loc=* | --lo=*)
+ localstatedir=$ac_optarg ;;
+
+ -mandir | --mandir | --mandi | --mand | --man | --ma | --m)
+ ac_prev=mandir ;;
+ -mandir=* | --mandir=* | --mandi=* | --mand=* | --man=* | --ma=* | --m=*)
+ mandir=$ac_optarg ;;
+
+ -nfp | --nfp | --nf)
+ # Obsolete; use --without-fp.
+ with_fp=no ;;
+
+ -no-create | --no-create | --no-creat | --no-crea | --no-cre \
+ | --no-cr | --no-c | -n)
+ no_create=yes ;;
+
+ -no-recursion | --no-recursion | --no-recursio | --no-recursi \
+ | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r)
+ no_recursion=yes ;;
+
+ -oldincludedir | --oldincludedir | --oldincludedi | --oldincluded \
+ | --oldinclude | --oldinclud | --oldinclu | --oldincl | --oldinc \
+ | --oldin | --oldi | --old | --ol | --o)
+ ac_prev=oldincludedir ;;
+ -oldincludedir=* | --oldincludedir=* | --oldincludedi=* | --oldincluded=* \
+ | --oldinclude=* | --oldinclud=* | --oldinclu=* | --oldincl=* | --oldinc=* \
+ | --oldin=* | --oldi=* | --old=* | --ol=* | --o=*)
+ oldincludedir=$ac_optarg ;;
+
+ -prefix | --prefix | --prefi | --pref | --pre | --pr | --p)
+ ac_prev=prefix ;;
+ -prefix=* | --prefix=* | --prefi=* | --pref=* | --pre=* | --pr=* | --p=*)
+ prefix=$ac_optarg ;;
+
+ -program-prefix | --program-prefix | --program-prefi | --program-pref \
+ | --program-pre | --program-pr | --program-p)
+ ac_prev=program_prefix ;;
+ -program-prefix=* | --program-prefix=* | --program-prefi=* \
+ | --program-pref=* | --program-pre=* | --program-pr=* | --program-p=*)
+ program_prefix=$ac_optarg ;;
+
+ -program-suffix | --program-suffix | --program-suffi | --program-suff \
+ | --program-suf | --program-su | --program-s)
+ ac_prev=program_suffix ;;
+ -program-suffix=* | --program-suffix=* | --program-suffi=* \
+ | --program-suff=* | --program-suf=* | --program-su=* | --program-s=*)
+ program_suffix=$ac_optarg ;;
+
+ -program-transform-name | --program-transform-name \
+ | --program-transform-nam | --program-transform-na \
+ | --program-transform-n | --program-transform- \
+ | --program-transform | --program-transfor \
+ | --program-transfo | --program-transf \
+ | --program-trans | --program-tran \
+ | --progr-tra | --program-tr | --program-t)
+ ac_prev=program_transform_name ;;
+ -program-transform-name=* | --program-transform-name=* \
+ | --program-transform-nam=* | --program-transform-na=* \
+ | --program-transform-n=* | --program-transform-=* \
+ | --program-transform=* | --program-transfor=* \
+ | --program-transfo=* | --program-transf=* \
+ | --program-trans=* | --program-tran=* \
+ | --progr-tra=* | --program-tr=* | --program-t=*)
+ program_transform_name=$ac_optarg ;;
+
+ -q | -quiet | --quiet | --quie | --qui | --qu | --q \
+ | -silent | --silent | --silen | --sile | --sil)
+ silent=yes ;;
+
+ -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
+ ac_prev=sbindir ;;
+ -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
+ | --sbi=* | --sb=*)
+ sbindir=$ac_optarg ;;
+
+ -sharedstatedir | --sharedstatedir | --sharedstatedi \
+ | --sharedstated | --sharedstate | --sharedstat | --sharedsta \
+ | --sharedst | --shareds | --shared | --share | --shar \
+ | --sha | --sh)
+ ac_prev=sharedstatedir ;;
+ -sharedstatedir=* | --sharedstatedir=* | --sharedstatedi=* \
+ | --sharedstated=* | --sharedstate=* | --sharedstat=* | --sharedsta=* \
+ | --sharedst=* | --shareds=* | --shared=* | --share=* | --shar=* \
+ | --sha=* | --sh=*)
+ sharedstatedir=$ac_optarg ;;
+
+ -site | --site | --sit)
+ ac_prev=site ;;
+ -site=* | --site=* | --sit=*)
+ site=$ac_optarg ;;
+
+ -srcdir | --srcdir | --srcdi | --srcd | --src | --sr)
+ ac_prev=srcdir ;;
+ -srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*)
+ srcdir=$ac_optarg ;;
+
+ -sysconfdir | --sysconfdir | --sysconfdi | --sysconfd | --sysconf \
+ | --syscon | --sysco | --sysc | --sys | --sy)
+ ac_prev=sysconfdir ;;
+ -sysconfdir=* | --sysconfdir=* | --sysconfdi=* | --sysconfd=* | --sysconf=* \
+ | --syscon=* | --sysco=* | --sysc=* | --sys=* | --sy=*)
+ sysconfdir=$ac_optarg ;;
+
+ -target | --target | --targe | --targ | --tar | --ta | --t)
+ ac_prev=target_alias ;;
+ -target=* | --target=* | --targe=* | --targ=* | --tar=* | --ta=* | --t=*)
+ target_alias=$ac_optarg ;;
+
+ -v | -verbose | --verbose | --verbos | --verbo | --verb)
+ verbose=yes ;;
+
+ -version | --version | --versio | --versi | --vers | -V)
+ ac_init_version=: ;;
+
+ -with-* | --with-*)
+ ac_package=`expr "x$ac_option" : 'x-*with-\([^=]*\)'`
+ # Reject names that are not valid shell variable names.
+ expr "x$ac_package" : ".*[^-_$as_cr_alnum]" >/dev/null &&
+ { echo "$as_me: error: invalid package name: $ac_package" >&2
+ { (exit 1); exit 1; }; }
+ ac_package=`echo $ac_package| sed 's/-/_/g'`
+ case $ac_option in
+ *=*) ac_optarg=`echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"`;;
+ *) ac_optarg=yes ;;
+ esac
+ eval "with_$ac_package='$ac_optarg'" ;;
+
+ -without-* | --without-*)
+ ac_package=`expr "x$ac_option" : 'x-*without-\(.*\)'`
+ # Reject names that are not valid shell variable names.
+ expr "x$ac_package" : ".*[^-_$as_cr_alnum]" >/dev/null &&
+ { echo "$as_me: error: invalid package name: $ac_package" >&2
+ { (exit 1); exit 1; }; }
+ ac_package=`echo $ac_package | sed 's/-/_/g'`
+ eval "with_$ac_package=no" ;;
+
+ --x)
+ # Obsolete; use --with-x.
+ with_x=yes ;;
+
+ -x-includes | --x-includes | --x-include | --x-includ | --x-inclu \
+ | --x-incl | --x-inc | --x-in | --x-i)
+ ac_prev=x_includes ;;
+ -x-includes=* | --x-includes=* | --x-include=* | --x-includ=* | --x-inclu=* \
+ | --x-incl=* | --x-inc=* | --x-in=* | --x-i=*)
+ x_includes=$ac_optarg ;;
+
+ -x-libraries | --x-libraries | --x-librarie | --x-librari \
+ | --x-librar | --x-libra | --x-libr | --x-lib | --x-li | --x-l)
+ ac_prev=x_libraries ;;
+ -x-libraries=* | --x-libraries=* | --x-librarie=* | --x-librari=* \
+ | --x-librar=* | --x-libra=* | --x-libr=* | --x-lib=* | --x-li=* | --x-l=*)
+ x_libraries=$ac_optarg ;;
+
+ -*) { echo "$as_me: error: unrecognized option: $ac_option
+Try \`$0 --help' for more information." >&2
+ { (exit 1); exit 1; }; }
+ ;;
+
+ *=*)
+ ac_envvar=`expr "x$ac_option" : 'x\([^=]*\)='`
+ # Reject names that are not valid shell variable names.
+ expr "x$ac_envvar" : ".*[^_$as_cr_alnum]" >/dev/null &&
+ { echo "$as_me: error: invalid variable name: $ac_envvar" >&2
+ { (exit 1); exit 1; }; }
+ ac_optarg=`echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"`
+ eval "$ac_envvar='$ac_optarg'"
+ export $ac_envvar ;;
+
+ *)
+ # FIXME: should be removed in autoconf 3.0.
+ echo "$as_me: WARNING: you should use --build, --host, --target" >&2
+ expr "x$ac_option" : ".*[^-._$as_cr_alnum]" >/dev/null &&
+ echo "$as_me: WARNING: invalid host type: $ac_option" >&2
+ : ${build_alias=$ac_option} ${host_alias=$ac_option} ${target_alias=$ac_option}
+ ;;
+
+ esac
+done
+
+if test -n "$ac_prev"; then
+ ac_option=--`echo $ac_prev | sed 's/_/-/g'`
+ { echo "$as_me: error: missing argument to $ac_option" >&2
+ { (exit 1); exit 1; }; }
+fi
+
+# Be sure to have absolute paths.
+for ac_var in exec_prefix prefix
+do
+ eval ac_val=$`echo $ac_var`
+ case $ac_val in
+ [\\/$]* | ?:[\\/]* | NONE | '' ) ;;
+ *) { echo "$as_me: error: expected an absolute directory name for --$ac_var: $ac_val" >&2
+ { (exit 1); exit 1; }; };;
+ esac
+done
+
+# Be sure to have absolute paths.
+for ac_var in bindir sbindir libexecdir datadir sysconfdir sharedstatedir \
+ localstatedir libdir includedir oldincludedir infodir mandir
+do
+ eval ac_val=$`echo $ac_var`
+ case $ac_val in
+ [\\/$]* | ?:[\\/]* ) ;;
+ *) { echo "$as_me: error: expected an absolute directory name for --$ac_var: $ac_val" >&2
+ { (exit 1); exit 1; }; };;
+ esac
+done
+
+# There might be people who depend on the old broken behavior: `$host'
+# used to hold the argument of --host etc.
+# FIXME: To remove some day.
+build=$build_alias
+host=$host_alias
+target=$target_alias
+
+# FIXME: To remove some day.
+if test "x$host_alias" != x; then
+ if test "x$build_alias" = x; then
+ cross_compiling=maybe
+ echo "$as_me: WARNING: If you wanted to set the --build type, don't use --host.
+ If a cross compiler is detected then cross compile mode will be used." >&2
+ elif test "x$build_alias" != "x$host_alias"; then
+ cross_compiling=yes
+ fi
+fi
+
+ac_tool_prefix=
+test -n "$host_alias" && ac_tool_prefix=$host_alias-
+
+test "$silent" = yes && exec 6>/dev/null
+
+
+# Find the source files, if location was not specified.
+if test -z "$srcdir"; then
+ ac_srcdir_defaulted=yes
+ # Try the directory containing this script, then its parent.
+ ac_confdir=`(dirname "$0") 2>/dev/null ||
+$as_expr X"$0" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+ X"$0" : 'X\(//\)[^/]' \| \
+ X"$0" : 'X\(//\)$' \| \
+ X"$0" : 'X\(/\)' \| \
+ . : '\(.\)' 2>/dev/null ||
+echo X"$0" |
+ sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
+ /^X\(\/\/\)[^/].*/{ s//\1/; q; }
+ /^X\(\/\/\)$/{ s//\1/; q; }
+ /^X\(\/\).*/{ s//\1/; q; }
+ s/.*/./; q'`
+ srcdir=$ac_confdir
+ if test ! -r $srcdir/$ac_unique_file; then
+ srcdir=..
+ fi
+else
+ ac_srcdir_defaulted=no
+fi
+if test ! -r $srcdir/$ac_unique_file; then
+ if test "$ac_srcdir_defaulted" = yes; then
+ { echo "$as_me: error: cannot find sources ($ac_unique_file) in $ac_confdir or .." >&2
+ { (exit 1); exit 1; }; }
+ else
+ { echo "$as_me: error: cannot find sources ($ac_unique_file) in $srcdir" >&2
+ { (exit 1); exit 1; }; }
+ fi
+fi
+(cd $srcdir && test -r ./$ac_unique_file) 2>/dev/null ||
+ { echo "$as_me: error: sources are in $srcdir, but \`cd $srcdir' does not work" >&2
+ { (exit 1); exit 1; }; }
+srcdir=`echo "$srcdir" | sed 's%\([^\\/]\)[\\/]*$%\1%'`
+ac_env_build_alias_set=${build_alias+set}
+ac_env_build_alias_value=$build_alias
+ac_cv_env_build_alias_set=${build_alias+set}
+ac_cv_env_build_alias_value=$build_alias
+ac_env_host_alias_set=${host_alias+set}
+ac_env_host_alias_value=$host_alias
+ac_cv_env_host_alias_set=${host_alias+set}
+ac_cv_env_host_alias_value=$host_alias
+ac_env_target_alias_set=${target_alias+set}
+ac_env_target_alias_value=$target_alias
+ac_cv_env_target_alias_set=${target_alias+set}
+ac_cv_env_target_alias_value=$target_alias
+ac_env_CC_set=${CC+set}
+ac_env_CC_value=$CC
+ac_cv_env_CC_set=${CC+set}
+ac_cv_env_CC_value=$CC
+ac_env_CFLAGS_set=${CFLAGS+set}
+ac_env_CFLAGS_value=$CFLAGS
+ac_cv_env_CFLAGS_set=${CFLAGS+set}
+ac_cv_env_CFLAGS_value=$CFLAGS
+ac_env_LDFLAGS_set=${LDFLAGS+set}
+ac_env_LDFLAGS_value=$LDFLAGS
+ac_cv_env_LDFLAGS_set=${LDFLAGS+set}
+ac_cv_env_LDFLAGS_value=$LDFLAGS
+ac_env_CPPFLAGS_set=${CPPFLAGS+set}
+ac_env_CPPFLAGS_value=$CPPFLAGS
+ac_cv_env_CPPFLAGS_set=${CPPFLAGS+set}
+ac_cv_env_CPPFLAGS_value=$CPPFLAGS
+ac_env_CPP_set=${CPP+set}
+ac_env_CPP_value=$CPP
+ac_cv_env_CPP_set=${CPP+set}
+ac_cv_env_CPP_value=$CPP
+
+#
+# Report the --help message.
+#
+if test "$ac_init_help" = "long"; then
+ # Omit some internal or obsolete options to make the list less imposing.
+ # This message is too long to be a string in the A/UX 3.1 sh.
+ cat <<_ACEOF
+\`configure' configures this package to adapt to many kinds of systems.
+
+Usage: $0 [OPTION]... [VAR=VALUE]...
+
+To assign environment variables (e.g., CC, CFLAGS...), specify them as
+VAR=VALUE. See below for descriptions of some of the useful variables.
+
+Defaults for the options are specified in brackets.
+
+Configuration:
+ -h, --help display this help and exit
+ --help=short display options specific to this package
+ --help=recursive display the short help of all the included packages
+ -V, --version display version information and exit
+ -q, --quiet, --silent do not print \`checking...' messages
+ --cache-file=FILE cache test results in FILE [disabled]
+ -C, --config-cache alias for \`--cache-file=config.cache'
+ -n, --no-create do not create output files
+ --srcdir=DIR find the sources in DIR [configure dir or \`..']
+
+_ACEOF
+
+ cat <<_ACEOF
+Installation directories:
+ --prefix=PREFIX install architecture-independent files in PREFIX
+ [$ac_default_prefix]
+ --exec-prefix=EPREFIX install architecture-dependent files in EPREFIX
+ [PREFIX]
+
+By default, \`make install' will install all the files in
+\`$ac_default_prefix/bin', \`$ac_default_prefix/lib' etc. You can specify
+an installation prefix other than \`$ac_default_prefix' using \`--prefix',
+for instance \`--prefix=\$HOME'.
+
+For better control, use the options below.
+
+Fine tuning of the installation directories:
+ --bindir=DIR user executables [EPREFIX/bin]
+ --sbindir=DIR system admin executables [EPREFIX/sbin]
+ --libexecdir=DIR program executables [EPREFIX/libexec]
+ --datadir=DIR read-only architecture-independent data [PREFIX/share]
+ --sysconfdir=DIR read-only single-machine data [PREFIX/etc]
+ --sharedstatedir=DIR modifiable architecture-independent data [PREFIX/com]
+ --localstatedir=DIR modifiable single-machine data [PREFIX/var]
+ --libdir=DIR object code libraries [EPREFIX/lib]
+ --includedir=DIR C header files [PREFIX/include]
+ --oldincludedir=DIR C header files for non-gcc [/usr/include]
+ --infodir=DIR info documentation [PREFIX/info]
+ --mandir=DIR man documentation [PREFIX/man]
+_ACEOF
+
+ cat <<\_ACEOF
+
+Program names:
+ --program-prefix=PREFIX prepend PREFIX to installed program names
+ --program-suffix=SUFFIX append SUFFIX to installed program names
+ --program-transform-name=PROGRAM run sed PROGRAM on installed program names
+
+System types:
+ --build=BUILD configure for building on BUILD [guessed]
+ --host=HOST cross-compile to build programs to run on HOST [BUILD]
+ --target=TARGET configure for building compilers for TARGET [HOST]
+_ACEOF
+fi
+
+if test -n "$ac_init_help"; then
+
+ cat <<\_ACEOF
+
+Optional Features:
+ --disable-FEATURE do not include FEATURE (same as --enable-FEATURE=no)
+ --enable-FEATURE[=ARG] include FEATURE [ARG=yes]
+ --disable-nls do not use Native Language Support
+ --enable-maintainer-mode Enable developer functionality.
+ --enable-sim-bswap Use Host specific BSWAP instruction.
+ --enable-sim-cflags=opts Extra CFLAGS for use in building simulator
+ --enable-sim-debug=opts Enable debugging flags
+ --enable-sim-stdio Specify whether to use stdio for console input/output.
+ --enable-sim-trace=opts Enable tracing flags
+ --enable-sim-profile=opts Enable profiling flags
+ --enable-sim-alignment=align Specify strict, nonstrict or forced alignment of memory accesses.
+ --enable-sim-hostendian=end Specify host byte endian orientation.
+ --enable-sim-scache=size Specify simulator execution cache size.
+ --enable-sim-default-model=model Specify default model to simulate.
+ --enable-sim-environment=environment Specify mixed, user, virtual or operating environment.
+ --enable-sim-inline=inlines Specify which functions should be inlined.
+ --enable-cgen-maint=DIR build cgen generated files
+
+Optional Packages:
+ --with-PACKAGE[=ARG] use PACKAGE [ARG=yes]
+ --without-PACKAGE do not use PACKAGE (same as --with-PACKAGE=no)
+ --with-included-gettext use the GNU gettext library included here
+
+Some influential environment variables:
+ CC C compiler command
+ CFLAGS C compiler flags
+ LDFLAGS linker flags, e.g. -L<lib dir> if you have libraries in a
+ nonstandard directory <lib dir>
+ CPPFLAGS C/C++ preprocessor flags, e.g. -I<include dir> if you have
+ headers in a nonstandard directory <include dir>
+ CPP C preprocessor
+
+Use these variables to override the choices made by `configure' or to help
+it to find libraries and programs with nonstandard names/locations.
+
+_ACEOF
+fi
+
+if test "$ac_init_help" = "recursive"; then
+ # If there are subdirs, report their specific --help.
+ ac_popdir=`pwd`
+ for ac_dir in : $ac_subdirs_all; do test "x$ac_dir" = x: && continue
+ test -d $ac_dir || continue
+ ac_builddir=.
+
+if test "$ac_dir" != .; then
+ ac_dir_suffix=/`echo "$ac_dir" | sed 's,^\.[\\/],,'`
+ # A "../" for each directory in $ac_dir_suffix.
+ ac_top_builddir=`echo "$ac_dir_suffix" | sed 's,/[^\\/]*,../,g'`
+else
+ ac_dir_suffix= ac_top_builddir=
+fi
+
+case $srcdir in
+ .) # No --srcdir option. We are building in place.
+ ac_srcdir=.
+ if test -z "$ac_top_builddir"; then
+ ac_top_srcdir=.
+ else
+ ac_top_srcdir=`echo $ac_top_builddir | sed 's,/$,,'`
+ fi ;;
+ [\\/]* | ?:[\\/]* ) # Absolute path.
+ ac_srcdir=$srcdir$ac_dir_suffix;
+ ac_top_srcdir=$srcdir ;;
+ *) # Relative path.
+ ac_srcdir=$ac_top_builddir$srcdir$ac_dir_suffix
+ ac_top_srcdir=$ac_top_builddir$srcdir ;;
+esac
+
+# Do not use `cd foo && pwd` to compute absolute paths, because
+# the directories may not exist.
+case `pwd` in
+.) ac_abs_builddir="$ac_dir";;
+*)
+ case "$ac_dir" in
+ .) ac_abs_builddir=`pwd`;;
+ [\\/]* | ?:[\\/]* ) ac_abs_builddir="$ac_dir";;
+ *) ac_abs_builddir=`pwd`/"$ac_dir";;
+ esac;;
+esac
+case $ac_abs_builddir in
+.) ac_abs_top_builddir=${ac_top_builddir}.;;
+*)
+ case ${ac_top_builddir}. in
+ .) ac_abs_top_builddir=$ac_abs_builddir;;
+ [\\/]* | ?:[\\/]* ) ac_abs_top_builddir=${ac_top_builddir}.;;
+ *) ac_abs_top_builddir=$ac_abs_builddir/${ac_top_builddir}.;;
+ esac;;
+esac
+case $ac_abs_builddir in
+.) ac_abs_srcdir=$ac_srcdir;;
+*)
+ case $ac_srcdir in
+ .) ac_abs_srcdir=$ac_abs_builddir;;
+ [\\/]* | ?:[\\/]* ) ac_abs_srcdir=$ac_srcdir;;
+ *) ac_abs_srcdir=$ac_abs_builddir/$ac_srcdir;;
+ esac;;
+esac
+case $ac_abs_builddir in
+.) ac_abs_top_srcdir=$ac_top_srcdir;;
+*)
+ case $ac_top_srcdir in
+ .) ac_abs_top_srcdir=$ac_abs_builddir;;
+ [\\/]* | ?:[\\/]* ) ac_abs_top_srcdir=$ac_top_srcdir;;
+ *) ac_abs_top_srcdir=$ac_abs_builddir/$ac_top_srcdir;;
+ esac;;
+esac
+
+ cd $ac_dir
+ # Check for guested configure; otherwise get Cygnus style configure.
+ if test -f $ac_srcdir/configure.gnu; then
+ echo
+ $SHELL $ac_srcdir/configure.gnu --help=recursive
+ elif test -f $ac_srcdir/configure; then
+ echo
+ $SHELL $ac_srcdir/configure --help=recursive
+ elif test -f $ac_srcdir/configure.ac ||
+ test -f $ac_srcdir/configure.in; then
+ echo
+ $ac_configure --help
+ else
+ echo "$as_me: WARNING: no configuration information is in $ac_dir" >&2
+ fi
+ cd $ac_popdir
+ done
+fi
+
+test -n "$ac_init_help" && exit 0
+if $ac_init_version; then
+ cat <<\_ACEOF
+
+Copyright (C) 2003 Free Software Foundation, Inc.
+This configure script is free software; the Free Software Foundation
+gives unlimited permission to copy, distribute and modify it.
+_ACEOF
+ exit 0
+fi
+exec 5>config.log
+cat >&5 <<_ACEOF
+This file contains any messages produced by compilers while
+running configure, to aid debugging if configure makes a mistake.
+
+It was created by $as_me, which was
+generated by GNU Autoconf 2.59. Invocation command line was
+
+ $ $0 $@
+
+_ACEOF
+{
+cat <<_ASUNAME
+## --------- ##
+## Platform. ##
+## --------- ##
+
+hostname = `(hostname || uname -n) 2>/dev/null | sed 1q`
+uname -m = `(uname -m) 2>/dev/null || echo unknown`
+uname -r = `(uname -r) 2>/dev/null || echo unknown`
+uname -s = `(uname -s) 2>/dev/null || echo unknown`
+uname -v = `(uname -v) 2>/dev/null || echo unknown`
+
+/usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null || echo unknown`
+/bin/uname -X = `(/bin/uname -X) 2>/dev/null || echo unknown`
+
+/bin/arch = `(/bin/arch) 2>/dev/null || echo unknown`
+/usr/bin/arch -k = `(/usr/bin/arch -k) 2>/dev/null || echo unknown`
+/usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null || echo unknown`
+hostinfo = `(hostinfo) 2>/dev/null || echo unknown`
+/bin/machine = `(/bin/machine) 2>/dev/null || echo unknown`
+/usr/bin/oslevel = `(/usr/bin/oslevel) 2>/dev/null || echo unknown`
+/bin/universe = `(/bin/universe) 2>/dev/null || echo unknown`
+
+_ASUNAME
+
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ echo "PATH: $as_dir"
+done
+
+} >&5
+
+cat >&5 <<_ACEOF
+
+
+## ----------- ##
+## Core tests. ##
+## ----------- ##
+
+_ACEOF
+
+
+# Keep a trace of the command line.
+# Strip out --no-create and --no-recursion so they do not pile up.
+# Strip out --silent because we don't want to record it for future runs.
+# Also quote any args containing shell meta-characters.
+# Make two passes to allow for proper duplicate-argument suppression.
+ac_configure_args=
+ac_configure_args0=
+ac_configure_args1=
+ac_sep=
+ac_must_keep_next=false
+for ac_pass in 1 2
+do
+ for ac_arg
+ do
+ case $ac_arg in
+ -no-create | --no-c* | -n | -no-recursion | --no-r*) continue ;;
+ -q | -quiet | --quiet | --quie | --qui | --qu | --q \
+ | -silent | --silent | --silen | --sile | --sil)
+ continue ;;
+ *" "*|*" "*|*[\[\]\~\#\$\^\&\*\(\)\{\}\\\|\;\<\>\?\"\']*)
+ ac_arg=`echo "$ac_arg" | sed "s/'/'\\\\\\\\''/g"` ;;
+ esac
+ case $ac_pass in
+ 1) ac_configure_args0="$ac_configure_args0 '$ac_arg'" ;;
+ 2)
+ ac_configure_args1="$ac_configure_args1 '$ac_arg'"
+ if test $ac_must_keep_next = true; then
+ ac_must_keep_next=false # Got value, back to normal.
+ else
+ case $ac_arg in
+ *=* | --config-cache | -C | -disable-* | --disable-* \
+ | -enable-* | --enable-* | -gas | --g* | -nfp | --nf* \
+ | -q | -quiet | --q* | -silent | --sil* | -v | -verb* \
+ | -with-* | --with-* | -without-* | --without-* | --x)
+ case "$ac_configure_args0 " in
+ "$ac_configure_args1"*" '$ac_arg' "* ) continue ;;
+ esac
+ ;;
+ -* ) ac_must_keep_next=true ;;
+ esac
+ fi
+ ac_configure_args="$ac_configure_args$ac_sep'$ac_arg'"
+ # Get rid of the leading space.
+ ac_sep=" "
+ ;;
+ esac
+ done
+done
+$as_unset ac_configure_args0 || test "${ac_configure_args0+set}" != set || { ac_configure_args0=; export ac_configure_args0; }
+$as_unset ac_configure_args1 || test "${ac_configure_args1+set}" != set || { ac_configure_args1=; export ac_configure_args1; }
+
+# When interrupted or exit'd, cleanup temporary files, and complete
+# config.log. We remove comments because anyway the quotes in there
+# would cause problems or look ugly.
+# WARNING: Be sure not to use single quotes in there, as some shells,
+# such as our DU 5.0 friend, will then `close' the trap.
+trap 'exit_status=$?
+ # Save into config.log some information that might help in debugging.
+ {
+ echo
+
+ cat <<\_ASBOX
+## ---------------- ##
+## Cache variables. ##
+## ---------------- ##
+_ASBOX
+ echo
+ # The following way of writing the cache mishandles newlines in values,
+{
+ (set) 2>&1 |
+ case `(ac_space='"'"' '"'"'; set | grep ac_space) 2>&1` in
+ *ac_space=\ *)
+ sed -n \
+ "s/'"'"'/'"'"'\\\\'"'"''"'"'/g;
+ s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='"'"'\\2'"'"'/p"
+ ;;
+ *)
+ sed -n \
+ "s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1=\\2/p"
+ ;;
+ esac;
+}
+ echo
+
+ cat <<\_ASBOX
+## ----------------- ##
+## Output variables. ##
+## ----------------- ##
+_ASBOX
+ echo
+ for ac_var in $ac_subst_vars
+ do
+ eval ac_val=$`echo $ac_var`
+ echo "$ac_var='"'"'$ac_val'"'"'"
+ done | sort
+ echo
+
+ if test -n "$ac_subst_files"; then
+ cat <<\_ASBOX
+## ------------- ##
+## Output files. ##
+## ------------- ##
+_ASBOX
+ echo
+ for ac_var in $ac_subst_files
+ do
+ eval ac_val=$`echo $ac_var`
+ echo "$ac_var='"'"'$ac_val'"'"'"
+ done | sort
+ echo
+ fi
+
+ if test -s confdefs.h; then
+ cat <<\_ASBOX
+## ----------- ##
+## confdefs.h. ##
+## ----------- ##
+_ASBOX
+ echo
+ sed "/^$/d" confdefs.h | sort
+ echo
+ fi
+ test "$ac_signal" != 0 &&
+ echo "$as_me: caught signal $ac_signal"
+ echo "$as_me: exit $exit_status"
+ } >&5
+ rm -f core *.core &&
+ rm -rf conftest* confdefs* conf$$* $ac_clean_files &&
+ exit $exit_status
+ ' 0
+for ac_signal in 1 2 13 15; do
+ trap 'ac_signal='$ac_signal'; { (exit 1); exit 1; }' $ac_signal
+done
+ac_signal=0
+
+# confdefs.h avoids OS command line length limits that DEFS can exceed.
+rm -rf conftest* confdefs.h
+# AIX cpp loses on an empty file, so make sure it contains at least a newline.
+echo >confdefs.h
+
+# Predefined preprocessor variables.
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_NAME "$PACKAGE_NAME"
+_ACEOF
+
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_TARNAME "$PACKAGE_TARNAME"
+_ACEOF
+
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_VERSION "$PACKAGE_VERSION"
+_ACEOF
+
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_STRING "$PACKAGE_STRING"
+_ACEOF
+
+
+cat >>confdefs.h <<_ACEOF
+#define PACKAGE_BUGREPORT "$PACKAGE_BUGREPORT"
+_ACEOF
+
+
+# Let the site file select an alternate cache file if it wants to.
+# Prefer explicitly selected file to automatically selected ones.
+if test -z "$CONFIG_SITE"; then
+ if test "x$prefix" != xNONE; then
+ CONFIG_SITE="$prefix/share/config.site $prefix/etc/config.site"
+ else
+ CONFIG_SITE="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site"
+ fi
+fi
+for ac_site_file in $CONFIG_SITE; do
+ if test -r "$ac_site_file"; then
+ { echo "$as_me:$LINENO: loading site script $ac_site_file" >&5
+echo "$as_me: loading site script $ac_site_file" >&6;}
+ sed 's/^/| /' "$ac_site_file" >&5
+ . "$ac_site_file"
+ fi
+done
+
+if test -r "$cache_file"; then
+ # Some versions of bash will fail to source /dev/null (special
+ # files actually), so we avoid doing that.
+ if test -f "$cache_file"; then
+ { echo "$as_me:$LINENO: loading cache $cache_file" >&5
+echo "$as_me: loading cache $cache_file" >&6;}
+ case $cache_file in
+ [\\/]* | ?:[\\/]* ) . $cache_file;;
+ *) . ./$cache_file;;
+ esac
+ fi
+else
+ { echo "$as_me:$LINENO: creating cache $cache_file" >&5
+echo "$as_me: creating cache $cache_file" >&6;}
+ >$cache_file
+fi
+
+# Check that the precious variables saved in the cache have kept the same
+# value.
+ac_cache_corrupted=false
+for ac_var in `(set) 2>&1 |
+ sed -n 's/^ac_env_\([a-zA-Z_0-9]*\)_set=.*/\1/p'`; do
+ eval ac_old_set=\$ac_cv_env_${ac_var}_set
+ eval ac_new_set=\$ac_env_${ac_var}_set
+ eval ac_old_val="\$ac_cv_env_${ac_var}_value"
+ eval ac_new_val="\$ac_env_${ac_var}_value"
+ case $ac_old_set,$ac_new_set in
+ set,)
+ { echo "$as_me:$LINENO: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&5
+echo "$as_me: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&2;}
+ ac_cache_corrupted=: ;;
+ ,set)
+ { echo "$as_me:$LINENO: error: \`$ac_var' was not set in the previous run" >&5
+echo "$as_me: error: \`$ac_var' was not set in the previous run" >&2;}
+ ac_cache_corrupted=: ;;
+ ,);;
+ *)
+ if test "x$ac_old_val" != "x$ac_new_val"; then
+ { echo "$as_me:$LINENO: error: \`$ac_var' has changed since the previous run:" >&5
+echo "$as_me: error: \`$ac_var' has changed since the previous run:" >&2;}
+ { echo "$as_me:$LINENO: former value: $ac_old_val" >&5
+echo "$as_me: former value: $ac_old_val" >&2;}
+ { echo "$as_me:$LINENO: current value: $ac_new_val" >&5
+echo "$as_me: current value: $ac_new_val" >&2;}
+ ac_cache_corrupted=:
+ fi;;
+ esac
+ # Pass precious variables to config.status.
+ if test "$ac_new_set" = set; then
+ case $ac_new_val in
+ *" "*|*" "*|*[\[\]\~\#\$\^\&\*\(\)\{\}\\\|\;\<\>\?\"\']*)
+ ac_arg=$ac_var=`echo "$ac_new_val" | sed "s/'/'\\\\\\\\''/g"` ;;
+ *) ac_arg=$ac_var=$ac_new_val ;;
+ esac
+ case " $ac_configure_args " in
+ *" '$ac_arg' "*) ;; # Avoid dups. Use of quotes ensures accuracy.
+ *) ac_configure_args="$ac_configure_args '$ac_arg'" ;;
+ esac
+ fi
+done
+if $ac_cache_corrupted; then
+ { echo "$as_me:$LINENO: error: changes in the environment can compromise the build" >&5
+echo "$as_me: error: changes in the environment can compromise the build" >&2;}
+ { { echo "$as_me:$LINENO: error: run \`make distclean' and/or \`rm $cache_file' and start over" >&5
+echo "$as_me: error: run \`make distclean' and/or \`rm $cache_file' and start over" >&2;}
+ { (exit 1); exit 1; }; }
+fi
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ ac_config_headers="$ac_config_headers config.h:config.in"
+
+
+# This file contains common code used by all simulators.
+#
+# SIM_AC_COMMON invokes AC macros used by all simulators and by the common
+# directory. It is intended to be invoked before any target specific stuff.
+# SIM_AC_OUTPUT is a cover function to AC_OUTPUT to generate the Makefile.
+# It is intended to be invoked last.
+#
+# The simulator's configure.in should look like:
+#
+# dnl Process this file with autoconf to produce a configure script.
+# sinclude(../common/aclocal.m4)
+# AC_PREREQ(2.5)dnl
+# AC_INIT(Makefile.in)
+#
+# SIM_AC_COMMON
+#
+# ... target specific stuff ...
+#
+# SIM_AC_OUTPUT
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+sim_inline="-DDEFAULT_INLINE=0"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+# This file is derived from `gettext.m4'. The difference is that the
+# included macros assume Cygnus-style source and build trees.
+
+# Macro to add for using GNU gettext.
+# Ulrich Drepper <drepper@cygnus.com>, 1995.
+#
+# This file file be copied and used freely without restrictions. It can
+# be used in projects which are not available under the GNU Public License
+# but which still want to provide support for the GNU gettext functionality.
+# Please note that the actual code is *not* freely available.
+
+# serial 3
+
+
+
+
+
+# Search path for a program which passes the given test.
+# Ulrich Drepper <drepper@cygnus.com>, 1996.
+#
+# This file file be copied and used freely without restrictions. It can
+# be used in projects which are not available under the GNU Public License
+# but which still want to provide support for the GNU gettext functionality.
+# Please note that the actual code is *not* freely available.
+
+# serial 1
+
+
+
+# Check whether LC_MESSAGES is available in <locale.h>.
+# Ulrich Drepper <drepper@cygnus.com>, 1995.
+#
+# This file file be copied and used freely without restrictions. It can
+# be used in projects which are not available under the GNU Public License
+# but which still want to provide support for the GNU gettext functionality.
+# Please note that the actual code is *not* freely available.
+
+# serial 1
+
+
+
+
+
+
+
+# Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around
+# it by inlining the macro's contents.
+# This file contains common code used by all simulators.
+#
+# common.m4 invokes AC macros used by all simulators and by the common
+# directory. It is intended to be included before any target specific
+# stuff. SIM_AC_OUTPUT is a cover function to AC_OUTPUT to generate
+# the Makefile. It is intended to be invoked last.
+#
+# The simulator's configure.in should look like:
+#
+# dnl Process this file with autoconf to produce a configure script.
+# AC_PREREQ(2.5)dnl
+# AC_INIT(Makefile.in)
+# AC_CONFIG_HEADER(config.h:config.in)
+#
+# sinclude(../common/aclocal.m4)
+# sinclude(../common/common.m4)
+#
+# ... target specific stuff ...
+
+ac_aux_dir=
+for ac_dir in $srcdir $srcdir/.. $srcdir/../..; do
+ if test -f $ac_dir/install-sh; then
+ ac_aux_dir=$ac_dir
+ ac_install_sh="$ac_aux_dir/install-sh -c"
+ break
+ elif test -f $ac_dir/install.sh; then
+ ac_aux_dir=$ac_dir
+ ac_install_sh="$ac_aux_dir/install.sh -c"
+ break
+ elif test -f $ac_dir/shtool; then
+ ac_aux_dir=$ac_dir
+ ac_install_sh="$ac_aux_dir/shtool install -c"
+ break
+ fi
+done
+if test -z "$ac_aux_dir"; then
+ { { echo "$as_me:$LINENO: error: cannot find install-sh or install.sh in $srcdir $srcdir/.. $srcdir/../.." >&5
+echo "$as_me: error: cannot find install-sh or install.sh in $srcdir $srcdir/.. $srcdir/../.." >&2;}
+ { (exit 1); exit 1; }; }
+fi
+ac_config_guess="$SHELL $ac_aux_dir/config.guess"
+ac_config_sub="$SHELL $ac_aux_dir/config.sub"
+ac_configure="$SHELL $ac_aux_dir/configure" # This should be Cygnus configure.
+
+# Make sure we can run config.sub.
+$ac_config_sub sun4 >/dev/null 2>&1 ||
+ { { echo "$as_me:$LINENO: error: cannot run $ac_config_sub" >&5
+echo "$as_me: error: cannot run $ac_config_sub" >&2;}
+ { (exit 1); exit 1; }; }
+
+echo "$as_me:$LINENO: checking build system type" >&5
+echo $ECHO_N "checking build system type... $ECHO_C" >&6
+if test "${ac_cv_build+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ ac_cv_build_alias=$build_alias
+test -z "$ac_cv_build_alias" &&
+ ac_cv_build_alias=`$ac_config_guess`
+test -z "$ac_cv_build_alias" &&
+ { { echo "$as_me:$LINENO: error: cannot guess build type; you must specify one" >&5
+echo "$as_me: error: cannot guess build type; you must specify one" >&2;}
+ { (exit 1); exit 1; }; }
+ac_cv_build=`$ac_config_sub $ac_cv_build_alias` ||
+ { { echo "$as_me:$LINENO: error: $ac_config_sub $ac_cv_build_alias failed" >&5
+echo "$as_me: error: $ac_config_sub $ac_cv_build_alias failed" >&2;}
+ { (exit 1); exit 1; }; }
+
+fi
+echo "$as_me:$LINENO: result: $ac_cv_build" >&5
+echo "${ECHO_T}$ac_cv_build" >&6
+build=$ac_cv_build
+build_cpu=`echo $ac_cv_build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
+build_vendor=`echo $ac_cv_build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
+build_os=`echo $ac_cv_build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
+
+
+echo "$as_me:$LINENO: checking host system type" >&5
+echo $ECHO_N "checking host system type... $ECHO_C" >&6
+if test "${ac_cv_host+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ ac_cv_host_alias=$host_alias
+test -z "$ac_cv_host_alias" &&
+ ac_cv_host_alias=$ac_cv_build_alias
+ac_cv_host=`$ac_config_sub $ac_cv_host_alias` ||
+ { { echo "$as_me:$LINENO: error: $ac_config_sub $ac_cv_host_alias failed" >&5
+echo "$as_me: error: $ac_config_sub $ac_cv_host_alias failed" >&2;}
+ { (exit 1); exit 1; }; }
+
+fi
+echo "$as_me:$LINENO: result: $ac_cv_host" >&5
+echo "${ECHO_T}$ac_cv_host" >&6
+host=$ac_cv_host
+host_cpu=`echo $ac_cv_host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
+host_vendor=`echo $ac_cv_host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
+host_os=`echo $ac_cv_host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
+
+
+echo "$as_me:$LINENO: checking target system type" >&5
+echo $ECHO_N "checking target system type... $ECHO_C" >&6
+if test "${ac_cv_target+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ ac_cv_target_alias=$target_alias
+test "x$ac_cv_target_alias" = "x" &&
+ ac_cv_target_alias=$ac_cv_host_alias
+ac_cv_target=`$ac_config_sub $ac_cv_target_alias` ||
+ { { echo "$as_me:$LINENO: error: $ac_config_sub $ac_cv_target_alias failed" >&5
+echo "$as_me: error: $ac_config_sub $ac_cv_target_alias failed" >&2;}
+ { (exit 1); exit 1; }; }
+
+fi
+echo "$as_me:$LINENO: result: $ac_cv_target" >&5
+echo "${ECHO_T}$ac_cv_target" >&6
+target=$ac_cv_target
+target_cpu=`echo $ac_cv_target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
+target_vendor=`echo $ac_cv_target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
+target_os=`echo $ac_cv_target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
+
+
+# The aliases save the names the user supplied, while $host etc.
+# will get canonicalized.
+test -n "$target_alias" &&
+ test "$program_prefix$program_suffix$program_transform_name" = \
+ NONENONEs,x,x, &&
+ program_prefix=${target_alias}-
+test "$program_prefix" != NONE &&
+ program_transform_name="s,^,$program_prefix,;$program_transform_name"
+# Use a double $ so make ignores it.
+test "$program_suffix" != NONE &&
+ program_transform_name="s,\$,$program_suffix,;$program_transform_name"
+# Double any \ or $. echo might interpret backslashes.
+# By default was `s,x,x', remove it if useless.
+cat <<\_ACEOF >conftest.sed
+s/[\\$]/&&/g;s/;s,x,x,$//
+_ACEOF
+program_transform_name=`echo $program_transform_name | sed -f conftest.sed`
+rm conftest.sed
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+if test -n "$ac_tool_prefix"; then
+ # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args.
+set dummy ${ac_tool_prefix}gcc; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_CC+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ if test -n "$CC"; then
+ ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+ ac_cv_prog_CC="${ac_tool_prefix}gcc"
+ echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+done
+
+fi
+fi
+CC=$ac_cv_prog_CC
+if test -n "$CC"; then
+ echo "$as_me:$LINENO: result: $CC" >&5
+echo "${ECHO_T}$CC" >&6
+else
+ echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+fi
+if test -z "$ac_cv_prog_CC"; then
+ ac_ct_CC=$CC
+ # Extract the first word of "gcc", so it can be a program name with args.
+set dummy gcc; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_ac_ct_CC+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ if test -n "$ac_ct_CC"; then
+ ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+ ac_cv_prog_ac_ct_CC="gcc"
+ echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+done
+
+fi
+fi
+ac_ct_CC=$ac_cv_prog_ac_ct_CC
+if test -n "$ac_ct_CC"; then
+ echo "$as_me:$LINENO: result: $ac_ct_CC" >&5
+echo "${ECHO_T}$ac_ct_CC" >&6
+else
+ echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+ CC=$ac_ct_CC
+else
+ CC="$ac_cv_prog_CC"
+fi
+
+if test -z "$CC"; then
+ if test -n "$ac_tool_prefix"; then
+ # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args.
+set dummy ${ac_tool_prefix}cc; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_CC+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ if test -n "$CC"; then
+ ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+ ac_cv_prog_CC="${ac_tool_prefix}cc"
+ echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+done
+
+fi
+fi
+CC=$ac_cv_prog_CC
+if test -n "$CC"; then
+ echo "$as_me:$LINENO: result: $CC" >&5
+echo "${ECHO_T}$CC" >&6
+else
+ echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+fi
+if test -z "$ac_cv_prog_CC"; then
+ ac_ct_CC=$CC
+ # Extract the first word of "cc", so it can be a program name with args.
+set dummy cc; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_ac_ct_CC+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ if test -n "$ac_ct_CC"; then
+ ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+ ac_cv_prog_ac_ct_CC="cc"
+ echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+done
+
+fi
+fi
+ac_ct_CC=$ac_cv_prog_ac_ct_CC
+if test -n "$ac_ct_CC"; then
+ echo "$as_me:$LINENO: result: $ac_ct_CC" >&5
+echo "${ECHO_T}$ac_ct_CC" >&6
+else
+ echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+ CC=$ac_ct_CC
+else
+ CC="$ac_cv_prog_CC"
+fi
+
+fi
+if test -z "$CC"; then
+ # Extract the first word of "cc", so it can be a program name with args.
+set dummy cc; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_CC+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ if test -n "$CC"; then
+ ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+ ac_prog_rejected=no
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+ if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then
+ ac_prog_rejected=yes
+ continue
+ fi
+ ac_cv_prog_CC="cc"
+ echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+done
+
+if test $ac_prog_rejected = yes; then
+ # We found a bogon in the path, so make sure we never use it.
+ set dummy $ac_cv_prog_CC
+ shift
+ if test $# != 0; then
+ # We chose a different compiler from the bogus one.
+ # However, it has the same basename, so the bogon will be chosen
+ # first if we set CC to just the basename; use the full file name.
+ shift
+ ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@"
+ fi
+fi
+fi
+fi
+CC=$ac_cv_prog_CC
+if test -n "$CC"; then
+ echo "$as_me:$LINENO: result: $CC" >&5
+echo "${ECHO_T}$CC" >&6
+else
+ echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+fi
+if test -z "$CC"; then
+ if test -n "$ac_tool_prefix"; then
+ for ac_prog in cl
+ do
+ # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args.
+set dummy $ac_tool_prefix$ac_prog; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_CC+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ if test -n "$CC"; then
+ ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+ ac_cv_prog_CC="$ac_tool_prefix$ac_prog"
+ echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+done
+
+fi
+fi
+CC=$ac_cv_prog_CC
+if test -n "$CC"; then
+ echo "$as_me:$LINENO: result: $CC" >&5
+echo "${ECHO_T}$CC" >&6
+else
+ echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+ test -n "$CC" && break
+ done
+fi
+if test -z "$CC"; then
+ ac_ct_CC=$CC
+ for ac_prog in cl
+do
+ # Extract the first word of "$ac_prog", so it can be a program name with args.
+set dummy $ac_prog; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_ac_ct_CC+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ if test -n "$ac_ct_CC"; then
+ ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+ ac_cv_prog_ac_ct_CC="$ac_prog"
+ echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+done
+
+fi
+fi
+ac_ct_CC=$ac_cv_prog_ac_ct_CC
+if test -n "$ac_ct_CC"; then
+ echo "$as_me:$LINENO: result: $ac_ct_CC" >&5
+echo "${ECHO_T}$ac_ct_CC" >&6
+else
+ echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+ test -n "$ac_ct_CC" && break
+done
+
+ CC=$ac_ct_CC
+fi
+
+fi
+
+
+test -z "$CC" && { { echo "$as_me:$LINENO: error: no acceptable C compiler found in \$PATH
+See \`config.log' for more details." >&5
+echo "$as_me: error: no acceptable C compiler found in \$PATH
+See \`config.log' for more details." >&2;}
+ { (exit 1); exit 1; }; }
+
+# Provide some information about the compiler.
+echo "$as_me:$LINENO:" \
+ "checking for C compiler version" >&5
+ac_compiler=`set X $ac_compile; echo $2`
+{ (eval echo "$as_me:$LINENO: \"$ac_compiler --version </dev/null >&5\"") >&5
+ (eval $ac_compiler --version </dev/null >&5) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }
+{ (eval echo "$as_me:$LINENO: \"$ac_compiler -v </dev/null >&5\"") >&5
+ (eval $ac_compiler -v </dev/null >&5) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }
+{ (eval echo "$as_me:$LINENO: \"$ac_compiler -V </dev/null >&5\"") >&5
+ (eval $ac_compiler -V </dev/null >&5) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }
+
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+
+int
+main ()
+{
+
+ ;
+ return 0;
+}
+_ACEOF
+ac_clean_files_save=$ac_clean_files
+ac_clean_files="$ac_clean_files a.out a.exe b.out"
+# Try to create an executable without -o first, disregard a.out.
+# It will help us diagnose broken compilers, and finding out an intuition
+# of exeext.
+echo "$as_me:$LINENO: checking for C compiler default output file name" >&5
+echo $ECHO_N "checking for C compiler default output file name... $ECHO_C" >&6
+ac_link_default=`echo "$ac_link" | sed 's/ -o *conftest[^ ]*//'`
+if { (eval echo "$as_me:$LINENO: \"$ac_link_default\"") >&5
+ (eval $ac_link_default) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; then
+ # Find the output, starting from the most likely. This scheme is
+# not robust to junk in `.', hence go to wildcards (a.*) only as a last
+# resort.
+
+# Be careful to initialize this variable, since it used to be cached.
+# Otherwise an old cache value of `no' led to `EXEEXT = no' in a Makefile.
+ac_cv_exeext=
+# b.out is created by i960 compilers.
+for ac_file in a_out.exe a.exe conftest.exe a.out conftest a.* conftest.* b.out
+do
+ test -f "$ac_file" || continue
+ case $ac_file in
+ *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.o | *.obj )
+ ;;
+ conftest.$ac_ext )
+ # This is the source file.
+ ;;
+ [ab].out )
+ # We found the default executable, but exeext='' is most
+ # certainly right.
+ break;;
+ *.* )
+ ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'`
+ # FIXME: I believe we export ac_cv_exeext for Libtool,
+ # but it would be cool to find out if it's true. Does anybody
+ # maintain Libtool? --akim.
+ export ac_cv_exeext
+ break;;
+ * )
+ break;;
+ esac
+done
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+{ { echo "$as_me:$LINENO: error: C compiler cannot create executables
+See \`config.log' for more details." >&5
+echo "$as_me: error: C compiler cannot create executables
+See \`config.log' for more details." >&2;}
+ { (exit 77); exit 77; }; }
+fi
+
+ac_exeext=$ac_cv_exeext
+echo "$as_me:$LINENO: result: $ac_file" >&5
+echo "${ECHO_T}$ac_file" >&6
+
+# Check the compiler produces executables we can run. If not, either
+# the compiler is broken, or we cross compile.
+echo "$as_me:$LINENO: checking whether the C compiler works" >&5
+echo $ECHO_N "checking whether the C compiler works... $ECHO_C" >&6
+# FIXME: These cross compiler hacks should be removed for Autoconf 3.0
+# If not cross compiling, check that we can run a simple program.
+if test "$cross_compiling" != yes; then
+ if { ac_try='./$ac_file'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ cross_compiling=no
+ else
+ if test "$cross_compiling" = maybe; then
+ cross_compiling=yes
+ else
+ { { echo "$as_me:$LINENO: error: cannot run C compiled programs.
+If you meant to cross compile, use \`--host'.
+See \`config.log' for more details." >&5
+echo "$as_me: error: cannot run C compiled programs.
+If you meant to cross compile, use \`--host'.
+See \`config.log' for more details." >&2;}
+ { (exit 1); exit 1; }; }
+ fi
+ fi
+fi
+echo "$as_me:$LINENO: result: yes" >&5
+echo "${ECHO_T}yes" >&6
+
+rm -f a.out a.exe conftest$ac_cv_exeext b.out
+ac_clean_files=$ac_clean_files_save
+# Check the compiler produces executables we can run. If not, either
+# the compiler is broken, or we cross compile.
+echo "$as_me:$LINENO: checking whether we are cross compiling" >&5
+echo $ECHO_N "checking whether we are cross compiling... $ECHO_C" >&6
+echo "$as_me:$LINENO: result: $cross_compiling" >&5
+echo "${ECHO_T}$cross_compiling" >&6
+
+echo "$as_me:$LINENO: checking for suffix of executables" >&5
+echo $ECHO_N "checking for suffix of executables... $ECHO_C" >&6
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; then
+ # If both `conftest.exe' and `conftest' are `present' (well, observable)
+# catch `conftest.exe'. For instance with Cygwin, `ls conftest' will
+# work properly (i.e., refer to `conftest.exe'), while it won't with
+# `rm'.
+for ac_file in conftest.exe conftest conftest.*; do
+ test -f "$ac_file" || continue
+ case $ac_file in
+ *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.o | *.obj ) ;;
+ *.* ) ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'`
+ export ac_cv_exeext
+ break;;
+ * ) break;;
+ esac
+done
+else
+ { { echo "$as_me:$LINENO: error: cannot compute suffix of executables: cannot compile and link
+See \`config.log' for more details." >&5
+echo "$as_me: error: cannot compute suffix of executables: cannot compile and link
+See \`config.log' for more details." >&2;}
+ { (exit 1); exit 1; }; }
+fi
+
+rm -f conftest$ac_cv_exeext
+echo "$as_me:$LINENO: result: $ac_cv_exeext" >&5
+echo "${ECHO_T}$ac_cv_exeext" >&6
+
+rm -f conftest.$ac_ext
+EXEEXT=$ac_cv_exeext
+ac_exeext=$EXEEXT
+echo "$as_me:$LINENO: checking for suffix of object files" >&5
+echo $ECHO_N "checking for suffix of object files... $ECHO_C" >&6
+if test "${ac_cv_objext+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+
+int
+main ()
+{
+
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.o conftest.obj
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; then
+ for ac_file in `(ls conftest.o conftest.obj; ls conftest.*) 2>/dev/null`; do
+ case $ac_file in
+ *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg ) ;;
+ *) ac_cv_objext=`expr "$ac_file" : '.*\.\(.*\)'`
+ break;;
+ esac
+done
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+{ { echo "$as_me:$LINENO: error: cannot compute suffix of object files: cannot compile
+See \`config.log' for more details." >&5
+echo "$as_me: error: cannot compute suffix of object files: cannot compile
+See \`config.log' for more details." >&2;}
+ { (exit 1); exit 1; }; }
+fi
+
+rm -f conftest.$ac_cv_objext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: $ac_cv_objext" >&5
+echo "${ECHO_T}$ac_cv_objext" >&6
+OBJEXT=$ac_cv_objext
+ac_objext=$OBJEXT
+echo "$as_me:$LINENO: checking whether we are using the GNU C compiler" >&5
+echo $ECHO_N "checking whether we are using the GNU C compiler... $ECHO_C" >&6
+if test "${ac_cv_c_compiler_gnu+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+
+int
+main ()
+{
+#ifndef __GNUC__
+ choke me
+#endif
+
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_compiler_gnu=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_compiler_gnu=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+ac_cv_c_compiler_gnu=$ac_compiler_gnu
+
+fi
+echo "$as_me:$LINENO: result: $ac_cv_c_compiler_gnu" >&5
+echo "${ECHO_T}$ac_cv_c_compiler_gnu" >&6
+GCC=`test $ac_compiler_gnu = yes && echo yes`
+ac_test_CFLAGS=${CFLAGS+set}
+ac_save_CFLAGS=$CFLAGS
+CFLAGS="-g"
+echo "$as_me:$LINENO: checking whether $CC accepts -g" >&5
+echo $ECHO_N "checking whether $CC accepts -g... $ECHO_C" >&6
+if test "${ac_cv_prog_cc_g+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+
+int
+main ()
+{
+
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_prog_cc_g=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_prog_cc_g=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: $ac_cv_prog_cc_g" >&5
+echo "${ECHO_T}$ac_cv_prog_cc_g" >&6
+if test "$ac_test_CFLAGS" = set; then
+ CFLAGS=$ac_save_CFLAGS
+elif test $ac_cv_prog_cc_g = yes; then
+ if test "$GCC" = yes; then
+ CFLAGS="-g -O2"
+ else
+ CFLAGS="-g"
+ fi
+else
+ if test "$GCC" = yes; then
+ CFLAGS="-O2"
+ else
+ CFLAGS=
+ fi
+fi
+echo "$as_me:$LINENO: checking for $CC option to accept ANSI C" >&5
+echo $ECHO_N "checking for $CC option to accept ANSI C... $ECHO_C" >&6
+if test "${ac_cv_prog_cc_stdc+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ ac_cv_prog_cc_stdc=no
+ac_save_CC=$CC
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <stdarg.h>
+#include <stdio.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+/* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */
+struct buf { int x; };
+FILE * (*rcsopen) (struct buf *, struct stat *, int);
+static char *e (p, i)
+ char **p;
+ int i;
+{
+ return p[i];
+}
+static char *f (char * (*g) (char **, int), char **p, ...)
+{
+ char *s;
+ va_list v;
+ va_start (v,p);
+ s = g (p, va_arg (v,int));
+ va_end (v);
+ return s;
+}
+
+/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has
+ function prototypes and stuff, but not '\xHH' hex character constants.
+ These don't provoke an error unfortunately, instead are silently treated
+ as 'x'. The following induces an error, until -std1 is added to get
+ proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an
+ array size at least. It's necessary to write '\x00'==0 to get something
+ that's true only with -std1. */
+int osf4_cc_array ['\x00' == 0 ? 1 : -1];
+
+int test (int i, double x);
+struct s1 {int (*f) (int a);};
+struct s2 {int (*f) (double a);};
+int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int);
+int argc;
+char **argv;
+int
+main ()
+{
+return f (e, argv, 0) != argv[0] || f (e, argv, 1) != argv[1];
+ ;
+ return 0;
+}
+_ACEOF
+# Don't try gcc -ansi; that turns off useful extensions and
+# breaks some systems' header files.
+# AIX -qlanglvl=ansi
+# Ultrix and OSF/1 -std1
+# HP-UX 10.20 and later -Ae
+# HP-UX older versions -Aa -D_HPUX_SOURCE
+# SVR4 -Xc -D__EXTENSIONS__
+for ac_arg in "" -qlanglvl=ansi -std1 -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__"
+do
+ CC="$ac_save_CC $ac_arg"
+ rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_prog_cc_stdc=$ac_arg
+break
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+fi
+rm -f conftest.err conftest.$ac_objext
+done
+rm -f conftest.$ac_ext conftest.$ac_objext
+CC=$ac_save_CC
+
+fi
+
+case "x$ac_cv_prog_cc_stdc" in
+ x|xno)
+ echo "$as_me:$LINENO: result: none needed" >&5
+echo "${ECHO_T}none needed" >&6 ;;
+ *)
+ echo "$as_me:$LINENO: result: $ac_cv_prog_cc_stdc" >&5
+echo "${ECHO_T}$ac_cv_prog_cc_stdc" >&6
+ CC="$CC $ac_cv_prog_cc_stdc" ;;
+esac
+
+# Some people use a C++ compiler to compile C. Since we use `exit',
+# in C++ we need to declare it. In case someone uses the same compiler
+# for both compiling C and C++ we need to have the C++ compiler decide
+# the declaration of exit, since it's the most demanding environment.
+cat >conftest.$ac_ext <<_ACEOF
+#ifndef __cplusplus
+ choke me
+#endif
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ for ac_declaration in \
+ '' \
+ 'extern "C" void std::exit (int) throw (); using std::exit;' \
+ 'extern "C" void std::exit (int); using std::exit;' \
+ 'extern "C" void exit (int) throw ();' \
+ 'extern "C" void exit (int);' \
+ 'void exit (int);'
+do
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+$ac_declaration
+#include <stdlib.h>
+int
+main ()
+{
+exit (42);
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ :
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+continue
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+$ac_declaration
+int
+main ()
+{
+exit (42);
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ break
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+done
+rm -f conftest*
+if test -n "$ac_declaration"; then
+ echo '#ifdef __cplusplus' >>confdefs.h
+ echo $ac_declaration >>confdefs.h
+ echo '#endif' >>confdefs.h
+fi
+
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+
+# Find a good install program. We prefer a C program (faster),
+# so one script is as good as another. But avoid the broken or
+# incompatible versions:
+# SysV /etc/install, /usr/sbin/install
+# SunOS /usr/etc/install
+# IRIX /sbin/install
+# AIX /bin/install
+# AmigaOS /C/install, which installs bootblocks on floppy discs
+# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag
+# AFS /usr/afsws/bin/install, which mishandles nonexistent args
+# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
+# OS/2's system install, which has a completely different semantic
+# ./install, which can be erroneously created by make from ./install.sh.
+echo "$as_me:$LINENO: checking for a BSD-compatible install" >&5
+echo $ECHO_N "checking for a BSD-compatible install... $ECHO_C" >&6
+if test -z "$INSTALL"; then
+if test "${ac_cv_path_install+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ # Account for people who put trailing slashes in PATH elements.
+case $as_dir/ in
+ ./ | .// | /cC/* | \
+ /etc/* | /usr/sbin/* | /usr/etc/* | /sbin/* | /usr/afsws/bin/* | \
+ ?:\\/os2\\/install\\/* | ?:\\/OS2\\/INSTALL\\/* | \
+ /usr/ucb/* ) ;;
+ *)
+ # OSF1 and SCO ODT 3.0 have their own names for install.
+ # Don't use installbsd from OSF since it installs stuff as root
+ # by default.
+ for ac_prog in ginstall scoinst install; do
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if $as_executable_p "$as_dir/$ac_prog$ac_exec_ext"; then
+ if test $ac_prog = install &&
+ grep dspmsg "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then
+ # AIX install. It has an incompatible calling convention.
+ :
+ elif test $ac_prog = install &&
+ grep pwplus "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then
+ # program-specific install script used by HP pwplus--don't use.
+ :
+ else
+ ac_cv_path_install="$as_dir/$ac_prog$ac_exec_ext -c"
+ break 3
+ fi
+ fi
+ done
+ done
+ ;;
+esac
+done
+
+
+fi
+ if test "${ac_cv_path_install+set}" = set; then
+ INSTALL=$ac_cv_path_install
+ else
+ # As a last resort, use the slow shell script. We don't cache a
+ # path for INSTALL within a source directory, because that will
+ # break other packages using the cache if that directory is
+ # removed, or if the path is relative.
+ INSTALL=$ac_install_sh
+ fi
+fi
+echo "$as_me:$LINENO: result: $INSTALL" >&5
+echo "${ECHO_T}$INSTALL" >&6
+
+# Use test -z because SunOS4 sh mishandles braces in ${var-val}.
+# It thinks the first close brace ends the variable substitution.
+test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}'
+
+test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL}'
+
+test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644'
+
+
+# Put a plausible default for CC_FOR_BUILD in Makefile.
+if test "x$cross_compiling" = "xno"; then
+ CC_FOR_BUILD='$(CC)'
+else
+ CC_FOR_BUILD=gcc
+fi
+
+
+
+
+AR=${AR-ar}
+
+if test -n "$ac_tool_prefix"; then
+ # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args.
+set dummy ${ac_tool_prefix}ranlib; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_RANLIB+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ if test -n "$RANLIB"; then
+ ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+ ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib"
+ echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+done
+
+fi
+fi
+RANLIB=$ac_cv_prog_RANLIB
+if test -n "$RANLIB"; then
+ echo "$as_me:$LINENO: result: $RANLIB" >&5
+echo "${ECHO_T}$RANLIB" >&6
+else
+ echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+fi
+if test -z "$ac_cv_prog_RANLIB"; then
+ ac_ct_RANLIB=$RANLIB
+ # Extract the first word of "ranlib", so it can be a program name with args.
+set dummy ranlib; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ if test -n "$ac_ct_RANLIB"; then
+ ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test.
+else
+as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+ ac_cv_prog_ac_ct_RANLIB="ranlib"
+ echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+done
+
+ test -z "$ac_cv_prog_ac_ct_RANLIB" && ac_cv_prog_ac_ct_RANLIB=":"
+fi
+fi
+ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB
+if test -n "$ac_ct_RANLIB"; then
+ echo "$as_me:$LINENO: result: $ac_ct_RANLIB" >&5
+echo "${ECHO_T}$ac_ct_RANLIB" >&6
+else
+ echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+ RANLIB=$ac_ct_RANLIB
+else
+ RANLIB="$ac_cv_prog_RANLIB"
+fi
+
+
+ALL_LINGUAS=
+echo "$as_me:$LINENO: checking whether ${MAKE-make} sets \$(MAKE)" >&5
+echo $ECHO_N "checking whether ${MAKE-make} sets \$(MAKE)... $ECHO_C" >&6
+set dummy ${MAKE-make}; ac_make=`echo "$2" | sed 'y,:./+-,___p_,'`
+if eval "test \"\${ac_cv_prog_make_${ac_make}_set+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.make <<\_ACEOF
+all:
+ @echo 'ac_maketemp="$(MAKE)"'
+_ACEOF
+# GNU make sometimes prints "make[1]: Entering...", which would confuse us.
+eval `${MAKE-make} -f conftest.make 2>/dev/null | grep temp=`
+if test -n "$ac_maketemp"; then
+ eval ac_cv_prog_make_${ac_make}_set=yes
+else
+ eval ac_cv_prog_make_${ac_make}_set=no
+fi
+rm -f conftest.make
+fi
+if eval "test \"`echo '$ac_cv_prog_make_'${ac_make}_set`\" = yes"; then
+ echo "$as_me:$LINENO: result: yes" >&5
+echo "${ECHO_T}yes" >&6
+ SET_MAKE=
+else
+ echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+ SET_MAKE="MAKE=${MAKE-make}"
+fi
+
+
+echo "$as_me:$LINENO: checking for library containing strerror" >&5
+echo $ECHO_N "checking for library containing strerror... $ECHO_C" >&6
+if test "${ac_cv_search_strerror+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ ac_func_search_save_LIBS=$LIBS
+ac_cv_search_strerror=no
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+
+/* Override any gcc2 internal prototype to avoid an error. */
+#ifdef __cplusplus
+extern "C"
+#endif
+/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char strerror ();
+int
+main ()
+{
+strerror ();
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest$ac_exeext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_search_strerror="none required"
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+fi
+rm -f conftest.err conftest.$ac_objext \
+ conftest$ac_exeext conftest.$ac_ext
+if test "$ac_cv_search_strerror" = no; then
+ for ac_lib in cposix; do
+ LIBS="-l$ac_lib $ac_func_search_save_LIBS"
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+
+/* Override any gcc2 internal prototype to avoid an error. */
+#ifdef __cplusplus
+extern "C"
+#endif
+/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char strerror ();
+int
+main ()
+{
+strerror ();
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest$ac_exeext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_search_strerror="-l$ac_lib"
+break
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+fi
+rm -f conftest.err conftest.$ac_objext \
+ conftest$ac_exeext conftest.$ac_ext
+ done
+fi
+LIBS=$ac_func_search_save_LIBS
+fi
+echo "$as_me:$LINENO: result: $ac_cv_search_strerror" >&5
+echo "${ECHO_T}$ac_cv_search_strerror" >&6
+if test "$ac_cv_search_strerror" != no; then
+ test "$ac_cv_search_strerror" = "none required" || LIBS="$ac_cv_search_strerror $LIBS"
+
+fi
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+echo "$as_me:$LINENO: checking how to run the C preprocessor" >&5
+echo $ECHO_N "checking how to run the C preprocessor... $ECHO_C" >&6
+# On Suns, sometimes $CPP names a directory.
+if test -n "$CPP" && test -d "$CPP"; then
+ CPP=
+fi
+if test -z "$CPP"; then
+ if test "${ac_cv_prog_CPP+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ # Double quotes because CPP needs to be expanded
+ for CPP in "$CC -E" "$CC -E -traditional-cpp" "/lib/cpp"
+ do
+ ac_preproc_ok=false
+for ac_c_preproc_warn_flag in '' yes
+do
+ # Use a header file that comes with gcc, so configuring glibc
+ # with a fresh cross-compiler works.
+ # Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
+ # <limits.h> exists even on freestanding compilers.
+ # On the NeXT, cc -E runs the code through the compiler's parser,
+ # not just through cpp. "Syntax error" is here to catch this case.
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#ifdef __STDC__
+# include <limits.h>
+#else
+# include <assert.h>
+#endif
+ Syntax error
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+ (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } >/dev/null; then
+ if test -s conftest.err; then
+ ac_cpp_err=$ac_c_preproc_warn_flag
+ ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+ else
+ ac_cpp_err=
+ fi
+else
+ ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+ :
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ # Broken: fails on valid input.
+continue
+fi
+rm -f conftest.err conftest.$ac_ext
+
+ # OK, works on sane cases. Now check whether non-existent headers
+ # can be detected and how.
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <ac_nonexistent.h>
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+ (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } >/dev/null; then
+ if test -s conftest.err; then
+ ac_cpp_err=$ac_c_preproc_warn_flag
+ ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+ else
+ ac_cpp_err=
+ fi
+else
+ ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+ # Broken: success on invalid input.
+continue
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ # Passes both tests.
+ac_preproc_ok=:
+break
+fi
+rm -f conftest.err conftest.$ac_ext
+
+done
+# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.
+rm -f conftest.err conftest.$ac_ext
+if $ac_preproc_ok; then
+ break
+fi
+
+ done
+ ac_cv_prog_CPP=$CPP
+
+fi
+ CPP=$ac_cv_prog_CPP
+else
+ ac_cv_prog_CPP=$CPP
+fi
+echo "$as_me:$LINENO: result: $CPP" >&5
+echo "${ECHO_T}$CPP" >&6
+ac_preproc_ok=false
+for ac_c_preproc_warn_flag in '' yes
+do
+ # Use a header file that comes with gcc, so configuring glibc
+ # with a fresh cross-compiler works.
+ # Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
+ # <limits.h> exists even on freestanding compilers.
+ # On the NeXT, cc -E runs the code through the compiler's parser,
+ # not just through cpp. "Syntax error" is here to catch this case.
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#ifdef __STDC__
+# include <limits.h>
+#else
+# include <assert.h>
+#endif
+ Syntax error
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+ (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } >/dev/null; then
+ if test -s conftest.err; then
+ ac_cpp_err=$ac_c_preproc_warn_flag
+ ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+ else
+ ac_cpp_err=
+ fi
+else
+ ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+ :
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ # Broken: fails on valid input.
+continue
+fi
+rm -f conftest.err conftest.$ac_ext
+
+ # OK, works on sane cases. Now check whether non-existent headers
+ # can be detected and how.
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <ac_nonexistent.h>
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+ (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } >/dev/null; then
+ if test -s conftest.err; then
+ ac_cpp_err=$ac_c_preproc_warn_flag
+ ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+ else
+ ac_cpp_err=
+ fi
+else
+ ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+ # Broken: success on invalid input.
+continue
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ # Passes both tests.
+ac_preproc_ok=:
+break
+fi
+rm -f conftest.err conftest.$ac_ext
+
+done
+# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped.
+rm -f conftest.err conftest.$ac_ext
+if $ac_preproc_ok; then
+ :
+else
+ { { echo "$as_me:$LINENO: error: C preprocessor \"$CPP\" fails sanity check
+See \`config.log' for more details." >&5
+echo "$as_me: error: C preprocessor \"$CPP\" fails sanity check
+See \`config.log' for more details." >&2;}
+ { (exit 1); exit 1; }; }
+fi
+
+ac_ext=c
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5'
+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5'
+ac_compiler_gnu=$ac_cv_c_compiler_gnu
+
+
+echo "$as_me:$LINENO: checking for egrep" >&5
+echo $ECHO_N "checking for egrep... $ECHO_C" >&6
+if test "${ac_cv_prog_egrep+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ if echo a | (grep -E '(a|b)') >/dev/null 2>&1
+ then ac_cv_prog_egrep='grep -E'
+ else ac_cv_prog_egrep='egrep'
+ fi
+fi
+echo "$as_me:$LINENO: result: $ac_cv_prog_egrep" >&5
+echo "${ECHO_T}$ac_cv_prog_egrep" >&6
+ EGREP=$ac_cv_prog_egrep
+
+
+echo "$as_me:$LINENO: checking for ANSI C header files" >&5
+echo $ECHO_N "checking for ANSI C header files... $ECHO_C" >&6
+if test "${ac_cv_header_stdc+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <stdlib.h>
+#include <stdarg.h>
+#include <string.h>
+#include <float.h>
+
+int
+main ()
+{
+
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_header_stdc=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_header_stdc=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+
+if test $ac_cv_header_stdc = yes; then
+ # SunOS 4.x string.h does not declare mem*, contrary to ANSI.
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <string.h>
+
+_ACEOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+ $EGREP "memchr" >/dev/null 2>&1; then
+ :
+else
+ ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+fi
+
+if test $ac_cv_header_stdc = yes; then
+ # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI.
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <stdlib.h>
+
+_ACEOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+ $EGREP "free" >/dev/null 2>&1; then
+ :
+else
+ ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+fi
+
+if test $ac_cv_header_stdc = yes; then
+ # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi.
+ if test "$cross_compiling" = yes; then
+ :
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <ctype.h>
+#if ((' ' & 0x0FF) == 0x020)
+# define ISLOWER(c) ('a' <= (c) && (c) <= 'z')
+# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c))
+#else
+# define ISLOWER(c) \
+ (('a' <= (c) && (c) <= 'i') \
+ || ('j' <= (c) && (c) <= 'r') \
+ || ('s' <= (c) && (c) <= 'z'))
+# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c))
+#endif
+
+#define XOR(e, f) (((e) && !(f)) || (!(e) && (f)))
+int
+main ()
+{
+ int i;
+ for (i = 0; i < 256; i++)
+ if (XOR (islower (i), ISLOWER (i))
+ || toupper (i) != TOUPPER (i))
+ exit(2);
+ exit (0);
+}
+_ACEOF
+rm -f conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } && { ac_try='./conftest$ac_exeext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ :
+else
+ echo "$as_me: program exited with status $ac_status" >&5
+echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+( exit $ac_status )
+ac_cv_header_stdc=no
+fi
+rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext
+fi
+fi
+fi
+echo "$as_me:$LINENO: result: $ac_cv_header_stdc" >&5
+echo "${ECHO_T}$ac_cv_header_stdc" >&6
+if test $ac_cv_header_stdc = yes; then
+
+cat >>confdefs.h <<\_ACEOF
+#define STDC_HEADERS 1
+_ACEOF
+
+fi
+
+echo "$as_me:$LINENO: checking for an ANSI C-conforming const" >&5
+echo $ECHO_N "checking for an ANSI C-conforming const... $ECHO_C" >&6
+if test "${ac_cv_c_const+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+
+int
+main ()
+{
+/* FIXME: Include the comments suggested by Paul. */
+#ifndef __cplusplus
+ /* Ultrix mips cc rejects this. */
+ typedef int charset[2];
+ const charset x;
+ /* SunOS 4.1.1 cc rejects this. */
+ char const *const *ccp;
+ char **p;
+ /* NEC SVR4.0.2 mips cc rejects this. */
+ struct point {int x, y;};
+ static struct point const zero = {0,0};
+ /* AIX XL C 1.02.0.0 rejects this.
+ It does not let you subtract one const X* pointer from another in
+ an arm of an if-expression whose if-part is not a constant
+ expression */
+ const char *g = "string";
+ ccp = &g + (g ? g-g : 0);
+ /* HPUX 7.0 cc rejects these. */
+ ++ccp;
+ p = (char**) ccp;
+ ccp = (char const *const *) p;
+ { /* SCO 3.2v4 cc rejects this. */
+ char *t;
+ char const *s = 0 ? (char *) 0 : (char const *) 0;
+
+ *t++ = 0;
+ }
+ { /* Someone thinks the Sun supposedly-ANSI compiler will reject this. */
+ int x[] = {25, 17};
+ const int *foo = &x[0];
+ ++foo;
+ }
+ { /* Sun SC1.0 ANSI compiler rejects this -- but not the above. */
+ typedef const int *iptr;
+ iptr p = 0;
+ ++p;
+ }
+ { /* AIX XL C 1.02.0.0 rejects this saying
+ "k.c", line 2.27: 1506-025 (S) Operand must be a modifiable lvalue. */
+ struct s { int j; const int *ap[3]; };
+ struct s *b; b->j = 5;
+ }
+ { /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */
+ const int foo = 10;
+ }
+#endif
+
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_c_const=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_c_const=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: $ac_cv_c_const" >&5
+echo "${ECHO_T}$ac_cv_c_const" >&6
+if test $ac_cv_c_const = no; then
+
+cat >>confdefs.h <<\_ACEOF
+#define const
+_ACEOF
+
+fi
+
+echo "$as_me:$LINENO: checking for inline" >&5
+echo $ECHO_N "checking for inline... $ECHO_C" >&6
+if test "${ac_cv_c_inline+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ ac_cv_c_inline=no
+for ac_kw in inline __inline__ __inline; do
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#ifndef __cplusplus
+typedef int foo_t;
+static $ac_kw foo_t static_foo () {return 0; }
+$ac_kw foo_t foo () {return 0; }
+#endif
+
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_c_inline=$ac_kw; break
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+done
+
+fi
+echo "$as_me:$LINENO: result: $ac_cv_c_inline" >&5
+echo "${ECHO_T}$ac_cv_c_inline" >&6
+
+
+case $ac_cv_c_inline in
+ inline | yes) ;;
+ *)
+ case $ac_cv_c_inline in
+ no) ac_val=;;
+ *) ac_val=$ac_cv_c_inline;;
+ esac
+ cat >>confdefs.h <<_ACEOF
+#ifndef __cplusplus
+#define inline $ac_val
+#endif
+_ACEOF
+ ;;
+esac
+
+# On IRIX 5.3, sys/types and inttypes.h are conflicting.
+
+
+
+
+
+
+
+
+
+for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \
+ inttypes.h stdint.h unistd.h
+do
+as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
+echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+$ac_includes_default
+
+#include <$ac_header>
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ eval "$as_ac_Header=yes"
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+eval "$as_ac_Header=no"
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
+if test `eval echo '${'$as_ac_Header'}'` = yes; then
+ cat >>confdefs.h <<_ACEOF
+#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+
+echo "$as_me:$LINENO: checking for off_t" >&5
+echo $ECHO_N "checking for off_t... $ECHO_C" >&6
+if test "${ac_cv_type_off_t+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+$ac_includes_default
+int
+main ()
+{
+if ((off_t *) 0)
+ return 0;
+if (sizeof (off_t))
+ return 0;
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_type_off_t=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_type_off_t=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: $ac_cv_type_off_t" >&5
+echo "${ECHO_T}$ac_cv_type_off_t" >&6
+if test $ac_cv_type_off_t = yes; then
+ :
+else
+
+cat >>confdefs.h <<_ACEOF
+#define off_t long
+_ACEOF
+
+fi
+
+echo "$as_me:$LINENO: checking for size_t" >&5
+echo $ECHO_N "checking for size_t... $ECHO_C" >&6
+if test "${ac_cv_type_size_t+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+$ac_includes_default
+int
+main ()
+{
+if ((size_t *) 0)
+ return 0;
+if (sizeof (size_t))
+ return 0;
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_type_size_t=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_type_size_t=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: $ac_cv_type_size_t" >&5
+echo "${ECHO_T}$ac_cv_type_size_t" >&6
+if test $ac_cv_type_size_t = yes; then
+ :
+else
+
+cat >>confdefs.h <<_ACEOF
+#define size_t unsigned
+_ACEOF
+
+fi
+
+# The Ultrix 4.2 mips builtin alloca declared by alloca.h only works
+# for constant arguments. Useless!
+echo "$as_me:$LINENO: checking for working alloca.h" >&5
+echo $ECHO_N "checking for working alloca.h... $ECHO_C" >&6
+if test "${ac_cv_working_alloca_h+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <alloca.h>
+int
+main ()
+{
+char *p = (char *) alloca (2 * sizeof (int));
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest$ac_exeext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_working_alloca_h=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_working_alloca_h=no
+fi
+rm -f conftest.err conftest.$ac_objext \
+ conftest$ac_exeext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: $ac_cv_working_alloca_h" >&5
+echo "${ECHO_T}$ac_cv_working_alloca_h" >&6
+if test $ac_cv_working_alloca_h = yes; then
+
+cat >>confdefs.h <<\_ACEOF
+#define HAVE_ALLOCA_H 1
+_ACEOF
+
+fi
+
+echo "$as_me:$LINENO: checking for alloca" >&5
+echo $ECHO_N "checking for alloca... $ECHO_C" >&6
+if test "${ac_cv_func_alloca_works+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#ifdef __GNUC__
+# define alloca __builtin_alloca
+#else
+# ifdef _MSC_VER
+# include <malloc.h>
+# define alloca _alloca
+# else
+# if HAVE_ALLOCA_H
+# include <alloca.h>
+# else
+# ifdef _AIX
+ #pragma alloca
+# else
+# ifndef alloca /* predefined by HP cc +Olibcalls */
+char *alloca ();
+# endif
+# endif
+# endif
+# endif
+#endif
+
+int
+main ()
+{
+char *p = (char *) alloca (1);
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest$ac_exeext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_func_alloca_works=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_func_alloca_works=no
+fi
+rm -f conftest.err conftest.$ac_objext \
+ conftest$ac_exeext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: $ac_cv_func_alloca_works" >&5
+echo "${ECHO_T}$ac_cv_func_alloca_works" >&6
+
+if test $ac_cv_func_alloca_works = yes; then
+
+cat >>confdefs.h <<\_ACEOF
+#define HAVE_ALLOCA 1
+_ACEOF
+
+else
+ # The SVR3 libPW and SVR4 libucb both contain incompatible functions
+# that cause trouble. Some versions do not even contain alloca or
+# contain a buggy version. If you still want to use their alloca,
+# use ar to extract alloca.o from them instead of compiling alloca.c.
+
+ALLOCA=alloca.$ac_objext
+
+cat >>confdefs.h <<\_ACEOF
+#define C_ALLOCA 1
+_ACEOF
+
+
+echo "$as_me:$LINENO: checking whether \`alloca.c' needs Cray hooks" >&5
+echo $ECHO_N "checking whether \`alloca.c' needs Cray hooks... $ECHO_C" >&6
+if test "${ac_cv_os_cray+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#if defined(CRAY) && ! defined(CRAY2)
+webecray
+#else
+wenotbecray
+#endif
+
+_ACEOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+ $EGREP "webecray" >/dev/null 2>&1; then
+ ac_cv_os_cray=yes
+else
+ ac_cv_os_cray=no
+fi
+rm -f conftest*
+
+fi
+echo "$as_me:$LINENO: result: $ac_cv_os_cray" >&5
+echo "${ECHO_T}$ac_cv_os_cray" >&6
+if test $ac_cv_os_cray = yes; then
+ for ac_func in _getb67 GETB67 getb67; do
+ as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
+echo "$as_me:$LINENO: checking for $ac_func" >&5
+echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6
+if eval "test \"\${$as_ac_var+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
+ For example, HP-UX 11i <limits.h> declares gettimeofday. */
+#define $ac_func innocuous_$ac_func
+
+/* System header to define __stub macros and hopefully few prototypes,
+ which can conflict with char $ac_func (); below.
+ Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
+ <limits.h> exists even on freestanding compilers. */
+
+#ifdef __STDC__
+# include <limits.h>
+#else
+# include <assert.h>
+#endif
+
+#undef $ac_func
+
+/* Override any gcc2 internal prototype to avoid an error. */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char $ac_func ();
+/* The GNU C library defines this for functions which it implements
+ to always fail with ENOSYS. Some functions are actually named
+ something starting with __ and the normal name is an alias. */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+char (*f) () = $ac_func;
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+int
+main ()
+{
+return f != $ac_func;
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest$ac_exeext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ eval "$as_ac_var=yes"
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+eval "$as_ac_var=no"
+fi
+rm -f conftest.err conftest.$ac_objext \
+ conftest$ac_exeext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6
+if test `eval echo '${'$as_ac_var'}'` = yes; then
+
+cat >>confdefs.h <<_ACEOF
+#define CRAY_STACKSEG_END $ac_func
+_ACEOF
+
+ break
+fi
+
+ done
+fi
+
+echo "$as_me:$LINENO: checking stack direction for C alloca" >&5
+echo $ECHO_N "checking stack direction for C alloca... $ECHO_C" >&6
+if test "${ac_cv_c_stack_direction+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ if test "$cross_compiling" = yes; then
+ ac_cv_c_stack_direction=0
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+int
+find_stack_direction ()
+{
+ static char *addr = 0;
+ auto char dummy;
+ if (addr == 0)
+ {
+ addr = &dummy;
+ return find_stack_direction ();
+ }
+ else
+ return (&dummy > addr) ? 1 : -1;
+}
+
+int
+main ()
+{
+ exit (find_stack_direction () < 0);
+}
+_ACEOF
+rm -f conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } && { ac_try='./conftest$ac_exeext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_c_stack_direction=1
+else
+ echo "$as_me: program exited with status $ac_status" >&5
+echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+( exit $ac_status )
+ac_cv_c_stack_direction=-1
+fi
+rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext
+fi
+fi
+echo "$as_me:$LINENO: result: $ac_cv_c_stack_direction" >&5
+echo "${ECHO_T}$ac_cv_c_stack_direction" >&6
+
+cat >>confdefs.h <<_ACEOF
+#define STACK_DIRECTION $ac_cv_c_stack_direction
+_ACEOF
+
+
+fi
+
+
+
+for ac_header in stdlib.h unistd.h
+do
+as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
+else
+ # Is the header compilable?
+echo "$as_me:$LINENO: checking $ac_header usability" >&5
+echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+$ac_includes_default
+#include <$ac_header>
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_header_compiler=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_header_compiler=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
+echo "${ECHO_T}$ac_header_compiler" >&6
+
+# Is the header present?
+echo "$as_me:$LINENO: checking $ac_header presence" >&5
+echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <$ac_header>
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+ (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } >/dev/null; then
+ if test -s conftest.err; then
+ ac_cpp_err=$ac_c_preproc_warn_flag
+ ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+ else
+ ac_cpp_err=
+ fi
+else
+ ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+ ac_header_preproc=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ ac_header_preproc=no
+fi
+rm -f conftest.err conftest.$ac_ext
+echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
+echo "${ECHO_T}$ac_header_preproc" >&6
+
+# So? What about this header?
+case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
+ yes:no: )
+ { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
+echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
+echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
+ ac_header_preproc=yes
+ ;;
+ no:yes:* )
+ { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
+echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5
+echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
+echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5
+echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
+echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
+echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
+ (
+ cat <<\_ASBOX
+## ------------------------------------------ ##
+## Report this to the AC_PACKAGE_NAME lists. ##
+## ------------------------------------------ ##
+_ASBOX
+ ) |
+ sed "s/^/$as_me: WARNING: /" >&2
+ ;;
+esac
+echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ eval "$as_ac_Header=\$ac_header_preproc"
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
+
+fi
+if test `eval echo '${'$as_ac_Header'}'` = yes; then
+ cat >>confdefs.h <<_ACEOF
+#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+
+for ac_func in getpagesize
+do
+as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
+echo "$as_me:$LINENO: checking for $ac_func" >&5
+echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6
+if eval "test \"\${$as_ac_var+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
+ For example, HP-UX 11i <limits.h> declares gettimeofday. */
+#define $ac_func innocuous_$ac_func
+
+/* System header to define __stub macros and hopefully few prototypes,
+ which can conflict with char $ac_func (); below.
+ Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
+ <limits.h> exists even on freestanding compilers. */
+
+#ifdef __STDC__
+# include <limits.h>
+#else
+# include <assert.h>
+#endif
+
+#undef $ac_func
+
+/* Override any gcc2 internal prototype to avoid an error. */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char $ac_func ();
+/* The GNU C library defines this for functions which it implements
+ to always fail with ENOSYS. Some functions are actually named
+ something starting with __ and the normal name is an alias. */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+char (*f) () = $ac_func;
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+int
+main ()
+{
+return f != $ac_func;
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest$ac_exeext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ eval "$as_ac_var=yes"
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+eval "$as_ac_var=no"
+fi
+rm -f conftest.err conftest.$ac_objext \
+ conftest$ac_exeext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6
+if test `eval echo '${'$as_ac_var'}'` = yes; then
+ cat >>confdefs.h <<_ACEOF
+#define `echo "HAVE_$ac_func" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+done
+
+echo "$as_me:$LINENO: checking for working mmap" >&5
+echo $ECHO_N "checking for working mmap... $ECHO_C" >&6
+if test "${ac_cv_func_mmap_fixed_mapped+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ if test "$cross_compiling" = yes; then
+ ac_cv_func_mmap_fixed_mapped=no
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+$ac_includes_default
+/* malloc might have been renamed as rpl_malloc. */
+#undef malloc
+
+/* Thanks to Mike Haertel and Jim Avera for this test.
+ Here is a matrix of mmap possibilities:
+ mmap private not fixed
+ mmap private fixed at somewhere currently unmapped
+ mmap private fixed at somewhere already mapped
+ mmap shared not fixed
+ mmap shared fixed at somewhere currently unmapped
+ mmap shared fixed at somewhere already mapped
+ For private mappings, we should verify that changes cannot be read()
+ back from the file, nor mmap's back from the file at a different
+ address. (There have been systems where private was not correctly
+ implemented like the infamous i386 svr4.0, and systems where the
+ VM page cache was not coherent with the file system buffer cache
+ like early versions of FreeBSD and possibly contemporary NetBSD.)
+ For shared mappings, we should conversely verify that changes get
+ propagated back to all the places they're supposed to be.
+
+ Grep wants private fixed already mapped.
+ The main things grep needs to know about mmap are:
+ * does it exist and is it safe to write into the mmap'd area
+ * how to use it (BSD variants) */
+
+#include <fcntl.h>
+#include <sys/mman.h>
+
+#if !STDC_HEADERS && !HAVE_STDLIB_H
+char *malloc ();
+#endif
+
+/* This mess was copied from the GNU getpagesize.h. */
+#if !HAVE_GETPAGESIZE
+/* Assume that all systems that can run configure have sys/param.h. */
+# if !HAVE_SYS_PARAM_H
+# define HAVE_SYS_PARAM_H 1
+# endif
+
+# ifdef _SC_PAGESIZE
+# define getpagesize() sysconf(_SC_PAGESIZE)
+# else /* no _SC_PAGESIZE */
+# if HAVE_SYS_PARAM_H
+# include <sys/param.h>
+# ifdef EXEC_PAGESIZE
+# define getpagesize() EXEC_PAGESIZE
+# else /* no EXEC_PAGESIZE */
+# ifdef NBPG
+# define getpagesize() NBPG * CLSIZE
+# ifndef CLSIZE
+# define CLSIZE 1
+# endif /* no CLSIZE */
+# else /* no NBPG */
+# ifdef NBPC
+# define getpagesize() NBPC
+# else /* no NBPC */
+# ifdef PAGESIZE
+# define getpagesize() PAGESIZE
+# endif /* PAGESIZE */
+# endif /* no NBPC */
+# endif /* no NBPG */
+# endif /* no EXEC_PAGESIZE */
+# else /* no HAVE_SYS_PARAM_H */
+# define getpagesize() 8192 /* punt totally */
+# endif /* no HAVE_SYS_PARAM_H */
+# endif /* no _SC_PAGESIZE */
+
+#endif /* no HAVE_GETPAGESIZE */
+
+int
+main ()
+{
+ char *data, *data2, *data3;
+ int i, pagesize;
+ int fd;
+
+ pagesize = getpagesize ();
+
+ /* First, make a file with some known garbage in it. */
+ data = (char *) malloc (pagesize);
+ if (!data)
+ exit (1);
+ for (i = 0; i < pagesize; ++i)
+ *(data + i) = rand ();
+ umask (0);
+ fd = creat ("conftest.mmap", 0600);
+ if (fd < 0)
+ exit (1);
+ if (write (fd, data, pagesize) != pagesize)
+ exit (1);
+ close (fd);
+
+ /* Next, try to mmap the file at a fixed address which already has
+ something else allocated at it. If we can, also make sure that
+ we see the same garbage. */
+ fd = open ("conftest.mmap", O_RDWR);
+ if (fd < 0)
+ exit (1);
+ data2 = (char *) malloc (2 * pagesize);
+ if (!data2)
+ exit (1);
+ data2 += (pagesize - ((long) data2 & (pagesize - 1))) & (pagesize - 1);
+ if (data2 != mmap (data2, pagesize, PROT_READ | PROT_WRITE,
+ MAP_PRIVATE | MAP_FIXED, fd, 0L))
+ exit (1);
+ for (i = 0; i < pagesize; ++i)
+ if (*(data + i) != *(data2 + i))
+ exit (1);
+
+ /* Finally, make sure that changes to the mapped area do not
+ percolate back to the file as seen by read(). (This is a bug on
+ some variants of i386 svr4.0.) */
+ for (i = 0; i < pagesize; ++i)
+ *(data2 + i) = *(data2 + i) + 1;
+ data3 = (char *) malloc (pagesize);
+ if (!data3)
+ exit (1);
+ if (read (fd, data3, pagesize) != pagesize)
+ exit (1);
+ for (i = 0; i < pagesize; ++i)
+ if (*(data + i) != *(data3 + i))
+ exit (1);
+ close (fd);
+ exit (0);
+}
+_ACEOF
+rm -f conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } && { ac_try='./conftest$ac_exeext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_func_mmap_fixed_mapped=yes
+else
+ echo "$as_me: program exited with status $ac_status" >&5
+echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+( exit $ac_status )
+ac_cv_func_mmap_fixed_mapped=no
+fi
+rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext
+fi
+fi
+echo "$as_me:$LINENO: result: $ac_cv_func_mmap_fixed_mapped" >&5
+echo "${ECHO_T}$ac_cv_func_mmap_fixed_mapped" >&6
+if test $ac_cv_func_mmap_fixed_mapped = yes; then
+
+cat >>confdefs.h <<\_ACEOF
+#define HAVE_MMAP 1
+_ACEOF
+
+fi
+rm -f conftest.mmap
+
+
+
+
+
+
+
+
+
+
+
+for ac_header in argz.h limits.h locale.h nl_types.h malloc.h string.h \
+unistd.h values.h sys/param.h
+do
+as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
+else
+ # Is the header compilable?
+echo "$as_me:$LINENO: checking $ac_header usability" >&5
+echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+$ac_includes_default
+#include <$ac_header>
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_header_compiler=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_header_compiler=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
+echo "${ECHO_T}$ac_header_compiler" >&6
+
+# Is the header present?
+echo "$as_me:$LINENO: checking $ac_header presence" >&5
+echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <$ac_header>
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+ (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } >/dev/null; then
+ if test -s conftest.err; then
+ ac_cpp_err=$ac_c_preproc_warn_flag
+ ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+ else
+ ac_cpp_err=
+ fi
+else
+ ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+ ac_header_preproc=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ ac_header_preproc=no
+fi
+rm -f conftest.err conftest.$ac_ext
+echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
+echo "${ECHO_T}$ac_header_preproc" >&6
+
+# So? What about this header?
+case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
+ yes:no: )
+ { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
+echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
+echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
+ ac_header_preproc=yes
+ ;;
+ no:yes:* )
+ { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
+echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5
+echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
+echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5
+echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
+echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
+echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
+ (
+ cat <<\_ASBOX
+## ------------------------------------------ ##
+## Report this to the AC_PACKAGE_NAME lists. ##
+## ------------------------------------------ ##
+_ASBOX
+ ) |
+ sed "s/^/$as_me: WARNING: /" >&2
+ ;;
+esac
+echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ eval "$as_ac_Header=\$ac_header_preproc"
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
+
+fi
+if test `eval echo '${'$as_ac_Header'}'` = yes; then
+ cat >>confdefs.h <<_ACEOF
+#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+
+
+
+
+
+
+
+
+
+
+for ac_func in getcwd munmap putenv setenv setlocale strchr strcasecmp \
+__argz_count __argz_stringify __argz_next
+do
+as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
+echo "$as_me:$LINENO: checking for $ac_func" >&5
+echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6
+if eval "test \"\${$as_ac_var+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
+ For example, HP-UX 11i <limits.h> declares gettimeofday. */
+#define $ac_func innocuous_$ac_func
+
+/* System header to define __stub macros and hopefully few prototypes,
+ which can conflict with char $ac_func (); below.
+ Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
+ <limits.h> exists even on freestanding compilers. */
+
+#ifdef __STDC__
+# include <limits.h>
+#else
+# include <assert.h>
+#endif
+
+#undef $ac_func
+
+/* Override any gcc2 internal prototype to avoid an error. */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char $ac_func ();
+/* The GNU C library defines this for functions which it implements
+ to always fail with ENOSYS. Some functions are actually named
+ something starting with __ and the normal name is an alias. */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+char (*f) () = $ac_func;
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+int
+main ()
+{
+return f != $ac_func;
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest$ac_exeext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ eval "$as_ac_var=yes"
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+eval "$as_ac_var=no"
+fi
+rm -f conftest.err conftest.$ac_objext \
+ conftest$ac_exeext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6
+if test `eval echo '${'$as_ac_var'}'` = yes; then
+ cat >>confdefs.h <<_ACEOF
+#define `echo "HAVE_$ac_func" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+done
+
+
+ if test "${ac_cv_func_stpcpy+set}" != "set"; then
+
+for ac_func in stpcpy
+do
+as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
+echo "$as_me:$LINENO: checking for $ac_func" >&5
+echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6
+if eval "test \"\${$as_ac_var+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
+ For example, HP-UX 11i <limits.h> declares gettimeofday. */
+#define $ac_func innocuous_$ac_func
+
+/* System header to define __stub macros and hopefully few prototypes,
+ which can conflict with char $ac_func (); below.
+ Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
+ <limits.h> exists even on freestanding compilers. */
+
+#ifdef __STDC__
+# include <limits.h>
+#else
+# include <assert.h>
+#endif
+
+#undef $ac_func
+
+/* Override any gcc2 internal prototype to avoid an error. */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char $ac_func ();
+/* The GNU C library defines this for functions which it implements
+ to always fail with ENOSYS. Some functions are actually named
+ something starting with __ and the normal name is an alias. */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+char (*f) () = $ac_func;
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+int
+main ()
+{
+return f != $ac_func;
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest$ac_exeext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ eval "$as_ac_var=yes"
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+eval "$as_ac_var=no"
+fi
+rm -f conftest.err conftest.$ac_objext \
+ conftest$ac_exeext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6
+if test `eval echo '${'$as_ac_var'}'` = yes; then
+ cat >>confdefs.h <<_ACEOF
+#define `echo "HAVE_$ac_func" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+done
+
+ fi
+ if test "${ac_cv_func_stpcpy}" = "yes"; then
+ cat >>confdefs.h <<\_ACEOF
+#define HAVE_STPCPY 1
+_ACEOF
+
+ fi
+
+ if test $ac_cv_header_locale_h = yes; then
+ echo "$as_me:$LINENO: checking for LC_MESSAGES" >&5
+echo $ECHO_N "checking for LC_MESSAGES... $ECHO_C" >&6
+if test "${am_cv_val_LC_MESSAGES+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <locale.h>
+int
+main ()
+{
+return LC_MESSAGES
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest$ac_exeext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ am_cv_val_LC_MESSAGES=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+am_cv_val_LC_MESSAGES=no
+fi
+rm -f conftest.err conftest.$ac_objext \
+ conftest$ac_exeext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: $am_cv_val_LC_MESSAGES" >&5
+echo "${ECHO_T}$am_cv_val_LC_MESSAGES" >&6
+ if test $am_cv_val_LC_MESSAGES = yes; then
+ cat >>confdefs.h <<\_ACEOF
+#define HAVE_LC_MESSAGES 1
+_ACEOF
+
+ fi
+ fi
+ echo "$as_me:$LINENO: checking whether NLS is requested" >&5
+echo $ECHO_N "checking whether NLS is requested... $ECHO_C" >&6
+ # Check whether --enable-nls or --disable-nls was given.
+if test "${enable_nls+set}" = set; then
+ enableval="$enable_nls"
+ USE_NLS=$enableval
+else
+ USE_NLS=yes
+fi;
+ echo "$as_me:$LINENO: result: $USE_NLS" >&5
+echo "${ECHO_T}$USE_NLS" >&6
+
+
+ USE_INCLUDED_LIBINTL=no
+
+ if test "$USE_NLS" = "yes"; then
+ cat >>confdefs.h <<\_ACEOF
+#define ENABLE_NLS 1
+_ACEOF
+
+ echo "$as_me:$LINENO: checking whether included gettext is requested" >&5
+echo $ECHO_N "checking whether included gettext is requested... $ECHO_C" >&6
+
+# Check whether --with-included-gettext or --without-included-gettext was given.
+if test "${with_included_gettext+set}" = set; then
+ withval="$with_included_gettext"
+ nls_cv_force_use_gnu_gettext=$withval
+else
+ nls_cv_force_use_gnu_gettext=no
+fi;
+ echo "$as_me:$LINENO: result: $nls_cv_force_use_gnu_gettext" >&5
+echo "${ECHO_T}$nls_cv_force_use_gnu_gettext" >&6
+
+ nls_cv_use_gnu_gettext="$nls_cv_force_use_gnu_gettext"
+ if test "$nls_cv_force_use_gnu_gettext" != "yes"; then
+ nls_cv_header_intl=
+ nls_cv_header_libgt=
+ CATOBJEXT=NONE
+
+ if test "${ac_cv_header_libintl_h+set}" = set; then
+ echo "$as_me:$LINENO: checking for libintl.h" >&5
+echo $ECHO_N "checking for libintl.h... $ECHO_C" >&6
+if test "${ac_cv_header_libintl_h+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+fi
+echo "$as_me:$LINENO: result: $ac_cv_header_libintl_h" >&5
+echo "${ECHO_T}$ac_cv_header_libintl_h" >&6
+else
+ # Is the header compilable?
+echo "$as_me:$LINENO: checking libintl.h usability" >&5
+echo $ECHO_N "checking libintl.h usability... $ECHO_C" >&6
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+$ac_includes_default
+#include <libintl.h>
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_header_compiler=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_header_compiler=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
+echo "${ECHO_T}$ac_header_compiler" >&6
+
+# Is the header present?
+echo "$as_me:$LINENO: checking libintl.h presence" >&5
+echo $ECHO_N "checking libintl.h presence... $ECHO_C" >&6
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <libintl.h>
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+ (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } >/dev/null; then
+ if test -s conftest.err; then
+ ac_cpp_err=$ac_c_preproc_warn_flag
+ ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+ else
+ ac_cpp_err=
+ fi
+else
+ ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+ ac_header_preproc=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ ac_header_preproc=no
+fi
+rm -f conftest.err conftest.$ac_ext
+echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
+echo "${ECHO_T}$ac_header_preproc" >&6
+
+# So? What about this header?
+case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
+ yes:no: )
+ { echo "$as_me:$LINENO: WARNING: libintl.h: accepted by the compiler, rejected by the preprocessor!" >&5
+echo "$as_me: WARNING: libintl.h: accepted by the compiler, rejected by the preprocessor!" >&2;}
+ { echo "$as_me:$LINENO: WARNING: libintl.h: proceeding with the compiler's result" >&5
+echo "$as_me: WARNING: libintl.h: proceeding with the compiler's result" >&2;}
+ ac_header_preproc=yes
+ ;;
+ no:yes:* )
+ { echo "$as_me:$LINENO: WARNING: libintl.h: present but cannot be compiled" >&5
+echo "$as_me: WARNING: libintl.h: present but cannot be compiled" >&2;}
+ { echo "$as_me:$LINENO: WARNING: libintl.h: check for missing prerequisite headers?" >&5
+echo "$as_me: WARNING: libintl.h: check for missing prerequisite headers?" >&2;}
+ { echo "$as_me:$LINENO: WARNING: libintl.h: see the Autoconf documentation" >&5
+echo "$as_me: WARNING: libintl.h: see the Autoconf documentation" >&2;}
+ { echo "$as_me:$LINENO: WARNING: libintl.h: section \"Present But Cannot Be Compiled\"" >&5
+echo "$as_me: WARNING: libintl.h: section \"Present But Cannot Be Compiled\"" >&2;}
+ { echo "$as_me:$LINENO: WARNING: libintl.h: proceeding with the preprocessor's result" >&5
+echo "$as_me: WARNING: libintl.h: proceeding with the preprocessor's result" >&2;}
+ { echo "$as_me:$LINENO: WARNING: libintl.h: in the future, the compiler will take precedence" >&5
+echo "$as_me: WARNING: libintl.h: in the future, the compiler will take precedence" >&2;}
+ (
+ cat <<\_ASBOX
+## ------------------------------------------ ##
+## Report this to the AC_PACKAGE_NAME lists. ##
+## ------------------------------------------ ##
+_ASBOX
+ ) |
+ sed "s/^/$as_me: WARNING: /" >&2
+ ;;
+esac
+echo "$as_me:$LINENO: checking for libintl.h" >&5
+echo $ECHO_N "checking for libintl.h... $ECHO_C" >&6
+if test "${ac_cv_header_libintl_h+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ ac_cv_header_libintl_h=$ac_header_preproc
+fi
+echo "$as_me:$LINENO: result: $ac_cv_header_libintl_h" >&5
+echo "${ECHO_T}$ac_cv_header_libintl_h" >&6
+
+fi
+if test $ac_cv_header_libintl_h = yes; then
+ echo "$as_me:$LINENO: checking for gettext in libc" >&5
+echo $ECHO_N "checking for gettext in libc... $ECHO_C" >&6
+if test "${gt_cv_func_gettext_libc+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <libintl.h>
+int
+main ()
+{
+return (int) gettext ("")
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest$ac_exeext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ gt_cv_func_gettext_libc=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+gt_cv_func_gettext_libc=no
+fi
+rm -f conftest.err conftest.$ac_objext \
+ conftest$ac_exeext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: $gt_cv_func_gettext_libc" >&5
+echo "${ECHO_T}$gt_cv_func_gettext_libc" >&6
+
+ if test "$gt_cv_func_gettext_libc" != "yes"; then
+ echo "$as_me:$LINENO: checking for bindtextdomain in -lintl" >&5
+echo $ECHO_N "checking for bindtextdomain in -lintl... $ECHO_C" >&6
+if test "${ac_cv_lib_intl_bindtextdomain+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ ac_check_lib_save_LIBS=$LIBS
+LIBS="-lintl $LIBS"
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+
+/* Override any gcc2 internal prototype to avoid an error. */
+#ifdef __cplusplus
+extern "C"
+#endif
+/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char bindtextdomain ();
+int
+main ()
+{
+bindtextdomain ();
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest$ac_exeext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_lib_intl_bindtextdomain=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_lib_intl_bindtextdomain=no
+fi
+rm -f conftest.err conftest.$ac_objext \
+ conftest$ac_exeext conftest.$ac_ext
+LIBS=$ac_check_lib_save_LIBS
+fi
+echo "$as_me:$LINENO: result: $ac_cv_lib_intl_bindtextdomain" >&5
+echo "${ECHO_T}$ac_cv_lib_intl_bindtextdomain" >&6
+if test $ac_cv_lib_intl_bindtextdomain = yes; then
+ echo "$as_me:$LINENO: checking for gettext in libintl" >&5
+echo $ECHO_N "checking for gettext in libintl... $ECHO_C" >&6
+if test "${gt_cv_func_gettext_libintl+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+
+int
+main ()
+{
+return (int) gettext ("")
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest$ac_exeext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ gt_cv_func_gettext_libintl=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+gt_cv_func_gettext_libintl=no
+fi
+rm -f conftest.err conftest.$ac_objext \
+ conftest$ac_exeext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: $gt_cv_func_gettext_libintl" >&5
+echo "${ECHO_T}$gt_cv_func_gettext_libintl" >&6
+fi
+
+ fi
+
+ if test "$gt_cv_func_gettext_libc" = "yes" \
+ || test "$gt_cv_func_gettext_libintl" = "yes"; then
+ cat >>confdefs.h <<\_ACEOF
+#define HAVE_GETTEXT 1
+_ACEOF
+
+ # Extract the first word of "msgfmt", so it can be a program name with args.
+set dummy msgfmt; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_path_MSGFMT+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ case "$MSGFMT" in
+ /*)
+ ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path.
+ ;;
+ *)
+ IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:"
+ for ac_dir in $PATH; do
+ test -z "$ac_dir" && ac_dir=.
+ if test -f $ac_dir/$ac_word; then
+ if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then
+ ac_cv_path_MSGFMT="$ac_dir/$ac_word"
+ break
+ fi
+ fi
+ done
+ IFS="$ac_save_ifs"
+ test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="no"
+ ;;
+esac
+fi
+MSGFMT="$ac_cv_path_MSGFMT"
+if test -n "$MSGFMT"; then
+ echo "$as_me:$LINENO: result: $MSGFMT" >&5
+echo "${ECHO_T}$MSGFMT" >&6
+else
+ echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+ if test "$MSGFMT" != "no"; then
+
+for ac_func in dcgettext
+do
+as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
+echo "$as_me:$LINENO: checking for $ac_func" >&5
+echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6
+if eval "test \"\${$as_ac_var+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
+ For example, HP-UX 11i <limits.h> declares gettimeofday. */
+#define $ac_func innocuous_$ac_func
+
+/* System header to define __stub macros and hopefully few prototypes,
+ which can conflict with char $ac_func (); below.
+ Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
+ <limits.h> exists even on freestanding compilers. */
+
+#ifdef __STDC__
+# include <limits.h>
+#else
+# include <assert.h>
+#endif
+
+#undef $ac_func
+
+/* Override any gcc2 internal prototype to avoid an error. */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char $ac_func ();
+/* The GNU C library defines this for functions which it implements
+ to always fail with ENOSYS. Some functions are actually named
+ something starting with __ and the normal name is an alias. */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+char (*f) () = $ac_func;
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+int
+main ()
+{
+return f != $ac_func;
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest$ac_exeext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ eval "$as_ac_var=yes"
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+eval "$as_ac_var=no"
+fi
+rm -f conftest.err conftest.$ac_objext \
+ conftest$ac_exeext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6
+if test `eval echo '${'$as_ac_var'}'` = yes; then
+ cat >>confdefs.h <<_ACEOF
+#define `echo "HAVE_$ac_func" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+done
+
+ # Extract the first word of "gmsgfmt", so it can be a program name with args.
+set dummy gmsgfmt; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_path_GMSGFMT+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ case $GMSGFMT in
+ [\\/]* | ?:[\\/]*)
+ ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path.
+ ;;
+ *)
+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+ ac_cv_path_GMSGFMT="$as_dir/$ac_word$ac_exec_ext"
+ echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+done
+
+ test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT"
+ ;;
+esac
+fi
+GMSGFMT=$ac_cv_path_GMSGFMT
+
+if test -n "$GMSGFMT"; then
+ echo "$as_me:$LINENO: result: $GMSGFMT" >&5
+echo "${ECHO_T}$GMSGFMT" >&6
+else
+ echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+ # Extract the first word of "xgettext", so it can be a program name with args.
+set dummy xgettext; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_path_XGETTEXT+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ case "$XGETTEXT" in
+ /*)
+ ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path.
+ ;;
+ *)
+ IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:"
+ for ac_dir in $PATH; do
+ test -z "$ac_dir" && ac_dir=.
+ if test -f $ac_dir/$ac_word; then
+ if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then
+ ac_cv_path_XGETTEXT="$ac_dir/$ac_word"
+ break
+ fi
+ fi
+ done
+ IFS="$ac_save_ifs"
+ test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":"
+ ;;
+esac
+fi
+XGETTEXT="$ac_cv_path_XGETTEXT"
+if test -n "$XGETTEXT"; then
+ echo "$as_me:$LINENO: result: $XGETTEXT" >&5
+echo "${ECHO_T}$XGETTEXT" >&6
+else
+ echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+
+int
+main ()
+{
+extern int _nl_msg_cat_cntr;
+ return _nl_msg_cat_cntr
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest$ac_exeext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ CATOBJEXT=.gmo
+ DATADIRNAME=share
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+CATOBJEXT=.mo
+ DATADIRNAME=lib
+fi
+rm -f conftest.err conftest.$ac_objext \
+ conftest$ac_exeext conftest.$ac_ext
+ INSTOBJEXT=.mo
+ fi
+ fi
+
+fi
+
+
+
+
+ if test "$CATOBJEXT" = "NONE"; then
+ nls_cv_use_gnu_gettext=yes
+ fi
+ fi
+
+ if test "$nls_cv_use_gnu_gettext" = "yes"; then
+ INTLOBJS="\$(GETTOBJS)"
+ # Extract the first word of "msgfmt", so it can be a program name with args.
+set dummy msgfmt; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_path_MSGFMT+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ case "$MSGFMT" in
+ /*)
+ ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path.
+ ;;
+ *)
+ IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:"
+ for ac_dir in $PATH; do
+ test -z "$ac_dir" && ac_dir=.
+ if test -f $ac_dir/$ac_word; then
+ if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then
+ ac_cv_path_MSGFMT="$ac_dir/$ac_word"
+ break
+ fi
+ fi
+ done
+ IFS="$ac_save_ifs"
+ test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="msgfmt"
+ ;;
+esac
+fi
+MSGFMT="$ac_cv_path_MSGFMT"
+if test -n "$MSGFMT"; then
+ echo "$as_me:$LINENO: result: $MSGFMT" >&5
+echo "${ECHO_T}$MSGFMT" >&6
+else
+ echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+ # Extract the first word of "gmsgfmt", so it can be a program name with args.
+set dummy gmsgfmt; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_path_GMSGFMT+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ case $GMSGFMT in
+ [\\/]* | ?:[\\/]*)
+ ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path.
+ ;;
+ *)
+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for ac_exec_ext in '' $ac_executable_extensions; do
+ if $as_executable_p "$as_dir/$ac_word$ac_exec_ext"; then
+ ac_cv_path_GMSGFMT="$as_dir/$ac_word$ac_exec_ext"
+ echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5
+ break 2
+ fi
+done
+done
+
+ test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT"
+ ;;
+esac
+fi
+GMSGFMT=$ac_cv_path_GMSGFMT
+
+if test -n "$GMSGFMT"; then
+ echo "$as_me:$LINENO: result: $GMSGFMT" >&5
+echo "${ECHO_T}$GMSGFMT" >&6
+else
+ echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+ # Extract the first word of "xgettext", so it can be a program name with args.
+set dummy xgettext; ac_word=$2
+echo "$as_me:$LINENO: checking for $ac_word" >&5
+echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6
+if test "${ac_cv_path_XGETTEXT+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ case "$XGETTEXT" in
+ /*)
+ ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path.
+ ;;
+ *)
+ IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:"
+ for ac_dir in $PATH; do
+ test -z "$ac_dir" && ac_dir=.
+ if test -f $ac_dir/$ac_word; then
+ if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then
+ ac_cv_path_XGETTEXT="$ac_dir/$ac_word"
+ break
+ fi
+ fi
+ done
+ IFS="$ac_save_ifs"
+ test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":"
+ ;;
+esac
+fi
+XGETTEXT="$ac_cv_path_XGETTEXT"
+if test -n "$XGETTEXT"; then
+ echo "$as_me:$LINENO: result: $XGETTEXT" >&5
+echo "${ECHO_T}$XGETTEXT" >&6
+else
+ echo "$as_me:$LINENO: result: no" >&5
+echo "${ECHO_T}no" >&6
+fi
+
+
+ USE_INCLUDED_LIBINTL=yes
+ CATOBJEXT=.gmo
+ INSTOBJEXT=.mo
+ DATADIRNAME=share
+ INTLDEPS='$(top_builddir)/../intl/libintl.a'
+ INTLLIBS=$INTLDEPS
+ LIBS=`echo $LIBS | sed -e 's/-lintl//'`
+ nls_cv_header_intl=libintl.h
+ nls_cv_header_libgt=libgettext.h
+ fi
+
+ if test "$XGETTEXT" != ":"; then
+ if $XGETTEXT --omit-header /dev/null 2> /dev/null; then
+ : ;
+ else
+ echo "$as_me:$LINENO: result: found xgettext programs is not GNU xgettext; ignore it" >&5
+echo "${ECHO_T}found xgettext programs is not GNU xgettext; ignore it" >&6
+ XGETTEXT=":"
+ fi
+ fi
+
+ # We need to process the po/ directory.
+ POSUB=po
+ else
+ DATADIRNAME=share
+ nls_cv_header_intl=libintl.h
+ nls_cv_header_libgt=libgettext.h
+ fi
+
+ # If this is used in GNU gettext we have to set USE_NLS to `yes'
+ # because some of the sources are only built for this goal.
+ if test "$PACKAGE" = gettext; then
+ USE_NLS=yes
+ USE_INCLUDED_LIBINTL=yes
+ fi
+
+ for lang in $ALL_LINGUAS; do
+ GMOFILES="$GMOFILES $lang.gmo"
+ POFILES="$POFILES $lang.po"
+ done
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ if test "x$CATOBJEXT" != "x"; then
+ if test "x$ALL_LINGUAS" = "x"; then
+ LINGUAS=
+ else
+ echo "$as_me:$LINENO: checking for catalogs to be installed" >&5
+echo $ECHO_N "checking for catalogs to be installed... $ECHO_C" >&6
+ NEW_LINGUAS=
+ for lang in ${LINGUAS=$ALL_LINGUAS}; do
+ case "$ALL_LINGUAS" in
+ *$lang*) NEW_LINGUAS="$NEW_LINGUAS $lang" ;;
+ esac
+ done
+ LINGUAS=$NEW_LINGUAS
+ echo "$as_me:$LINENO: result: $LINGUAS" >&5
+echo "${ECHO_T}$LINGUAS" >&6
+ fi
+
+ if test -n "$LINGUAS"; then
+ for lang in $LINGUAS; do CATALOGS="$CATALOGS $lang$CATOBJEXT"; done
+ fi
+ fi
+
+ if test $ac_cv_header_locale_h = yes; then
+ INCLUDE_LOCALE_H="#include <locale.h>"
+ else
+ INCLUDE_LOCALE_H="\
+/* The system does not provide the header <locale.h>. Take care yourself. */"
+ fi
+
+
+ if test -f $srcdir/po2tbl.sed.in; then
+ if test "$CATOBJEXT" = ".cat"; then
+ if test "${ac_cv_header_linux_version_h+set}" = set; then
+ echo "$as_me:$LINENO: checking for linux/version.h" >&5
+echo $ECHO_N "checking for linux/version.h... $ECHO_C" >&6
+if test "${ac_cv_header_linux_version_h+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+fi
+echo "$as_me:$LINENO: result: $ac_cv_header_linux_version_h" >&5
+echo "${ECHO_T}$ac_cv_header_linux_version_h" >&6
+else
+ # Is the header compilable?
+echo "$as_me:$LINENO: checking linux/version.h usability" >&5
+echo $ECHO_N "checking linux/version.h usability... $ECHO_C" >&6
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+$ac_includes_default
+#include <linux/version.h>
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_header_compiler=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_header_compiler=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
+echo "${ECHO_T}$ac_header_compiler" >&6
+
+# Is the header present?
+echo "$as_me:$LINENO: checking linux/version.h presence" >&5
+echo $ECHO_N "checking linux/version.h presence... $ECHO_C" >&6
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <linux/version.h>
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+ (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } >/dev/null; then
+ if test -s conftest.err; then
+ ac_cpp_err=$ac_c_preproc_warn_flag
+ ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+ else
+ ac_cpp_err=
+ fi
+else
+ ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+ ac_header_preproc=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ ac_header_preproc=no
+fi
+rm -f conftest.err conftest.$ac_ext
+echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
+echo "${ECHO_T}$ac_header_preproc" >&6
+
+# So? What about this header?
+case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
+ yes:no: )
+ { echo "$as_me:$LINENO: WARNING: linux/version.h: accepted by the compiler, rejected by the preprocessor!" >&5
+echo "$as_me: WARNING: linux/version.h: accepted by the compiler, rejected by the preprocessor!" >&2;}
+ { echo "$as_me:$LINENO: WARNING: linux/version.h: proceeding with the compiler's result" >&5
+echo "$as_me: WARNING: linux/version.h: proceeding with the compiler's result" >&2;}
+ ac_header_preproc=yes
+ ;;
+ no:yes:* )
+ { echo "$as_me:$LINENO: WARNING: linux/version.h: present but cannot be compiled" >&5
+echo "$as_me: WARNING: linux/version.h: present but cannot be compiled" >&2;}
+ { echo "$as_me:$LINENO: WARNING: linux/version.h: check for missing prerequisite headers?" >&5
+echo "$as_me: WARNING: linux/version.h: check for missing prerequisite headers?" >&2;}
+ { echo "$as_me:$LINENO: WARNING: linux/version.h: see the Autoconf documentation" >&5
+echo "$as_me: WARNING: linux/version.h: see the Autoconf documentation" >&2;}
+ { echo "$as_me:$LINENO: WARNING: linux/version.h: section \"Present But Cannot Be Compiled\"" >&5
+echo "$as_me: WARNING: linux/version.h: section \"Present But Cannot Be Compiled\"" >&2;}
+ { echo "$as_me:$LINENO: WARNING: linux/version.h: proceeding with the preprocessor's result" >&5
+echo "$as_me: WARNING: linux/version.h: proceeding with the preprocessor's result" >&2;}
+ { echo "$as_me:$LINENO: WARNING: linux/version.h: in the future, the compiler will take precedence" >&5
+echo "$as_me: WARNING: linux/version.h: in the future, the compiler will take precedence" >&2;}
+ (
+ cat <<\_ASBOX
+## ------------------------------------------ ##
+## Report this to the AC_PACKAGE_NAME lists. ##
+## ------------------------------------------ ##
+_ASBOX
+ ) |
+ sed "s/^/$as_me: WARNING: /" >&2
+ ;;
+esac
+echo "$as_me:$LINENO: checking for linux/version.h" >&5
+echo $ECHO_N "checking for linux/version.h... $ECHO_C" >&6
+if test "${ac_cv_header_linux_version_h+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ ac_cv_header_linux_version_h=$ac_header_preproc
+fi
+echo "$as_me:$LINENO: result: $ac_cv_header_linux_version_h" >&5
+echo "${ECHO_T}$ac_cv_header_linux_version_h" >&6
+
+fi
+if test $ac_cv_header_linux_version_h = yes; then
+ msgformat=linux
+else
+ msgformat=xopen
+fi
+
+
+
+ sed -e '/^#/d' $srcdir/$msgformat-msg.sed > po2msg.sed
+ fi
+ sed -e '/^#.*[^\\]$/d' -e '/^#$/d' \
+ $srcdir/po2tbl.sed.in > po2tbl.sed
+ fi
+
+ if test "$PACKAGE" = "gettext"; then
+ GT_NO="#NO#"
+ GT_YES=
+ else
+ GT_NO=
+ GT_YES="#YES#"
+ fi
+
+
+
+ MKINSTALLDIRS="\$(srcdir)/../../mkinstalldirs"
+
+
+ l=
+
+
+ if test -d $srcdir/po; then
+ test -d po || mkdir po
+ if test "x$srcdir" != "x."; then
+ if test "x`echo $srcdir | sed 's@/.*@@'`" = "x"; then
+ posrcprefix="$srcdir/"
+ else
+ posrcprefix="../$srcdir/"
+ fi
+ else
+ posrcprefix="../"
+ fi
+ rm -f po/POTFILES
+ sed -e "/^#/d" -e "/^\$/d" -e "s,.*, $posrcprefix& \\\\," -e "\$s/\(.*\) \\\\/\1/" \
+ < $srcdir/po/POTFILES.in > po/POTFILES
+ fi
+
+
+# Check for common headers.
+# FIXME: Seems to me this can cause problems for i386-windows hosts.
+# At one point there were hardcoded AC_DEFINE's if ${host} = i386-*-windows*.
+
+
+
+
+
+for ac_header in stdlib.h string.h strings.h unistd.h time.h
+do
+as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
+else
+ # Is the header compilable?
+echo "$as_me:$LINENO: checking $ac_header usability" >&5
+echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+$ac_includes_default
+#include <$ac_header>
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_header_compiler=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_header_compiler=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
+echo "${ECHO_T}$ac_header_compiler" >&6
+
+# Is the header present?
+echo "$as_me:$LINENO: checking $ac_header presence" >&5
+echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <$ac_header>
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+ (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } >/dev/null; then
+ if test -s conftest.err; then
+ ac_cpp_err=$ac_c_preproc_warn_flag
+ ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+ else
+ ac_cpp_err=
+ fi
+else
+ ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+ ac_header_preproc=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ ac_header_preproc=no
+fi
+rm -f conftest.err conftest.$ac_ext
+echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
+echo "${ECHO_T}$ac_header_preproc" >&6
+
+# So? What about this header?
+case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
+ yes:no: )
+ { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
+echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
+echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
+ ac_header_preproc=yes
+ ;;
+ no:yes:* )
+ { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
+echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5
+echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
+echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5
+echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
+echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
+echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
+ (
+ cat <<\_ASBOX
+## ------------------------------------------ ##
+## Report this to the AC_PACKAGE_NAME lists. ##
+## ------------------------------------------ ##
+_ASBOX
+ ) |
+ sed "s/^/$as_me: WARNING: /" >&2
+ ;;
+esac
+echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ eval "$as_ac_Header=\$ac_header_preproc"
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
+
+fi
+if test `eval echo '${'$as_ac_Header'}'` = yes; then
+ cat >>confdefs.h <<_ACEOF
+#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+
+
+for ac_header in sys/time.h sys/resource.h
+do
+as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
+else
+ # Is the header compilable?
+echo "$as_me:$LINENO: checking $ac_header usability" >&5
+echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+$ac_includes_default
+#include <$ac_header>
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_header_compiler=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_header_compiler=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
+echo "${ECHO_T}$ac_header_compiler" >&6
+
+# Is the header present?
+echo "$as_me:$LINENO: checking $ac_header presence" >&5
+echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <$ac_header>
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+ (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } >/dev/null; then
+ if test -s conftest.err; then
+ ac_cpp_err=$ac_c_preproc_warn_flag
+ ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+ else
+ ac_cpp_err=
+ fi
+else
+ ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+ ac_header_preproc=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ ac_header_preproc=no
+fi
+rm -f conftest.err conftest.$ac_ext
+echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
+echo "${ECHO_T}$ac_header_preproc" >&6
+
+# So? What about this header?
+case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
+ yes:no: )
+ { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
+echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
+echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
+ ac_header_preproc=yes
+ ;;
+ no:yes:* )
+ { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
+echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5
+echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
+echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5
+echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
+echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
+echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
+ (
+ cat <<\_ASBOX
+## ------------------------------------------ ##
+## Report this to the AC_PACKAGE_NAME lists. ##
+## ------------------------------------------ ##
+_ASBOX
+ ) |
+ sed "s/^/$as_me: WARNING: /" >&2
+ ;;
+esac
+echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ eval "$as_ac_Header=\$ac_header_preproc"
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
+
+fi
+if test `eval echo '${'$as_ac_Header'}'` = yes; then
+ cat >>confdefs.h <<_ACEOF
+#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+
+
+for ac_header in fcntl.h fpu_control.h
+do
+as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
+else
+ # Is the header compilable?
+echo "$as_me:$LINENO: checking $ac_header usability" >&5
+echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+$ac_includes_default
+#include <$ac_header>
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_header_compiler=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_header_compiler=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
+echo "${ECHO_T}$ac_header_compiler" >&6
+
+# Is the header present?
+echo "$as_me:$LINENO: checking $ac_header presence" >&5
+echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <$ac_header>
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+ (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } >/dev/null; then
+ if test -s conftest.err; then
+ ac_cpp_err=$ac_c_preproc_warn_flag
+ ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+ else
+ ac_cpp_err=
+ fi
+else
+ ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+ ac_header_preproc=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ ac_header_preproc=no
+fi
+rm -f conftest.err conftest.$ac_ext
+echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
+echo "${ECHO_T}$ac_header_preproc" >&6
+
+# So? What about this header?
+case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
+ yes:no: )
+ { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
+echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
+echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
+ ac_header_preproc=yes
+ ;;
+ no:yes:* )
+ { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
+echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5
+echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
+echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5
+echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
+echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
+echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
+ (
+ cat <<\_ASBOX
+## ------------------------------------------ ##
+## Report this to the AC_PACKAGE_NAME lists. ##
+## ------------------------------------------ ##
+_ASBOX
+ ) |
+ sed "s/^/$as_me: WARNING: /" >&2
+ ;;
+esac
+echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ eval "$as_ac_Header=\$ac_header_preproc"
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
+
+fi
+if test `eval echo '${'$as_ac_Header'}'` = yes; then
+ cat >>confdefs.h <<_ACEOF
+#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+
+
+
+for ac_header in dlfcn.h errno.h sys/stat.h
+do
+as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh`
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
+else
+ # Is the header compilable?
+echo "$as_me:$LINENO: checking $ac_header usability" >&5
+echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+$ac_includes_default
+#include <$ac_header>
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_header_compiler=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_header_compiler=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+echo "$as_me:$LINENO: result: $ac_header_compiler" >&5
+echo "${ECHO_T}$ac_header_compiler" >&6
+
+# Is the header present?
+echo "$as_me:$LINENO: checking $ac_header presence" >&5
+echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <$ac_header>
+_ACEOF
+if { (eval echo "$as_me:$LINENO: \"$ac_cpp conftest.$ac_ext\"") >&5
+ (eval $ac_cpp conftest.$ac_ext) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } >/dev/null; then
+ if test -s conftest.err; then
+ ac_cpp_err=$ac_c_preproc_warn_flag
+ ac_cpp_err=$ac_cpp_err$ac_c_werror_flag
+ else
+ ac_cpp_err=
+ fi
+else
+ ac_cpp_err=yes
+fi
+if test -z "$ac_cpp_err"; then
+ ac_header_preproc=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ ac_header_preproc=no
+fi
+rm -f conftest.err conftest.$ac_ext
+echo "$as_me:$LINENO: result: $ac_header_preproc" >&5
+echo "${ECHO_T}$ac_header_preproc" >&6
+
+# So? What about this header?
+case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in
+ yes:no: )
+ { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5
+echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5
+echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;}
+ ac_header_preproc=yes
+ ;;
+ no:yes:* )
+ { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5
+echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5
+echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5
+echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5
+echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5
+echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;}
+ { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5
+echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;}
+ (
+ cat <<\_ASBOX
+## ------------------------------------------ ##
+## Report this to the AC_PACKAGE_NAME lists. ##
+## ------------------------------------------ ##
+_ASBOX
+ ) |
+ sed "s/^/$as_me: WARNING: /" >&2
+ ;;
+esac
+echo "$as_me:$LINENO: checking for $ac_header" >&5
+echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6
+if eval "test \"\${$as_ac_Header+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ eval "$as_ac_Header=\$ac_header_preproc"
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_Header'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_Header'}'`" >&6
+
+fi
+if test `eval echo '${'$as_ac_Header'}'` = yes; then
+ cat >>confdefs.h <<_ACEOF
+#define `echo "HAVE_$ac_header" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+
+done
+
+
+
+
+
+for ac_func in getrusage time sigaction __setfpucw
+do
+as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh`
+echo "$as_me:$LINENO: checking for $ac_func" >&5
+echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6
+if eval "test \"\${$as_ac_var+set}\" = set"; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+/* Define $ac_func to an innocuous variant, in case <limits.h> declares $ac_func.
+ For example, HP-UX 11i <limits.h> declares gettimeofday. */
+#define $ac_func innocuous_$ac_func
+
+/* System header to define __stub macros and hopefully few prototypes,
+ which can conflict with char $ac_func (); below.
+ Prefer <limits.h> to <assert.h> if __STDC__ is defined, since
+ <limits.h> exists even on freestanding compilers. */
+
+#ifdef __STDC__
+# include <limits.h>
+#else
+# include <assert.h>
+#endif
+
+#undef $ac_func
+
+/* Override any gcc2 internal prototype to avoid an error. */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char $ac_func ();
+/* The GNU C library defines this for functions which it implements
+ to always fail with ENOSYS. Some functions are actually named
+ something starting with __ and the normal name is an alias. */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+char (*f) () = $ac_func;
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+int
+main ()
+{
+return f != $ac_func;
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest$ac_exeext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ eval "$as_ac_var=yes"
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+eval "$as_ac_var=no"
+fi
+rm -f conftest.err conftest.$ac_objext \
+ conftest$ac_exeext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: `eval echo '${'$as_ac_var'}'`" >&5
+echo "${ECHO_T}`eval echo '${'$as_ac_var'}'`" >&6
+if test `eval echo '${'$as_ac_var'}'` = yes; then
+ cat >>confdefs.h <<_ACEOF
+#define `echo "HAVE_$ac_func" | $as_tr_cpp` 1
+_ACEOF
+
+fi
+done
+
+
+# Check for socket libraries
+
+echo "$as_me:$LINENO: checking for bind in -lsocket" >&5
+echo $ECHO_N "checking for bind in -lsocket... $ECHO_C" >&6
+if test "${ac_cv_lib_socket_bind+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ ac_check_lib_save_LIBS=$LIBS
+LIBS="-lsocket $LIBS"
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+
+/* Override any gcc2 internal prototype to avoid an error. */
+#ifdef __cplusplus
+extern "C"
+#endif
+/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char bind ();
+int
+main ()
+{
+bind ();
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest$ac_exeext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_lib_socket_bind=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_lib_socket_bind=no
+fi
+rm -f conftest.err conftest.$ac_objext \
+ conftest$ac_exeext conftest.$ac_ext
+LIBS=$ac_check_lib_save_LIBS
+fi
+echo "$as_me:$LINENO: result: $ac_cv_lib_socket_bind" >&5
+echo "${ECHO_T}$ac_cv_lib_socket_bind" >&6
+if test $ac_cv_lib_socket_bind = yes; then
+ cat >>confdefs.h <<_ACEOF
+#define HAVE_LIBSOCKET 1
+_ACEOF
+
+ LIBS="-lsocket $LIBS"
+
+fi
+
+
+echo "$as_me:$LINENO: checking for gethostbyname in -lnsl" >&5
+echo $ECHO_N "checking for gethostbyname in -lnsl... $ECHO_C" >&6
+if test "${ac_cv_lib_nsl_gethostbyname+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ ac_check_lib_save_LIBS=$LIBS
+LIBS="-lnsl $LIBS"
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+
+/* Override any gcc2 internal prototype to avoid an error. */
+#ifdef __cplusplus
+extern "C"
+#endif
+/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char gethostbyname ();
+int
+main ()
+{
+gethostbyname ();
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest$ac_exeext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_lib_nsl_gethostbyname=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_lib_nsl_gethostbyname=no
+fi
+rm -f conftest.err conftest.$ac_objext \
+ conftest$ac_exeext conftest.$ac_ext
+LIBS=$ac_check_lib_save_LIBS
+fi
+echo "$as_me:$LINENO: result: $ac_cv_lib_nsl_gethostbyname" >&5
+echo "${ECHO_T}$ac_cv_lib_nsl_gethostbyname" >&6
+if test $ac_cv_lib_nsl_gethostbyname = yes; then
+ cat >>confdefs.h <<_ACEOF
+#define HAVE_LIBNSL 1
+_ACEOF
+
+ LIBS="-lnsl $LIBS"
+
+fi
+
+
+. ${srcdir}/../../bfd/configure.host
+
+
+
+USE_MAINTAINER_MODE=no
+# Check whether --enable-maintainer-mode or --disable-maintainer-mode was given.
+if test "${enable_maintainer_mode+set}" = set; then
+ enableval="$enable_maintainer_mode"
+ case "${enableval}" in
+ yes) MAINT="" USE_MAINTAINER_MODE=yes ;;
+ no) MAINT="#" ;;
+ *) { { echo "$as_me:$LINENO: error: \"--enable-maintainer-mode does not take a value\"" >&5
+echo "$as_me: error: \"--enable-maintainer-mode does not take a value\"" >&2;}
+ { (exit 1); exit 1; }; }; MAINT="#" ;;
+esac
+if test x"$silent" != x"yes" && test x"$MAINT" = x""; then
+ echo "Setting maintainer mode" 6>&1
+fi
+else
+ MAINT="#"
+fi;
+
+
+# Check whether --enable-sim-bswap or --disable-sim-bswap was given.
+if test "${enable_sim_bswap+set}" = set; then
+ enableval="$enable_sim_bswap"
+ case "${enableval}" in
+ yes) sim_bswap="-DWITH_BSWAP=1 -DUSE_BSWAP=1";;
+ no) sim_bswap="-DWITH_BSWAP=0";;
+ *) { { echo "$as_me:$LINENO: error: \"--enable-sim-bswap does not take a value\"" >&5
+echo "$as_me: error: \"--enable-sim-bswap does not take a value\"" >&2;}
+ { (exit 1); exit 1; }; }; sim_bswap="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_bswap" != x""; then
+ echo "Setting bswap flags = $sim_bswap" 6>&1
+fi
+else
+ sim_bswap=""
+fi;
+
+
+# Check whether --enable-sim-cflags or --disable-sim-cflags was given.
+if test "${enable_sim_cflags+set}" = set; then
+ enableval="$enable_sim_cflags"
+ case "${enableval}" in
+ yes) sim_cflags="-O2 -fomit-frame-pointer";;
+ trace) { { echo "$as_me:$LINENO: error: \"Please use --enable-sim-debug instead.\"" >&5
+echo "$as_me: error: \"Please use --enable-sim-debug instead.\"" >&2;}
+ { (exit 1); exit 1; }; }; sim_cflags="";;
+ no) sim_cflags="";;
+ *) sim_cflags=`echo "${enableval}" | sed -e "s/,/ /g"`;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_cflags" != x""; then
+ echo "Setting sim cflags = $sim_cflags" 6>&1
+fi
+else
+ sim_cflags=""
+fi;
+
+
+# Check whether --enable-sim-debug or --disable-sim-debug was given.
+if test "${enable_sim_debug+set}" = set; then
+ enableval="$enable_sim_debug"
+ case "${enableval}" in
+ yes) sim_debug="-DDEBUG=7 -DWITH_DEBUG=7";;
+ no) sim_debug="-DDEBUG=0 -DWITH_DEBUG=0";;
+ *) sim_debug="-DDEBUG='(${enableval})' -DWITH_DEBUG='(${enableval})'";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_debug" != x""; then
+ echo "Setting sim debug = $sim_debug" 6>&1
+fi
+else
+ sim_debug=""
+fi;
+
+
+# Check whether --enable-sim-stdio or --disable-sim-stdio was given.
+if test "${enable_sim_stdio+set}" = set; then
+ enableval="$enable_sim_stdio"
+ case "${enableval}" in
+ yes) sim_stdio="-DWITH_STDIO=DO_USE_STDIO";;
+ no) sim_stdio="-DWITH_STDIO=DONT_USE_STDIO";;
+ *) { { echo "$as_me:$LINENO: error: \"Unknown value $enableval passed to --enable-sim-stdio\"" >&5
+echo "$as_me: error: \"Unknown value $enableval passed to --enable-sim-stdio\"" >&2;}
+ { (exit 1); exit 1; }; }; sim_stdio="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_stdio" != x""; then
+ echo "Setting stdio flags = $sim_stdio" 6>&1
+fi
+else
+ sim_stdio=""
+fi;
+
+
+# Check whether --enable-sim-trace or --disable-sim-trace was given.
+if test "${enable_sim_trace+set}" = set; then
+ enableval="$enable_sim_trace"
+ case "${enableval}" in
+ yes) sim_trace="-DTRACE=1 -DWITH_TRACE=-1";;
+ no) sim_trace="-DTRACE=0 -DWITH_TRACE=0";;
+ [-0-9]*)
+ sim_trace="-DTRACE='(${enableval})' -DWITH_TRACE='(${enableval})'";;
+ [a-z]*)
+ sim_trace=""
+ for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
+ if test x"$sim_trace" = x; then
+ sim_trace="-DWITH_TRACE='(TRACE_$x"
+ else
+ sim_trace="${sim_trace}|TRACE_$x"
+ fi
+ done
+ sim_trace="$sim_trace)'" ;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_trace" != x""; then
+ echo "Setting sim trace = $sim_trace" 6>&1
+fi
+else
+ sim_trace=""
+fi;
+
+
+# Check whether --enable-sim-profile or --disable-sim-profile was given.
+if test "${enable_sim_profile+set}" = set; then
+ enableval="$enable_sim_profile"
+ case "${enableval}" in
+ yes) sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1";;
+ no) sim_profile="-DPROFILE=0 -DWITH_PROFILE=0";;
+ [-0-9]*)
+ sim_profile="-DPROFILE='(${enableval})' -DWITH_PROFILE='(${enableval})'";;
+ [a-z]*)
+ sim_profile=""
+ for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
+ if test x"$sim_profile" = x; then
+ sim_profile="-DWITH_PROFILE='(PROFILE_$x"
+ else
+ sim_profile="${sim_profile}|PROFILE_$x"
+ fi
+ done
+ sim_profile="$sim_profile)'" ;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_profile" != x""; then
+ echo "Setting sim profile = $sim_profile" 6>&1
+fi
+else
+ sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1"
+fi;
+
+
+echo "$as_me:$LINENO: checking return type of signal handlers" >&5
+echo $ECHO_N "checking return type of signal handlers... $ECHO_C" >&6
+if test "${ac_cv_type_signal+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <sys/types.h>
+#include <signal.h>
+#ifdef signal
+# undef signal
+#endif
+#ifdef __cplusplus
+extern "C" void (*signal (int, void (*)(int)))(int);
+#else
+void (*signal ()) ();
+#endif
+
+int
+main ()
+{
+int i;
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_type_signal=void
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_type_signal=int
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: $ac_cv_type_signal" >&5
+echo "${ECHO_T}$ac_cv_type_signal" >&6
+
+cat >>confdefs.h <<_ACEOF
+#define RETSIGTYPE $ac_cv_type_signal
+_ACEOF
+
+
+
+
+
+sim_link_files=
+sim_link_links=
+
+sim_link_links=tconfig.h
+if test -f ${srcdir}/tconfig.in
+then
+ sim_link_files=tconfig.in
+else
+ sim_link_files=../common/tconfig.in
+fi
+
+# targ-vals.def points to the libc macro description file.
+case "${target}" in
+*-*-*) TARG_VALS_DEF=../common/nltvals.def ;;
+esac
+sim_link_files="${sim_link_files} ${TARG_VALS_DEF}"
+sim_link_links="${sim_link_links} targ-vals.def"
+
+
+wire_alignment="NONSTRICT_ALIGNMENT"
+default_alignment=""
+
+# Check whether --enable-sim-alignment or --disable-sim-alignment was given.
+if test "${enable_sim_alignment+set}" = set; then
+ enableval="$enable_sim_alignment"
+ case "${enableval}" in
+ strict | STRICT) sim_alignment="-DWITH_ALIGNMENT=STRICT_ALIGNMENT";;
+ nonstrict | NONSTRICT) sim_alignment="-DWITH_ALIGNMENT=NONSTRICT_ALIGNMENT";;
+ forced | FORCED) sim_alignment="-DWITH_ALIGNMENT=FORCED_ALIGNMENT";;
+ yes) if test x"$wire_alignment" != x; then
+ sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}"
+ else
+ if test x"$default_alignment" != x; then
+ sim_alignment="-DWITH_ALIGNMENT=${default_alignment}"
+ else
+ echo "No hard-wired alignment for target $target" 1>&6
+ sim_alignment="-DWITH_ALIGNMENT=0"
+ fi
+ fi;;
+ no) if test x"$default_alignment" != x; then
+ sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}"
+ else
+ if test x"$wire_alignment" != x; then
+ sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${wire_alignment}"
+ else
+ echo "No default alignment for target $target" 1>&6
+ sim_alignment="-DWITH_DEFAULT_ALIGNMENT=0"
+ fi
+ fi;;
+ *) { { echo "$as_me:$LINENO: error: \"Unknown value $enableval passed to --enable-sim-alignment\"" >&5
+echo "$as_me: error: \"Unknown value $enableval passed to --enable-sim-alignment\"" >&2;}
+ { (exit 1); exit 1; }; }; sim_alignment="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_alignment" != x""; then
+ echo "Setting alignment flags = $sim_alignment" 6>&1
+fi
+else
+ if test x"$default_alignment" != x; then
+ sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}"
+else
+ if test x"$wire_alignment" != x; then
+ sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}"
+ else
+ sim_alignment=
+ fi
+fi
+fi;
+
+# Check whether --enable-sim-hostendian or --disable-sim-hostendian was given.
+if test "${enable_sim_hostendian+set}" = set; then
+ enableval="$enable_sim_hostendian"
+ case "${enableval}" in
+ no) sim_hostendian="-DWITH_HOST_BYTE_ORDER=0";;
+ b*|B*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN";;
+ l*|L*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN";;
+ *) { { echo "$as_me:$LINENO: error: \"Unknown value $enableval for --enable-sim-hostendian\"" >&5
+echo "$as_me: error: \"Unknown value $enableval for --enable-sim-hostendian\"" >&2;}
+ { (exit 1); exit 1; }; }; sim_hostendian="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_hostendian" != x""; then
+ echo "Setting hostendian flags = $sim_hostendian" 6>&1
+fi
+else
+
+if test "x$cross_compiling" = "xno"; then
+ echo "$as_me:$LINENO: checking whether byte ordering is bigendian" >&5
+echo $ECHO_N "checking whether byte ordering is bigendian... $ECHO_C" >&6
+if test "${ac_cv_c_bigendian+set}" = set; then
+ echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+ # See if sys/param.h defines the BYTE_ORDER macro.
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <sys/types.h>
+#include <sys/param.h>
+
+int
+main ()
+{
+#if !BYTE_ORDER || !BIG_ENDIAN || !LITTLE_ENDIAN
+ bogus endian macros
+#endif
+
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ # It does; now see whether it defined to BIG_ENDIAN or not.
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+#include <sys/types.h>
+#include <sys/param.h>
+
+int
+main ()
+{
+#if BYTE_ORDER != BIG_ENDIAN
+ not big endian
+#endif
+
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_c_bigendian=yes
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_c_bigendian=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+# It does not; compile a test program.
+if test "$cross_compiling" = yes; then
+ # try to guess the endianness by grepping values into an object file
+ ac_cv_c_bigendian=unknown
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+short ascii_mm[] = { 0x4249, 0x4765, 0x6E44, 0x6961, 0x6E53, 0x7953, 0 };
+short ascii_ii[] = { 0x694C, 0x5454, 0x656C, 0x6E45, 0x6944, 0x6E61, 0 };
+void _ascii () { char *s = (char *) ascii_mm; s = (char *) ascii_ii; }
+short ebcdic_ii[] = { 0x89D3, 0xE3E3, 0x8593, 0x95C5, 0x89C4, 0x9581, 0 };
+short ebcdic_mm[] = { 0xC2C9, 0xC785, 0x95C4, 0x8981, 0x95E2, 0xA8E2, 0 };
+void _ebcdic () { char *s = (char *) ebcdic_mm; s = (char *) ebcdic_ii; }
+int
+main ()
+{
+ _ascii (); _ebcdic ();
+ ;
+ return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+ (eval $ac_compile) 2>conftest.er1
+ ac_status=$?
+ grep -v '^ *+' conftest.er1 >conftest.err
+ rm -f conftest.er1
+ cat conftest.err >&5
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } &&
+ { ac_try='test -z "$ac_c_werror_flag"
+ || test ! -s conftest.err'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; } &&
+ { ac_try='test -s conftest.$ac_objext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ if grep BIGenDianSyS conftest.$ac_objext >/dev/null ; then
+ ac_cv_c_bigendian=yes
+fi
+if grep LiTTleEnDian conftest.$ac_objext >/dev/null ; then
+ if test "$ac_cv_c_bigendian" = unknown; then
+ ac_cv_c_bigendian=no
+ else
+ # finding both strings is unlikely to happen, but who knows?
+ ac_cv_c_bigendian=unknown
+ fi
+fi
+else
+ echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+else
+ cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h. */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h. */
+int
+main ()
+{
+ /* Are we little or big endian? From Harbison&Steele. */
+ union
+ {
+ long l;
+ char c[sizeof (long)];
+ } u;
+ u.l = 1;
+ exit (u.c[sizeof (long) - 1] == 1);
+}
+_ACEOF
+rm -f conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+ (eval $ac_link) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); } && { ac_try='./conftest$ac_exeext'
+ { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ echo "$as_me:$LINENO: \$? = $ac_status" >&5
+ (exit $ac_status); }; }; then
+ ac_cv_c_bigendian=no
+else
+ echo "$as_me: program exited with status $ac_status" >&5
+echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+( exit $ac_status )
+ac_cv_c_bigendian=yes
+fi
+rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext
+fi
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: $ac_cv_c_bigendian" >&5
+echo "${ECHO_T}$ac_cv_c_bigendian" >&6
+case $ac_cv_c_bigendian in
+ yes)
+
+cat >>confdefs.h <<\_ACEOF
+#define WORDS_BIGENDIAN 1
+_ACEOF
+ ;;
+ no)
+ ;;
+ *)
+ { { echo "$as_me:$LINENO: error: unknown endianness
+presetting ac_cv_c_bigendian=no (or yes) will help" >&5
+echo "$as_me: error: unknown endianness
+presetting ac_cv_c_bigendian=no (or yes) will help" >&2;}
+ { (exit 1); exit 1; }; } ;;
+esac
+
+ if test $ac_cv_c_bigendian = yes; then
+ sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN"
+ else
+ sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN"
+ fi
+else
+ sim_hostendian="-DWITH_HOST_BYTE_ORDER=0"
+fi
+fi;
+
+default_sim_scache="16384"
+# Check whether --enable-sim-scache or --disable-sim-scache was given.
+if test "${enable_sim_scache+set}" = set; then
+ enableval="$enable_sim_scache"
+ case "${enableval}" in
+ yes) sim_scache="-DWITH_SCACHE=${default_sim_scache}";;
+ no) sim_scache="-DWITH_SCACHE=0" ;;
+ [0-9]*) sim_scache="-DWITH_SCACHE=${enableval}";;
+ *) { { echo "$as_me:$LINENO: error: \"Bad value $enableval passed to --enable-sim-scache\"" >&5
+echo "$as_me: error: \"Bad value $enableval passed to --enable-sim-scache\"" >&2;}
+ { (exit 1); exit 1; }; };
+ sim_scache="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_scache" != x""; then
+ echo "Setting scache size = $sim_scache" 6>&1
+fi
+else
+ sim_scache="-DWITH_SCACHE=${default_sim_scache}"
+fi;
+
+
+# The default model shouldn't matter as long as there's a BFD.
+
+default_sim_default_model="crisv32"
+# Check whether --enable-sim-default-model or --disable-sim-default-model was given.
+if test "${enable_sim_default_model+set}" = set; then
+ enableval="$enable_sim_default_model"
+ case "${enableval}" in
+ yes|no) { { echo "$as_me:$LINENO: error: \"Missing argument to --enable-sim-default-model\"" >&5
+echo "$as_me: error: \"Missing argument to --enable-sim-default-model\"" >&2;}
+ { (exit 1); exit 1; }; };;
+ *) sim_default_model="-DWITH_DEFAULT_MODEL='\"${enableval}\"'";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_default_model" != x""; then
+ echo "Setting default model = $sim_default_model" 6>&1
+fi
+else
+ sim_default_model="-DWITH_DEFAULT_MODEL='\"${default_sim_default_model}\"'"
+fi;
+
+
+# Check whether --enable-sim-environment or --disable-sim-environment was given.
+if test "${enable_sim_environment+set}" = set; then
+ enableval="$enable_sim_environment"
+ case "${enableval}" in
+ all | ALL) sim_environment="-DWITH_ENVIRONMENT=ALL_ENVIRONMENT";;
+ user | USER) sim_environment="-DWITH_ENVIRONMENT=USER_ENVIRONMENT";;
+ virtual | VIRTUAL) sim_environment="-DWITH_ENVIRONMENT=VIRTUAL_ENVIRONMENT";;
+ operating | OPERATING) sim_environment="-DWITH_ENVIRONMENT=OPERATING_ENVIRONMENT";;
+ *) { { echo "$as_me:$LINENO: error: \"Unknown value $enableval passed to --enable-sim-environment\"" >&5
+echo "$as_me: error: \"Unknown value $enableval passed to --enable-sim-environment\"" >&2;}
+ { (exit 1); exit 1; }; };
+ sim_environment="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_environment" != x""; then
+ echo "Setting sim environment = $sim_environment" 6>&1
+fi
+else
+ sim_environment="-DWITH_ENVIRONMENT=ALL_ENVIRONMENT"
+fi;
+
+default_sim_inline=""
+# Check whether --enable-sim-inline or --disable-sim-inline was given.
+if test "${enable_sim_inline+set}" = set; then
+ enableval="$enable_sim_inline"
+ sim_inline=""
+case "$enableval" in
+ no) sim_inline="-DDEFAULT_INLINE=0";;
+ 0) sim_inline="-DDEFAULT_INLINE=0";;
+ yes | 2) sim_inline="-DDEFAULT_INLINE=ALL_C_INLINE";;
+ 1) sim_inline="-DDEFAULT_INLINE=INLINE_LOCALS";;
+ *) for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
+ new_flag=""
+ case "$x" in
+ *_INLINE=*) new_flag="-D$x";;
+ *=*) new_flag=`echo "$x" | sed -e "s/=/_INLINE=/" -e "s/^/-D/"`;;
+ *_INLINE) new_flag="-D$x=ALL_C_INLINE";;
+ *) new_flag="-D$x""_INLINE=ALL_C_INLINE";;
+ esac
+ if test x"$sim_inline" = x""; then
+ sim_inline="$new_flag"
+ else
+ sim_inline="$sim_inline $new_flag"
+ fi
+ done;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_inline" != x""; then
+ echo "Setting inline flags = $sim_inline" 6>&1
+fi
+else
+
+if test "x$cross_compiling" = "xno"; then
+ if test x"$GCC" != "x" -a x"${default_sim_inline}" != "x" ; then
+ sim_inline="${default_sim_inline}"
+ if test x"$silent" != x"yes"; then
+ echo "Setting inline flags = $sim_inline" 6>&1
+ fi
+ else
+ sim_inline=""
+ fi
+else
+ sim_inline="-DDEFAULT_INLINE=0"
+fi
+fi;
+
+cgen_maint=no
+cgen=guile
+cgendir='$(srcdir)/../../cgen'
+# Check whether --enable-cgen-maint or --disable-cgen-maint was given.
+if test "${enable_cgen_maint+set}" = set; then
+ enableval="$enable_cgen_maint"
+ case "${enableval}" in
+ yes) cgen_maint=yes ;;
+ no) cgen_maint=no ;;
+ *)
+ # argument is cgen install directory (not implemented yet).
+ # Having a `share' directory might be more appropriate for the .scm,
+ # .cpu, etc. files.
+ cgendir=${cgen_maint}/lib/cgen
+ cgen=guile
+ ;;
+esac
+fi; if test x${cgen_maint} != xno ; then
+ CGEN_MAINT=''
+else
+ CGEN_MAINT='#'
+fi
+
+
+
+
+
+
+ac_sources="$sim_link_files"
+ac_dests="$sim_link_links"
+while test -n "$ac_sources"; do
+ set $ac_dests; ac_dest=$1; shift; ac_dests=$*
+ set $ac_sources; ac_source=$1; shift; ac_sources=$*
+ ac_config_links_1="$ac_config_links_1 $ac_dest:$ac_source"
+done
+ ac_config_links="$ac_config_links $ac_config_links_1"
+
+cgen_breaks=""
+if grep CGEN_MAINT $srcdir/Makefile.in >/dev/null; then
+cgen_breaks="break cgen_rtx_error";
+fi
+
+ ac_config_files="$ac_config_files Makefile.sim:Makefile.in"
+
+ ac_config_files="$ac_config_files Make-common.sim:../common/Make-common.in"
+
+ ac_config_files="$ac_config_files .gdbinit:../common/gdbinit.in"
+
+ ac_config_commands="$ac_config_commands Makefile"
+
+ ac_config_commands="$ac_config_commands stamp-h"
+
+cat >confcache <<\_ACEOF
+# This file is a shell script that caches the results of configure
+# tests run on this system so they can be shared between configure
+# scripts and configure runs, see configure's option --config-cache.
+# It is not useful on other systems. If it contains results you don't
+# want to keep, you may remove or edit it.
+#
+# config.status only pays attention to the cache file if you give it
+# the --recheck option to rerun configure.
+#
+# `ac_cv_env_foo' variables (set or unset) will be overridden when
+# loading this file, other *unset* `ac_cv_foo' will be assigned the
+# following values.
+
+_ACEOF
+
+# The following way of writing the cache mishandles newlines in values,
+# but we know of no workaround that is simple, portable, and efficient.
+# So, don't put newlines in cache variables' values.
+# Ultrix sh set writes to stderr and can't be redirected directly,
+# and sets the high bit in the cache file unless we assign to the vars.
+{
+ (set) 2>&1 |
+ case `(ac_space=' '; set | grep ac_space) 2>&1` in
+ *ac_space=\ *)
+ # `set' does not quote correctly, so add quotes (double-quote
+ # substitution turns \\\\ into \\, and sed turns \\ into \).
+ sed -n \
+ "s/'/'\\\\''/g;
+ s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p"
+ ;;
+ *)
+ # `set' quotes correctly as required by POSIX, so do not add quotes.
+ sed -n \
+ "s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1=\\2/p"
+ ;;
+ esac;
+} |
+ sed '
+ t clear
+ : clear
+ s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/
+ t end
+ /^ac_cv_env/!s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/
+ : end' >>confcache
+if diff $cache_file confcache >/dev/null 2>&1; then :; else
+ if test -w $cache_file; then
+ test "x$cache_file" != "x/dev/null" && echo "updating cache $cache_file"
+ cat confcache >$cache_file
+ else
+ echo "not updating unwritable cache $cache_file"
+ fi
+fi
+rm -f confcache
+
+test "x$prefix" = xNONE && prefix=$ac_default_prefix
+# Let make expand exec_prefix.
+test "x$exec_prefix" = xNONE && exec_prefix='${prefix}'
+
+# VPATH may cause trouble with some makes, so we remove $(srcdir),
+# ${srcdir} and @srcdir@ from VPATH if srcdir is ".", strip leading and
+# trailing colons and then remove the whole line if VPATH becomes empty
+# (actually we leave an empty line to preserve line numbers).
+if test "x$srcdir" = x.; then
+ ac_vpsub='/^[ ]*VPATH[ ]*=/{
+s/:*\$(srcdir):*/:/;
+s/:*\${srcdir}:*/:/;
+s/:*@srcdir@:*/:/;
+s/^\([^=]*=[ ]*\):*/\1/;
+s/:*$//;
+s/^[^=]*=[ ]*$//;
+}'
+fi
+
+DEFS=-DHAVE_CONFIG_H
+
+ac_libobjs=
+ac_ltlibobjs=
+for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue
+ # 1. Remove the extension, and $U if already installed.
+ ac_i=`echo "$ac_i" |
+ sed 's/\$U\././;s/\.o$//;s/\.obj$//'`
+ # 2. Add them.
+ ac_libobjs="$ac_libobjs $ac_i\$U.$ac_objext"
+ ac_ltlibobjs="$ac_ltlibobjs $ac_i"'$U.lo'
+done
+LIBOBJS=$ac_libobjs
+
+LTLIBOBJS=$ac_ltlibobjs
+
+
+
+: ${CONFIG_STATUS=./config.status}
+ac_clean_files_save=$ac_clean_files
+ac_clean_files="$ac_clean_files $CONFIG_STATUS"
+{ echo "$as_me:$LINENO: creating $CONFIG_STATUS" >&5
+echo "$as_me: creating $CONFIG_STATUS" >&6;}
+cat >$CONFIG_STATUS <<_ACEOF
+#! $SHELL
+# Generated by $as_me.
+# Run this file to recreate the current configuration.
+# Compiler output produced by configure, useful for debugging
+# configure, is in config.log if it exists.
+
+debug=false
+ac_cs_recheck=false
+ac_cs_silent=false
+SHELL=\${CONFIG_SHELL-$SHELL}
+_ACEOF
+
+cat >>$CONFIG_STATUS <<\_ACEOF
+## --------------------- ##
+## M4sh Initialization. ##
+## --------------------- ##
+
+# Be Bourne compatible
+if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then
+ emulate sh
+ NULLCMD=:
+ # Zsh 3.x and 4.x performs word splitting on ${1+"$@"}, which
+ # is contrary to our usage. Disable this feature.
+ alias -g '${1+"$@"}'='"$@"'
+elif test -n "${BASH_VERSION+set}" && (set -o posix) >/dev/null 2>&1; then
+ set -o posix
+fi
+DUALCASE=1; export DUALCASE # for MKS sh
+
+# Support unset when possible.
+if ( (MAIL=60; unset MAIL) || exit) >/dev/null 2>&1; then
+ as_unset=unset
+else
+ as_unset=false
+fi
+
+
+# Work around bugs in pre-3.0 UWIN ksh.
+$as_unset ENV MAIL MAILPATH
+PS1='$ '
+PS2='> '
+PS4='+ '
+
+# NLS nuisances.
+for as_var in \
+ LANG LANGUAGE LC_ADDRESS LC_ALL LC_COLLATE LC_CTYPE LC_IDENTIFICATION \
+ LC_MEASUREMENT LC_MESSAGES LC_MONETARY LC_NAME LC_NUMERIC LC_PAPER \
+ LC_TELEPHONE LC_TIME
+do
+ if (set +x; test -z "`(eval $as_var=C; export $as_var) 2>&1`"); then
+ eval $as_var=C; export $as_var
+ else
+ $as_unset $as_var
+ fi
+done
+
+# Required to use basename.
+if expr a : '\(a\)' >/dev/null 2>&1; then
+ as_expr=expr
+else
+ as_expr=false
+fi
+
+if (basename /) >/dev/null 2>&1 && test "X`basename / 2>&1`" = "X/"; then
+ as_basename=basename
+else
+ as_basename=false
+fi
+
+
+# Name of the executable.
+as_me=`$as_basename "$0" ||
+$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \
+ X"$0" : 'X\(//\)$' \| \
+ X"$0" : 'X\(/\)$' \| \
+ . : '\(.\)' 2>/dev/null ||
+echo X/"$0" |
+ sed '/^.*\/\([^/][^/]*\)\/*$/{ s//\1/; q; }
+ /^X\/\(\/\/\)$/{ s//\1/; q; }
+ /^X\/\(\/\).*/{ s//\1/; q; }
+ s/.*/./; q'`
+
+
+# PATH needs CR, and LINENO needs CR and PATH.
+# Avoid depending upon Character Ranges.
+as_cr_letters='abcdefghijklmnopqrstuvwxyz'
+as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
+as_cr_Letters=$as_cr_letters$as_cr_LETTERS
+as_cr_digits='0123456789'
+as_cr_alnum=$as_cr_Letters$as_cr_digits
+
+# The user is always right.
+if test "${PATH_SEPARATOR+set}" != set; then
+ echo "#! /bin/sh" >conf$$.sh
+ echo "exit 0" >>conf$$.sh
+ chmod +x conf$$.sh
+ if (PATH="/nonexistent;."; conf$$.sh) >/dev/null 2>&1; then
+ PATH_SEPARATOR=';'
+ else
+ PATH_SEPARATOR=:
+ fi
+ rm -f conf$$.sh
+fi
+
+
+ as_lineno_1=$LINENO
+ as_lineno_2=$LINENO
+ as_lineno_3=`(expr $as_lineno_1 + 1) 2>/dev/null`
+ test "x$as_lineno_1" != "x$as_lineno_2" &&
+ test "x$as_lineno_3" = "x$as_lineno_2" || {
+ # Find who we are. Look in the path if we contain no path at all
+ # relative or not.
+ case $0 in
+ *[\\/]* ) as_myself=$0 ;;
+ *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in $PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break
+done
+
+ ;;
+ esac
+ # We did not find ourselves, most probably we were run as `sh COMMAND'
+ # in which case we are not to be found in the path.
+ if test "x$as_myself" = x; then
+ as_myself=$0
+ fi
+ if test ! -f "$as_myself"; then
+ { { echo "$as_me:$LINENO: error: cannot find myself; rerun with an absolute path" >&5
+echo "$as_me: error: cannot find myself; rerun with an absolute path" >&2;}
+ { (exit 1); exit 1; }; }
+ fi
+ case $CONFIG_SHELL in
+ '')
+ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR
+for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH
+do
+ IFS=$as_save_IFS
+ test -z "$as_dir" && as_dir=.
+ for as_base in sh bash ksh sh5; do
+ case $as_dir in
+ /*)
+ if ("$as_dir/$as_base" -c '
+ as_lineno_1=$LINENO
+ as_lineno_2=$LINENO
+ as_lineno_3=`(expr $as_lineno_1 + 1) 2>/dev/null`
+ test "x$as_lineno_1" != "x$as_lineno_2" &&
+ test "x$as_lineno_3" = "x$as_lineno_2" ') 2>/dev/null; then
+ $as_unset BASH_ENV || test "${BASH_ENV+set}" != set || { BASH_ENV=; export BASH_ENV; }
+ $as_unset ENV || test "${ENV+set}" != set || { ENV=; export ENV; }
+ CONFIG_SHELL=$as_dir/$as_base
+ export CONFIG_SHELL
+ exec "$CONFIG_SHELL" "$0" ${1+"$@"}
+ fi;;
+ esac
+ done
+done
+;;
+ esac
+
+ # Create $as_me.lineno as a copy of $as_myself, but with $LINENO
+ # uniformly replaced by the line number. The first 'sed' inserts a
+ # line-number line before each line; the second 'sed' does the real
+ # work. The second script uses 'N' to pair each line-number line
+ # with the numbered line, and appends trailing '-' during
+ # substitution so that $LINENO is not a special case at line end.
+ # (Raja R Harinath suggested sed '=', and Paul Eggert wrote the
+ # second 'sed' script. Blame Lee E. McMahon for sed's syntax. :-)
+ sed '=' <$as_myself |
+ sed '
+ N
+ s,$,-,
+ : loop
+ s,^\(['$as_cr_digits']*\)\(.*\)[$]LINENO\([^'$as_cr_alnum'_]\),\1\2\1\3,
+ t loop
+ s,-$,,
+ s,^['$as_cr_digits']*\n,,
+ ' >$as_me.lineno &&
+ chmod +x $as_me.lineno ||
+ { { echo "$as_me:$LINENO: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&5
+echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2;}
+ { (exit 1); exit 1; }; }
+
+ # Don't try to exec as it changes $[0], causing all sort of problems
+ # (the dirname of $[0] is not the place where we might find the
+ # original and so on. Autoconf is especially sensible to this).
+ . ./$as_me.lineno
+ # Exit status is that of the last command.
+ exit
+}
+
+
+case `echo "testing\c"; echo 1,2,3`,`echo -n testing; echo 1,2,3` in
+ *c*,-n*) ECHO_N= ECHO_C='
+' ECHO_T=' ' ;;
+ *c*,* ) ECHO_N=-n ECHO_C= ECHO_T= ;;
+ *) ECHO_N= ECHO_C='\c' ECHO_T= ;;
+esac
+
+if expr a : '\(a\)' >/dev/null 2>&1; then
+ as_expr=expr
+else
+ as_expr=false
+fi
+
+rm -f conf$$ conf$$.exe conf$$.file
+echo >conf$$.file
+if ln -s conf$$.file conf$$ 2>/dev/null; then
+ # We could just check for DJGPP; but this test a) works b) is more generic
+ # and c) will remain valid once DJGPP supports symlinks (DJGPP 2.04).
+ if test -f conf$$.exe; then
+ # Don't use ln at all; we don't have any links
+ as_ln_s='cp -p'
+ else
+ as_ln_s='ln -s'
+ fi
+elif ln conf$$.file conf$$ 2>/dev/null; then
+ as_ln_s=ln
+else
+ as_ln_s='cp -p'
+fi
+rm -f conf$$ conf$$.exe conf$$.file
+
+if mkdir -p . 2>/dev/null; then
+ as_mkdir_p=:
+else
+ test -d ./-p && rmdir ./-p
+ as_mkdir_p=false
+fi
+
+as_executable_p="test -f"
+
+# Sed expression to map a string onto a valid CPP name.
+as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'"
+
+# Sed expression to map a string onto a valid variable name.
+as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'"
+
+
+# IFS
+# We need space, tab and new line, in precisely that order.
+as_nl='
+'
+IFS=" $as_nl"
+
+# CDPATH.
+$as_unset CDPATH
+
+exec 6>&1
+
+# Open the log real soon, to keep \$[0] and so on meaningful, and to
+# report actual input values of CONFIG_FILES etc. instead of their
+# values after options handling. Logging --version etc. is OK.
+exec 5>>config.log
+{
+ echo
+ sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX
+## Running $as_me. ##
+_ASBOX
+} >&5
+cat >&5 <<_CSEOF
+
+This file was extended by $as_me, which was
+generated by GNU Autoconf 2.59. Invocation command line was
+
+ CONFIG_FILES = $CONFIG_FILES
+ CONFIG_HEADERS = $CONFIG_HEADERS
+ CONFIG_LINKS = $CONFIG_LINKS
+ CONFIG_COMMANDS = $CONFIG_COMMANDS
+ $ $0 $@
+
+_CSEOF
+echo "on `(hostname || uname -n) 2>/dev/null | sed 1q`" >&5
+echo >&5
+_ACEOF
+
+# Files that config.status was made for.
+if test -n "$ac_config_files"; then
+ echo "config_files=\"$ac_config_files\"" >>$CONFIG_STATUS
+fi
+
+if test -n "$ac_config_headers"; then
+ echo "config_headers=\"$ac_config_headers\"" >>$CONFIG_STATUS
+fi
+
+if test -n "$ac_config_links"; then
+ echo "config_links=\"$ac_config_links\"" >>$CONFIG_STATUS
+fi
+
+if test -n "$ac_config_commands"; then
+ echo "config_commands=\"$ac_config_commands\"" >>$CONFIG_STATUS
+fi
+
+cat >>$CONFIG_STATUS <<\_ACEOF
+
+ac_cs_usage="\
+\`$as_me' instantiates files from templates according to the
+current configuration.
+
+Usage: $0 [OPTIONS] [FILE]...
+
+ -h, --help print this help, then exit
+ -V, --version print version number, then exit
+ -q, --quiet do not print progress messages
+ -d, --debug don't remove temporary files
+ --recheck update $as_me by reconfiguring in the same conditions
+ --file=FILE[:TEMPLATE]
+ instantiate the configuration file FILE
+ --header=FILE[:TEMPLATE]
+ instantiate the configuration header FILE
+
+Configuration files:
+$config_files
+
+Configuration headers:
+$config_headers
+
+Configuration links:
+$config_links
+
+Configuration commands:
+$config_commands
+
+Report bugs to <bug-autoconf@gnu.org>."
+_ACEOF
+
+cat >>$CONFIG_STATUS <<_ACEOF
+ac_cs_version="\\
+config.status
+configured by $0, generated by GNU Autoconf 2.59,
+ with options \\"`echo "$ac_configure_args" | sed 's/[\\""\`\$]/\\\\&/g'`\\"
+
+Copyright (C) 2003 Free Software Foundation, Inc.
+This config.status script is free software; the Free Software Foundation
+gives unlimited permission to copy, distribute and modify it."
+srcdir=$srcdir
+INSTALL="$INSTALL"
+_ACEOF
+
+cat >>$CONFIG_STATUS <<\_ACEOF
+# If no file are specified by the user, then we need to provide default
+# value. By we need to know if files were specified by the user.
+ac_need_defaults=:
+while test $# != 0
+do
+ case $1 in
+ --*=*)
+ ac_option=`expr "x$1" : 'x\([^=]*\)='`
+ ac_optarg=`expr "x$1" : 'x[^=]*=\(.*\)'`
+ ac_shift=:
+ ;;
+ -*)
+ ac_option=$1
+ ac_optarg=$2
+ ac_shift=shift
+ ;;
+ *) # This is not an option, so the user has probably given explicit
+ # arguments.
+ ac_option=$1
+ ac_need_defaults=false;;
+ esac
+
+ case $ac_option in
+ # Handling of the options.
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF
+ -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r)
+ ac_cs_recheck=: ;;
+ --version | --vers* | -V )
+ echo "$ac_cs_version"; exit 0 ;;
+ --he | --h)
+ # Conflict between --help and --header
+ { { echo "$as_me:$LINENO: error: ambiguous option: $1
+Try \`$0 --help' for more information." >&5
+echo "$as_me: error: ambiguous option: $1
+Try \`$0 --help' for more information." >&2;}
+ { (exit 1); exit 1; }; };;
+ --help | --hel | -h )
+ echo "$ac_cs_usage"; exit 0 ;;
+ --debug | --d* | -d )
+ debug=: ;;
+ --file | --fil | --fi | --f )
+ $ac_shift
+ CONFIG_FILES="$CONFIG_FILES $ac_optarg"
+ ac_need_defaults=false;;
+ --header | --heade | --head | --hea )
+ $ac_shift
+ CONFIG_HEADERS="$CONFIG_HEADERS $ac_optarg"
+ ac_need_defaults=false;;
+ -q | -quiet | --quiet | --quie | --qui | --qu | --q \
+ | -silent | --silent | --silen | --sile | --sil | --si | --s)
+ ac_cs_silent=: ;;
+
+ # This is an error.
+ -*) { { echo "$as_me:$LINENO: error: unrecognized option: $1
+Try \`$0 --help' for more information." >&5
+echo "$as_me: error: unrecognized option: $1
+Try \`$0 --help' for more information." >&2;}
+ { (exit 1); exit 1; }; } ;;
+
+ *) ac_config_targets="$ac_config_targets $1" ;;
+
+ esac
+ shift
+done
+
+ac_configure_extra_args=
+
+if $ac_cs_silent; then
+ exec 6>/dev/null
+ ac_configure_extra_args="$ac_configure_extra_args --silent"
+fi
+
+_ACEOF
+cat >>$CONFIG_STATUS <<_ACEOF
+if \$ac_cs_recheck; then
+ echo "running $SHELL $0 " $ac_configure_args \$ac_configure_extra_args " --no-create --no-recursion" >&6
+ exec $SHELL $0 $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion
+fi
+
+_ACEOF
+
+
+
+
+
+cat >>$CONFIG_STATUS <<\_ACEOF
+for ac_config_target in $ac_config_targets
+do
+ case "$ac_config_target" in
+ # Handling of arguments.
+ "Makefile.sim" ) CONFIG_FILES="$CONFIG_FILES Makefile.sim:Makefile.in" ;;
+ "Make-common.sim" ) CONFIG_FILES="$CONFIG_FILES Make-common.sim:../common/Make-common.in" ;;
+ ".gdbinit" ) CONFIG_FILES="$CONFIG_FILES .gdbinit:../common/gdbinit.in" ;;
+ "$ac_config_links_1" ) CONFIG_LINKS="$CONFIG_LINKS $ac_config_links_1" ;;
+ "Makefile" ) CONFIG_COMMANDS="$CONFIG_COMMANDS Makefile" ;;
+ "stamp-h" ) CONFIG_COMMANDS="$CONFIG_COMMANDS stamp-h" ;;
+ "config.h" ) CONFIG_HEADERS="$CONFIG_HEADERS config.h:config.in" ;;
+ *) { { echo "$as_me:$LINENO: error: invalid argument: $ac_config_target" >&5
+echo "$as_me: error: invalid argument: $ac_config_target" >&2;}
+ { (exit 1); exit 1; }; };;
+ esac
+done
+
+# If the user did not use the arguments to specify the items to instantiate,
+# then the envvar interface is used. Set only those that are not.
+# We use the long form for the default assignment because of an extremely
+# bizarre bug on SunOS 4.1.3.
+if $ac_need_defaults; then
+ test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files
+ test "${CONFIG_HEADERS+set}" = set || CONFIG_HEADERS=$config_headers
+ test "${CONFIG_LINKS+set}" = set || CONFIG_LINKS=$config_links
+ test "${CONFIG_COMMANDS+set}" = set || CONFIG_COMMANDS=$config_commands
+fi
+
+# Have a temporary directory for convenience. Make it in the build tree
+# simply because there is no reason to put it here, and in addition,
+# creating and moving files from /tmp can sometimes cause problems.
+# Create a temporary directory, and hook for its removal unless debugging.
+$debug ||
+{
+ trap 'exit_status=$?; rm -rf $tmp && exit $exit_status' 0
+ trap '{ (exit 1); exit 1; }' 1 2 13 15
+}
+
+# Create a (secure) tmp directory for tmp files.
+
+{
+ tmp=`(umask 077 && mktemp -d -q "./confstatXXXXXX") 2>/dev/null` &&
+ test -n "$tmp" && test -d "$tmp"
+} ||
+{
+ tmp=./confstat$$-$RANDOM
+ (umask 077 && mkdir $tmp)
+} ||
+{
+ echo "$me: cannot create a temporary directory in ." >&2
+ { (exit 1); exit 1; }
+}
+
+_ACEOF
+
+cat >>$CONFIG_STATUS <<_ACEOF
+
+#
+# CONFIG_FILES section.
+#
+
+# No need to generate the scripts if there are no CONFIG_FILES.
+# This happens for instance when ./config.status config.h
+if test -n "\$CONFIG_FILES"; then
+ # Protect against being on the right side of a sed subst in config.status.
+ sed 's/,@/@@/; s/@,/@@/; s/,;t t\$/@;t t/; /@;t t\$/s/[\\\\&,]/\\\\&/g;
+ s/@@/,@/; s/@@/@,/; s/@;t t\$/,;t t/' >\$tmp/subs.sed <<\\CEOF
+s,@SHELL@,$SHELL,;t t
+s,@PATH_SEPARATOR@,$PATH_SEPARATOR,;t t
+s,@PACKAGE_NAME@,$PACKAGE_NAME,;t t
+s,@PACKAGE_TARNAME@,$PACKAGE_TARNAME,;t t
+s,@PACKAGE_VERSION@,$PACKAGE_VERSION,;t t
+s,@PACKAGE_STRING@,$PACKAGE_STRING,;t t
+s,@PACKAGE_BUGREPORT@,$PACKAGE_BUGREPORT,;t t
+s,@exec_prefix@,$exec_prefix,;t t
+s,@prefix@,$prefix,;t t
+s,@program_transform_name@,$program_transform_name,;t t
+s,@bindir@,$bindir,;t t
+s,@sbindir@,$sbindir,;t t
+s,@libexecdir@,$libexecdir,;t t
+s,@datadir@,$datadir,;t t
+s,@sysconfdir@,$sysconfdir,;t t
+s,@sharedstatedir@,$sharedstatedir,;t t
+s,@localstatedir@,$localstatedir,;t t
+s,@libdir@,$libdir,;t t
+s,@includedir@,$includedir,;t t
+s,@oldincludedir@,$oldincludedir,;t t
+s,@infodir@,$infodir,;t t
+s,@mandir@,$mandir,;t t
+s,@build_alias@,$build_alias,;t t
+s,@host_alias@,$host_alias,;t t
+s,@target_alias@,$target_alias,;t t
+s,@DEFS@,$DEFS,;t t
+s,@ECHO_C@,$ECHO_C,;t t
+s,@ECHO_N@,$ECHO_N,;t t
+s,@ECHO_T@,$ECHO_T,;t t
+s,@LIBS@,$LIBS,;t t
+s,@sim_environment@,$sim_environment,;t t
+s,@sim_alignment@,$sim_alignment,;t t
+s,@sim_assert@,$sim_assert,;t t
+s,@sim_bitsize@,$sim_bitsize,;t t
+s,@sim_endian@,$sim_endian,;t t
+s,@sim_hostendian@,$sim_hostendian,;t t
+s,@sim_float@,$sim_float,;t t
+s,@sim_scache@,$sim_scache,;t t
+s,@sim_default_model@,$sim_default_model,;t t
+s,@sim_hw_cflags@,$sim_hw_cflags,;t t
+s,@sim_hw_objs@,$sim_hw_objs,;t t
+s,@sim_hw@,$sim_hw,;t t
+s,@sim_inline@,$sim_inline,;t t
+s,@sim_packages@,$sim_packages,;t t
+s,@sim_regparm@,$sim_regparm,;t t
+s,@sim_reserved_bits@,$sim_reserved_bits,;t t
+s,@sim_smp@,$sim_smp,;t t
+s,@sim_stdcall@,$sim_stdcall,;t t
+s,@sim_xor_endian@,$sim_xor_endian,;t t
+s,@WARN_CFLAGS@,$WARN_CFLAGS,;t t
+s,@WERROR_CFLAGS@,$WERROR_CFLAGS,;t t
+s,@build@,$build,;t t
+s,@build_cpu@,$build_cpu,;t t
+s,@build_vendor@,$build_vendor,;t t
+s,@build_os@,$build_os,;t t
+s,@host@,$host,;t t
+s,@host_cpu@,$host_cpu,;t t
+s,@host_vendor@,$host_vendor,;t t
+s,@host_os@,$host_os,;t t
+s,@target@,$target,;t t
+s,@target_cpu@,$target_cpu,;t t
+s,@target_vendor@,$target_vendor,;t t
+s,@target_os@,$target_os,;t t
+s,@CC@,$CC,;t t
+s,@CFLAGS@,$CFLAGS,;t t
+s,@LDFLAGS@,$LDFLAGS,;t t
+s,@CPPFLAGS@,$CPPFLAGS,;t t
+s,@ac_ct_CC@,$ac_ct_CC,;t t
+s,@EXEEXT@,$EXEEXT,;t t
+s,@OBJEXT@,$OBJEXT,;t t
+s,@INSTALL_PROGRAM@,$INSTALL_PROGRAM,;t t
+s,@INSTALL_SCRIPT@,$INSTALL_SCRIPT,;t t
+s,@INSTALL_DATA@,$INSTALL_DATA,;t t
+s,@CC_FOR_BUILD@,$CC_FOR_BUILD,;t t
+s,@HDEFINES@,$HDEFINES,;t t
+s,@AR@,$AR,;t t
+s,@RANLIB@,$RANLIB,;t t
+s,@ac_ct_RANLIB@,$ac_ct_RANLIB,;t t
+s,@SET_MAKE@,$SET_MAKE,;t t
+s,@CPP@,$CPP,;t t
+s,@EGREP@,$EGREP,;t t
+s,@ALLOCA@,$ALLOCA,;t t
+s,@USE_NLS@,$USE_NLS,;t t
+s,@MSGFMT@,$MSGFMT,;t t
+s,@GMSGFMT@,$GMSGFMT,;t t
+s,@XGETTEXT@,$XGETTEXT,;t t
+s,@USE_INCLUDED_LIBINTL@,$USE_INCLUDED_LIBINTL,;t t
+s,@CATALOGS@,$CATALOGS,;t t
+s,@CATOBJEXT@,$CATOBJEXT,;t t
+s,@DATADIRNAME@,$DATADIRNAME,;t t
+s,@GMOFILES@,$GMOFILES,;t t
+s,@INSTOBJEXT@,$INSTOBJEXT,;t t
+s,@INTLDEPS@,$INTLDEPS,;t t
+s,@INTLLIBS@,$INTLLIBS,;t t
+s,@INTLOBJS@,$INTLOBJS,;t t
+s,@POFILES@,$POFILES,;t t
+s,@POSUB@,$POSUB,;t t
+s,@INCLUDE_LOCALE_H@,$INCLUDE_LOCALE_H,;t t
+s,@GT_NO@,$GT_NO,;t t
+s,@GT_YES@,$GT_YES,;t t
+s,@MKINSTALLDIRS@,$MKINSTALLDIRS,;t t
+s,@l@,$l,;t t
+s,@MAINT@,$MAINT,;t t
+s,@sim_bswap@,$sim_bswap,;t t
+s,@sim_cflags@,$sim_cflags,;t t
+s,@sim_debug@,$sim_debug,;t t
+s,@sim_stdio@,$sim_stdio,;t t
+s,@sim_trace@,$sim_trace,;t t
+s,@sim_profile@,$sim_profile,;t t
+s,@CGEN_MAINT@,$CGEN_MAINT,;t t
+s,@cgendir@,$cgendir,;t t
+s,@cgen@,$cgen,;t t
+s,@cgen_breaks@,$cgen_breaks,;t t
+s,@LIBOBJS@,$LIBOBJS,;t t
+s,@LTLIBOBJS@,$LTLIBOBJS,;t t
+CEOF
+
+_ACEOF
+
+ cat >>$CONFIG_STATUS <<\_ACEOF
+ # Split the substitutions into bite-sized pieces for seds with
+ # small command number limits, like on Digital OSF/1 and HP-UX.
+ ac_max_sed_lines=48
+ ac_sed_frag=1 # Number of current file.
+ ac_beg=1 # First line for current file.
+ ac_end=$ac_max_sed_lines # Line after last line for current file.
+ ac_more_lines=:
+ ac_sed_cmds=
+ while $ac_more_lines; do
+ if test $ac_beg -gt 1; then
+ sed "1,${ac_beg}d; ${ac_end}q" $tmp/subs.sed >$tmp/subs.frag
+ else
+ sed "${ac_end}q" $tmp/subs.sed >$tmp/subs.frag
+ fi
+ if test ! -s $tmp/subs.frag; then
+ ac_more_lines=false
+ else
+ # The purpose of the label and of the branching condition is to
+ # speed up the sed processing (if there are no `@' at all, there
+ # is no need to browse any of the substitutions).
+ # These are the two extra sed commands mentioned above.
+ (echo ':t
+ /@[a-zA-Z_][a-zA-Z_0-9]*@/!b' && cat $tmp/subs.frag) >$tmp/subs-$ac_sed_frag.sed
+ if test -z "$ac_sed_cmds"; then
+ ac_sed_cmds="sed -f $tmp/subs-$ac_sed_frag.sed"
+ else
+ ac_sed_cmds="$ac_sed_cmds | sed -f $tmp/subs-$ac_sed_frag.sed"
+ fi
+ ac_sed_frag=`expr $ac_sed_frag + 1`
+ ac_beg=$ac_end
+ ac_end=`expr $ac_end + $ac_max_sed_lines`
+ fi
+ done
+ if test -z "$ac_sed_cmds"; then
+ ac_sed_cmds=cat
+ fi
+fi # test -n "$CONFIG_FILES"
+
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF
+for ac_file in : $CONFIG_FILES; do test "x$ac_file" = x: && continue
+ # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
+ case $ac_file in
+ - | *:- | *:-:* ) # input from stdin
+ cat >$tmp/stdin
+ ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'`
+ ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;;
+ *:* ) ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'`
+ ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;;
+ * ) ac_file_in=$ac_file.in ;;
+ esac
+
+ # Compute @srcdir@, @top_srcdir@, and @INSTALL@ for subdirectories.
+ ac_dir=`(dirname "$ac_file") 2>/dev/null ||
+$as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+ X"$ac_file" : 'X\(//\)[^/]' \| \
+ X"$ac_file" : 'X\(//\)$' \| \
+ X"$ac_file" : 'X\(/\)' \| \
+ . : '\(.\)' 2>/dev/null ||
+echo X"$ac_file" |
+ sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
+ /^X\(\/\/\)[^/].*/{ s//\1/; q; }
+ /^X\(\/\/\)$/{ s//\1/; q; }
+ /^X\(\/\).*/{ s//\1/; q; }
+ s/.*/./; q'`
+ { if $as_mkdir_p; then
+ mkdir -p "$ac_dir"
+ else
+ as_dir="$ac_dir"
+ as_dirs=
+ while test ! -d "$as_dir"; do
+ as_dirs="$as_dir $as_dirs"
+ as_dir=`(dirname "$as_dir") 2>/dev/null ||
+$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+ X"$as_dir" : 'X\(//\)[^/]' \| \
+ X"$as_dir" : 'X\(//\)$' \| \
+ X"$as_dir" : 'X\(/\)' \| \
+ . : '\(.\)' 2>/dev/null ||
+echo X"$as_dir" |
+ sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
+ /^X\(\/\/\)[^/].*/{ s//\1/; q; }
+ /^X\(\/\/\)$/{ s//\1/; q; }
+ /^X\(\/\).*/{ s//\1/; q; }
+ s/.*/./; q'`
+ done
+ test ! -n "$as_dirs" || mkdir $as_dirs
+ fi || { { echo "$as_me:$LINENO: error: cannot create directory \"$ac_dir\"" >&5
+echo "$as_me: error: cannot create directory \"$ac_dir\"" >&2;}
+ { (exit 1); exit 1; }; }; }
+
+ ac_builddir=.
+
+if test "$ac_dir" != .; then
+ ac_dir_suffix=/`echo "$ac_dir" | sed 's,^\.[\\/],,'`
+ # A "../" for each directory in $ac_dir_suffix.
+ ac_top_builddir=`echo "$ac_dir_suffix" | sed 's,/[^\\/]*,../,g'`
+else
+ ac_dir_suffix= ac_top_builddir=
+fi
+
+case $srcdir in
+ .) # No --srcdir option. We are building in place.
+ ac_srcdir=.
+ if test -z "$ac_top_builddir"; then
+ ac_top_srcdir=.
+ else
+ ac_top_srcdir=`echo $ac_top_builddir | sed 's,/$,,'`
+ fi ;;
+ [\\/]* | ?:[\\/]* ) # Absolute path.
+ ac_srcdir=$srcdir$ac_dir_suffix;
+ ac_top_srcdir=$srcdir ;;
+ *) # Relative path.
+ ac_srcdir=$ac_top_builddir$srcdir$ac_dir_suffix
+ ac_top_srcdir=$ac_top_builddir$srcdir ;;
+esac
+
+# Do not use `cd foo && pwd` to compute absolute paths, because
+# the directories may not exist.
+case `pwd` in
+.) ac_abs_builddir="$ac_dir";;
+*)
+ case "$ac_dir" in
+ .) ac_abs_builddir=`pwd`;;
+ [\\/]* | ?:[\\/]* ) ac_abs_builddir="$ac_dir";;
+ *) ac_abs_builddir=`pwd`/"$ac_dir";;
+ esac;;
+esac
+case $ac_abs_builddir in
+.) ac_abs_top_builddir=${ac_top_builddir}.;;
+*)
+ case ${ac_top_builddir}. in
+ .) ac_abs_top_builddir=$ac_abs_builddir;;
+ [\\/]* | ?:[\\/]* ) ac_abs_top_builddir=${ac_top_builddir}.;;
+ *) ac_abs_top_builddir=$ac_abs_builddir/${ac_top_builddir}.;;
+ esac;;
+esac
+case $ac_abs_builddir in
+.) ac_abs_srcdir=$ac_srcdir;;
+*)
+ case $ac_srcdir in
+ .) ac_abs_srcdir=$ac_abs_builddir;;
+ [\\/]* | ?:[\\/]* ) ac_abs_srcdir=$ac_srcdir;;
+ *) ac_abs_srcdir=$ac_abs_builddir/$ac_srcdir;;
+ esac;;
+esac
+case $ac_abs_builddir in
+.) ac_abs_top_srcdir=$ac_top_srcdir;;
+*)
+ case $ac_top_srcdir in
+ .) ac_abs_top_srcdir=$ac_abs_builddir;;
+ [\\/]* | ?:[\\/]* ) ac_abs_top_srcdir=$ac_top_srcdir;;
+ *) ac_abs_top_srcdir=$ac_abs_builddir/$ac_top_srcdir;;
+ esac;;
+esac
+
+
+ case $INSTALL in
+ [\\/$]* | ?:[\\/]* ) ac_INSTALL=$INSTALL ;;
+ *) ac_INSTALL=$ac_top_builddir$INSTALL ;;
+ esac
+
+ if test x"$ac_file" != x-; then
+ { echo "$as_me:$LINENO: creating $ac_file" >&5
+echo "$as_me: creating $ac_file" >&6;}
+ rm -f "$ac_file"
+ fi
+ # Let's still pretend it is `configure' which instantiates (i.e., don't
+ # use $as_me), people would be surprised to read:
+ # /* config.h. Generated by config.status. */
+ if test x"$ac_file" = x-; then
+ configure_input=
+ else
+ configure_input="$ac_file. "
+ fi
+ configure_input=$configure_input"Generated from `echo $ac_file_in |
+ sed 's,.*/,,'` by configure."
+
+ # First look for the input files in the build tree, otherwise in the
+ # src tree.
+ ac_file_inputs=`IFS=:
+ for f in $ac_file_in; do
+ case $f in
+ -) echo $tmp/stdin ;;
+ [\\/$]*)
+ # Absolute (can't be DOS-style, as IFS=:)
+ test -f "$f" || { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5
+echo "$as_me: error: cannot find input file: $f" >&2;}
+ { (exit 1); exit 1; }; }
+ echo "$f";;
+ *) # Relative
+ if test -f "$f"; then
+ # Build tree
+ echo "$f"
+ elif test -f "$srcdir/$f"; then
+ # Source tree
+ echo "$srcdir/$f"
+ else
+ # /dev/null tree
+ { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5
+echo "$as_me: error: cannot find input file: $f" >&2;}
+ { (exit 1); exit 1; }; }
+ fi;;
+ esac
+ done` || { (exit 1); exit 1; }
+_ACEOF
+cat >>$CONFIG_STATUS <<_ACEOF
+ sed "$ac_vpsub
+$extrasub
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF
+:t
+/@[a-zA-Z_][a-zA-Z_0-9]*@/!b
+s,@configure_input@,$configure_input,;t t
+s,@srcdir@,$ac_srcdir,;t t
+s,@abs_srcdir@,$ac_abs_srcdir,;t t
+s,@top_srcdir@,$ac_top_srcdir,;t t
+s,@abs_top_srcdir@,$ac_abs_top_srcdir,;t t
+s,@builddir@,$ac_builddir,;t t
+s,@abs_builddir@,$ac_abs_builddir,;t t
+s,@top_builddir@,$ac_top_builddir,;t t
+s,@abs_top_builddir@,$ac_abs_top_builddir,;t t
+s,@INSTALL@,$ac_INSTALL,;t t
+" $ac_file_inputs | (eval "$ac_sed_cmds") >$tmp/out
+ rm -f $tmp/stdin
+ if test x"$ac_file" != x-; then
+ mv $tmp/out $ac_file
+ else
+ cat $tmp/out
+ rm -f $tmp/out
+ fi
+
+done
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF
+
+#
+# CONFIG_HEADER section.
+#
+
+# These sed commands are passed to sed as "A NAME B NAME C VALUE D", where
+# NAME is the cpp macro being defined and VALUE is the value it is being given.
+#
+# ac_d sets the value in "#define NAME VALUE" lines.
+ac_dA='s,^\([ ]*\)#\([ ]*define[ ][ ]*\)'
+ac_dB='[ ].*$,\1#\2'
+ac_dC=' '
+ac_dD=',;t'
+# ac_u turns "#undef NAME" without trailing blanks into "#define NAME VALUE".
+ac_uA='s,^\([ ]*\)#\([ ]*\)undef\([ ][ ]*\)'
+ac_uB='$,\1#\2define\3'
+ac_uC=' '
+ac_uD=',;t'
+
+for ac_file in : $CONFIG_HEADERS; do test "x$ac_file" = x: && continue
+ # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
+ case $ac_file in
+ - | *:- | *:-:* ) # input from stdin
+ cat >$tmp/stdin
+ ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'`
+ ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;;
+ *:* ) ac_file_in=`echo "$ac_file" | sed 's,[^:]*:,,'`
+ ac_file=`echo "$ac_file" | sed 's,:.*,,'` ;;
+ * ) ac_file_in=$ac_file.in ;;
+ esac
+
+ test x"$ac_file" != x- && { echo "$as_me:$LINENO: creating $ac_file" >&5
+echo "$as_me: creating $ac_file" >&6;}
+
+ # First look for the input files in the build tree, otherwise in the
+ # src tree.
+ ac_file_inputs=`IFS=:
+ for f in $ac_file_in; do
+ case $f in
+ -) echo $tmp/stdin ;;
+ [\\/$]*)
+ # Absolute (can't be DOS-style, as IFS=:)
+ test -f "$f" || { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5
+echo "$as_me: error: cannot find input file: $f" >&2;}
+ { (exit 1); exit 1; }; }
+ # Do quote $f, to prevent DOS paths from being IFS'd.
+ echo "$f";;
+ *) # Relative
+ if test -f "$f"; then
+ # Build tree
+ echo "$f"
+ elif test -f "$srcdir/$f"; then
+ # Source tree
+ echo "$srcdir/$f"
+ else
+ # /dev/null tree
+ { { echo "$as_me:$LINENO: error: cannot find input file: $f" >&5
+echo "$as_me: error: cannot find input file: $f" >&2;}
+ { (exit 1); exit 1; }; }
+ fi;;
+ esac
+ done` || { (exit 1); exit 1; }
+ # Remove the trailing spaces.
+ sed 's/[ ]*$//' $ac_file_inputs >$tmp/in
+
+_ACEOF
+
+# Transform confdefs.h into two sed scripts, `conftest.defines' and
+# `conftest.undefs', that substitutes the proper values into
+# config.h.in to produce config.h. The first handles `#define'
+# templates, and the second `#undef' templates.
+# And first: Protect against being on the right side of a sed subst in
+# config.status. Protect against being in an unquoted here document
+# in config.status.
+rm -f conftest.defines conftest.undefs
+# Using a here document instead of a string reduces the quoting nightmare.
+# Putting comments in sed scripts is not portable.
+#
+# `end' is used to avoid that the second main sed command (meant for
+# 0-ary CPP macros) applies to n-ary macro definitions.
+# See the Autoconf documentation for `clear'.
+cat >confdef2sed.sed <<\_ACEOF
+s/[\\&,]/\\&/g
+s,[\\$`],\\&,g
+t clear
+: clear
+s,^[ ]*#[ ]*define[ ][ ]*\([^ (][^ (]*\)\(([^)]*)\)[ ]*\(.*\)$,${ac_dA}\1${ac_dB}\1\2${ac_dC}\3${ac_dD},gp
+t end
+s,^[ ]*#[ ]*define[ ][ ]*\([^ ][^ ]*\)[ ]*\(.*\)$,${ac_dA}\1${ac_dB}\1${ac_dC}\2${ac_dD},gp
+: end
+_ACEOF
+# If some macros were called several times there might be several times
+# the same #defines, which is useless. Nevertheless, we may not want to
+# sort them, since we want the *last* AC-DEFINE to be honored.
+uniq confdefs.h | sed -n -f confdef2sed.sed >conftest.defines
+sed 's/ac_d/ac_u/g' conftest.defines >conftest.undefs
+rm -f confdef2sed.sed
+
+# This sed command replaces #undef with comments. This is necessary, for
+# example, in the case of _POSIX_SOURCE, which is predefined and required
+# on some systems where configure will not decide to define it.
+cat >>conftest.undefs <<\_ACEOF
+s,^[ ]*#[ ]*undef[ ][ ]*[a-zA-Z_][a-zA-Z_0-9]*,/* & */,
+_ACEOF
+
+# Break up conftest.defines because some shells have a limit on the size
+# of here documents, and old seds have small limits too (100 cmds).
+echo ' # Handle all the #define templates only if necessary.' >>$CONFIG_STATUS
+echo ' if grep "^[ ]*#[ ]*define" $tmp/in >/dev/null; then' >>$CONFIG_STATUS
+echo ' # If there are no defines, we may have an empty if/fi' >>$CONFIG_STATUS
+echo ' :' >>$CONFIG_STATUS
+rm -f conftest.tail
+while grep . conftest.defines >/dev/null
+do
+ # Write a limited-size here document to $tmp/defines.sed.
+ echo ' cat >$tmp/defines.sed <<CEOF' >>$CONFIG_STATUS
+ # Speed up: don't consider the non `#define' lines.
+ echo '/^[ ]*#[ ]*define/!b' >>$CONFIG_STATUS
+ # Work around the forget-to-reset-the-flag bug.
+ echo 't clr' >>$CONFIG_STATUS
+ echo ': clr' >>$CONFIG_STATUS
+ sed ${ac_max_here_lines}q conftest.defines >>$CONFIG_STATUS
+ echo 'CEOF
+ sed -f $tmp/defines.sed $tmp/in >$tmp/out
+ rm -f $tmp/in
+ mv $tmp/out $tmp/in
+' >>$CONFIG_STATUS
+ sed 1,${ac_max_here_lines}d conftest.defines >conftest.tail
+ rm -f conftest.defines
+ mv conftest.tail conftest.defines
+done
+rm -f conftest.defines
+echo ' fi # grep' >>$CONFIG_STATUS
+echo >>$CONFIG_STATUS
+
+# Break up conftest.undefs because some shells have a limit on the size
+# of here documents, and old seds have small limits too (100 cmds).
+echo ' # Handle all the #undef templates' >>$CONFIG_STATUS
+rm -f conftest.tail
+while grep . conftest.undefs >/dev/null
+do
+ # Write a limited-size here document to $tmp/undefs.sed.
+ echo ' cat >$tmp/undefs.sed <<CEOF' >>$CONFIG_STATUS
+ # Speed up: don't consider the non `#undef'
+ echo '/^[ ]*#[ ]*undef/!b' >>$CONFIG_STATUS
+ # Work around the forget-to-reset-the-flag bug.
+ echo 't clr' >>$CONFIG_STATUS
+ echo ': clr' >>$CONFIG_STATUS
+ sed ${ac_max_here_lines}q conftest.undefs >>$CONFIG_STATUS
+ echo 'CEOF
+ sed -f $tmp/undefs.sed $tmp/in >$tmp/out
+ rm -f $tmp/in
+ mv $tmp/out $tmp/in
+' >>$CONFIG_STATUS
+ sed 1,${ac_max_here_lines}d conftest.undefs >conftest.tail
+ rm -f conftest.undefs
+ mv conftest.tail conftest.undefs
+done
+rm -f conftest.undefs
+
+cat >>$CONFIG_STATUS <<\_ACEOF
+ # Let's still pretend it is `configure' which instantiates (i.e., don't
+ # use $as_me), people would be surprised to read:
+ # /* config.h. Generated by config.status. */
+ if test x"$ac_file" = x-; then
+ echo "/* Generated by configure. */" >$tmp/config.h
+ else
+ echo "/* $ac_file. Generated by configure. */" >$tmp/config.h
+ fi
+ cat $tmp/in >>$tmp/config.h
+ rm -f $tmp/in
+ if test x"$ac_file" != x-; then
+ if diff $ac_file $tmp/config.h >/dev/null 2>&1; then
+ { echo "$as_me:$LINENO: $ac_file is unchanged" >&5
+echo "$as_me: $ac_file is unchanged" >&6;}
+ else
+ ac_dir=`(dirname "$ac_file") 2>/dev/null ||
+$as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+ X"$ac_file" : 'X\(//\)[^/]' \| \
+ X"$ac_file" : 'X\(//\)$' \| \
+ X"$ac_file" : 'X\(/\)' \| \
+ . : '\(.\)' 2>/dev/null ||
+echo X"$ac_file" |
+ sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
+ /^X\(\/\/\)[^/].*/{ s//\1/; q; }
+ /^X\(\/\/\)$/{ s//\1/; q; }
+ /^X\(\/\).*/{ s//\1/; q; }
+ s/.*/./; q'`
+ { if $as_mkdir_p; then
+ mkdir -p "$ac_dir"
+ else
+ as_dir="$ac_dir"
+ as_dirs=
+ while test ! -d "$as_dir"; do
+ as_dirs="$as_dir $as_dirs"
+ as_dir=`(dirname "$as_dir") 2>/dev/null ||
+$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+ X"$as_dir" : 'X\(//\)[^/]' \| \
+ X"$as_dir" : 'X\(//\)$' \| \
+ X"$as_dir" : 'X\(/\)' \| \
+ . : '\(.\)' 2>/dev/null ||
+echo X"$as_dir" |
+ sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
+ /^X\(\/\/\)[^/].*/{ s//\1/; q; }
+ /^X\(\/\/\)$/{ s//\1/; q; }
+ /^X\(\/\).*/{ s//\1/; q; }
+ s/.*/./; q'`
+ done
+ test ! -n "$as_dirs" || mkdir $as_dirs
+ fi || { { echo "$as_me:$LINENO: error: cannot create directory \"$ac_dir\"" >&5
+echo "$as_me: error: cannot create directory \"$ac_dir\"" >&2;}
+ { (exit 1); exit 1; }; }; }
+
+ rm -f $ac_file
+ mv $tmp/config.h $ac_file
+ fi
+ else
+ cat $tmp/config.h
+ rm -f $tmp/config.h
+ fi
+done
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF
+
+#
+# CONFIG_LINKS section.
+#
+
+for ac_file in : $CONFIG_LINKS; do test "x$ac_file" = x: && continue
+ ac_dest=`echo "$ac_file" | sed 's,:.*,,'`
+ ac_source=`echo "$ac_file" | sed 's,[^:]*:,,'`
+
+ { echo "$as_me:$LINENO: linking $srcdir/$ac_source to $ac_dest" >&5
+echo "$as_me: linking $srcdir/$ac_source to $ac_dest" >&6;}
+
+ if test ! -r $srcdir/$ac_source; then
+ { { echo "$as_me:$LINENO: error: $srcdir/$ac_source: file not found" >&5
+echo "$as_me: error: $srcdir/$ac_source: file not found" >&2;}
+ { (exit 1); exit 1; }; }
+ fi
+ rm -f $ac_dest
+
+ # Make relative symlinks.
+ ac_dest_dir=`(dirname "$ac_dest") 2>/dev/null ||
+$as_expr X"$ac_dest" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+ X"$ac_dest" : 'X\(//\)[^/]' \| \
+ X"$ac_dest" : 'X\(//\)$' \| \
+ X"$ac_dest" : 'X\(/\)' \| \
+ . : '\(.\)' 2>/dev/null ||
+echo X"$ac_dest" |
+ sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
+ /^X\(\/\/\)[^/].*/{ s//\1/; q; }
+ /^X\(\/\/\)$/{ s//\1/; q; }
+ /^X\(\/\).*/{ s//\1/; q; }
+ s/.*/./; q'`
+ { if $as_mkdir_p; then
+ mkdir -p "$ac_dest_dir"
+ else
+ as_dir="$ac_dest_dir"
+ as_dirs=
+ while test ! -d "$as_dir"; do
+ as_dirs="$as_dir $as_dirs"
+ as_dir=`(dirname "$as_dir") 2>/dev/null ||
+$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+ X"$as_dir" : 'X\(//\)[^/]' \| \
+ X"$as_dir" : 'X\(//\)$' \| \
+ X"$as_dir" : 'X\(/\)' \| \
+ . : '\(.\)' 2>/dev/null ||
+echo X"$as_dir" |
+ sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
+ /^X\(\/\/\)[^/].*/{ s//\1/; q; }
+ /^X\(\/\/\)$/{ s//\1/; q; }
+ /^X\(\/\).*/{ s//\1/; q; }
+ s/.*/./; q'`
+ done
+ test ! -n "$as_dirs" || mkdir $as_dirs
+ fi || { { echo "$as_me:$LINENO: error: cannot create directory \"$ac_dest_dir\"" >&5
+echo "$as_me: error: cannot create directory \"$ac_dest_dir\"" >&2;}
+ { (exit 1); exit 1; }; }; }
+
+ ac_builddir=.
+
+if test "$ac_dest_dir" != .; then
+ ac_dir_suffix=/`echo "$ac_dest_dir" | sed 's,^\.[\\/],,'`
+ # A "../" for each directory in $ac_dir_suffix.
+ ac_top_builddir=`echo "$ac_dir_suffix" | sed 's,/[^\\/]*,../,g'`
+else
+ ac_dir_suffix= ac_top_builddir=
+fi
+
+case $srcdir in
+ .) # No --srcdir option. We are building in place.
+ ac_srcdir=.
+ if test -z "$ac_top_builddir"; then
+ ac_top_srcdir=.
+ else
+ ac_top_srcdir=`echo $ac_top_builddir | sed 's,/$,,'`
+ fi ;;
+ [\\/]* | ?:[\\/]* ) # Absolute path.
+ ac_srcdir=$srcdir$ac_dir_suffix;
+ ac_top_srcdir=$srcdir ;;
+ *) # Relative path.
+ ac_srcdir=$ac_top_builddir$srcdir$ac_dir_suffix
+ ac_top_srcdir=$ac_top_builddir$srcdir ;;
+esac
+
+# Do not use `cd foo && pwd` to compute absolute paths, because
+# the directories may not exist.
+case `pwd` in
+.) ac_abs_builddir="$ac_dest_dir";;
+*)
+ case "$ac_dest_dir" in
+ .) ac_abs_builddir=`pwd`;;
+ [\\/]* | ?:[\\/]* ) ac_abs_builddir="$ac_dest_dir";;
+ *) ac_abs_builddir=`pwd`/"$ac_dest_dir";;
+ esac;;
+esac
+case $ac_abs_builddir in
+.) ac_abs_top_builddir=${ac_top_builddir}.;;
+*)
+ case ${ac_top_builddir}. in
+ .) ac_abs_top_builddir=$ac_abs_builddir;;
+ [\\/]* | ?:[\\/]* ) ac_abs_top_builddir=${ac_top_builddir}.;;
+ *) ac_abs_top_builddir=$ac_abs_builddir/${ac_top_builddir}.;;
+ esac;;
+esac
+case $ac_abs_builddir in
+.) ac_abs_srcdir=$ac_srcdir;;
+*)
+ case $ac_srcdir in
+ .) ac_abs_srcdir=$ac_abs_builddir;;
+ [\\/]* | ?:[\\/]* ) ac_abs_srcdir=$ac_srcdir;;
+ *) ac_abs_srcdir=$ac_abs_builddir/$ac_srcdir;;
+ esac;;
+esac
+case $ac_abs_builddir in
+.) ac_abs_top_srcdir=$ac_top_srcdir;;
+*)
+ case $ac_top_srcdir in
+ .) ac_abs_top_srcdir=$ac_abs_builddir;;
+ [\\/]* | ?:[\\/]* ) ac_abs_top_srcdir=$ac_top_srcdir;;
+ *) ac_abs_top_srcdir=$ac_abs_builddir/$ac_top_srcdir;;
+ esac;;
+esac
+
+
+ case $srcdir in
+ [\\/$]* | ?:[\\/]* ) ac_rel_source=$srcdir/$ac_source ;;
+ *) ac_rel_source=$ac_top_builddir$srcdir/$ac_source ;;
+ esac
+
+ # Try a symlink, then a hard link, then a copy.
+ ln -s $ac_rel_source $ac_dest 2>/dev/null ||
+ ln $srcdir/$ac_source $ac_dest 2>/dev/null ||
+ cp -p $srcdir/$ac_source $ac_dest ||
+ { { echo "$as_me:$LINENO: error: cannot link or copy $srcdir/$ac_source to $ac_dest" >&5
+echo "$as_me: error: cannot link or copy $srcdir/$ac_source to $ac_dest" >&2;}
+ { (exit 1); exit 1; }; }
+done
+_ACEOF
+cat >>$CONFIG_STATUS <<\_ACEOF
+
+#
+# CONFIG_COMMANDS section.
+#
+for ac_file in : $CONFIG_COMMANDS; do test "x$ac_file" = x: && continue
+ ac_dest=`echo "$ac_file" | sed 's,:.*,,'`
+ ac_source=`echo "$ac_file" | sed 's,[^:]*:,,'`
+ ac_dir=`(dirname "$ac_dest") 2>/dev/null ||
+$as_expr X"$ac_dest" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+ X"$ac_dest" : 'X\(//\)[^/]' \| \
+ X"$ac_dest" : 'X\(//\)$' \| \
+ X"$ac_dest" : 'X\(/\)' \| \
+ . : '\(.\)' 2>/dev/null ||
+echo X"$ac_dest" |
+ sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
+ /^X\(\/\/\)[^/].*/{ s//\1/; q; }
+ /^X\(\/\/\)$/{ s//\1/; q; }
+ /^X\(\/\).*/{ s//\1/; q; }
+ s/.*/./; q'`
+ { if $as_mkdir_p; then
+ mkdir -p "$ac_dir"
+ else
+ as_dir="$ac_dir"
+ as_dirs=
+ while test ! -d "$as_dir"; do
+ as_dirs="$as_dir $as_dirs"
+ as_dir=`(dirname "$as_dir") 2>/dev/null ||
+$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \
+ X"$as_dir" : 'X\(//\)[^/]' \| \
+ X"$as_dir" : 'X\(//\)$' \| \
+ X"$as_dir" : 'X\(/\)' \| \
+ . : '\(.\)' 2>/dev/null ||
+echo X"$as_dir" |
+ sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/; q; }
+ /^X\(\/\/\)[^/].*/{ s//\1/; q; }
+ /^X\(\/\/\)$/{ s//\1/; q; }
+ /^X\(\/\).*/{ s//\1/; q; }
+ s/.*/./; q'`
+ done
+ test ! -n "$as_dirs" || mkdir $as_dirs
+ fi || { { echo "$as_me:$LINENO: error: cannot create directory \"$ac_dir\"" >&5
+echo "$as_me: error: cannot create directory \"$ac_dir\"" >&2;}
+ { (exit 1); exit 1; }; }; }
+
+ ac_builddir=.
+
+if test "$ac_dir" != .; then
+ ac_dir_suffix=/`echo "$ac_dir" | sed 's,^\.[\\/],,'`
+ # A "../" for each directory in $ac_dir_suffix.
+ ac_top_builddir=`echo "$ac_dir_suffix" | sed 's,/[^\\/]*,../,g'`
+else
+ ac_dir_suffix= ac_top_builddir=
+fi
+
+case $srcdir in
+ .) # No --srcdir option. We are building in place.
+ ac_srcdir=.
+ if test -z "$ac_top_builddir"; then
+ ac_top_srcdir=.
+ else
+ ac_top_srcdir=`echo $ac_top_builddir | sed 's,/$,,'`
+ fi ;;
+ [\\/]* | ?:[\\/]* ) # Absolute path.
+ ac_srcdir=$srcdir$ac_dir_suffix;
+ ac_top_srcdir=$srcdir ;;
+ *) # Relative path.
+ ac_srcdir=$ac_top_builddir$srcdir$ac_dir_suffix
+ ac_top_srcdir=$ac_top_builddir$srcdir ;;
+esac
+
+# Do not use `cd foo && pwd` to compute absolute paths, because
+# the directories may not exist.
+case `pwd` in
+.) ac_abs_builddir="$ac_dir";;
+*)
+ case "$ac_dir" in
+ .) ac_abs_builddir=`pwd`;;
+ [\\/]* | ?:[\\/]* ) ac_abs_builddir="$ac_dir";;
+ *) ac_abs_builddir=`pwd`/"$ac_dir";;
+ esac;;
+esac
+case $ac_abs_builddir in
+.) ac_abs_top_builddir=${ac_top_builddir}.;;
+*)
+ case ${ac_top_builddir}. in
+ .) ac_abs_top_builddir=$ac_abs_builddir;;
+ [\\/]* | ?:[\\/]* ) ac_abs_top_builddir=${ac_top_builddir}.;;
+ *) ac_abs_top_builddir=$ac_abs_builddir/${ac_top_builddir}.;;
+ esac;;
+esac
+case $ac_abs_builddir in
+.) ac_abs_srcdir=$ac_srcdir;;
+*)
+ case $ac_srcdir in
+ .) ac_abs_srcdir=$ac_abs_builddir;;
+ [\\/]* | ?:[\\/]* ) ac_abs_srcdir=$ac_srcdir;;
+ *) ac_abs_srcdir=$ac_abs_builddir/$ac_srcdir;;
+ esac;;
+esac
+case $ac_abs_builddir in
+.) ac_abs_top_srcdir=$ac_top_srcdir;;
+*)
+ case $ac_top_srcdir in
+ .) ac_abs_top_srcdir=$ac_abs_builddir;;
+ [\\/]* | ?:[\\/]* ) ac_abs_top_srcdir=$ac_top_srcdir;;
+ *) ac_abs_top_srcdir=$ac_abs_builddir/$ac_top_srcdir;;
+ esac;;
+esac
+
+
+ { echo "$as_me:$LINENO: executing $ac_dest commands" >&5
+echo "$as_me: executing $ac_dest commands" >&6;}
+ case $ac_dest in
+ Makefile ) echo "Merging Makefile.sim+Make-common.sim into Makefile ..."
+ rm -f Makesim1.tmp Makesim2.tmp Makefile
+ sed -n -e '/^## COMMON_PRE_/,/^## End COMMON_PRE_/ p' <Make-common.sim >Makesim1.tmp
+ sed -n -e '/^## COMMON_POST_/,/^## End COMMON_POST_/ p' <Make-common.sim >Makesim2.tmp
+ sed -e '/^## COMMON_PRE_/ r Makesim1.tmp' \
+ -e '/^## COMMON_POST_/ r Makesim2.tmp' \
+ <Makefile.sim >Makefile
+ rm -f Makefile.sim Make-common.sim Makesim1.tmp Makesim2.tmp
+ ;;
+ stamp-h ) echo > stamp-h ;;
+ esac
+done
+_ACEOF
+
+cat >>$CONFIG_STATUS <<\_ACEOF
+
+{ (exit 0); exit 0; }
+_ACEOF
+chmod +x $CONFIG_STATUS
+ac_clean_files=$ac_clean_files_save
+
+
+# configure is writing to config.log, and then calls config.status.
+# config.status does its own redirection, appending to config.log.
+# Unfortunately, on DOS this fails, as config.log is still kept open
+# by configure, so config.status won't be able to write to it; its
+# output is simply discarded. So we exec the FD to /dev/null,
+# effectively closing config.log, so it can be properly (re)opened and
+# appended to by config.status. When coming back to configure, we
+# need to make the FD available again.
+if test "$no_create" != yes; then
+ ac_cs_success=:
+ ac_config_status_args=
+ test "$silent" = yes &&
+ ac_config_status_args="$ac_config_status_args --quiet"
+ exec 5>/dev/null
+ $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false
+ exec 5>>config.log
+ # Use ||, not &&, to avoid exiting from the if with $? = 1, which
+ # would make configure fail if this is the last instruction.
+ $ac_cs_success || { (exit 1); exit 1; }
+fi
+
+
--- /dev/null
+dnl Process this file with autoconf to produce a configure script.
+AC_PREREQ(2.59)dnl
+AC_INIT(Makefile.in)
+AC_CONFIG_HEADER(config.h:config.in)
+
+sinclude(../common/aclocal.m4)
+
+# Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around
+# it by inlining the macro's contents.
+sinclude(../common/common.m4)
+
+SIM_AC_OPTION_ALIGNMENT(NONSTRICT_ALIGNMENT)
+SIM_AC_OPTION_HOSTENDIAN
+SIM_AC_OPTION_SCACHE(16384)
+
+# The default model shouldn't matter as long as there's a BFD.
+SIM_AC_OPTION_DEFAULT_MODEL(crisv32)
+SIM_AC_OPTION_ENVIRONMENT
+SIM_AC_OPTION_INLINE()
+SIM_AC_OPTION_CGEN_MAINT
+
+SIM_AC_OUTPUT
--- /dev/null
+/* Simulator CPU header for cris.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2004 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef CRIS_CPUALL_H
+#define CRIS_CPUALL_H
+
+/* Include files for each cpu family. */
+
+#ifdef WANT_CPU_CRISV0F
+#include "engv0.h"
+#include "cgen-engine.h"
+#include "cpuv0.h"
+#include "decodev0.h"
+#endif
+
+#ifdef WANT_CPU_CRISV3F
+#include "engv3.h"
+#include "cgen-engine.h"
+#include "cpuv3.h"
+#include "decodev3.h"
+#endif
+
+#ifdef WANT_CPU_CRISV8F
+#include "engv8.h"
+#include "cgen-engine.h"
+#include "cpuv8.h"
+#include "decodev8.h"
+#endif
+
+#ifdef WANT_CPU_CRISV10F
+#include "engv10.h"
+#include "cgen-engine.h"
+#include "cpuv10.h"
+#include "decodev10.h"
+#endif
+
+#ifdef WANT_CPU_CRISV32F
+#include "engv32.h"
+#include "cgen-engine.h"
+#include "cpuv32.h"
+#include "decodev32.h"
+#endif
+
+extern const MACH crisv10_mach;
+extern const MACH crisv32_mach;
+
+#ifndef WANT_CPU
+/* The ARGBUF struct. */
+struct argbuf {
+ /* These are the baseclass definitions. */
+ IADDR addr;
+ const IDESC *idesc;
+ char trace_p;
+ char profile_p;
+ /* ??? Temporary hack for skip insns. */
+ char skip_count;
+ char unused;
+ /* cpu specific data follows */
+};
+#endif
+
+#ifndef WANT_CPU
+/* A cached insn.
+
+ ??? SCACHE used to contain more than just argbuf. We could delete the
+ type entirely and always just use ARGBUF, but for future concerns and as
+ a level of abstraction it is left in. */
+
+struct scache {
+ struct argbuf argbuf;
+};
+#endif
+
+#endif /* CRIS_CPUALL_H */
--- /dev/null
+/* Misc. support for CPU family crisv10f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2004 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU crisv10f
+#define WANT_CPU_CRISV10F
+
+#include "sim-main.h"
+#include "cgen-ops.h"
+
+/* Get the value of h-v32-non-v32. */
+
+BI
+crisv10f_h_v32_non_v32_get (SIM_CPU *current_cpu)
+{
+ return GET_H_V32_NON_V32 ();
+}
+
+/* Set a value for h-v32-non-v32. */
+
+void
+crisv10f_h_v32_non_v32_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_V32_NON_V32 (newval);
+}
+
+/* Get the value of h-pc. */
+
+USI
+crisv10f_h_pc_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_pc);
+}
+
+/* Set a value for h-pc. */
+
+void
+crisv10f_h_pc_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_PC (newval);
+}
+
+/* Get the value of h-gr. */
+
+SI
+crisv10f_h_gr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_GR (regno);
+}
+
+/* Set a value for h-gr. */
+
+void
+crisv10f_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_GR (regno, newval);
+}
+
+/* Get the value of h-gr-pc. */
+
+SI
+crisv10f_h_gr_pc_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_GR_PC (regno);
+}
+
+/* Set a value for h-gr-pc. */
+
+void
+crisv10f_h_gr_pc_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_GR_PC (regno, newval);
+}
+
+/* Get the value of h-gr-real-pc. */
+
+SI
+crisv10f_h_gr_real_pc_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return CPU (h_gr_real_pc[regno]);
+}
+
+/* Set a value for h-gr-real-pc. */
+
+void
+crisv10f_h_gr_real_pc_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ CPU (h_gr_real_pc[regno]) = newval;
+}
+
+/* Get the value of h-raw-gr-pc. */
+
+SI
+crisv10f_h_raw_gr_pc_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_RAW_GR_PC (regno);
+}
+
+/* Set a value for h-raw-gr-pc. */
+
+void
+crisv10f_h_raw_gr_pc_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_RAW_GR_PC (regno, newval);
+}
+
+/* Get the value of h-sr. */
+
+SI
+crisv10f_h_sr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_SR (regno);
+}
+
+/* Set a value for h-sr. */
+
+void
+crisv10f_h_sr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_SR (regno, newval);
+}
+
+/* Get the value of h-sr-v10. */
+
+SI
+crisv10f_h_sr_v10_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_SR_V10 (regno);
+}
+
+/* Set a value for h-sr-v10. */
+
+void
+crisv10f_h_sr_v10_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_SR_V10 (regno, newval);
+}
+
+/* Get the value of h-cbit. */
+
+BI
+crisv10f_h_cbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_cbit);
+}
+
+/* Set a value for h-cbit. */
+
+void
+crisv10f_h_cbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_cbit) = newval;
+}
+
+/* Get the value of h-cbit-move. */
+
+BI
+crisv10f_h_cbit_move_get (SIM_CPU *current_cpu)
+{
+ return GET_H_CBIT_MOVE ();
+}
+
+/* Set a value for h-cbit-move. */
+
+void
+crisv10f_h_cbit_move_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_CBIT_MOVE (newval);
+}
+
+/* Get the value of h-cbit-move-pre-v32. */
+
+BI
+crisv10f_h_cbit_move_pre_v32_get (SIM_CPU *current_cpu)
+{
+ return GET_H_CBIT_MOVE_PRE_V32 ();
+}
+
+/* Set a value for h-cbit-move-pre-v32. */
+
+void
+crisv10f_h_cbit_move_pre_v32_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_CBIT_MOVE_PRE_V32 (newval);
+}
+
+/* Get the value of h-vbit. */
+
+BI
+crisv10f_h_vbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_vbit);
+}
+
+/* Set a value for h-vbit. */
+
+void
+crisv10f_h_vbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_vbit) = newval;
+}
+
+/* Get the value of h-vbit-move. */
+
+BI
+crisv10f_h_vbit_move_get (SIM_CPU *current_cpu)
+{
+ return GET_H_VBIT_MOVE ();
+}
+
+/* Set a value for h-vbit-move. */
+
+void
+crisv10f_h_vbit_move_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_VBIT_MOVE (newval);
+}
+
+/* Get the value of h-vbit-move-pre-v32. */
+
+BI
+crisv10f_h_vbit_move_pre_v32_get (SIM_CPU *current_cpu)
+{
+ return GET_H_VBIT_MOVE_PRE_V32 ();
+}
+
+/* Set a value for h-vbit-move-pre-v32. */
+
+void
+crisv10f_h_vbit_move_pre_v32_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_VBIT_MOVE_PRE_V32 (newval);
+}
+
+/* Get the value of h-zbit. */
+
+BI
+crisv10f_h_zbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_zbit);
+}
+
+/* Set a value for h-zbit. */
+
+void
+crisv10f_h_zbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_zbit) = newval;
+}
+
+/* Get the value of h-zbit-move. */
+
+BI
+crisv10f_h_zbit_move_get (SIM_CPU *current_cpu)
+{
+ return GET_H_ZBIT_MOVE ();
+}
+
+/* Set a value for h-zbit-move. */
+
+void
+crisv10f_h_zbit_move_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_ZBIT_MOVE (newval);
+}
+
+/* Get the value of h-zbit-move-pre-v32. */
+
+BI
+crisv10f_h_zbit_move_pre_v32_get (SIM_CPU *current_cpu)
+{
+ return GET_H_ZBIT_MOVE_PRE_V32 ();
+}
+
+/* Set a value for h-zbit-move-pre-v32. */
+
+void
+crisv10f_h_zbit_move_pre_v32_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_ZBIT_MOVE_PRE_V32 (newval);
+}
+
+/* Get the value of h-nbit. */
+
+BI
+crisv10f_h_nbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_nbit);
+}
+
+/* Set a value for h-nbit. */
+
+void
+crisv10f_h_nbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_nbit) = newval;
+}
+
+/* Get the value of h-nbit-move. */
+
+BI
+crisv10f_h_nbit_move_get (SIM_CPU *current_cpu)
+{
+ return GET_H_NBIT_MOVE ();
+}
+
+/* Set a value for h-nbit-move. */
+
+void
+crisv10f_h_nbit_move_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_NBIT_MOVE (newval);
+}
+
+/* Get the value of h-nbit-move-pre-v32. */
+
+BI
+crisv10f_h_nbit_move_pre_v32_get (SIM_CPU *current_cpu)
+{
+ return GET_H_NBIT_MOVE_PRE_V32 ();
+}
+
+/* Set a value for h-nbit-move-pre-v32. */
+
+void
+crisv10f_h_nbit_move_pre_v32_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_NBIT_MOVE_PRE_V32 (newval);
+}
+
+/* Get the value of h-xbit. */
+
+BI
+crisv10f_h_xbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_xbit);
+}
+
+/* Set a value for h-xbit. */
+
+void
+crisv10f_h_xbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_xbit) = newval;
+}
+
+/* Get the value of h-ibit. */
+
+BI
+crisv10f_h_ibit_get (SIM_CPU *current_cpu)
+{
+ return GET_H_IBIT ();
+}
+
+/* Set a value for h-ibit. */
+
+void
+crisv10f_h_ibit_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_IBIT (newval);
+}
+
+/* Get the value of h-ibit-pre-v32. */
+
+BI
+crisv10f_h_ibit_pre_v32_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_ibit_pre_v32);
+}
+
+/* Set a value for h-ibit-pre-v32. */
+
+void
+crisv10f_h_ibit_pre_v32_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_ibit_pre_v32) = newval;
+}
+
+/* Get the value of h-pbit. */
+
+BI
+crisv10f_h_pbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_pbit);
+}
+
+/* Set a value for h-pbit. */
+
+void
+crisv10f_h_pbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_pbit) = newval;
+}
+
+/* Get the value of h-ubit. */
+
+BI
+crisv10f_h_ubit_get (SIM_CPU *current_cpu)
+{
+ return GET_H_UBIT ();
+}
+
+/* Set a value for h-ubit. */
+
+void
+crisv10f_h_ubit_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_UBIT (newval);
+}
+
+/* Get the value of h-ubit-pre-v32. */
+
+BI
+crisv10f_h_ubit_pre_v32_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_ubit_pre_v32);
+}
+
+/* Set a value for h-ubit-pre-v32. */
+
+void
+crisv10f_h_ubit_pre_v32_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_ubit_pre_v32) = newval;
+}
+
+/* Get the value of h-insn-prefixed-p. */
+
+BI
+crisv10f_h_insn_prefixed_p_get (SIM_CPU *current_cpu)
+{
+ return GET_H_INSN_PREFIXED_P ();
+}
+
+/* Set a value for h-insn-prefixed-p. */
+
+void
+crisv10f_h_insn_prefixed_p_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_INSN_PREFIXED_P (newval);
+}
+
+/* Get the value of h-insn-prefixed-p-pre-v32. */
+
+BI
+crisv10f_h_insn_prefixed_p_pre_v32_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_insn_prefixed_p_pre_v32);
+}
+
+/* Set a value for h-insn-prefixed-p-pre-v32. */
+
+void
+crisv10f_h_insn_prefixed_p_pre_v32_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_insn_prefixed_p_pre_v32) = newval;
+}
+
+/* Get the value of h-prefixreg-pre-v32. */
+
+SI
+crisv10f_h_prefixreg_pre_v32_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_prefixreg_pre_v32);
+}
+
+/* Set a value for h-prefixreg-pre-v32. */
+
+void
+crisv10f_h_prefixreg_pre_v32_set (SIM_CPU *current_cpu, SI newval)
+{
+ CPU (h_prefixreg_pre_v32) = newval;
+}
+
+/* Record trace results for INSN. */
+
+void
+crisv10f_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
+ int *indices, TRACE_RECORD *tr)
+{
+}
--- /dev/null
+/* CPU family header for crisv10f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2004 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef CPU_CRISV10F_H
+#define CPU_CRISV10F_H
+
+/* Maximum number of instructions that are fetched at a time.
+ This is for LIW type instructions sets (e.g. m32r). */
+#define MAX_LIW_INSNS 1
+
+/* Maximum number of instructions that can be executed in parallel. */
+#define MAX_PARALLEL_INSNS 1
+
+/* CPU state information. */
+typedef struct {
+ /* Hardware elements. */
+ struct {
+ /* program counter */
+ USI h_pc;
+#define GET_H_PC() CPU (h_pc)
+#define SET_H_PC(x) \
+do { \
+CPU (h_pc) = ANDSI ((x), (~ (1)));\
+;} while (0)
+ /* General purpose registers */
+ SI h_gr_real_pc[16];
+#define GET_H_GR_REAL_PC(a1) CPU (h_gr_real_pc)[a1]
+#define SET_H_GR_REAL_PC(a1, x) (CPU (h_gr_real_pc)[a1] = (x))
+ /* Special registers for v10 */
+ SI h_sr_v10[16];
+#define GET_H_SR_V10(index) (ORIF (ORIF (((index) == (((UINT) 0))), ((index) == (((UINT) 4)))), ((index) == (((UINT) 8))))) ? (0) : (((index) == (((UINT) 1)))) ? (10) : (ORIF (((index) == (((UINT) 5))), ((index) == (((UINT) 13))))) ? (ORSI (ANDSI (CPU (h_sr_v10[((UINT) 5)]), 0xffffff00), ORSI (ZEXTBISI (CPU (h_cbit)), ORSI (SLLSI (ZEXTBISI (CPU (h_vbit)), 1), ORSI (SLLSI (ZEXTBISI (CPU (h_zbit)), 2), ORSI (SLLSI (ZEXTBISI (CPU (h_nbit)), 3), ORSI (SLLSI (ZEXTBISI (CPU (h_xbit)), 4), ORSI (SLLSI (ZEXTBISI (GET_H_IBIT ()), 5), ORSI (SLLSI (ZEXTBISI (GET_H_UBIT ()), 6), ORSI (SLLSI (ZEXTBISI (CPU (h_pbit)), 7), 0)))))))))) : (CPU (h_sr_v10[index]))
+#define SET_H_SR_V10(index, x) \
+do { \
+if (ORIF (ORIF ((((index)) == (((UINT) 0))), (((index)) == (((UINT) 4)))), ORIF ((((index)) == (((UINT) 8))), (((index)) == (((UINT) 1)))))) {\
+((void) 0); /*nop*/\
+}\
+ else if (ORIF ((((index)) == (((UINT) 5))), (((index)) == (((UINT) 13))))) {\
+{\
+CPU (h_cbit) = ((NESI (ANDSI ((x), ((1) << (0))), 0)) ? (1) : (0));\
+CPU (h_vbit) = ((NESI (ANDSI ((x), ((1) << (1))), 0)) ? (1) : (0));\
+CPU (h_zbit) = ((NESI (ANDSI ((x), ((1) << (2))), 0)) ? (1) : (0));\
+CPU (h_nbit) = ((NESI (ANDSI ((x), ((1) << (3))), 0)) ? (1) : (0));\
+CPU (h_xbit) = ((NESI (ANDSI ((x), ((1) << (4))), 0)) ? (1) : (0));\
+SET_H_IBIT (((NESI (ANDSI ((x), ((1) << (5))), 0)) ? (1) : (0)));\
+SET_H_UBIT (((NESI (ANDSI ((x), ((1) << (6))), 0)) ? (1) : (0)));\
+CPU (h_pbit) = ((NESI (ANDSI ((x), ((1) << (7))), 0)) ? (1) : (0));\
+CPU (h_sr_v10[((UINT) 5)]) = (x);\
+CPU (h_sr_v10[((UINT) 13)]) = (x);\
+}\
+}\
+ else {\
+CPU (h_sr_v10[(index)]) = (x);\
+}\
+;} while (0)
+ /* carry bit */
+ BI h_cbit;
+#define GET_H_CBIT() CPU (h_cbit)
+#define SET_H_CBIT(x) (CPU (h_cbit) = (x))
+ /* overflow bit */
+ BI h_vbit;
+#define GET_H_VBIT() CPU (h_vbit)
+#define SET_H_VBIT(x) (CPU (h_vbit) = (x))
+ /* zero bit */
+ BI h_zbit;
+#define GET_H_ZBIT() CPU (h_zbit)
+#define SET_H_ZBIT(x) (CPU (h_zbit) = (x))
+ /* sign bit */
+ BI h_nbit;
+#define GET_H_NBIT() CPU (h_nbit)
+#define SET_H_NBIT(x) (CPU (h_nbit) = (x))
+ /* extended-arithmetic bit */
+ BI h_xbit;
+#define GET_H_XBIT() CPU (h_xbit)
+#define SET_H_XBIT(x) (CPU (h_xbit) = (x))
+ /* interrupt-enable bit */
+ BI h_ibit_pre_v32;
+#define GET_H_IBIT_PRE_V32() CPU (h_ibit_pre_v32)
+#define SET_H_IBIT_PRE_V32(x) (CPU (h_ibit_pre_v32) = (x))
+ /* sequence-broken bit */
+ BI h_pbit;
+#define GET_H_PBIT() CPU (h_pbit)
+#define SET_H_PBIT(x) (CPU (h_pbit) = (x))
+ /* user mode bit */
+ BI h_ubit_pre_v32;
+#define GET_H_UBIT_PRE_V32() CPU (h_ubit_pre_v32)
+#define SET_H_UBIT_PRE_V32(x) (CPU (h_ubit_pre_v32) = (x))
+ /* instruction-is-prefixed bit */
+ BI h_insn_prefixed_p_pre_v32;
+#define GET_H_INSN_PREFIXED_P_PRE_V32() CPU (h_insn_prefixed_p_pre_v32)
+#define SET_H_INSN_PREFIXED_P_PRE_V32(x) (CPU (h_insn_prefixed_p_pre_v32) = (x))
+ /* Prefix-address register */
+ SI h_prefixreg_pre_v32;
+#define GET_H_PREFIXREG_PRE_V32() CPU (h_prefixreg_pre_v32)
+#define SET_H_PREFIXREG_PRE_V32(x) (CPU (h_prefixreg_pre_v32) = (x))
+ } hardware;
+#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
+} CRISV10F_CPU_DATA;
+
+/* Virtual regs. */
+
+#define GET_H_V32_NON_V32() 0
+#define SET_H_V32_NON_V32(x) \
+do { \
+cgen_rtx_error (current_cpu, "Can't set h-v32");\
+;} while (0)
+#define GET_H_GR(index) GET_H_GR_PC (index)
+#define SET_H_GR(index, x) \
+do { \
+SET_H_GR_PC ((index), (x));\
+;} while (0)
+#define GET_H_GR_PC(index) ((((index) == (15))) ? ((cgen_rtx_error (current_cpu, "General register read of PC is not implemented."), 0)) : (CPU (h_gr_real_pc[index])))
+#define SET_H_GR_PC(index, x) \
+do { \
+{\
+if ((((index)) == (15))) {\
+cgen_rtx_error (current_cpu, "General register write to PC is not implemented.");\
+}\
+CPU (h_gr_real_pc[(index)]) = (x);\
+}\
+;} while (0)
+#define GET_H_RAW_GR_PC(index) CPU (h_gr_real_pc[index])
+#define SET_H_RAW_GR_PC(index, x) \
+do { \
+CPU (h_gr_real_pc[(index)]) = (x);\
+;} while (0)
+#define GET_H_SR(index) GET_H_SR_V10 (index)
+#define SET_H_SR(index, x) \
+do { \
+SET_H_SR_V10 ((index), (x));\
+;} while (0)
+#define GET_H_CBIT_MOVE() GET_H_CBIT_MOVE_PRE_V32 ()
+#define SET_H_CBIT_MOVE(x) \
+do { \
+SET_H_CBIT_MOVE_PRE_V32 ((x));\
+;} while (0)
+#define GET_H_CBIT_MOVE_PRE_V32() CPU (h_cbit)
+#define SET_H_CBIT_MOVE_PRE_V32(x) \
+do { \
+CPU (h_cbit) = (x);\
+;} while (0)
+#define GET_H_VBIT_MOVE() GET_H_VBIT_MOVE_PRE_V32 ()
+#define SET_H_VBIT_MOVE(x) \
+do { \
+SET_H_VBIT_MOVE_PRE_V32 ((x));\
+;} while (0)
+#define GET_H_VBIT_MOVE_PRE_V32() CPU (h_vbit)
+#define SET_H_VBIT_MOVE_PRE_V32(x) \
+do { \
+CPU (h_vbit) = (x);\
+;} while (0)
+#define GET_H_ZBIT_MOVE() GET_H_ZBIT_MOVE_PRE_V32 ()
+#define SET_H_ZBIT_MOVE(x) \
+do { \
+SET_H_ZBIT_MOVE_PRE_V32 ((x));\
+;} while (0)
+#define GET_H_ZBIT_MOVE_PRE_V32() CPU (h_zbit)
+#define SET_H_ZBIT_MOVE_PRE_V32(x) \
+do { \
+CPU (h_zbit) = (x);\
+;} while (0)
+#define GET_H_NBIT_MOVE() GET_H_NBIT_MOVE_PRE_V32 ()
+#define SET_H_NBIT_MOVE(x) \
+do { \
+SET_H_NBIT_MOVE_PRE_V32 ((x));\
+;} while (0)
+#define GET_H_NBIT_MOVE_PRE_V32() CPU (h_nbit)
+#define SET_H_NBIT_MOVE_PRE_V32(x) \
+do { \
+CPU (h_nbit) = (x);\
+;} while (0)
+#define GET_H_IBIT() CPU (h_ibit_pre_v32)
+#define SET_H_IBIT(x) \
+do { \
+CPU (h_ibit_pre_v32) = (x);\
+;} while (0)
+#define GET_H_UBIT() CPU (h_ubit_pre_v32)
+#define SET_H_UBIT(x) \
+do { \
+CPU (h_ubit_pre_v32) = (x);\
+;} while (0)
+#define GET_H_INSN_PREFIXED_P() CPU (h_insn_prefixed_p_pre_v32)
+#define SET_H_INSN_PREFIXED_P(x) \
+do { \
+CPU (h_insn_prefixed_p_pre_v32) = (x);\
+;} while (0)
+
+/* Cover fns for register access. */
+BI crisv10f_h_v32_non_v32_get (SIM_CPU *);
+void crisv10f_h_v32_non_v32_set (SIM_CPU *, BI);
+USI crisv10f_h_pc_get (SIM_CPU *);
+void crisv10f_h_pc_set (SIM_CPU *, USI);
+SI crisv10f_h_gr_get (SIM_CPU *, UINT);
+void crisv10f_h_gr_set (SIM_CPU *, UINT, SI);
+SI crisv10f_h_gr_pc_get (SIM_CPU *, UINT);
+void crisv10f_h_gr_pc_set (SIM_CPU *, UINT, SI);
+SI crisv10f_h_gr_real_pc_get (SIM_CPU *, UINT);
+void crisv10f_h_gr_real_pc_set (SIM_CPU *, UINT, SI);
+SI crisv10f_h_raw_gr_pc_get (SIM_CPU *, UINT);
+void crisv10f_h_raw_gr_pc_set (SIM_CPU *, UINT, SI);
+SI crisv10f_h_sr_get (SIM_CPU *, UINT);
+void crisv10f_h_sr_set (SIM_CPU *, UINT, SI);
+SI crisv10f_h_sr_v10_get (SIM_CPU *, UINT);
+void crisv10f_h_sr_v10_set (SIM_CPU *, UINT, SI);
+BI crisv10f_h_cbit_get (SIM_CPU *);
+void crisv10f_h_cbit_set (SIM_CPU *, BI);
+BI crisv10f_h_cbit_move_get (SIM_CPU *);
+void crisv10f_h_cbit_move_set (SIM_CPU *, BI);
+BI crisv10f_h_cbit_move_pre_v32_get (SIM_CPU *);
+void crisv10f_h_cbit_move_pre_v32_set (SIM_CPU *, BI);
+BI crisv10f_h_vbit_get (SIM_CPU *);
+void crisv10f_h_vbit_set (SIM_CPU *, BI);
+BI crisv10f_h_vbit_move_get (SIM_CPU *);
+void crisv10f_h_vbit_move_set (SIM_CPU *, BI);
+BI crisv10f_h_vbit_move_pre_v32_get (SIM_CPU *);
+void crisv10f_h_vbit_move_pre_v32_set (SIM_CPU *, BI);
+BI crisv10f_h_zbit_get (SIM_CPU *);
+void crisv10f_h_zbit_set (SIM_CPU *, BI);
+BI crisv10f_h_zbit_move_get (SIM_CPU *);
+void crisv10f_h_zbit_move_set (SIM_CPU *, BI);
+BI crisv10f_h_zbit_move_pre_v32_get (SIM_CPU *);
+void crisv10f_h_zbit_move_pre_v32_set (SIM_CPU *, BI);
+BI crisv10f_h_nbit_get (SIM_CPU *);
+void crisv10f_h_nbit_set (SIM_CPU *, BI);
+BI crisv10f_h_nbit_move_get (SIM_CPU *);
+void crisv10f_h_nbit_move_set (SIM_CPU *, BI);
+BI crisv10f_h_nbit_move_pre_v32_get (SIM_CPU *);
+void crisv10f_h_nbit_move_pre_v32_set (SIM_CPU *, BI);
+BI crisv10f_h_xbit_get (SIM_CPU *);
+void crisv10f_h_xbit_set (SIM_CPU *, BI);
+BI crisv10f_h_ibit_get (SIM_CPU *);
+void crisv10f_h_ibit_set (SIM_CPU *, BI);
+BI crisv10f_h_ibit_pre_v32_get (SIM_CPU *);
+void crisv10f_h_ibit_pre_v32_set (SIM_CPU *, BI);
+BI crisv10f_h_pbit_get (SIM_CPU *);
+void crisv10f_h_pbit_set (SIM_CPU *, BI);
+BI crisv10f_h_ubit_get (SIM_CPU *);
+void crisv10f_h_ubit_set (SIM_CPU *, BI);
+BI crisv10f_h_ubit_pre_v32_get (SIM_CPU *);
+void crisv10f_h_ubit_pre_v32_set (SIM_CPU *, BI);
+BI crisv10f_h_insn_prefixed_p_get (SIM_CPU *);
+void crisv10f_h_insn_prefixed_p_set (SIM_CPU *, BI);
+BI crisv10f_h_insn_prefixed_p_pre_v32_get (SIM_CPU *);
+void crisv10f_h_insn_prefixed_p_pre_v32_set (SIM_CPU *, BI);
+SI crisv10f_h_prefixreg_pre_v32_get (SIM_CPU *);
+void crisv10f_h_prefixreg_pre_v32_set (SIM_CPU *, SI);
+
+/* These must be hand-written. */
+extern CPUREG_FETCH_FN crisv10f_fetch_register;
+extern CPUREG_STORE_FN crisv10f_store_register;
+
+typedef struct {
+ int empty;
+} MODEL_CRISV10_DATA;
+
+/* Instruction argument buffer. */
+
+union sem_fields {
+ struct { /* no operands */
+ int empty;
+ } fmt_empty;
+ struct { /* */
+ UINT f_u4;
+ } sfmt_break;
+ struct { /* */
+ UINT f_dstsrc;
+ } sfmt_setf;
+ struct { /* */
+ IADDR i_o_word_pcrel;
+ UINT f_operand2;
+ } sfmt_bcc_w;
+ struct { /* */
+ IADDR i_o_pcrel;
+ UINT f_operand2;
+ } sfmt_bcc_b;
+ struct { /* */
+ INT f_s8;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ } sfmt_addoq;
+ struct { /* */
+ INT f_indir_pc__dword;
+ UINT f_operand2;
+ unsigned char out_Pd;
+ } sfmt_move_c_sprv10_p8;
+ struct { /* */
+ INT f_indir_pc__word;
+ UINT f_operand2;
+ unsigned char out_Pd;
+ } sfmt_move_c_sprv10_p4;
+ struct { /* */
+ INT f_indir_pc__byte;
+ UINT f_operand2;
+ unsigned char out_Pd;
+ } sfmt_move_c_sprv10_p0;
+ struct { /* */
+ INT f_s6;
+ UINT f_operand2;
+ unsigned char out_Rd;
+ } sfmt_moveq;
+ struct { /* */
+ INT f_indir_pc__dword;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ unsigned char out_Rd;
+ } sfmt_bound_cd;
+ struct { /* */
+ INT f_indir_pc__word;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ unsigned char out_Rd;
+ } sfmt_bound_cw;
+ struct { /* */
+ INT f_indir_pc__byte;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ unsigned char out_Rd;
+ } sfmt_bound_cb;
+ struct { /* */
+ UINT f_operand2;
+ UINT f_u5;
+ unsigned char in_Rd;
+ unsigned char out_Rd;
+ } sfmt_asrq;
+ struct { /* */
+ INT f_s6;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ unsigned char out_h_gr_SI_index_of__DFLT_Rd;
+ } sfmt_andq;
+ struct { /* */
+ INT f_indir_pc__dword;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ unsigned char out_h_gr_SI_index_of__DFLT_Rd;
+ } sfmt_addcdr;
+ struct { /* */
+ INT f_indir_pc__word;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ unsigned char out_h_gr_SI_index_of__DFLT_Rd;
+ } sfmt_addcwr;
+ struct { /* */
+ INT f_indir_pc__byte;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ unsigned char out_h_gr_SI_index_of__DFLT_Rd;
+ } sfmt_addcbr;
+ struct { /* */
+ UINT f_operand1;
+ UINT f_operand2;
+ unsigned char in_Ps;
+ unsigned char out_h_gr_SI_index_of__DFLT_Rs;
+ } sfmt_move_spr_rv10;
+ struct { /* */
+ UINT f_operand2;
+ UINT f_u6;
+ unsigned char in_Rd;
+ unsigned char out_h_gr_SI_index_of__DFLT_Rd;
+ } sfmt_addq;
+ struct { /* */
+ UINT f_operand1;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ unsigned char in_Rs;
+ unsigned char out_h_gr_SI_index_of__DFLT_Rd;
+ } sfmt_add_b_r;
+ struct { /* */
+ UINT f_operand1;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ unsigned char in_Rs;
+ unsigned char out_Rd;
+ unsigned char out_h_sr_SI_7;
+ } sfmt_muls_b;
+ struct { /* */
+ UINT f_memmode;
+ UINT f_operand1;
+ UINT f_operand2;
+ unsigned char in_Ps;
+ unsigned char in_Rs;
+ unsigned char out_Rs;
+ } sfmt_move_spr_mv10;
+ struct { /* */
+ UINT f_memmode;
+ UINT f_operand1;
+ UINT f_operand2;
+ unsigned char in_Rs;
+ unsigned char out_Pd;
+ unsigned char out_Rs;
+ } sfmt_move_m_sprv10;
+ struct { /* */
+ UINT f_memmode;
+ UINT f_operand1;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ unsigned char in_Rs;
+ unsigned char out_Rd;
+ unsigned char out_Rs;
+ } sfmt_bound_m_b_m;
+ struct { /* */
+ UINT f_memmode;
+ UINT f_operand1;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ unsigned char in_Rs;
+ unsigned char out_Rs;
+ unsigned char out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd;
+ } sfmt_add_m_b_m;
+ struct { /* */
+ UINT f_memmode;
+ UINT f_operand1;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ unsigned char in_Rs;
+ unsigned char out_Rs;
+ unsigned char out_h_gr_SI_0;
+ unsigned char out_h_gr_SI_1;
+ unsigned char out_h_gr_SI_10;
+ unsigned char out_h_gr_SI_11;
+ unsigned char out_h_gr_SI_12;
+ unsigned char out_h_gr_SI_13;
+ unsigned char out_h_gr_SI_14;
+ unsigned char out_h_gr_SI_2;
+ unsigned char out_h_gr_SI_3;
+ unsigned char out_h_gr_SI_4;
+ unsigned char out_h_gr_SI_5;
+ unsigned char out_h_gr_SI_6;
+ unsigned char out_h_gr_SI_7;
+ unsigned char out_h_gr_SI_8;
+ unsigned char out_h_gr_SI_9;
+ } sfmt_movem_m_r;
+ struct { /* */
+ UINT f_memmode;
+ UINT f_operand1;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ unsigned char in_Rs;
+ unsigned char in_h_gr_SI_0;
+ unsigned char in_h_gr_SI_1;
+ unsigned char in_h_gr_SI_10;
+ unsigned char in_h_gr_SI_11;
+ unsigned char in_h_gr_SI_12;
+ unsigned char in_h_gr_SI_13;
+ unsigned char in_h_gr_SI_14;
+ unsigned char in_h_gr_SI_15;
+ unsigned char in_h_gr_SI_2;
+ unsigned char in_h_gr_SI_3;
+ unsigned char in_h_gr_SI_4;
+ unsigned char in_h_gr_SI_5;
+ unsigned char in_h_gr_SI_6;
+ unsigned char in_h_gr_SI_7;
+ unsigned char in_h_gr_SI_8;
+ unsigned char in_h_gr_SI_9;
+ unsigned char out_Rs;
+ } sfmt_movem_r_m;
+#if WITH_SCACHE_PBB
+ /* Writeback handler. */
+ struct {
+ /* Pointer to argbuf entry for insn whose results need writing back. */
+ const struct argbuf *abuf;
+ } write;
+ /* x-before handler */
+ struct {
+ /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
+ int first_p;
+ } before;
+ /* x-after handler */
+ struct {
+ int empty;
+ } after;
+ /* This entry is used to terminate each pbb. */
+ struct {
+ /* Number of insns in pbb. */
+ int insn_count;
+ /* Next pbb to execute. */
+ SCACHE *next;
+ SCACHE *branch_target;
+ } chain;
+#endif
+};
+
+/* The ARGBUF struct. */
+struct argbuf {
+ /* These are the baseclass definitions. */
+ IADDR addr;
+ const IDESC *idesc;
+ char trace_p;
+ char profile_p;
+ /* ??? Temporary hack for skip insns. */
+ char skip_count;
+ char unused;
+ /* cpu specific data follows */
+ union sem semantic;
+ int written;
+ union sem_fields fields;
+};
+
+/* A cached insn.
+
+ ??? SCACHE used to contain more than just argbuf. We could delete the
+ type entirely and always just use ARGBUF, but for future concerns and as
+ a level of abstraction it is left in. */
+
+struct scache {
+ struct argbuf argbuf;
+};
+
+/* Macros to simplify extraction, reading and semantic code.
+ These define and assign the local vars that contain the insn's fields. */
+
+#define EXTRACT_IFMT_EMPTY_VARS \
+ unsigned int length;
+#define EXTRACT_IFMT_EMPTY_CODE \
+ length = 0; \
+
+#define EXTRACT_IFMT_NOP_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ unsigned int length;
+#define EXTRACT_IFMT_NOP_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVE_B_R_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVE_B_R_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVEPCR_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVEPCR_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVEQ_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ INT f_s6; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVEQ_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_s6 = EXTRACT_LSB0_INT (insn, 16, 5, 6); \
+
+#define EXTRACT_IFMT_MOVECBR_VARS \
+ UINT f_operand2; \
+ INT f_indir_pc__byte; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ /* Contents of trailing part of insn. */ \
+ UINT word_1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVECBR_CODE \
+ length = 4; \
+ word_1 = GETIMEMUHI (current_cpu, pc + 2); \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0)); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVECWR_VARS \
+ UINT f_operand2; \
+ INT f_indir_pc__word; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ /* Contents of trailing part of insn. */ \
+ UINT word_1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVECWR_CODE \
+ length = 4; \
+ word_1 = GETIMEMUHI (current_cpu, pc + 2); \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0)); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVECDR_VARS \
+ INT f_indir_pc__dword; \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ /* Contents of trailing part of insn. */ \
+ UINT word_1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVECDR_CODE \
+ length = 6; \
+ word_1 = GETIMEMUSI (current_cpu, pc + 2); \
+ f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVUCBR_VARS \
+ UINT f_operand2; \
+ INT f_indir_pc__byte; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ /* Contents of trailing part of insn. */ \
+ UINT word_1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVUCBR_CODE \
+ length = 4; \
+ word_1 = GETIMEMUHI (current_cpu, pc + 2); \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0)); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVUCWR_VARS \
+ UINT f_operand2; \
+ INT f_indir_pc__word; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ /* Contents of trailing part of insn. */ \
+ UINT word_1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVUCWR_CODE \
+ length = 4; \
+ word_1 = GETIMEMUHI (current_cpu, pc + 2); \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0)); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_ADDQ_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_u6; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADDQ_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_u6 = EXTRACT_LSB0_UINT (insn, 16, 5, 6); \
+
+#define EXTRACT_IFMT_CMP_M_B_M_VARS \
+ UINT f_operand2; \
+ UINT f_membit; \
+ UINT f_memmode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ unsigned int length;
+#define EXTRACT_IFMT_CMP_M_B_M_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVE_R_SPRV10_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVE_R_SPRV10_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVE_SPR_RV10_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVE_SPR_RV10_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_RET_TYPE_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ unsigned int length;
+#define EXTRACT_IFMT_RET_TYPE_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVE_M_SPRV10_VARS \
+ UINT f_operand2; \
+ UINT f_membit; \
+ UINT f_memmode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVE_M_SPRV10_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVE_C_SPRV10_P0_VARS \
+ UINT f_operand2; \
+ INT f_indir_pc__byte; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ /* Contents of trailing part of insn. */ \
+ UINT word_1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVE_C_SPRV10_P0_CODE \
+ length = 4; \
+ word_1 = GETIMEMUHI (current_cpu, pc + 2); \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0)); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVE_C_SPRV10_P4_VARS \
+ UINT f_operand2; \
+ INT f_indir_pc__word; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ /* Contents of trailing part of insn. */ \
+ UINT word_1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVE_C_SPRV10_P4_CODE \
+ length = 4; \
+ word_1 = GETIMEMUHI (current_cpu, pc + 2); \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0)); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVE_C_SPRV10_P8_VARS \
+ INT f_indir_pc__dword; \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ /* Contents of trailing part of insn. */ \
+ UINT word_1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVE_C_SPRV10_P8_CODE \
+ length = 6; \
+ word_1 = GETIMEMUSI (current_cpu, pc + 2); \
+ f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVE_SPR_MV10_VARS \
+ UINT f_operand2; \
+ UINT f_membit; \
+ UINT f_memmode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVE_SPR_MV10_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_SBFS_VARS \
+ UINT f_operand2; \
+ UINT f_membit; \
+ UINT f_memmode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ unsigned int length;
+#define EXTRACT_IFMT_SBFS_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_SWAP_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ unsigned int length;
+#define EXTRACT_IFMT_SWAP_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_ASRQ_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_b5; \
+ UINT f_u5; \
+ unsigned int length;
+#define EXTRACT_IFMT_ASRQ_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_b5 = EXTRACT_LSB0_UINT (insn, 16, 5, 1); \
+ f_u5 = EXTRACT_LSB0_UINT (insn, 16, 4, 5); \
+
+#define EXTRACT_IFMT_SETF_VARS \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand2; \
+ UINT f_operand1; \
+ UINT f_dstsrc; \
+ unsigned int length;
+#define EXTRACT_IFMT_SETF_CODE \
+ length = 2; \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+ f_dstsrc = ((((f_operand1) | (((f_operand2) << (4))))) & (255));\
+
+#define EXTRACT_IFMT_BCC_B_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode_hi; \
+ INT f_disp9_hi; \
+ UINT f_disp9_lo; \
+ INT f_disp9; \
+ unsigned int length;
+#define EXTRACT_IFMT_BCC_B_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
+ f_disp9_hi = EXTRACT_LSB0_INT (insn, 16, 0, 1); \
+ f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \
+{\
+ SI tmp_abslo;\
+ SI tmp_absval;\
+ tmp_abslo = ((f_disp9_lo) << (1));\
+ tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));\
+ f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_NON_V32 ()) ? (0) : (2))));\
+}\
+
+#define EXTRACT_IFMT_BA_B_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode_hi; \
+ INT f_disp9_hi; \
+ UINT f_disp9_lo; \
+ INT f_disp9; \
+ unsigned int length;
+#define EXTRACT_IFMT_BA_B_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
+ f_disp9_hi = EXTRACT_LSB0_INT (insn, 16, 0, 1); \
+ f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \
+{\
+ SI tmp_abslo;\
+ SI tmp_absval;\
+ tmp_abslo = ((f_disp9_lo) << (1));\
+ tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));\
+ f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_NON_V32 ()) ? (0) : (2))));\
+}\
+
+#define EXTRACT_IFMT_BCC_W_VARS \
+ UINT f_operand2; \
+ SI f_indir_pc__word_pcrel; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ /* Contents of trailing part of insn. */ \
+ UINT word_1; \
+ unsigned int length;
+#define EXTRACT_IFMT_BCC_W_CODE \
+ length = 4; \
+ word_1 = GETIMEMUHI (current_cpu, pc + 2); \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_NON_V32 ()) ? (0) : (4)))))); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_BA_W_VARS \
+ UINT f_operand2; \
+ SI f_indir_pc__word_pcrel; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ /* Contents of trailing part of insn. */ \
+ UINT word_1; \
+ unsigned int length;
+#define EXTRACT_IFMT_BA_W_CODE \
+ length = 4; \
+ word_1 = GETIMEMUHI (current_cpu, pc + 2); \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_NON_V32 ()) ? (0) : (4)))))); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_JUMP_C_VARS \
+ INT f_indir_pc__dword; \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ /* Contents of trailing part of insn. */ \
+ UINT word_1; \
+ unsigned int length;
+#define EXTRACT_IFMT_JUMP_C_CODE \
+ length = 6; \
+ word_1 = GETIMEMUSI (current_cpu, pc + 2); \
+ f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_BREAK_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_u4; \
+ unsigned int length;
+#define EXTRACT_IFMT_BREAK_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_u4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_SCC_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ unsigned int length;
+#define EXTRACT_IFMT_SCC_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_ADDOQ_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode_hi; \
+ INT f_s8; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADDOQ_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
+ f_s8 = EXTRACT_LSB0_INT (insn, 16, 7, 8); \
+
+#define EXTRACT_IFMT_BDAPQPC_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode_hi; \
+ INT f_s8; \
+ unsigned int length;
+#define EXTRACT_IFMT_BDAPQPC_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
+ f_s8 = EXTRACT_LSB0_INT (insn, 16, 7, 8); \
+
+/* Collection of various things for the trace handler to use. */
+
+typedef struct trace_record {
+ IADDR pc;
+ /* FIXME:wip */
+} TRACE_RECORD;
+
+#endif /* CPU_CRISV10F_H */
--- /dev/null
+/* Misc. support for CPU family crisv32f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2004 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU crisv32f
+#define WANT_CPU_CRISV32F
+
+#include "sim-main.h"
+#include "cgen-ops.h"
+
+/* Get the value of h-v32-v32. */
+
+BI
+crisv32f_h_v32_v32_get (SIM_CPU *current_cpu)
+{
+ return GET_H_V32_V32 ();
+}
+
+/* Set a value for h-v32-v32. */
+
+void
+crisv32f_h_v32_v32_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_V32_V32 (newval);
+}
+
+/* Get the value of h-pc. */
+
+USI
+crisv32f_h_pc_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_pc);
+}
+
+/* Set a value for h-pc. */
+
+void
+crisv32f_h_pc_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_PC (newval);
+}
+
+/* Get the value of h-gr. */
+
+SI
+crisv32f_h_gr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_GR (regno);
+}
+
+/* Set a value for h-gr. */
+
+void
+crisv32f_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_GR (regno, newval);
+}
+
+/* Get the value of h-gr-acr. */
+
+SI
+crisv32f_h_gr_acr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return CPU (h_gr_acr[regno]);
+}
+
+/* Set a value for h-gr-acr. */
+
+void
+crisv32f_h_gr_acr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ CPU (h_gr_acr[regno]) = newval;
+}
+
+/* Get the value of h-raw-gr-acr. */
+
+SI
+crisv32f_h_raw_gr_acr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_RAW_GR_ACR (regno);
+}
+
+/* Set a value for h-raw-gr-acr. */
+
+void
+crisv32f_h_raw_gr_acr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_RAW_GR_ACR (regno, newval);
+}
+
+/* Get the value of h-sr. */
+
+SI
+crisv32f_h_sr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_SR (regno);
+}
+
+/* Set a value for h-sr. */
+
+void
+crisv32f_h_sr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_SR (regno, newval);
+}
+
+/* Get the value of h-sr-v32. */
+
+SI
+crisv32f_h_sr_v32_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_SR_V32 (regno);
+}
+
+/* Set a value for h-sr-v32. */
+
+void
+crisv32f_h_sr_v32_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_SR_V32 (regno, newval);
+}
+
+/* Get the value of h-supr. */
+
+SI
+crisv32f_h_supr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_SUPR (regno);
+}
+
+/* Set a value for h-supr. */
+
+void
+crisv32f_h_supr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_SUPR (regno, newval);
+}
+
+/* Get the value of h-cbit. */
+
+BI
+crisv32f_h_cbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_cbit);
+}
+
+/* Set a value for h-cbit. */
+
+void
+crisv32f_h_cbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_cbit) = newval;
+}
+
+/* Get the value of h-cbit-move. */
+
+BI
+crisv32f_h_cbit_move_get (SIM_CPU *current_cpu)
+{
+ return GET_H_CBIT_MOVE ();
+}
+
+/* Set a value for h-cbit-move. */
+
+void
+crisv32f_h_cbit_move_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_CBIT_MOVE (newval);
+}
+
+/* Get the value of h-cbit-move-v32. */
+
+BI
+crisv32f_h_cbit_move_v32_get (SIM_CPU *current_cpu)
+{
+ return GET_H_CBIT_MOVE_V32 ();
+}
+
+/* Set a value for h-cbit-move-v32. */
+
+void
+crisv32f_h_cbit_move_v32_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_CBIT_MOVE_V32 (newval);
+}
+
+/* Get the value of h-vbit. */
+
+BI
+crisv32f_h_vbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_vbit);
+}
+
+/* Set a value for h-vbit. */
+
+void
+crisv32f_h_vbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_vbit) = newval;
+}
+
+/* Get the value of h-vbit-move. */
+
+BI
+crisv32f_h_vbit_move_get (SIM_CPU *current_cpu)
+{
+ return GET_H_VBIT_MOVE ();
+}
+
+/* Set a value for h-vbit-move. */
+
+void
+crisv32f_h_vbit_move_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_VBIT_MOVE (newval);
+}
+
+/* Get the value of h-vbit-move-v32. */
+
+BI
+crisv32f_h_vbit_move_v32_get (SIM_CPU *current_cpu)
+{
+ return GET_H_VBIT_MOVE_V32 ();
+}
+
+/* Set a value for h-vbit-move-v32. */
+
+void
+crisv32f_h_vbit_move_v32_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_VBIT_MOVE_V32 (newval);
+}
+
+/* Get the value of h-zbit. */
+
+BI
+crisv32f_h_zbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_zbit);
+}
+
+/* Set a value for h-zbit. */
+
+void
+crisv32f_h_zbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_zbit) = newval;
+}
+
+/* Get the value of h-zbit-move. */
+
+BI
+crisv32f_h_zbit_move_get (SIM_CPU *current_cpu)
+{
+ return GET_H_ZBIT_MOVE ();
+}
+
+/* Set a value for h-zbit-move. */
+
+void
+crisv32f_h_zbit_move_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_ZBIT_MOVE (newval);
+}
+
+/* Get the value of h-zbit-move-v32. */
+
+BI
+crisv32f_h_zbit_move_v32_get (SIM_CPU *current_cpu)
+{
+ return GET_H_ZBIT_MOVE_V32 ();
+}
+
+/* Set a value for h-zbit-move-v32. */
+
+void
+crisv32f_h_zbit_move_v32_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_ZBIT_MOVE_V32 (newval);
+}
+
+/* Get the value of h-nbit. */
+
+BI
+crisv32f_h_nbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_nbit);
+}
+
+/* Set a value for h-nbit. */
+
+void
+crisv32f_h_nbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_nbit) = newval;
+}
+
+/* Get the value of h-nbit-move. */
+
+BI
+crisv32f_h_nbit_move_get (SIM_CPU *current_cpu)
+{
+ return GET_H_NBIT_MOVE ();
+}
+
+/* Set a value for h-nbit-move. */
+
+void
+crisv32f_h_nbit_move_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_NBIT_MOVE (newval);
+}
+
+/* Get the value of h-nbit-move-v32. */
+
+BI
+crisv32f_h_nbit_move_v32_get (SIM_CPU *current_cpu)
+{
+ return GET_H_NBIT_MOVE_V32 ();
+}
+
+/* Set a value for h-nbit-move-v32. */
+
+void
+crisv32f_h_nbit_move_v32_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_NBIT_MOVE_V32 (newval);
+}
+
+/* Get the value of h-xbit. */
+
+BI
+crisv32f_h_xbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_xbit);
+}
+
+/* Set a value for h-xbit. */
+
+void
+crisv32f_h_xbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_xbit) = newval;
+}
+
+/* Get the value of h-ibit. */
+
+BI
+crisv32f_h_ibit_get (SIM_CPU *current_cpu)
+{
+ return GET_H_IBIT ();
+}
+
+/* Set a value for h-ibit. */
+
+void
+crisv32f_h_ibit_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_IBIT (newval);
+}
+
+/* Get the value of h-pbit. */
+
+BI
+crisv32f_h_pbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_pbit);
+}
+
+/* Set a value for h-pbit. */
+
+void
+crisv32f_h_pbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_pbit) = newval;
+}
+
+/* Get the value of h-rbit. */
+
+BI
+crisv32f_h_rbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_rbit);
+}
+
+/* Set a value for h-rbit. */
+
+void
+crisv32f_h_rbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_rbit) = newval;
+}
+
+/* Get the value of h-ubit. */
+
+BI
+crisv32f_h_ubit_get (SIM_CPU *current_cpu)
+{
+ return GET_H_UBIT ();
+}
+
+/* Set a value for h-ubit. */
+
+void
+crisv32f_h_ubit_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_UBIT (newval);
+}
+
+/* Get the value of h-gbit. */
+
+BI
+crisv32f_h_gbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_gbit);
+}
+
+/* Set a value for h-gbit. */
+
+void
+crisv32f_h_gbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_gbit) = newval;
+}
+
+/* Get the value of h-kernel-sp. */
+
+SI
+crisv32f_h_kernel_sp_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_kernel_sp);
+}
+
+/* Set a value for h-kernel-sp. */
+
+void
+crisv32f_h_kernel_sp_set (SIM_CPU *current_cpu, SI newval)
+{
+ CPU (h_kernel_sp) = newval;
+}
+
+/* Get the value of h-ubit-v32. */
+
+BI
+crisv32f_h_ubit_v32_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_ubit_v32);
+}
+
+/* Set a value for h-ubit-v32. */
+
+void
+crisv32f_h_ubit_v32_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_UBIT_V32 (newval);
+}
+
+/* Get the value of h-ibit-v32. */
+
+BI
+crisv32f_h_ibit_v32_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_ibit_v32);
+}
+
+/* Set a value for h-ibit-v32. */
+
+void
+crisv32f_h_ibit_v32_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_IBIT_V32 (newval);
+}
+
+/* Get the value of h-mbit. */
+
+BI
+crisv32f_h_mbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_mbit);
+}
+
+/* Set a value for h-mbit. */
+
+void
+crisv32f_h_mbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_MBIT (newval);
+}
+
+/* Get the value of h-qbit. */
+
+BI
+crisv32f_h_qbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_qbit);
+}
+
+/* Set a value for h-qbit. */
+
+void
+crisv32f_h_qbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_QBIT (newval);
+}
+
+/* Get the value of h-sbit. */
+
+BI
+crisv32f_h_sbit_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_sbit);
+}
+
+/* Set a value for h-sbit. */
+
+void
+crisv32f_h_sbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_SBIT (newval);
+}
+
+/* Get the value of h-insn-prefixed-p. */
+
+BI
+crisv32f_h_insn_prefixed_p_get (SIM_CPU *current_cpu)
+{
+ return GET_H_INSN_PREFIXED_P ();
+}
+
+/* Set a value for h-insn-prefixed-p. */
+
+void
+crisv32f_h_insn_prefixed_p_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_INSN_PREFIXED_P (newval);
+}
+
+/* Get the value of h-insn-prefixed-p-v32. */
+
+BI
+crisv32f_h_insn_prefixed_p_v32_get (SIM_CPU *current_cpu)
+{
+ return GET_H_INSN_PREFIXED_P_V32 ();
+}
+
+/* Set a value for h-insn-prefixed-p-v32. */
+
+void
+crisv32f_h_insn_prefixed_p_v32_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_INSN_PREFIXED_P_V32 (newval);
+}
+
+/* Get the value of h-prefixreg-v32. */
+
+SI
+crisv32f_h_prefixreg_v32_get (SIM_CPU *current_cpu)
+{
+ return GET_H_PREFIXREG_V32 ();
+}
+
+/* Set a value for h-prefixreg-v32. */
+
+void
+crisv32f_h_prefixreg_v32_set (SIM_CPU *current_cpu, SI newval)
+{
+ SET_H_PREFIXREG_V32 (newval);
+}
+
+/* Record trace results for INSN. */
+
+void
+crisv32f_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
+ int *indices, TRACE_RECORD *tr)
+{
+}
--- /dev/null
+/* CPU family header for crisv32f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2004 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef CPU_CRISV32F_H
+#define CPU_CRISV32F_H
+
+/* Maximum number of instructions that are fetched at a time.
+ This is for LIW type instructions sets (e.g. m32r). */
+#define MAX_LIW_INSNS 1
+
+/* Maximum number of instructions that can be executed in parallel. */
+#define MAX_PARALLEL_INSNS 1
+
+/* CPU state information. */
+typedef struct {
+ /* Hardware elements. */
+ struct {
+ /* program counter */
+ USI h_pc;
+#define GET_H_PC() CPU (h_pc)
+#define SET_H_PC(x) \
+do { \
+CPU (h_pc) = ANDSI ((x), (~ (1)));\
+;} while (0)
+ /* General purpose registers */
+ SI h_gr_acr[16];
+#define GET_H_GR_ACR(a1) CPU (h_gr_acr)[a1]
+#define SET_H_GR_ACR(a1, x) (CPU (h_gr_acr)[a1] = (x))
+ /* Special registers for v32 */
+ SI h_sr_v32[16];
+#define GET_H_SR_V32(index) (ORIF (ORIF (((index) == (((UINT) 0))), ((index) == (((UINT) 4)))), ((index) == (((UINT) 8))))) ? (0) : (((index) == (((UINT) 1)))) ? (32) : (((index) == (((UINT) 13)))) ? (ORSI (ANDSI (CPU (h_sr_v32[((UINT) 13)]), 1073740800), ORSI (ZEXTBISI (CPU (h_cbit)), ORSI (SLLSI (ZEXTBISI (CPU (h_vbit)), 1), ORSI (SLLSI (ZEXTBISI (CPU (h_zbit)), 2), ORSI (SLLSI (ZEXTBISI (CPU (h_nbit)), 3), ORSI (SLLSI (ZEXTBISI (CPU (h_xbit)), 4), ORSI (SLLSI (ZEXTBISI (GET_H_IBIT ()), 5), ORSI (SLLSI (ZEXTBISI (GET_H_UBIT ()), 6), ORSI (SLLSI (ZEXTBISI (CPU (h_pbit)), 7), ORSI (SLLSI (ZEXTBISI (CPU (h_rbit)), 8), ORSI (SLLSI (ZEXTBISI (CPU (h_sbit)), 9), ORSI (SLLSI (ZEXTBISI (CPU (h_mbit)), 30), ORSI (SLLSI (ZEXTBISI (CPU (h_qbit)), 31), 0)))))))))))))) : (((index) == (((UINT) 14)))) ? (((GET_H_UBIT ()) ? (CPU (h_gr_acr[((UINT) 14)])) : (CPU (h_sr_v32[((UINT) 14)])))) : (CPU (h_sr_v32[index]))
+#define SET_H_SR_V32(index, x) \
+do { \
+if (ORIF (ORIF ((((index)) == (((UINT) 0))), (((index)) == (((UINT) 4)))), ORIF ((((index)) == (((UINT) 8))), (((index)) == (((UINT) 1)))))) {\
+((void) 0); /*nop*/\
+}\
+ else if ((((index)) == (((UINT) 13)))) {\
+{\
+CPU (h_cbit) = ((NESI (ANDSI ((x), ((1) << (0))), 0)) ? (1) : (0));\
+CPU (h_vbit) = ((NESI (ANDSI ((x), ((1) << (1))), 0)) ? (1) : (0));\
+CPU (h_zbit) = ((NESI (ANDSI ((x), ((1) << (2))), 0)) ? (1) : (0));\
+CPU (h_nbit) = ((NESI (ANDSI ((x), ((1) << (3))), 0)) ? (1) : (0));\
+CPU (h_xbit) = ((NESI (ANDSI ((x), ((1) << (4))), 0)) ? (1) : (0));\
+SET_H_IBIT (((NESI (ANDSI ((x), ((1) << (5))), 0)) ? (1) : (0)));\
+SET_H_SBIT (((NESI (ANDSI ((x), ((1) << (9))), 0)) ? (1) : (0)));\
+SET_H_MBIT (((NESI (ANDSI ((x), ((1) << (30))), 0)) ? (1) : (0)));\
+CPU (h_pbit) = ((NESI (ANDSI ((x), ((1) << (7))), 0)) ? (1) : (0));\
+CPU (h_rbit) = ((NESI (ANDSI ((x), ((1) << (8))), 0)) ? (1) : (0));\
+SET_H_QBIT (((NESI (ANDSI ((x), ((1) << (31))), 0)) ? (1) : (0)));\
+SET_H_UBIT (((NESI (ANDSI ((x), ((1) << (6))), 0)) ? (1) : (0)));\
+CPU (h_sr_v32[(index)]) = (x);\
+}\
+}\
+ else if ((((index)) == (((UINT) 14)))) {\
+{\
+if (GET_H_UBIT ()) {\
+CPU (h_gr_acr[((UINT) 14)]) = (x);\
+}\
+CPU (h_sr_v32[((UINT) 14)]) = (x);\
+}\
+}\
+ else if ((((index)) == (((UINT) 3)))) {\
+if (NOTBI (GET_H_UBIT ())) {\
+CPU (h_sr_v32[((UINT) 3)]) = (x);\
+}\
+}\
+ else if ((((index)) == (((UINT) 9)))) {\
+if (NOTBI (GET_H_UBIT ())) {\
+CPU (h_sr_v32[((UINT) 9)]) = (x);\
+}\
+}\
+ else if ((((index)) == (((UINT) 2)))) {\
+if (NOTBI (GET_H_UBIT ())) {\
+{\
+crisv32f_write_pid_handler (current_cpu, (x));\
+CPU (h_sr_v32[((UINT) 2)]) = (x);\
+}\
+}\
+}\
+ else if ((((index)) == (((UINT) 15)))) {\
+if (NOTBI (GET_H_UBIT ())) {\
+CPU (h_sr_v32[((UINT) 15)]) = (x);\
+}\
+}\
+ else {\
+CPU (h_sr_v32[(index)]) = (x);\
+}\
+;} while (0)
+ /* carry bit */
+ BI h_cbit;
+#define GET_H_CBIT() CPU (h_cbit)
+#define SET_H_CBIT(x) (CPU (h_cbit) = (x))
+ /* overflow bit */
+ BI h_vbit;
+#define GET_H_VBIT() CPU (h_vbit)
+#define SET_H_VBIT(x) (CPU (h_vbit) = (x))
+ /* zero bit */
+ BI h_zbit;
+#define GET_H_ZBIT() CPU (h_zbit)
+#define SET_H_ZBIT(x) (CPU (h_zbit) = (x))
+ /* sign bit */
+ BI h_nbit;
+#define GET_H_NBIT() CPU (h_nbit)
+#define SET_H_NBIT(x) (CPU (h_nbit) = (x))
+ /* extended-arithmetic bit */
+ BI h_xbit;
+#define GET_H_XBIT() CPU (h_xbit)
+#define SET_H_XBIT(x) (CPU (h_xbit) = (x))
+ /* sequence-broken bit */
+ BI h_pbit;
+#define GET_H_PBIT() CPU (h_pbit)
+#define SET_H_PBIT(x) (CPU (h_pbit) = (x))
+ /* carry bit for MCP+restore-p bit */
+ BI h_rbit;
+#define GET_H_RBIT() CPU (h_rbit)
+#define SET_H_RBIT(x) (CPU (h_rbit) = (x))
+ /* guru mode bit */
+ BI h_gbit;
+#define GET_H_GBIT() CPU (h_gbit)
+#define SET_H_GBIT(x) (CPU (h_gbit) = (x))
+ /* Kernel stack pointer during user mode */
+ SI h_kernel_sp;
+#define GET_H_KERNEL_SP() CPU (h_kernel_sp)
+#define SET_H_KERNEL_SP(x) (CPU (h_kernel_sp) = (x))
+ /* User mode bit */
+ BI h_ubit_v32;
+#define GET_H_UBIT_V32() CPU (h_ubit_v32)
+#define SET_H_UBIT_V32(x) \
+do { \
+{\
+if (ANDIF ((x), NOTBI (CPU (h_ubit_v32)))) {\
+{\
+CPU (h_kernel_sp) = CPU (h_gr_acr[((UINT) 14)]);\
+CPU (h_gr_acr[((UINT) 14)]) = CPU (h_sr_v32[((UINT) 14)]);\
+CPU (h_ubit_v32) = (x);\
+crisv32f_usermode_enabled (current_cpu);\
+}\
+}\
+}\
+;} while (0)
+ /* Interrupt-enable bit */
+ BI h_ibit_v32;
+#define GET_H_IBIT_V32() CPU (h_ibit_v32)
+#define SET_H_IBIT_V32(x) \
+do { \
+{\
+if (NOTBI (GET_H_UBIT ())) {\
+{\
+ BI tmp_enabled;\
+ tmp_enabled = ANDIF ((x), NOTBI (CPU (h_ibit_v32)));\
+CPU (h_ibit_v32) = (x);\
+if (tmp_enabled) {\
+crisv32f_interrupts_enabled (current_cpu);\
+}\
+}\
+}\
+}\
+;} while (0)
+ /* NMI enable bit */
+ BI h_mbit;
+#define GET_H_MBIT() CPU (h_mbit)
+#define SET_H_MBIT(x) \
+do { \
+{\
+if (ANDIF ((x), ANDIF (NOTBI (CPU (h_mbit)), NOTBI (GET_H_UBIT ())))) {\
+{\
+CPU (h_mbit) = 1;\
+crisv32f_nmi_enabled (current_cpu);\
+}\
+}\
+}\
+;} while (0)
+ /* Pending single-step bit */
+ BI h_qbit;
+#define GET_H_QBIT() CPU (h_qbit)
+#define SET_H_QBIT(x) \
+do { \
+{\
+if (NOTBI (GET_H_UBIT ())) {\
+CPU (h_qbit) = (x);\
+}\
+}\
+;} while (0)
+ /* Cause single step exception on ... [see CRISv32 ref] bit */
+ BI h_sbit;
+#define GET_H_SBIT() CPU (h_sbit)
+#define SET_H_SBIT(x) \
+do { \
+{\
+if (NOTBI (GET_H_UBIT ())) {\
+{\
+ BI tmp_enabled;\
+ tmp_enabled = ANDIF ((x), NOTBI (CPU (h_sbit)));\
+CPU (h_sbit) = (x);\
+if (tmp_enabled) {\
+crisv32f_single_step_enabled (current_cpu);\
+}\
+}\
+}\
+}\
+;} while (0)
+ } hardware;
+#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
+} CRISV32F_CPU_DATA;
+
+/* Virtual regs. */
+
+#define GET_H_V32_V32() 1
+#define SET_H_V32_V32(x) \
+do { \
+cgen_rtx_error (current_cpu, "Can't set h-v32");\
+;} while (0)
+#define GET_H_GR(index) CPU (h_gr_acr[index])
+#define SET_H_GR(index, x) \
+do { \
+CPU (h_gr_acr[(index)]) = (x);\
+;} while (0)
+#define GET_H_RAW_GR_ACR(index) CPU (h_gr_acr[index])
+#define SET_H_RAW_GR_ACR(index, x) \
+do { \
+CPU (h_gr_acr[(index)]) = (x);\
+;} while (0)
+#define GET_H_SR(index) GET_H_SR_V32 (index)
+#define SET_H_SR(index, x) \
+do { \
+SET_H_SR_V32 ((index), (x));\
+;} while (0)
+#define GET_H_SUPR(index) crisv32f_read_supr (current_cpu, index)
+#define SET_H_SUPR(index, x) \
+do { \
+crisv32f_write_supr (current_cpu, (index), (x));\
+;} while (0)
+#define GET_H_CBIT_MOVE() GET_H_CBIT_MOVE_V32 ()
+#define SET_H_CBIT_MOVE(x) \
+do { \
+SET_H_CBIT_MOVE_V32 ((x));\
+;} while (0)
+#define GET_H_CBIT_MOVE_V32() (cgen_rtx_error (current_cpu, "Can't get h-cbit-move on CRISv32"), 0)
+#define SET_H_CBIT_MOVE_V32(x) \
+do { \
+((void) 0); /*nop*/\
+;} while (0)
+#define GET_H_VBIT_MOVE() GET_H_VBIT_MOVE_V32 ()
+#define SET_H_VBIT_MOVE(x) \
+do { \
+SET_H_VBIT_MOVE_V32 ((x));\
+;} while (0)
+#define GET_H_VBIT_MOVE_V32() (cgen_rtx_error (current_cpu, "Can't get h-vbit-move on CRISv32"), 0)
+#define SET_H_VBIT_MOVE_V32(x) \
+do { \
+((void) 0); /*nop*/\
+;} while (0)
+#define GET_H_ZBIT_MOVE() GET_H_ZBIT_MOVE_V32 ()
+#define SET_H_ZBIT_MOVE(x) \
+do { \
+SET_H_ZBIT_MOVE_V32 ((x));\
+;} while (0)
+#define GET_H_ZBIT_MOVE_V32() (cgen_rtx_error (current_cpu, "Can't get h-zbit-move on CRISv32"), 0)
+#define SET_H_ZBIT_MOVE_V32(x) \
+do { \
+((void) 0); /*nop*/\
+;} while (0)
+#define GET_H_NBIT_MOVE() GET_H_NBIT_MOVE_V32 ()
+#define SET_H_NBIT_MOVE(x) \
+do { \
+SET_H_NBIT_MOVE_V32 ((x));\
+;} while (0)
+#define GET_H_NBIT_MOVE_V32() (cgen_rtx_error (current_cpu, "Can't get h-nbit-move on CRISv32"), 0)
+#define SET_H_NBIT_MOVE_V32(x) \
+do { \
+((void) 0); /*nop*/\
+;} while (0)
+#define GET_H_IBIT() CPU (h_ibit_v32)
+#define SET_H_IBIT(x) \
+do { \
+SET_H_IBIT_V32 ((x));\
+;} while (0)
+#define GET_H_UBIT() CPU (h_ubit_v32)
+#define SET_H_UBIT(x) \
+do { \
+SET_H_UBIT_V32 ((x));\
+;} while (0)
+#define GET_H_INSN_PREFIXED_P() GET_H_INSN_PREFIXED_P_V32 ()
+#define SET_H_INSN_PREFIXED_P(x) \
+do { \
+SET_H_INSN_PREFIXED_P_V32 ((x));\
+;} while (0)
+#define GET_H_INSN_PREFIXED_P_V32() 0
+#define SET_H_INSN_PREFIXED_P_V32(x) \
+do { \
+((void) 0); /*nop*/\
+;} while (0)
+#define GET_H_PREFIXREG_V32() GET_H_GR (((UINT) 15))
+#define SET_H_PREFIXREG_V32(x) \
+do { \
+SET_H_GR (((UINT) 15), (x));\
+;} while (0)
+
+/* Cover fns for register access. */
+BI crisv32f_h_v32_v32_get (SIM_CPU *);
+void crisv32f_h_v32_v32_set (SIM_CPU *, BI);
+USI crisv32f_h_pc_get (SIM_CPU *);
+void crisv32f_h_pc_set (SIM_CPU *, USI);
+SI crisv32f_h_gr_get (SIM_CPU *, UINT);
+void crisv32f_h_gr_set (SIM_CPU *, UINT, SI);
+SI crisv32f_h_gr_acr_get (SIM_CPU *, UINT);
+void crisv32f_h_gr_acr_set (SIM_CPU *, UINT, SI);
+SI crisv32f_h_raw_gr_acr_get (SIM_CPU *, UINT);
+void crisv32f_h_raw_gr_acr_set (SIM_CPU *, UINT, SI);
+SI crisv32f_h_sr_get (SIM_CPU *, UINT);
+void crisv32f_h_sr_set (SIM_CPU *, UINT, SI);
+SI crisv32f_h_sr_v32_get (SIM_CPU *, UINT);
+void crisv32f_h_sr_v32_set (SIM_CPU *, UINT, SI);
+SI crisv32f_h_supr_get (SIM_CPU *, UINT);
+void crisv32f_h_supr_set (SIM_CPU *, UINT, SI);
+BI crisv32f_h_cbit_get (SIM_CPU *);
+void crisv32f_h_cbit_set (SIM_CPU *, BI);
+BI crisv32f_h_cbit_move_get (SIM_CPU *);
+void crisv32f_h_cbit_move_set (SIM_CPU *, BI);
+BI crisv32f_h_cbit_move_v32_get (SIM_CPU *);
+void crisv32f_h_cbit_move_v32_set (SIM_CPU *, BI);
+BI crisv32f_h_vbit_get (SIM_CPU *);
+void crisv32f_h_vbit_set (SIM_CPU *, BI);
+BI crisv32f_h_vbit_move_get (SIM_CPU *);
+void crisv32f_h_vbit_move_set (SIM_CPU *, BI);
+BI crisv32f_h_vbit_move_v32_get (SIM_CPU *);
+void crisv32f_h_vbit_move_v32_set (SIM_CPU *, BI);
+BI crisv32f_h_zbit_get (SIM_CPU *);
+void crisv32f_h_zbit_set (SIM_CPU *, BI);
+BI crisv32f_h_zbit_move_get (SIM_CPU *);
+void crisv32f_h_zbit_move_set (SIM_CPU *, BI);
+BI crisv32f_h_zbit_move_v32_get (SIM_CPU *);
+void crisv32f_h_zbit_move_v32_set (SIM_CPU *, BI);
+BI crisv32f_h_nbit_get (SIM_CPU *);
+void crisv32f_h_nbit_set (SIM_CPU *, BI);
+BI crisv32f_h_nbit_move_get (SIM_CPU *);
+void crisv32f_h_nbit_move_set (SIM_CPU *, BI);
+BI crisv32f_h_nbit_move_v32_get (SIM_CPU *);
+void crisv32f_h_nbit_move_v32_set (SIM_CPU *, BI);
+BI crisv32f_h_xbit_get (SIM_CPU *);
+void crisv32f_h_xbit_set (SIM_CPU *, BI);
+BI crisv32f_h_ibit_get (SIM_CPU *);
+void crisv32f_h_ibit_set (SIM_CPU *, BI);
+BI crisv32f_h_pbit_get (SIM_CPU *);
+void crisv32f_h_pbit_set (SIM_CPU *, BI);
+BI crisv32f_h_rbit_get (SIM_CPU *);
+void crisv32f_h_rbit_set (SIM_CPU *, BI);
+BI crisv32f_h_ubit_get (SIM_CPU *);
+void crisv32f_h_ubit_set (SIM_CPU *, BI);
+BI crisv32f_h_gbit_get (SIM_CPU *);
+void crisv32f_h_gbit_set (SIM_CPU *, BI);
+SI crisv32f_h_kernel_sp_get (SIM_CPU *);
+void crisv32f_h_kernel_sp_set (SIM_CPU *, SI);
+BI crisv32f_h_ubit_v32_get (SIM_CPU *);
+void crisv32f_h_ubit_v32_set (SIM_CPU *, BI);
+BI crisv32f_h_ibit_v32_get (SIM_CPU *);
+void crisv32f_h_ibit_v32_set (SIM_CPU *, BI);
+BI crisv32f_h_mbit_get (SIM_CPU *);
+void crisv32f_h_mbit_set (SIM_CPU *, BI);
+BI crisv32f_h_qbit_get (SIM_CPU *);
+void crisv32f_h_qbit_set (SIM_CPU *, BI);
+BI crisv32f_h_sbit_get (SIM_CPU *);
+void crisv32f_h_sbit_set (SIM_CPU *, BI);
+BI crisv32f_h_insn_prefixed_p_get (SIM_CPU *);
+void crisv32f_h_insn_prefixed_p_set (SIM_CPU *, BI);
+BI crisv32f_h_insn_prefixed_p_v32_get (SIM_CPU *);
+void crisv32f_h_insn_prefixed_p_v32_set (SIM_CPU *, BI);
+SI crisv32f_h_prefixreg_v32_get (SIM_CPU *);
+void crisv32f_h_prefixreg_v32_set (SIM_CPU *, SI);
+
+/* These must be hand-written. */
+extern CPUREG_FETCH_FN crisv32f_fetch_register;
+extern CPUREG_STORE_FN crisv32f_store_register;
+
+typedef struct {
+ UINT prev_prev_prev_modf_regs;
+ UINT prev_prev_modf_regs;
+ UINT prev_modf_regs;
+ UINT modf_regs;
+ UINT prev_prev_prev_movem_dest_regs;
+ UINT prev_prev_movem_dest_regs;
+ UINT prev_movem_dest_regs;
+ UINT movem_dest_regs;
+} MODEL_CRISV32_DATA;
+
+/* Instruction argument buffer. */
+
+union sem_fields {
+ struct { /* no operands */
+ int empty;
+ } fmt_empty;
+ struct { /* */
+ UINT f_u4;
+ } sfmt_break;
+ struct { /* */
+ UINT f_dstsrc;
+ } sfmt_setf;
+ struct { /* */
+ IADDR i_o_word_pcrel;
+ UINT f_operand2;
+ } sfmt_bcc_w;
+ struct { /* */
+ IADDR i_o_pcrel;
+ UINT f_operand2;
+ } sfmt_bcc_b;
+ struct { /* */
+ unsigned char in_h_sr_SI_13;
+ unsigned char out_h_sr_SI_13;
+ } sfmt_rfe;
+ struct { /* */
+ INT f_s8;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ } sfmt_addoq;
+ struct { /* */
+ ADDR i_const32_pcrel;
+ UINT f_operand2;
+ unsigned char out_Pd;
+ } sfmt_bas_c;
+ struct { /* */
+ ADDR i_qo;
+ UINT f_operand2;
+ unsigned char out_Rd;
+ } sfmt_lapcq;
+ struct { /* */
+ ADDR i_const32_pcrel;
+ UINT f_operand2;
+ unsigned char out_Rd;
+ } sfmt_lapc_d;
+ struct { /* */
+ INT f_indir_pc__dword;
+ UINT f_operand2;
+ unsigned char out_Pd;
+ } sfmt_move_c_sprv32_p0;
+ struct { /* */
+ INT f_s6;
+ UINT f_operand2;
+ unsigned char out_Rd;
+ } sfmt_moveq;
+ struct { /* */
+ INT f_indir_pc__dword;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ unsigned char out_Rd;
+ } sfmt_bound_cd;
+ struct { /* */
+ INT f_indir_pc__word;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ unsigned char out_Rd;
+ } sfmt_bound_cw;
+ struct { /* */
+ INT f_indir_pc__byte;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ unsigned char out_Rd;
+ } sfmt_bound_cb;
+ struct { /* */
+ UINT f_operand2;
+ UINT f_u5;
+ unsigned char in_Rd;
+ unsigned char out_Rd;
+ } sfmt_asrq;
+ struct { /* */
+ INT f_s6;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ unsigned char out_h_gr_SI_index_of__DFLT_Rd;
+ } sfmt_andq;
+ struct { /* */
+ INT f_indir_pc__dword;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ unsigned char out_h_gr_SI_index_of__DFLT_Rd;
+ } sfmt_addcdr;
+ struct { /* */
+ INT f_indir_pc__word;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ unsigned char out_h_gr_SI_index_of__DFLT_Rd;
+ } sfmt_addcwr;
+ struct { /* */
+ INT f_indir_pc__byte;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ unsigned char out_h_gr_SI_index_of__DFLT_Rd;
+ } sfmt_addcbr;
+ struct { /* */
+ UINT f_operand2;
+ UINT f_u6;
+ unsigned char in_Rd;
+ unsigned char out_h_gr_SI_index_of__DFLT_Rd;
+ } sfmt_addq;
+ struct { /* */
+ UINT f_operand1;
+ UINT f_operand2;
+ unsigned char in_Ps;
+ unsigned char in_Rs;
+ unsigned char out_h_gr_SI_index_of__DFLT_Rs;
+ } sfmt_mcp;
+ struct { /* */
+ UINT f_operand1;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ unsigned char in_Rs;
+ unsigned char out_Rd;
+ unsigned char out_h_sr_SI_7;
+ } sfmt_muls_b;
+ struct { /* */
+ UINT f_memmode;
+ UINT f_operand1;
+ UINT f_operand2;
+ unsigned char in_Ps;
+ unsigned char in_Rs;
+ unsigned char out_Rs;
+ } sfmt_move_spr_mv32;
+ struct { /* */
+ UINT f_memmode;
+ UINT f_operand1;
+ UINT f_operand2;
+ unsigned char in_Rs;
+ unsigned char out_Pd;
+ unsigned char out_Rs;
+ } sfmt_move_m_sprv32;
+ struct { /* */
+ UINT f_memmode;
+ UINT f_operand1;
+ UINT f_operand2;
+ unsigned char in_Rs;
+ unsigned char out_Rd;
+ unsigned char out_Rs;
+ } sfmt_movs_m_b_m;
+ struct { /* */
+ UINT f_memmode;
+ UINT f_operand1;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ unsigned char in_Rs;
+ unsigned char out_Rs;
+ unsigned char out_h_gr_SI_index_of__DFLT_Rd;
+ } sfmt_addc_m;
+ struct { /* */
+ UINT f_memmode;
+ UINT f_operand1;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ unsigned char in_Rs;
+ unsigned char out_Rs;
+ unsigned char out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd;
+ } sfmt_add_m_b_m;
+ struct { /* */
+ UINT f_memmode;
+ UINT f_operand1;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ unsigned char in_Rs;
+ unsigned char out_Rs;
+ unsigned char out_h_gr_SI_0;
+ unsigned char out_h_gr_SI_1;
+ unsigned char out_h_gr_SI_10;
+ unsigned char out_h_gr_SI_11;
+ unsigned char out_h_gr_SI_12;
+ unsigned char out_h_gr_SI_13;
+ unsigned char out_h_gr_SI_14;
+ unsigned char out_h_gr_SI_15;
+ unsigned char out_h_gr_SI_2;
+ unsigned char out_h_gr_SI_3;
+ unsigned char out_h_gr_SI_4;
+ unsigned char out_h_gr_SI_5;
+ unsigned char out_h_gr_SI_6;
+ unsigned char out_h_gr_SI_7;
+ unsigned char out_h_gr_SI_8;
+ unsigned char out_h_gr_SI_9;
+ } sfmt_movem_m_r_v32;
+ struct { /* */
+ UINT f_memmode;
+ UINT f_operand1;
+ UINT f_operand2;
+ unsigned char in_Rd;
+ unsigned char in_Rs;
+ unsigned char in_h_gr_SI_0;
+ unsigned char in_h_gr_SI_1;
+ unsigned char in_h_gr_SI_10;
+ unsigned char in_h_gr_SI_11;
+ unsigned char in_h_gr_SI_12;
+ unsigned char in_h_gr_SI_13;
+ unsigned char in_h_gr_SI_14;
+ unsigned char in_h_gr_SI_15;
+ unsigned char in_h_gr_SI_2;
+ unsigned char in_h_gr_SI_3;
+ unsigned char in_h_gr_SI_4;
+ unsigned char in_h_gr_SI_5;
+ unsigned char in_h_gr_SI_6;
+ unsigned char in_h_gr_SI_7;
+ unsigned char in_h_gr_SI_8;
+ unsigned char in_h_gr_SI_9;
+ unsigned char out_Rs;
+ } sfmt_movem_r_m_v32;
+#if WITH_SCACHE_PBB
+ /* Writeback handler. */
+ struct {
+ /* Pointer to argbuf entry for insn whose results need writing back. */
+ const struct argbuf *abuf;
+ } write;
+ /* x-before handler */
+ struct {
+ /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
+ int first_p;
+ } before;
+ /* x-after handler */
+ struct {
+ int empty;
+ } after;
+ /* This entry is used to terminate each pbb. */
+ struct {
+ /* Number of insns in pbb. */
+ int insn_count;
+ /* Next pbb to execute. */
+ SCACHE *next;
+ SCACHE *branch_target;
+ } chain;
+#endif
+};
+
+/* The ARGBUF struct. */
+struct argbuf {
+ /* These are the baseclass definitions. */
+ IADDR addr;
+ const IDESC *idesc;
+ char trace_p;
+ char profile_p;
+ /* ??? Temporary hack for skip insns. */
+ char skip_count;
+ char unused;
+ /* cpu specific data follows */
+ union sem semantic;
+ int written;
+ union sem_fields fields;
+};
+
+/* A cached insn.
+
+ ??? SCACHE used to contain more than just argbuf. We could delete the
+ type entirely and always just use ARGBUF, but for future concerns and as
+ a level of abstraction it is left in. */
+
+struct scache {
+ struct argbuf argbuf;
+};
+
+/* Macros to simplify extraction, reading and semantic code.
+ These define and assign the local vars that contain the insn's fields. */
+
+#define EXTRACT_IFMT_EMPTY_VARS \
+ unsigned int length;
+#define EXTRACT_IFMT_EMPTY_CODE \
+ length = 0; \
+
+#define EXTRACT_IFMT_MOVE_B_R_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVE_B_R_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVEQ_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ INT f_s6; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVEQ_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_s6 = EXTRACT_LSB0_INT (insn, 16, 5, 6); \
+
+#define EXTRACT_IFMT_MOVECBR_VARS \
+ UINT f_operand2; \
+ INT f_indir_pc__byte; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ /* Contents of trailing part of insn. */ \
+ UINT word_1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVECBR_CODE \
+ length = 4; \
+ word_1 = GETIMEMUHI (current_cpu, pc + 2); \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0)); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVECWR_VARS \
+ UINT f_operand2; \
+ INT f_indir_pc__word; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ /* Contents of trailing part of insn. */ \
+ UINT word_1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVECWR_CODE \
+ length = 4; \
+ word_1 = GETIMEMUHI (current_cpu, pc + 2); \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0)); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVECDR_VARS \
+ INT f_indir_pc__dword; \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ /* Contents of trailing part of insn. */ \
+ UINT word_1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVECDR_CODE \
+ length = 6; \
+ word_1 = GETIMEMUSI (current_cpu, pc + 2); \
+ f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVUCBR_VARS \
+ UINT f_operand2; \
+ INT f_indir_pc__byte; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ /* Contents of trailing part of insn. */ \
+ UINT word_1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVUCBR_CODE \
+ length = 4; \
+ word_1 = GETIMEMUHI (current_cpu, pc + 2); \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0)); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVUCWR_VARS \
+ UINT f_operand2; \
+ INT f_indir_pc__word; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ /* Contents of trailing part of insn. */ \
+ UINT word_1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVUCWR_CODE \
+ length = 4; \
+ word_1 = GETIMEMUHI (current_cpu, pc + 2); \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0)); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_ADDQ_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_u6; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADDQ_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_u6 = EXTRACT_LSB0_UINT (insn, 16, 5, 6); \
+
+#define EXTRACT_IFMT_CMP_M_B_M_VARS \
+ UINT f_operand2; \
+ UINT f_membit; \
+ UINT f_memmode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ unsigned int length;
+#define EXTRACT_IFMT_CMP_M_B_M_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVE_R_SPRV32_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVE_R_SPRV32_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVE_SPR_RV32_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVE_SPR_RV32_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVE_M_SPRV32_VARS \
+ UINT f_operand2; \
+ UINT f_membit; \
+ UINT f_memmode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVE_M_SPRV32_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVE_C_SPRV32_P0_VARS \
+ INT f_indir_pc__dword; \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ /* Contents of trailing part of insn. */ \
+ UINT word_1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVE_C_SPRV32_P0_CODE \
+ length = 6; \
+ word_1 = GETIMEMUSI (current_cpu, pc + 2); \
+ f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVE_SPR_MV32_VARS \
+ UINT f_operand2; \
+ UINT f_membit; \
+ UINT f_memmode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVE_SPR_MV32_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVE_SS_R_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVE_SS_R_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVE_R_SS_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVE_R_SS_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_LAPC_D_VARS \
+ SI f_indir_pc__dword_pcrel; \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ /* Contents of trailing part of insn. */ \
+ UINT word_1; \
+ unsigned int length;
+#define EXTRACT_IFMT_LAPC_D_CODE \
+ length = 6; \
+ word_1 = GETIMEMUSI (current_cpu, pc + 2); \
+ f_indir_pc__dword_pcrel = ((pc) + ((0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)))); \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_LAPCQ_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ SI f_qo; \
+ unsigned int length;
+#define EXTRACT_IFMT_LAPCQ_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_qo = ((pc) + (((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (1)))); \
+
+#define EXTRACT_IFMT_TEST_M_B_M_VARS \
+ UINT f_operand2; \
+ UINT f_membit; \
+ UINT f_memmode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ unsigned int length;
+#define EXTRACT_IFMT_TEST_M_B_M_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_SWAP_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ unsigned int length;
+#define EXTRACT_IFMT_SWAP_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_ASRQ_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_b5; \
+ UINT f_u5; \
+ unsigned int length;
+#define EXTRACT_IFMT_ASRQ_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_b5 = EXTRACT_LSB0_UINT (insn, 16, 5, 1); \
+ f_u5 = EXTRACT_LSB0_UINT (insn, 16, 4, 5); \
+
+#define EXTRACT_IFMT_SETF_VARS \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand2; \
+ UINT f_operand1; \
+ UINT f_dstsrc; \
+ unsigned int length;
+#define EXTRACT_IFMT_SETF_CODE \
+ length = 2; \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+ f_dstsrc = ((((f_operand1) | (((f_operand2) << (4))))) & (255));\
+
+#define EXTRACT_IFMT_RFE_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ unsigned int length;
+#define EXTRACT_IFMT_RFE_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_BCC_B_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode_hi; \
+ INT f_disp9_hi; \
+ UINT f_disp9_lo; \
+ INT f_disp9; \
+ unsigned int length;
+#define EXTRACT_IFMT_BCC_B_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
+ f_disp9_hi = EXTRACT_LSB0_INT (insn, 16, 0, 1); \
+ f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \
+{\
+ SI tmp_abslo;\
+ SI tmp_absval;\
+ tmp_abslo = ((f_disp9_lo) << (1));\
+ tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));\
+ f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_V32 ()) ? (0) : (2))));\
+}\
+
+#define EXTRACT_IFMT_BA_B_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode_hi; \
+ INT f_disp9_hi; \
+ UINT f_disp9_lo; \
+ INT f_disp9; \
+ unsigned int length;
+#define EXTRACT_IFMT_BA_B_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
+ f_disp9_hi = EXTRACT_LSB0_INT (insn, 16, 0, 1); \
+ f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \
+{\
+ SI tmp_abslo;\
+ SI tmp_absval;\
+ tmp_abslo = ((f_disp9_lo) << (1));\
+ tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));\
+ f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_V32 ()) ? (0) : (2))));\
+}\
+
+#define EXTRACT_IFMT_BCC_W_VARS \
+ UINT f_operand2; \
+ SI f_indir_pc__word_pcrel; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ /* Contents of trailing part of insn. */ \
+ UINT word_1; \
+ unsigned int length;
+#define EXTRACT_IFMT_BCC_W_CODE \
+ length = 4; \
+ word_1 = GETIMEMUHI (current_cpu, pc + 2); \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_V32 ()) ? (0) : (4)))))); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_BA_W_VARS \
+ UINT f_operand2; \
+ SI f_indir_pc__word_pcrel; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ /* Contents of trailing part of insn. */ \
+ UINT word_1; \
+ unsigned int length;
+#define EXTRACT_IFMT_BA_W_CODE \
+ length = 4; \
+ word_1 = GETIMEMUHI (current_cpu, pc + 2); \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_V32 ()) ? (0) : (4)))))); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_JAS_C_VARS \
+ INT f_indir_pc__dword; \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ /* Contents of trailing part of insn. */ \
+ UINT word_1; \
+ unsigned int length;
+#define EXTRACT_IFMT_JAS_C_CODE \
+ length = 6; \
+ word_1 = GETIMEMUSI (current_cpu, pc + 2); \
+ f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_JUMP_P_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ unsigned int length;
+#define EXTRACT_IFMT_JUMP_P_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_BAS_C_VARS \
+ SI f_indir_pc__dword_pcrel; \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ /* Contents of trailing part of insn. */ \
+ UINT word_1; \
+ unsigned int length;
+#define EXTRACT_IFMT_BAS_C_CODE \
+ length = 6; \
+ word_1 = GETIMEMUSI (current_cpu, pc + 2); \
+ f_indir_pc__dword_pcrel = ((pc) + ((0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)))); \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_BREAK_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_u4; \
+ unsigned int length;
+#define EXTRACT_IFMT_BREAK_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_u4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_SCC_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ unsigned int length;
+#define EXTRACT_IFMT_SCC_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_ADDOQ_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode_hi; \
+ INT f_s8; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADDOQ_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
+ f_s8 = EXTRACT_LSB0_INT (insn, 16, 7, 8); \
+
+#define EXTRACT_IFMT_FIDXI_VARS \
+ UINT f_operand2; \
+ UINT f_mode; \
+ UINT f_opcode; \
+ UINT f_size; \
+ UINT f_operand1; \
+ unsigned int length;
+#define EXTRACT_IFMT_FIDXI_CODE \
+ length = 2; \
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
+ f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+/* Collection of various things for the trace handler to use. */
+
+typedef struct trace_record {
+ IADDR pc;
+ /* FIXME:wip */
+} TRACE_RECORD;
+
+#endif /* CPU_CRISV32F_H */
--- /dev/null
+/* CPU data for cris.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2004 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#include "sysdep.h"
+#include <stdio.h>
+#include <stdarg.h>
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "cris-desc.h"
+#include "cris-opc.h"
+#include "opintl.h"
+#include "libiberty.h"
+#include "xregex.h"
+
+/* Attributes. */
+
+static const CGEN_ATTR_ENTRY bool_attr[] =
+{
+ { "#f", 0 },
+ { "#t", 1 },
+ { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY MACH_attr[] =
+{
+ { "base", MACH_BASE },
+ { "crisv0", MACH_CRISV0 },
+ { "crisv3", MACH_CRISV3 },
+ { "crisv8", MACH_CRISV8 },
+ { "crisv10", MACH_CRISV10 },
+ { "crisv32", MACH_CRISV32 },
+ { "max", MACH_MAX },
+ { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY ISA_attr[] =
+{
+ { "cris", ISA_CRIS },
+ { "max", ISA_MAX },
+ { 0, 0 }
+};
+
+const CGEN_ATTR_TABLE cris_cgen_ifield_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "RESERVED", &bool_attr[0], &bool_attr[0] },
+ { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+ { "SIGNED", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE cris_cgen_hardware_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "PC", &bool_attr[0], &bool_attr[0] },
+ { "PROFILE", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE cris_cgen_operand_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+ { "SIGNED", &bool_attr[0], &bool_attr[0] },
+ { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
+ { "RELAX", &bool_attr[0], &bool_attr[0] },
+ { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE cris_cgen_insn_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "ALIAS", &bool_attr[0], &bool_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
+ { "COND-CTI", &bool_attr[0], &bool_attr[0] },
+ { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
+ { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
+ { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
+ { "RELAXED", &bool_attr[0], &bool_attr[0] },
+ { "NO-DIS", &bool_attr[0], &bool_attr[0] },
+ { "PBB", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+/* Instruction set variants. */
+
+static const CGEN_ISA cris_cgen_isa_table[] = {
+ { "cris", 16, 16, 16, 48 },
+ { 0, 0, 0, 0, 0 }
+};
+
+/* Machine variants. */
+
+static const CGEN_MACH cris_cgen_mach_table[] = {
+ { "crisv0", "cris", MACH_CRISV0, 0 },
+ { "crisv3", "cris", MACH_CRISV3, 0 },
+ { "crisv8", "cris", MACH_CRISV8, 0 },
+ { "crisv10", "cris", MACH_CRISV10, 0 },
+ { "crisv32", "crisv32", MACH_CRISV32, 0 },
+ { 0, 0, 0, 0 }
+};
+
+static CGEN_KEYWORD_ENTRY cris_cgen_opval_gr_names_pcreg_entries[] =
+{
+ { "PC", 15, {0, {0}}, 0, 0 },
+ { "SP", 14, {0, {0}}, 0, 0 },
+ { "R0", 0, {0, {0}}, 0, 0 },
+ { "R1", 1, {0, {0}}, 0, 0 },
+ { "R2", 2, {0, {0}}, 0, 0 },
+ { "R3", 3, {0, {0}}, 0, 0 },
+ { "R4", 4, {0, {0}}, 0, 0 },
+ { "R5", 5, {0, {0}}, 0, 0 },
+ { "R6", 6, {0, {0}}, 0, 0 },
+ { "R7", 7, {0, {0}}, 0, 0 },
+ { "R8", 8, {0, {0}}, 0, 0 },
+ { "R9", 9, {0, {0}}, 0, 0 },
+ { "R10", 10, {0, {0}}, 0, 0 },
+ { "R11", 11, {0, {0}}, 0, 0 },
+ { "R12", 12, {0, {0}}, 0, 0 },
+ { "R13", 13, {0, {0}}, 0, 0 },
+ { "R14", 14, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD cris_cgen_opval_gr_names_pcreg =
+{
+ & cris_cgen_opval_gr_names_pcreg_entries[0],
+ 17,
+ 0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY cris_cgen_opval_gr_names_acr_entries[] =
+{
+ { "ACR", 15, {0, {0}}, 0, 0 },
+ { "SP", 14, {0, {0}}, 0, 0 },
+ { "R0", 0, {0, {0}}, 0, 0 },
+ { "R1", 1, {0, {0}}, 0, 0 },
+ { "R2", 2, {0, {0}}, 0, 0 },
+ { "R3", 3, {0, {0}}, 0, 0 },
+ { "R4", 4, {0, {0}}, 0, 0 },
+ { "R5", 5, {0, {0}}, 0, 0 },
+ { "R6", 6, {0, {0}}, 0, 0 },
+ { "R7", 7, {0, {0}}, 0, 0 },
+ { "R8", 8, {0, {0}}, 0, 0 },
+ { "R9", 9, {0, {0}}, 0, 0 },
+ { "R10", 10, {0, {0}}, 0, 0 },
+ { "R11", 11, {0, {0}}, 0, 0 },
+ { "R12", 12, {0, {0}}, 0, 0 },
+ { "R13", 13, {0, {0}}, 0, 0 },
+ { "R14", 14, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD cris_cgen_opval_gr_names_acr =
+{
+ & cris_cgen_opval_gr_names_acr_entries[0],
+ 17,
+ 0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY cris_cgen_opval_gr_names_v32_entries[] =
+{
+ { "ACR", 15, {0, {0}}, 0, 0 },
+ { "SP", 14, {0, {0}}, 0, 0 },
+ { "R0", 0, {0, {0}}, 0, 0 },
+ { "R1", 1, {0, {0}}, 0, 0 },
+ { "R2", 2, {0, {0}}, 0, 0 },
+ { "R3", 3, {0, {0}}, 0, 0 },
+ { "R4", 4, {0, {0}}, 0, 0 },
+ { "R5", 5, {0, {0}}, 0, 0 },
+ { "R6", 6, {0, {0}}, 0, 0 },
+ { "R7", 7, {0, {0}}, 0, 0 },
+ { "R8", 8, {0, {0}}, 0, 0 },
+ { "R9", 9, {0, {0}}, 0, 0 },
+ { "R10", 10, {0, {0}}, 0, 0 },
+ { "R11", 11, {0, {0}}, 0, 0 },
+ { "R12", 12, {0, {0}}, 0, 0 },
+ { "R13", 13, {0, {0}}, 0, 0 },
+ { "R14", 14, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD cris_cgen_opval_gr_names_v32 =
+{
+ & cris_cgen_opval_gr_names_v32_entries[0],
+ 17,
+ 0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY cris_cgen_opval_p_names_v10_entries[] =
+{
+ { "CCR", 5, {0, {0}}, 0, 0 },
+ { "MOF", 7, {0, {0}}, 0, 0 },
+ { "IBR", 9, {0, {0}}, 0, 0 },
+ { "IRP", 10, {0, {0}}, 0, 0 },
+ { "BAR", 12, {0, {0}}, 0, 0 },
+ { "DCCR", 13, {0, {0}}, 0, 0 },
+ { "BRP", 14, {0, {0}}, 0, 0 },
+ { "USP", 15, {0, {0}}, 0, 0 },
+ { "VR", 1, {0, {0}}, 0, 0 },
+ { "SRP", 11, {0, {0}}, 0, 0 },
+ { "P0", 0, {0, {0}}, 0, 0 },
+ { "P1", 1, {0, {0}}, 0, 0 },
+ { "P2", 2, {0, {0}}, 0, 0 },
+ { "P3", 3, {0, {0}}, 0, 0 },
+ { "P4", 4, {0, {0}}, 0, 0 },
+ { "P5", 5, {0, {0}}, 0, 0 },
+ { "P6", 6, {0, {0}}, 0, 0 },
+ { "P7", 7, {0, {0}}, 0, 0 },
+ { "P8", 8, {0, {0}}, 0, 0 },
+ { "P9", 9, {0, {0}}, 0, 0 },
+ { "P10", 10, {0, {0}}, 0, 0 },
+ { "P11", 11, {0, {0}}, 0, 0 },
+ { "P12", 12, {0, {0}}, 0, 0 },
+ { "P13", 13, {0, {0}}, 0, 0 },
+ { "P14", 14, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD cris_cgen_opval_p_names_v10 =
+{
+ & cris_cgen_opval_p_names_v10_entries[0],
+ 25,
+ 0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY cris_cgen_opval_p_names_v32_entries[] =
+{
+ { "BZ", 0, {0, {0}}, 0, 0 },
+ { "PID", 2, {0, {0}}, 0, 0 },
+ { "SRS", 3, {0, {0}}, 0, 0 },
+ { "WZ", 4, {0, {0}}, 0, 0 },
+ { "EXS", 5, {0, {0}}, 0, 0 },
+ { "EDA", 6, {0, {0}}, 0, 0 },
+ { "MOF", 7, {0, {0}}, 0, 0 },
+ { "DZ", 8, {0, {0}}, 0, 0 },
+ { "EBP", 9, {0, {0}}, 0, 0 },
+ { "ERP", 10, {0, {0}}, 0, 0 },
+ { "NRP", 12, {0, {0}}, 0, 0 },
+ { "CCS", 13, {0, {0}}, 0, 0 },
+ { "USP", 14, {0, {0}}, 0, 0 },
+ { "SPC", 15, {0, {0}}, 0, 0 },
+ { "VR", 1, {0, {0}}, 0, 0 },
+ { "SRP", 11, {0, {0}}, 0, 0 },
+ { "P0", 0, {0, {0}}, 0, 0 },
+ { "P1", 1, {0, {0}}, 0, 0 },
+ { "P2", 2, {0, {0}}, 0, 0 },
+ { "P3", 3, {0, {0}}, 0, 0 },
+ { "P4", 4, {0, {0}}, 0, 0 },
+ { "P5", 5, {0, {0}}, 0, 0 },
+ { "P6", 6, {0, {0}}, 0, 0 },
+ { "P7", 7, {0, {0}}, 0, 0 },
+ { "P8", 8, {0, {0}}, 0, 0 },
+ { "P9", 9, {0, {0}}, 0, 0 },
+ { "P10", 10, {0, {0}}, 0, 0 },
+ { "P11", 11, {0, {0}}, 0, 0 },
+ { "P12", 12, {0, {0}}, 0, 0 },
+ { "P13", 13, {0, {0}}, 0, 0 },
+ { "P14", 14, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD cris_cgen_opval_p_names_v32 =
+{
+ & cris_cgen_opval_p_names_v32_entries[0],
+ 31,
+ 0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY cris_cgen_opval_p_names_v32_x_entries[] =
+{
+ { "BZ", 0, {0, {0}}, 0, 0 },
+ { "PID", 2, {0, {0}}, 0, 0 },
+ { "SRS", 3, {0, {0}}, 0, 0 },
+ { "WZ", 4, {0, {0}}, 0, 0 },
+ { "EXS", 5, {0, {0}}, 0, 0 },
+ { "EDA", 6, {0, {0}}, 0, 0 },
+ { "MOF", 7, {0, {0}}, 0, 0 },
+ { "DZ", 8, {0, {0}}, 0, 0 },
+ { "EBP", 9, {0, {0}}, 0, 0 },
+ { "ERP", 10, {0, {0}}, 0, 0 },
+ { "NRP", 12, {0, {0}}, 0, 0 },
+ { "CCS", 13, {0, {0}}, 0, 0 },
+ { "USP", 14, {0, {0}}, 0, 0 },
+ { "SPC", 15, {0, {0}}, 0, 0 },
+ { "VR", 1, {0, {0}}, 0, 0 },
+ { "SRP", 11, {0, {0}}, 0, 0 },
+ { "P0", 0, {0, {0}}, 0, 0 },
+ { "P1", 1, {0, {0}}, 0, 0 },
+ { "P2", 2, {0, {0}}, 0, 0 },
+ { "P3", 3, {0, {0}}, 0, 0 },
+ { "P4", 4, {0, {0}}, 0, 0 },
+ { "P5", 5, {0, {0}}, 0, 0 },
+ { "P6", 6, {0, {0}}, 0, 0 },
+ { "P7", 7, {0, {0}}, 0, 0 },
+ { "P8", 8, {0, {0}}, 0, 0 },
+ { "P9", 9, {0, {0}}, 0, 0 },
+ { "P10", 10, {0, {0}}, 0, 0 },
+ { "P11", 11, {0, {0}}, 0, 0 },
+ { "P12", 12, {0, {0}}, 0, 0 },
+ { "P13", 13, {0, {0}}, 0, 0 },
+ { "P14", 14, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD cris_cgen_opval_p_names_v32_x =
+{
+ & cris_cgen_opval_p_names_v32_x_entries[0],
+ 31,
+ 0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_inc_entries[] =
+{
+ { "", 0, {0, {0}}, 0, 0 },
+ { "+", 1, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD cris_cgen_opval_h_inc =
+{
+ & cris_cgen_opval_h_inc_entries[0],
+ 2,
+ 0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_ccode_entries[] =
+{
+ { "cc", 0, {0, {0}}, 0, 0 },
+ { "cs", 1, {0, {0}}, 0, 0 },
+ { "ne", 2, {0, {0}}, 0, 0 },
+ { "eq", 3, {0, {0}}, 0, 0 },
+ { "vc", 4, {0, {0}}, 0, 0 },
+ { "vs", 5, {0, {0}}, 0, 0 },
+ { "pl", 6, {0, {0}}, 0, 0 },
+ { "mi", 7, {0, {0}}, 0, 0 },
+ { "ls", 8, {0, {0}}, 0, 0 },
+ { "hi", 9, {0, {0}}, 0, 0 },
+ { "ge", 10, {0, {0}}, 0, 0 },
+ { "lt", 11, {0, {0}}, 0, 0 },
+ { "gt", 12, {0, {0}}, 0, 0 },
+ { "le", 13, {0, {0}}, 0, 0 },
+ { "a", 14, {0, {0}}, 0, 0 },
+ { "wf", 15, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD cris_cgen_opval_h_ccode =
+{
+ & cris_cgen_opval_h_ccode_entries[0],
+ 16,
+ 0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_swap_entries[] =
+{
+ { " ", 0, {0, {0}}, 0, 0 },
+ { "r", 1, {0, {0}}, 0, 0 },
+ { "b", 2, {0, {0}}, 0, 0 },
+ { "br", 3, {0, {0}}, 0, 0 },
+ { "w", 4, {0, {0}}, 0, 0 },
+ { "wr", 5, {0, {0}}, 0, 0 },
+ { "wb", 6, {0, {0}}, 0, 0 },
+ { "wbr", 7, {0, {0}}, 0, 0 },
+ { "n", 8, {0, {0}}, 0, 0 },
+ { "nr", 9, {0, {0}}, 0, 0 },
+ { "nb", 10, {0, {0}}, 0, 0 },
+ { "nbr", 11, {0, {0}}, 0, 0 },
+ { "nw", 12, {0, {0}}, 0, 0 },
+ { "nwr", 13, {0, {0}}, 0, 0 },
+ { "nwb", 14, {0, {0}}, 0, 0 },
+ { "nwbr", 15, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD cris_cgen_opval_h_swap =
+{
+ & cris_cgen_opval_h_swap_entries[0],
+ 16,
+ 0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_flagbits_entries[] =
+{
+ { "_", 0, {0, {0}}, 0, 0 },
+ { "c", 1, {0, {0}}, 0, 0 },
+ { "v", 2, {0, {0}}, 0, 0 },
+ { "cv", 3, {0, {0}}, 0, 0 },
+ { "z", 4, {0, {0}}, 0, 0 },
+ { "cz", 5, {0, {0}}, 0, 0 },
+ { "vz", 6, {0, {0}}, 0, 0 },
+ { "cvz", 7, {0, {0}}, 0, 0 },
+ { "n", 8, {0, {0}}, 0, 0 },
+ { "cn", 9, {0, {0}}, 0, 0 },
+ { "vn", 10, {0, {0}}, 0, 0 },
+ { "cvn", 11, {0, {0}}, 0, 0 },
+ { "zn", 12, {0, {0}}, 0, 0 },
+ { "czn", 13, {0, {0}}, 0, 0 },
+ { "vzn", 14, {0, {0}}, 0, 0 },
+ { "cvzn", 15, {0, {0}}, 0, 0 },
+ { "x", 16, {0, {0}}, 0, 0 },
+ { "cx", 17, {0, {0}}, 0, 0 },
+ { "vx", 18, {0, {0}}, 0, 0 },
+ { "cvx", 19, {0, {0}}, 0, 0 },
+ { "zx", 20, {0, {0}}, 0, 0 },
+ { "czx", 21, {0, {0}}, 0, 0 },
+ { "vzx", 22, {0, {0}}, 0, 0 },
+ { "cvzx", 23, {0, {0}}, 0, 0 },
+ { "nx", 24, {0, {0}}, 0, 0 },
+ { "cnx", 25, {0, {0}}, 0, 0 },
+ { "vnx", 26, {0, {0}}, 0, 0 },
+ { "cvnx", 27, {0, {0}}, 0, 0 },
+ { "znx", 28, {0, {0}}, 0, 0 },
+ { "cznx", 29, {0, {0}}, 0, 0 },
+ { "vznx", 30, {0, {0}}, 0, 0 },
+ { "cvznx", 31, {0, {0}}, 0, 0 },
+ { "i", 32, {0, {0}}, 0, 0 },
+ { "ci", 33, {0, {0}}, 0, 0 },
+ { "vi", 34, {0, {0}}, 0, 0 },
+ { "cvi", 35, {0, {0}}, 0, 0 },
+ { "zi", 36, {0, {0}}, 0, 0 },
+ { "czi", 37, {0, {0}}, 0, 0 },
+ { "vzi", 38, {0, {0}}, 0, 0 },
+ { "cvzi", 39, {0, {0}}, 0, 0 },
+ { "ni", 40, {0, {0}}, 0, 0 },
+ { "cni", 41, {0, {0}}, 0, 0 },
+ { "vni", 42, {0, {0}}, 0, 0 },
+ { "cvni", 43, {0, {0}}, 0, 0 },
+ { "zni", 44, {0, {0}}, 0, 0 },
+ { "czni", 45, {0, {0}}, 0, 0 },
+ { "vzni", 46, {0, {0}}, 0, 0 },
+ { "cvzni", 47, {0, {0}}, 0, 0 },
+ { "xi", 48, {0, {0}}, 0, 0 },
+ { "cxi", 49, {0, {0}}, 0, 0 },
+ { "vxi", 50, {0, {0}}, 0, 0 },
+ { "cvxi", 51, {0, {0}}, 0, 0 },
+ { "zxi", 52, {0, {0}}, 0, 0 },
+ { "czxi", 53, {0, {0}}, 0, 0 },
+ { "vzxi", 54, {0, {0}}, 0, 0 },
+ { "cvzxi", 55, {0, {0}}, 0, 0 },
+ { "nxi", 56, {0, {0}}, 0, 0 },
+ { "cnxi", 57, {0, {0}}, 0, 0 },
+ { "vnxi", 58, {0, {0}}, 0, 0 },
+ { "cvnxi", 59, {0, {0}}, 0, 0 },
+ { "znxi", 60, {0, {0}}, 0, 0 },
+ { "cznxi", 61, {0, {0}}, 0, 0 },
+ { "vznxi", 62, {0, {0}}, 0, 0 },
+ { "cvznxi", 63, {0, {0}}, 0, 0 },
+ { "u", 64, {0, {0}}, 0, 0 },
+ { "cu", 65, {0, {0}}, 0, 0 },
+ { "vu", 66, {0, {0}}, 0, 0 },
+ { "cvu", 67, {0, {0}}, 0, 0 },
+ { "zu", 68, {0, {0}}, 0, 0 },
+ { "czu", 69, {0, {0}}, 0, 0 },
+ { "vzu", 70, {0, {0}}, 0, 0 },
+ { "cvzu", 71, {0, {0}}, 0, 0 },
+ { "nu", 72, {0, {0}}, 0, 0 },
+ { "cnu", 73, {0, {0}}, 0, 0 },
+ { "vnu", 74, {0, {0}}, 0, 0 },
+ { "cvnu", 75, {0, {0}}, 0, 0 },
+ { "znu", 76, {0, {0}}, 0, 0 },
+ { "cznu", 77, {0, {0}}, 0, 0 },
+ { "vznu", 78, {0, {0}}, 0, 0 },
+ { "cvznu", 79, {0, {0}}, 0, 0 },
+ { "xu", 80, {0, {0}}, 0, 0 },
+ { "cxu", 81, {0, {0}}, 0, 0 },
+ { "vxu", 82, {0, {0}}, 0, 0 },
+ { "cvxu", 83, {0, {0}}, 0, 0 },
+ { "zxu", 84, {0, {0}}, 0, 0 },
+ { "czxu", 85, {0, {0}}, 0, 0 },
+ { "vzxu", 86, {0, {0}}, 0, 0 },
+ { "cvzxu", 87, {0, {0}}, 0, 0 },
+ { "nxu", 88, {0, {0}}, 0, 0 },
+ { "cnxu", 89, {0, {0}}, 0, 0 },
+ { "vnxu", 90, {0, {0}}, 0, 0 },
+ { "cvnxu", 91, {0, {0}}, 0, 0 },
+ { "znxu", 92, {0, {0}}, 0, 0 },
+ { "cznxu", 93, {0, {0}}, 0, 0 },
+ { "vznxu", 94, {0, {0}}, 0, 0 },
+ { "cvznxu", 95, {0, {0}}, 0, 0 },
+ { "iu", 96, {0, {0}}, 0, 0 },
+ { "ciu", 97, {0, {0}}, 0, 0 },
+ { "viu", 98, {0, {0}}, 0, 0 },
+ { "cviu", 99, {0, {0}}, 0, 0 },
+ { "ziu", 100, {0, {0}}, 0, 0 },
+ { "cziu", 101, {0, {0}}, 0, 0 },
+ { "vziu", 102, {0, {0}}, 0, 0 },
+ { "cvziu", 103, {0, {0}}, 0, 0 },
+ { "niu", 104, {0, {0}}, 0, 0 },
+ { "cniu", 105, {0, {0}}, 0, 0 },
+ { "vniu", 106, {0, {0}}, 0, 0 },
+ { "cvniu", 107, {0, {0}}, 0, 0 },
+ { "zniu", 108, {0, {0}}, 0, 0 },
+ { "czniu", 109, {0, {0}}, 0, 0 },
+ { "vzniu", 110, {0, {0}}, 0, 0 },
+ { "cvzniu", 111, {0, {0}}, 0, 0 },
+ { "xiu", 112, {0, {0}}, 0, 0 },
+ { "cxiu", 113, {0, {0}}, 0, 0 },
+ { "vxiu", 114, {0, {0}}, 0, 0 },
+ { "cvxiu", 115, {0, {0}}, 0, 0 },
+ { "zxiu", 116, {0, {0}}, 0, 0 },
+ { "czxiu", 117, {0, {0}}, 0, 0 },
+ { "vzxiu", 118, {0, {0}}, 0, 0 },
+ { "cvzxiu", 119, {0, {0}}, 0, 0 },
+ { "nxiu", 120, {0, {0}}, 0, 0 },
+ { "cnxiu", 121, {0, {0}}, 0, 0 },
+ { "vnxiu", 122, {0, {0}}, 0, 0 },
+ { "cvnxiu", 123, {0, {0}}, 0, 0 },
+ { "znxiu", 124, {0, {0}}, 0, 0 },
+ { "cznxiu", 125, {0, {0}}, 0, 0 },
+ { "vznxiu", 126, {0, {0}}, 0, 0 },
+ { "cvznxiu", 127, {0, {0}}, 0, 0 },
+ { "p", 128, {0, {0}}, 0, 0 },
+ { "cp", 129, {0, {0}}, 0, 0 },
+ { "vp", 130, {0, {0}}, 0, 0 },
+ { "cvp", 131, {0, {0}}, 0, 0 },
+ { "zp", 132, {0, {0}}, 0, 0 },
+ { "czp", 133, {0, {0}}, 0, 0 },
+ { "vzp", 134, {0, {0}}, 0, 0 },
+ { "cvzp", 135, {0, {0}}, 0, 0 },
+ { "np", 136, {0, {0}}, 0, 0 },
+ { "cnp", 137, {0, {0}}, 0, 0 },
+ { "vnp", 138, {0, {0}}, 0, 0 },
+ { "cvnp", 139, {0, {0}}, 0, 0 },
+ { "znp", 140, {0, {0}}, 0, 0 },
+ { "cznp", 141, {0, {0}}, 0, 0 },
+ { "vznp", 142, {0, {0}}, 0, 0 },
+ { "cvznp", 143, {0, {0}}, 0, 0 },
+ { "xp", 144, {0, {0}}, 0, 0 },
+ { "cxp", 145, {0, {0}}, 0, 0 },
+ { "vxp", 146, {0, {0}}, 0, 0 },
+ { "cvxp", 147, {0, {0}}, 0, 0 },
+ { "zxp", 148, {0, {0}}, 0, 0 },
+ { "czxp", 149, {0, {0}}, 0, 0 },
+ { "vzxp", 150, {0, {0}}, 0, 0 },
+ { "cvzxp", 151, {0, {0}}, 0, 0 },
+ { "nxp", 152, {0, {0}}, 0, 0 },
+ { "cnxp", 153, {0, {0}}, 0, 0 },
+ { "vnxp", 154, {0, {0}}, 0, 0 },
+ { "cvnxp", 155, {0, {0}}, 0, 0 },
+ { "znxp", 156, {0, {0}}, 0, 0 },
+ { "cznxp", 157, {0, {0}}, 0, 0 },
+ { "vznxp", 158, {0, {0}}, 0, 0 },
+ { "cvznxp", 159, {0, {0}}, 0, 0 },
+ { "ip", 160, {0, {0}}, 0, 0 },
+ { "cip", 161, {0, {0}}, 0, 0 },
+ { "vip", 162, {0, {0}}, 0, 0 },
+ { "cvip", 163, {0, {0}}, 0, 0 },
+ { "zip", 164, {0, {0}}, 0, 0 },
+ { "czip", 165, {0, {0}}, 0, 0 },
+ { "vzip", 166, {0, {0}}, 0, 0 },
+ { "cvzip", 167, {0, {0}}, 0, 0 },
+ { "nip", 168, {0, {0}}, 0, 0 },
+ { "cnip", 169, {0, {0}}, 0, 0 },
+ { "vnip", 170, {0, {0}}, 0, 0 },
+ { "cvnip", 171, {0, {0}}, 0, 0 },
+ { "znip", 172, {0, {0}}, 0, 0 },
+ { "cznip", 173, {0, {0}}, 0, 0 },
+ { "vznip", 174, {0, {0}}, 0, 0 },
+ { "cvznip", 175, {0, {0}}, 0, 0 },
+ { "xip", 176, {0, {0}}, 0, 0 },
+ { "cxip", 177, {0, {0}}, 0, 0 },
+ { "vxip", 178, {0, {0}}, 0, 0 },
+ { "cvxip", 179, {0, {0}}, 0, 0 },
+ { "zxip", 180, {0, {0}}, 0, 0 },
+ { "czxip", 181, {0, {0}}, 0, 0 },
+ { "vzxip", 182, {0, {0}}, 0, 0 },
+ { "cvzxip", 183, {0, {0}}, 0, 0 },
+ { "nxip", 184, {0, {0}}, 0, 0 },
+ { "cnxip", 185, {0, {0}}, 0, 0 },
+ { "vnxip", 186, {0, {0}}, 0, 0 },
+ { "cvnxip", 187, {0, {0}}, 0, 0 },
+ { "znxip", 188, {0, {0}}, 0, 0 },
+ { "cznxip", 189, {0, {0}}, 0, 0 },
+ { "vznxip", 190, {0, {0}}, 0, 0 },
+ { "cvznxip", 191, {0, {0}}, 0, 0 },
+ { "up", 192, {0, {0}}, 0, 0 },
+ { "cup", 193, {0, {0}}, 0, 0 },
+ { "vup", 194, {0, {0}}, 0, 0 },
+ { "cvup", 195, {0, {0}}, 0, 0 },
+ { "zup", 196, {0, {0}}, 0, 0 },
+ { "czup", 197, {0, {0}}, 0, 0 },
+ { "vzup", 198, {0, {0}}, 0, 0 },
+ { "cvzup", 199, {0, {0}}, 0, 0 },
+ { "nup", 200, {0, {0}}, 0, 0 },
+ { "cnup", 201, {0, {0}}, 0, 0 },
+ { "vnup", 202, {0, {0}}, 0, 0 },
+ { "cvnup", 203, {0, {0}}, 0, 0 },
+ { "znup", 204, {0, {0}}, 0, 0 },
+ { "cznup", 205, {0, {0}}, 0, 0 },
+ { "vznup", 206, {0, {0}}, 0, 0 },
+ { "cvznup", 207, {0, {0}}, 0, 0 },
+ { "xup", 208, {0, {0}}, 0, 0 },
+ { "cxup", 209, {0, {0}}, 0, 0 },
+ { "vxup", 210, {0, {0}}, 0, 0 },
+ { "cvxup", 211, {0, {0}}, 0, 0 },
+ { "zxup", 212, {0, {0}}, 0, 0 },
+ { "czxup", 213, {0, {0}}, 0, 0 },
+ { "vzxup", 214, {0, {0}}, 0, 0 },
+ { "cvzxup", 215, {0, {0}}, 0, 0 },
+ { "nxup", 216, {0, {0}}, 0, 0 },
+ { "cnxup", 217, {0, {0}}, 0, 0 },
+ { "vnxup", 218, {0, {0}}, 0, 0 },
+ { "cvnxup", 219, {0, {0}}, 0, 0 },
+ { "znxup", 220, {0, {0}}, 0, 0 },
+ { "cznxup", 221, {0, {0}}, 0, 0 },
+ { "vznxup", 222, {0, {0}}, 0, 0 },
+ { "cvznxup", 223, {0, {0}}, 0, 0 },
+ { "iup", 224, {0, {0}}, 0, 0 },
+ { "ciup", 225, {0, {0}}, 0, 0 },
+ { "viup", 226, {0, {0}}, 0, 0 },
+ { "cviup", 227, {0, {0}}, 0, 0 },
+ { "ziup", 228, {0, {0}}, 0, 0 },
+ { "cziup", 229, {0, {0}}, 0, 0 },
+ { "vziup", 230, {0, {0}}, 0, 0 },
+ { "cvziup", 231, {0, {0}}, 0, 0 },
+ { "niup", 232, {0, {0}}, 0, 0 },
+ { "cniup", 233, {0, {0}}, 0, 0 },
+ { "vniup", 234, {0, {0}}, 0, 0 },
+ { "cvniup", 235, {0, {0}}, 0, 0 },
+ { "zniup", 236, {0, {0}}, 0, 0 },
+ { "czniup", 237, {0, {0}}, 0, 0 },
+ { "vzniup", 238, {0, {0}}, 0, 0 },
+ { "cvzniup", 239, {0, {0}}, 0, 0 },
+ { "xiup", 240, {0, {0}}, 0, 0 },
+ { "cxiup", 241, {0, {0}}, 0, 0 },
+ { "vxiup", 242, {0, {0}}, 0, 0 },
+ { "cvxiup", 243, {0, {0}}, 0, 0 },
+ { "zxiup", 244, {0, {0}}, 0, 0 },
+ { "czxiup", 245, {0, {0}}, 0, 0 },
+ { "vzxiup", 246, {0, {0}}, 0, 0 },
+ { "cvzxiup", 247, {0, {0}}, 0, 0 },
+ { "nxiup", 248, {0, {0}}, 0, 0 },
+ { "cnxiup", 249, {0, {0}}, 0, 0 },
+ { "vnxiup", 250, {0, {0}}, 0, 0 },
+ { "cvnxiup", 251, {0, {0}}, 0, 0 },
+ { "znxiup", 252, {0, {0}}, 0, 0 },
+ { "cznxiup", 253, {0, {0}}, 0, 0 },
+ { "vznxiup", 254, {0, {0}}, 0, 0 },
+ { "cvznxiup", 255, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD cris_cgen_opval_h_flagbits =
+{
+ & cris_cgen_opval_h_flagbits_entries[0],
+ 256,
+ 0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY cris_cgen_opval_h_supr_entries[] =
+{
+ { "S0", 0, {0, {0}}, 0, 0 },
+ { "S1", 1, {0, {0}}, 0, 0 },
+ { "S2", 2, {0, {0}}, 0, 0 },
+ { "S3", 3, {0, {0}}, 0, 0 },
+ { "S4", 4, {0, {0}}, 0, 0 },
+ { "S5", 5, {0, {0}}, 0, 0 },
+ { "S6", 6, {0, {0}}, 0, 0 },
+ { "S7", 7, {0, {0}}, 0, 0 },
+ { "S8", 8, {0, {0}}, 0, 0 },
+ { "S9", 9, {0, {0}}, 0, 0 },
+ { "S10", 10, {0, {0}}, 0, 0 },
+ { "S11", 11, {0, {0}}, 0, 0 },
+ { "S12", 12, {0, {0}}, 0, 0 },
+ { "S13", 13, {0, {0}}, 0, 0 },
+ { "S14", 14, {0, {0}}, 0, 0 },
+ { "S15", 15, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD cris_cgen_opval_h_supr =
+{
+ & cris_cgen_opval_h_supr_entries[0],
+ 16,
+ 0, 0, 0, 0, ""
+};
+
+
+/* The hardware table. */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_HW_##a)
+#else
+#define A(a) (1 << CGEN_HW_/**/a)
+#endif
+
+const CGEN_HW_ENTRY cris_cgen_hw_table[] =
+{
+ { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-inc", HW_H_INC, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_h_inc, { 0, { (1<<MACH_BASE) } } },
+ { "h-ccode", HW_H_CCODE, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_h_ccode, { 0, { (1<<MACH_BASE) } } },
+ { "h-swap", HW_H_SWAP, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_h_swap, { 0, { (1<<MACH_BASE) } } },
+ { "h-flagbits", HW_H_FLAGBITS, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_h_flagbits, { 0, { (1<<MACH_BASE) } } },
+ { "h-v32-v32", HW_H_V32, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_CRISV32) } } },
+ { "h-v32-non-v32", HW_H_V32, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } } },
+ { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
+ { "h-gr", HW_H_GR, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-gr-pc", HW_H_GR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_gr_names_pcreg, { 0|A(VIRTUAL), { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } } },
+ { "h-gr-real-pc", HW_H_GR_REAL_PC, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_gr_names_pcreg, { 0, { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } } },
+ { "h-raw-gr-pc", HW_H_RAW_GR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } } },
+ { "h-gr-acr", HW_H_GR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_gr_names_acr, { 0, { (1<<MACH_CRISV32) } } },
+ { "h-raw-gr-acr", HW_H_RAW_GR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_CRISV32) } } },
+ { "h-sr", HW_H_SR, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-sr-v0", HW_H_SR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_p_names_v10, { 0, { (1<<MACH_CRISV0) } } },
+ { "h-sr-v3", HW_H_SR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_p_names_v10, { 0, { (1<<MACH_CRISV3) } } },
+ { "h-sr-v8", HW_H_SR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_p_names_v10, { 0, { (1<<MACH_CRISV8) } } },
+ { "h-sr-v10", HW_H_SR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_p_names_v10, { 0, { (1<<MACH_CRISV10) } } },
+ { "h-sr-v32", HW_H_SR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_p_names_v32, { 0, { (1<<MACH_CRISV32) } } },
+ { "h-supr", HW_H_SUPR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_CRISV32) } } },
+ { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-cbit-move", HW_H_CBIT_MOVE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-cbit-move-v32", HW_H_CBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_CRISV32) } } },
+ { "h-cbit-move-pre-v32", HW_H_CBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } } },
+ { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-vbit-move", HW_H_VBIT_MOVE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-vbit-move-v32", HW_H_VBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_CRISV32) } } },
+ { "h-vbit-move-pre-v32", HW_H_VBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } } },
+ { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-zbit-move", HW_H_ZBIT_MOVE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-zbit-move-v32", HW_H_ZBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_CRISV32) } } },
+ { "h-zbit-move-pre-v32", HW_H_ZBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } } },
+ { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-nbit-move", HW_H_NBIT_MOVE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-nbit-move-v32", HW_H_NBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_CRISV32) } } },
+ { "h-nbit-move-pre-v32", HW_H_NBIT_MOVE_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } } },
+ { "h-xbit", HW_H_XBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-ibit-pre-v32", HW_H_IBIT_X, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } } },
+ { "h-pbit", HW_H_PBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_CRISV10)|(1<<MACH_CRISV32) } } },
+ { "h-rbit", HW_H_RBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_CRISV32) } } },
+ { "h-ubit", HW_H_UBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-ubit-pre-v32", HW_H_UBIT_X, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_CRISV10) } } },
+ { "h-gbit", HW_H_GBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_CRISV32) } } },
+ { "h-kernel-sp", HW_H_KERNEL_SP, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_CRISV32) } } },
+ { "h-ubit-v32", HW_H_UBIT_X, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_CRISV32) } } },
+ { "h-ibit-v32", HW_H_IBIT_X, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_CRISV32) } } },
+ { "h-mbit", HW_H_MBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_CRISV32) } } },
+ { "h-qbit", HW_H_QBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_CRISV32) } } },
+ { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_CRISV32) } } },
+ { "h-insn-prefixed-p", HW_H_INSN_PREFIXED_P, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-insn-prefixed-p-pre-v32", HW_H_INSN_PREFIXED_P_X, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } } },
+ { "h-insn-prefixed-p-v32", HW_H_INSN_PREFIXED_P_X, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_CRISV32) } } },
+ { "h-prefixreg-pre-v32", HW_H_PREFIXREG, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } } },
+ { "h-prefixreg-v32", HW_H_PREFIXREG, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_CRISV32) } } },
+ { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
+};
+
+#undef A
+
+
+/* The instruction field table. */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_IFLD_##a)
+#else
+#define A(a) (1 << CGEN_IFLD_/**/a)
+#endif
+
+const CGEN_IFLD cris_cgen_ifld_table[] =
+{
+ { CRIS_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
+ { CRIS_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
+ { CRIS_F_OPERAND1, "f-operand1", 0, 16, 3, 4, { 0, { (1<<MACH_BASE) } } },
+ { CRIS_F_SIZE, "f-size", 0, 16, 5, 2, { 0, { (1<<MACH_BASE) } } },
+ { CRIS_F_OPCODE, "f-opcode", 0, 16, 9, 4, { 0, { (1<<MACH_BASE) } } },
+ { CRIS_F_MODE, "f-mode", 0, 16, 11, 2, { 0, { (1<<MACH_BASE) } } },
+ { CRIS_F_OPERAND2, "f-operand2", 0, 16, 15, 4, { 0, { (1<<MACH_BASE) } } },
+ { CRIS_F_MEMMODE, "f-memmode", 0, 16, 10, 1, { 0, { (1<<MACH_BASE) } } },
+ { CRIS_F_MEMBIT, "f-membit", 0, 16, 11, 1, { 0, { (1<<MACH_BASE) } } },
+ { CRIS_F_B5, "f-b5", 0, 16, 5, 1, { 0, { (1<<MACH_BASE) } } },
+ { CRIS_F_OPCODE_HI, "f-opcode-hi", 0, 16, 9, 2, { 0, { (1<<MACH_BASE) } } },
+ { CRIS_F_DSTSRC, "f-dstsrc", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { CRIS_F_U6, "f-u6", 0, 16, 5, 6, { 0, { (1<<MACH_BASE) } } },
+ { CRIS_F_S6, "f-s6", 0, 16, 5, 6, { 0, { (1<<MACH_BASE) } } },
+ { CRIS_F_U5, "f-u5", 0, 16, 4, 5, { 0, { (1<<MACH_BASE) } } },
+ { CRIS_F_U4, "f-u4", 0, 16, 3, 4, { 0, { (1<<MACH_BASE) } } },
+ { CRIS_F_S8, "f-s8", 0, 16, 7, 8, { 0, { (1<<MACH_BASE) } } },
+ { CRIS_F_DISP9_HI, "f-disp9-hi", 0, 16, 0, 1, { 0, { (1<<MACH_BASE) } } },
+ { CRIS_F_DISP9_LO, "f-disp9-lo", 0, 16, 7, 7, { 0, { (1<<MACH_BASE) } } },
+ { CRIS_F_DISP9, "f-disp9", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { CRIS_F_QO, "f-qo", 0, 16, 3, 4, { 0|A(PCREL_ADDR), { (1<<MACH_CRISV32) } } },
+ { CRIS_F_INDIR_PC__BYTE, "f-indir-pc+-byte", 16, 16, 15, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
+ { CRIS_F_INDIR_PC__WORD, "f-indir-pc+-word", 16, 16, 15, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
+ { CRIS_F_INDIR_PC__WORD_PCREL, "f-indir-pc+-word-pcrel", 16, 16, 15, 16, { 0|A(SIGN_OPT)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
+ { CRIS_F_INDIR_PC__DWORD, "f-indir-pc+-dword", 16, 32, 31, 32, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
+ { CRIS_F_INDIR_PC__DWORD_PCREL, "f-indir-pc+-dword-pcrel", 16, 32, 31, 32, { 0|A(PCREL_ADDR)|A(SIGN_OPT), { (1<<MACH_CRISV32) } } },
+ { 0, 0, 0, 0, 0, 0, {0, {0}} }
+};
+
+#undef A
+
+
+
+/* multi ifield declarations */
+
+const CGEN_MAYBE_MULTI_IFLD CRIS_F_DSTSRC_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD CRIS_F_DISP9_MULTI_IFIELD [];
+
+
+/* multi ifield definitions */
+
+const CGEN_MAYBE_MULTI_IFLD CRIS_F_DSTSRC_MULTI_IFIELD [] =
+{
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND1] } },
+ { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD CRIS_F_DISP9_MULTI_IFIELD [] =
+{
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_DISP9_HI] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_DISP9_LO] } },
+ { 0, { (const PTR) 0 } }
+};
+
+/* The operand table. */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_OPERAND_##a)
+#else
+#define A(a) (1 << CGEN_OPERAND_/**/a)
+#endif
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define OPERAND(op) CRIS_OPERAND_##op
+#else
+#define OPERAND(op) CRIS_OPERAND_/**/op
+#endif
+
+const CGEN_OPERAND cris_cgen_operand_table[] =
+{
+/* pc: program counter */
+ { "pc", CRIS_OPERAND_PC, HW_H_PC, 0, 0,
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_NIL] } },
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* cbit: */
+ { "cbit", CRIS_OPERAND_CBIT, HW_H_CBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* cbit-move: cbit for pre-V32, nothing for newer */
+ { "cbit-move", CRIS_OPERAND_CBIT_MOVE, HW_H_CBIT_MOVE, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* vbit: */
+ { "vbit", CRIS_OPERAND_VBIT, HW_H_VBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* vbit-move: vbit for pre-V32, nothing for newer */
+ { "vbit-move", CRIS_OPERAND_VBIT_MOVE, HW_H_VBIT_MOVE, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* zbit: */
+ { "zbit", CRIS_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* zbit-move: zbit for pre-V32, nothing for newer */
+ { "zbit-move", CRIS_OPERAND_ZBIT_MOVE, HW_H_ZBIT_MOVE, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* nbit: */
+ { "nbit", CRIS_OPERAND_NBIT, HW_H_NBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* nbit-move: nbit for pre-V32, nothing for newer */
+ { "nbit-move", CRIS_OPERAND_NBIT_MOVE, HW_H_NBIT_MOVE, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* xbit: */
+ { "xbit", CRIS_OPERAND_XBIT, HW_H_XBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* ibit: */
+ { "ibit", CRIS_OPERAND_IBIT, HW_H_IBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* ubit: */
+ { "ubit", CRIS_OPERAND_UBIT, HW_H_UBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { (1<<MACH_CRISV10)|(1<<MACH_CRISV32) } } },
+/* pbit: */
+ { "pbit", CRIS_OPERAND_PBIT, HW_H_PBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { (1<<MACH_CRISV10)|(1<<MACH_CRISV32) } } },
+/* rbit: carry bit for MCP+restore-P flag bit */
+ { "rbit", CRIS_OPERAND_RBIT, HW_H_RBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { (1<<MACH_CRISV32) } } },
+/* sbit: */
+ { "sbit", CRIS_OPERAND_SBIT, HW_H_SBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { (1<<MACH_CRISV32) } } },
+/* mbit: */
+ { "mbit", CRIS_OPERAND_MBIT, HW_H_MBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { (1<<MACH_CRISV32) } } },
+/* qbit: */
+ { "qbit", CRIS_OPERAND_QBIT, HW_H_QBIT, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { (1<<MACH_CRISV32) } } },
+/* prefix-set: Instruction-prefixed flag */
+ { "prefix-set", CRIS_OPERAND_PREFIX_SET, HW_H_INSN_PREFIXED_P, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* prefixreg: Prefix address */
+ { "prefixreg", CRIS_OPERAND_PREFIXREG, HW_H_PREFIXREG, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
+/* Rs: Source general register */
+ { "Rs", CRIS_OPERAND_RS, HW_H_GR, 3, 4,
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND1] } },
+ { 0, { (1<<MACH_BASE) } } },
+/* inc: Incrementness of indirect operand */
+ { "inc", CRIS_OPERAND_INC, HW_H_INC, 10, 1,
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_MEMMODE] } },
+ { 0, { (1<<MACH_BASE) } } },
+/* Ps: Source special register */
+ { "Ps", CRIS_OPERAND_PS, HW_H_SR, 15, 4,
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
+ { 0, { (1<<MACH_BASE) } } },
+/* Ss: Source support register */
+ { "Ss", CRIS_OPERAND_SS, HW_H_SUPR, 15, 4,
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
+ { 0, { (1<<MACH_CRISV32) } } },
+/* Sd: Destination support register */
+ { "Sd", CRIS_OPERAND_SD, HW_H_SUPR, 15, 4,
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
+ { 0, { (1<<MACH_CRISV32) } } },
+/* i: Quick signed 6-bit */
+ { "i", CRIS_OPERAND_I, HW_H_SINT, 5, 6,
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_S6] } },
+ { 0, { (1<<MACH_BASE) } } },
+/* j: Quick unsigned 6-bit */
+ { "j", CRIS_OPERAND_J, HW_H_UINT, 5, 6,
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_U6] } },
+ { 0, { (1<<MACH_BASE) } } },
+/* c: Quick unsigned 5-bit */
+ { "c", CRIS_OPERAND_C, HW_H_UINT, 4, 5,
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_U5] } },
+ { 0, { (1<<MACH_BASE) } } },
+/* qo: Quick unsigned 4-bit, PC-relative */
+ { "qo", CRIS_OPERAND_QO, HW_H_ADDR, 3, 4,
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_QO] } },
+ { 0|A(PCREL_ADDR), { (1<<MACH_CRISV32) } } },
+/* Rd: Destination general register */
+ { "Rd", CRIS_OPERAND_RD, HW_H_GR, 15, 4,
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
+ { 0, { (1<<MACH_BASE) } } },
+/* sconst8: Signed byte [PC+] */
+ { "sconst8", CRIS_OPERAND_SCONST8, HW_H_SINT, 15, 16,
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__BYTE] } },
+ { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
+/* uconst8: Unsigned byte [PC+] */
+ { "uconst8", CRIS_OPERAND_UCONST8, HW_H_UINT, 15, 16,
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__BYTE] } },
+ { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
+/* sconst16: Signed word [PC+] */
+ { "sconst16", CRIS_OPERAND_SCONST16, HW_H_SINT, 15, 16,
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__WORD] } },
+ { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
+/* uconst16: Unsigned word [PC+] */
+ { "uconst16", CRIS_OPERAND_UCONST16, HW_H_UINT, 15, 16,
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__WORD] } },
+ { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
+/* const32: Dword [PC+] */
+ { "const32", CRIS_OPERAND_CONST32, HW_H_UINT, 31, 32,
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__DWORD] } },
+ { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
+/* const32-pcrel: Dword [PC+] */
+ { "const32-pcrel", CRIS_OPERAND_CONST32_PCREL, HW_H_ADDR, 31, 32,
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__DWORD_PCREL] } },
+ { 0|A(PCREL_ADDR)|A(SIGN_OPT), { (1<<MACH_CRISV32) } } },
+/* Pd: Destination special register */
+ { "Pd", CRIS_OPERAND_PD, HW_H_SR, 15, 4,
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
+ { 0, { (1<<MACH_BASE) } } },
+/* o: Signed 8-bit */
+ { "o", CRIS_OPERAND_O, HW_H_SINT, 7, 8,
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_S8] } },
+ { 0, { (1<<MACH_BASE) } } },
+/* o-pcrel: 9-bit signed immediate PC-rel */
+ { "o-pcrel", CRIS_OPERAND_O_PCREL, HW_H_IADDR, 0, 8,
+ { 2, { (const PTR) &CRIS_F_DISP9_MULTI_IFIELD[0] } },
+ { 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } },
+/* o-word-pcrel: 16-bit signed immediate PC-rel */
+ { "o-word-pcrel", CRIS_OPERAND_O_WORD_PCREL, HW_H_IADDR, 15, 16,
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__WORD_PCREL] } },
+ { 0|A(SIGN_OPT)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
+/* cc: Condition codes */
+ { "cc", CRIS_OPERAND_CC, HW_H_CCODE, 15, 4,
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
+ { 0, { (1<<MACH_BASE) } } },
+/* n: Quick unsigned 4-bit */
+ { "n", CRIS_OPERAND_N, HW_H_UINT, 3, 4,
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_U4] } },
+ { 0, { (1<<MACH_BASE) } } },
+/* swapoption: Swap option */
+ { "swapoption", CRIS_OPERAND_SWAPOPTION, HW_H_SWAP, 15, 4,
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
+ { 0, { (1<<MACH_BASE) } } },
+/* list-of-flags: Flag bits as operand */
+ { "list-of-flags", CRIS_OPERAND_LIST_OF_FLAGS, HW_H_FLAGBITS, 3, 8,
+ { 2, { (const PTR) &CRIS_F_DSTSRC_MULTI_IFIELD[0] } },
+ { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+/* sentinel */
+ { 0, 0, 0, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { 0 } } }
+};
+
+#undef A
+
+
+/* The instruction table. */
+
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_INSN_##a)
+#else
+#define A(a) (1 << CGEN_INSN_/**/a)
+#endif
+
+static const CGEN_IBASE cris_cgen_insn_table[MAX_INSNS] =
+{
+ /* Special null first entry.
+ A `num' value of zero is thus invalid.
+ Also, the special `invalid' insn resides here. */
+ { 0, 0, 0, 0, {0, {0}} },
+/* nop */
+ {
+ CRIS_INSN_NOP, "nop", "nop", 16,
+ { 0, { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } }
+ },
+/* move.b move.m ${Rs},${Rd} */
+ {
+ CRIS_INSN_MOVE_B_R, "move.b-r", "move.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* move.w move.m ${Rs},${Rd} */
+ {
+ CRIS_INSN_MOVE_W_R, "move.w-r", "move.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* move.d move.m ${Rs},${Rd} */
+ {
+ CRIS_INSN_MOVE_D_R, "move.d-r", "move.d", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* move.d PC,${Rd} */
+ {
+ CRIS_INSN_MOVEPCR, "movepcr", "move.d", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } }
+ },
+/* moveq $i,$Rd */
+ {
+ CRIS_INSN_MOVEQ, "moveq", "moveq", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* movs.b movs.m ${Rs},${Rd} */
+ {
+ CRIS_INSN_MOVS_B_R, "movs.b-r", "movs.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* movs.w movs.m ${Rs},${Rd} */
+ {
+ CRIS_INSN_MOVS_W_R, "movs.w-r", "movs.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* movu.b movu.m ${Rs},${Rd} */
+ {
+ CRIS_INSN_MOVU_B_R, "movu.b-r", "movu.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* movu.w movu.m ${Rs},${Rd} */
+ {
+ CRIS_INSN_MOVU_W_R, "movu.w-r", "movu.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* move.b ${sconst8},${Rd} */
+ {
+ CRIS_INSN_MOVECBR, "movecbr", "move.b", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* move.w ${sconst16},${Rd} */
+ {
+ CRIS_INSN_MOVECWR, "movecwr", "move.w", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* move.d ${const32},${Rd} */
+ {
+ CRIS_INSN_MOVECDR, "movecdr", "move.d", 48,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* movs.b ${sconst8},${Rd} */
+ {
+ CRIS_INSN_MOVSCBR, "movscbr", "movs.b", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* movs.w ${sconst16},${Rd} */
+ {
+ CRIS_INSN_MOVSCWR, "movscwr", "movs.w", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* movu.b ${uconst8},${Rd} */
+ {
+ CRIS_INSN_MOVUCBR, "movucbr", "movu.b", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* movu.w ${uconst16},${Rd} */
+ {
+ CRIS_INSN_MOVUCWR, "movucwr", "movu.w", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* addq $j,$Rd */
+ {
+ CRIS_INSN_ADDQ, "addq", "addq", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* subq $j,$Rd */
+ {
+ CRIS_INSN_SUBQ, "subq", "subq", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* cmp-r.b $Rs,$Rd */
+ {
+ CRIS_INSN_CMP_R_B_R, "cmp-r.b-r", "cmp-r.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* cmp-r.w $Rs,$Rd */
+ {
+ CRIS_INSN_CMP_R_W_R, "cmp-r.w-r", "cmp-r.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* cmp-r.d $Rs,$Rd */
+ {
+ CRIS_INSN_CMP_R_D_R, "cmp-r.d-r", "cmp-r.d", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* cmp-m.b [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_CMP_M_B_M, "cmp-m.b-m", "cmp-m.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* cmp-m.w [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_CMP_M_W_M, "cmp-m.w-m", "cmp-m.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* cmp-m.d [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_CMP_M_D_M, "cmp-m.d-m", "cmp-m.d", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* cmp.b $sconst8,$Rd */
+ {
+ CRIS_INSN_CMPCBR, "cmpcbr", "cmp.b", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* cmp.w $sconst16,$Rd */
+ {
+ CRIS_INSN_CMPCWR, "cmpcwr", "cmp.w", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* cmp.d $const32,$Rd */
+ {
+ CRIS_INSN_CMPCDR, "cmpcdr", "cmp.d", 48,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* cmpq $i,$Rd */
+ {
+ CRIS_INSN_CMPQ, "cmpq", "cmpq", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* cmps-m.b [${Rs}${inc}],$Rd */
+ {
+ CRIS_INSN_CMPS_M_B_M, "cmps-m.b-m", "cmps-m.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* cmps-m.w [${Rs}${inc}],$Rd */
+ {
+ CRIS_INSN_CMPS_M_W_M, "cmps-m.w-m", "cmps-m.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* [${Rs}${inc}],$Rd */
+ {
+ CRIS_INSN_CMPSCBR, "cmpscbr", "[", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* [${Rs}${inc}],$Rd */
+ {
+ CRIS_INSN_CMPSCWR, "cmpscwr", "[", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* cmpu-m.b [${Rs}${inc}],$Rd */
+ {
+ CRIS_INSN_CMPU_M_B_M, "cmpu-m.b-m", "cmpu-m.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* cmpu-m.w [${Rs}${inc}],$Rd */
+ {
+ CRIS_INSN_CMPU_M_W_M, "cmpu-m.w-m", "cmpu-m.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* [${Rs}${inc}],$Rd */
+ {
+ CRIS_INSN_CMPUCBR, "cmpucbr", "[", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* [${Rs}${inc}],$Rd */
+ {
+ CRIS_INSN_CMPUCWR, "cmpucwr", "[", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* move-m.b [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_MOVE_M_B_M, "move-m.b-m", "move-m.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* move-m.w [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_MOVE_M_W_M, "move-m.w-m", "move-m.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* move-m.d [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_MOVE_M_D_M, "move-m.d-m", "move-m.d", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* movs-m.b [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_MOVS_M_B_M, "movs-m.b-m", "movs-m.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* movs-m.w [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_MOVS_M_W_M, "movs-m.w-m", "movs-m.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* movu-m.b [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_MOVU_M_B_M, "movu-m.b-m", "movu-m.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* movu-m.w [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_MOVU_M_W_M, "movu-m.w-m", "movu-m.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* move ${Rs},${Pd} */
+ {
+ CRIS_INSN_MOVE_R_SPRV0, "move-r-sprv0", "move", 16,
+ { 0, { (1<<MACH_CRISV0) } }
+ },
+/* move ${Rs},${Pd} */
+ {
+ CRIS_INSN_MOVE_R_SPRV3, "move-r-sprv3", "move", 16,
+ { 0, { (1<<MACH_CRISV3) } }
+ },
+/* move ${Rs},${Pd} */
+ {
+ CRIS_INSN_MOVE_R_SPRV8, "move-r-sprv8", "move", 16,
+ { 0, { (1<<MACH_CRISV8) } }
+ },
+/* move ${Rs},${Pd} */
+ {
+ CRIS_INSN_MOVE_R_SPRV10, "move-r-sprv10", "move", 16,
+ { 0, { (1<<MACH_CRISV10) } }
+ },
+/* move ${Rs},${Pd} */
+ {
+ CRIS_INSN_MOVE_R_SPRV32, "move-r-sprv32", "move", 16,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* move ${Ps},${Rd-sfield} */
+ {
+ CRIS_INSN_MOVE_SPR_RV0, "move-spr-rv0", "move", 16,
+ { 0, { (1<<MACH_CRISV0) } }
+ },
+/* move ${Ps},${Rd-sfield} */
+ {
+ CRIS_INSN_MOVE_SPR_RV3, "move-spr-rv3", "move", 16,
+ { 0, { (1<<MACH_CRISV3) } }
+ },
+/* move ${Ps},${Rd-sfield} */
+ {
+ CRIS_INSN_MOVE_SPR_RV8, "move-spr-rv8", "move", 16,
+ { 0, { (1<<MACH_CRISV8) } }
+ },
+/* move ${Ps},${Rd-sfield} */
+ {
+ CRIS_INSN_MOVE_SPR_RV10, "move-spr-rv10", "move", 16,
+ { 0, { (1<<MACH_CRISV10) } }
+ },
+/* move ${Ps},${Rd-sfield} */
+ {
+ CRIS_INSN_MOVE_SPR_RV32, "move-spr-rv32", "move", 16,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* ret/reti/retb */
+ {
+ CRIS_INSN_RET_TYPE, "ret-type", "ret/reti/retb", 16,
+ { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } }
+ },
+/* move [${Rs}${inc}],${Pd} */
+ {
+ CRIS_INSN_MOVE_M_SPRV0, "move-m-sprv0", "move", 16,
+ { 0, { (1<<MACH_CRISV0) } }
+ },
+/* move [${Rs}${inc}],${Pd} */
+ {
+ CRIS_INSN_MOVE_M_SPRV3, "move-m-sprv3", "move", 16,
+ { 0, { (1<<MACH_CRISV3) } }
+ },
+/* move [${Rs}${inc}],${Pd} */
+ {
+ CRIS_INSN_MOVE_M_SPRV8, "move-m-sprv8", "move", 16,
+ { 0, { (1<<MACH_CRISV8) } }
+ },
+/* move [${Rs}${inc}],${Pd} */
+ {
+ CRIS_INSN_MOVE_M_SPRV10, "move-m-sprv10", "move", 16,
+ { 0, { (1<<MACH_CRISV10) } }
+ },
+/* move [${Rs}${inc}],${Pd} */
+ {
+ CRIS_INSN_MOVE_M_SPRV32, "move-m-sprv32", "move", 16,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* move ${sconst8},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV0_P0, "move-c-sprv0-p0", "move", 32,
+ { 0, { (1<<MACH_CRISV0) } }
+ },
+/* move ${sconst8},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV0_P1, "move-c-sprv0-p1", "move", 32,
+ { 0, { (1<<MACH_CRISV0) } }
+ },
+/* move ${sconst16},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV0_P4, "move-c-sprv0-p4", "move", 32,
+ { 0, { (1<<MACH_CRISV0) } }
+ },
+/* move ${sconst16},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV0_P5, "move-c-sprv0-p5", "move", 32,
+ { 0, { (1<<MACH_CRISV0) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV0_P8, "move-c-sprv0-p8", "move", 48,
+ { 0, { (1<<MACH_CRISV0) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV0_P9, "move-c-sprv0-p9", "move", 48,
+ { 0, { (1<<MACH_CRISV0) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV0_P10, "move-c-sprv0-p10", "move", 48,
+ { 0, { (1<<MACH_CRISV0) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV0_P11, "move-c-sprv0-p11", "move", 48,
+ { 0, { (1<<MACH_CRISV0) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV0_P12, "move-c-sprv0-p12", "move", 48,
+ { 0, { (1<<MACH_CRISV0) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV0_P13, "move-c-sprv0-p13", "move", 48,
+ { 0, { (1<<MACH_CRISV0) } }
+ },
+/* move ${sconst16},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV0_P6, "move-c-sprv0-p6", "move", 32,
+ { 0, { (1<<MACH_CRISV0) } }
+ },
+/* move ${sconst16},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV0_P7, "move-c-sprv0-p7", "move", 32,
+ { 0, { (1<<MACH_CRISV0) } }
+ },
+/* move ${sconst8},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV3_P0, "move-c-sprv3-p0", "move", 32,
+ { 0, { (1<<MACH_CRISV3) } }
+ },
+/* move ${sconst8},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV3_P1, "move-c-sprv3-p1", "move", 32,
+ { 0, { (1<<MACH_CRISV3) } }
+ },
+/* move ${sconst16},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV3_P4, "move-c-sprv3-p4", "move", 32,
+ { 0, { (1<<MACH_CRISV3) } }
+ },
+/* move ${sconst16},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV3_P5, "move-c-sprv3-p5", "move", 32,
+ { 0, { (1<<MACH_CRISV3) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV3_P8, "move-c-sprv3-p8", "move", 48,
+ { 0, { (1<<MACH_CRISV3) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV3_P9, "move-c-sprv3-p9", "move", 48,
+ { 0, { (1<<MACH_CRISV3) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV3_P10, "move-c-sprv3-p10", "move", 48,
+ { 0, { (1<<MACH_CRISV3) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV3_P11, "move-c-sprv3-p11", "move", 48,
+ { 0, { (1<<MACH_CRISV3) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV3_P12, "move-c-sprv3-p12", "move", 48,
+ { 0, { (1<<MACH_CRISV3) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV3_P13, "move-c-sprv3-p13", "move", 48,
+ { 0, { (1<<MACH_CRISV3) } }
+ },
+/* move ${sconst16},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV3_P6, "move-c-sprv3-p6", "move", 32,
+ { 0, { (1<<MACH_CRISV3) } }
+ },
+/* move ${sconst16},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV3_P7, "move-c-sprv3-p7", "move", 32,
+ { 0, { (1<<MACH_CRISV3) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV3_P14, "move-c-sprv3-p14", "move", 48,
+ { 0, { (1<<MACH_CRISV3) } }
+ },
+/* move ${sconst8},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV8_P0, "move-c-sprv8-p0", "move", 32,
+ { 0, { (1<<MACH_CRISV8) } }
+ },
+/* move ${sconst8},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV8_P1, "move-c-sprv8-p1", "move", 32,
+ { 0, { (1<<MACH_CRISV8) } }
+ },
+/* move ${sconst16},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV8_P4, "move-c-sprv8-p4", "move", 32,
+ { 0, { (1<<MACH_CRISV8) } }
+ },
+/* move ${sconst16},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV8_P5, "move-c-sprv8-p5", "move", 32,
+ { 0, { (1<<MACH_CRISV8) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV8_P8, "move-c-sprv8-p8", "move", 48,
+ { 0, { (1<<MACH_CRISV8) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV8_P9, "move-c-sprv8-p9", "move", 48,
+ { 0, { (1<<MACH_CRISV8) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV8_P10, "move-c-sprv8-p10", "move", 48,
+ { 0, { (1<<MACH_CRISV8) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV8_P11, "move-c-sprv8-p11", "move", 48,
+ { 0, { (1<<MACH_CRISV8) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV8_P12, "move-c-sprv8-p12", "move", 48,
+ { 0, { (1<<MACH_CRISV8) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV8_P13, "move-c-sprv8-p13", "move", 48,
+ { 0, { (1<<MACH_CRISV8) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV8_P14, "move-c-sprv8-p14", "move", 48,
+ { 0, { (1<<MACH_CRISV8) } }
+ },
+/* move ${sconst8},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV10_P0, "move-c-sprv10-p0", "move", 32,
+ { 0, { (1<<MACH_CRISV10) } }
+ },
+/* move ${sconst8},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV10_P1, "move-c-sprv10-p1", "move", 32,
+ { 0, { (1<<MACH_CRISV10) } }
+ },
+/* move ${sconst16},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV10_P4, "move-c-sprv10-p4", "move", 32,
+ { 0, { (1<<MACH_CRISV10) } }
+ },
+/* move ${sconst16},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV10_P5, "move-c-sprv10-p5", "move", 32,
+ { 0, { (1<<MACH_CRISV10) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV10_P8, "move-c-sprv10-p8", "move", 48,
+ { 0, { (1<<MACH_CRISV10) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV10_P9, "move-c-sprv10-p9", "move", 48,
+ { 0, { (1<<MACH_CRISV10) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV10_P10, "move-c-sprv10-p10", "move", 48,
+ { 0, { (1<<MACH_CRISV10) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV10_P11, "move-c-sprv10-p11", "move", 48,
+ { 0, { (1<<MACH_CRISV10) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV10_P12, "move-c-sprv10-p12", "move", 48,
+ { 0, { (1<<MACH_CRISV10) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV10_P13, "move-c-sprv10-p13", "move", 48,
+ { 0, { (1<<MACH_CRISV10) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV10_P7, "move-c-sprv10-p7", "move", 48,
+ { 0, { (1<<MACH_CRISV10) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV10_P14, "move-c-sprv10-p14", "move", 48,
+ { 0, { (1<<MACH_CRISV10) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV10_P15, "move-c-sprv10-p15", "move", 48,
+ { 0, { (1<<MACH_CRISV10) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV32_P0, "move-c-sprv32-p0", "move", 48,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV32_P1, "move-c-sprv32-p1", "move", 48,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV32_P2, "move-c-sprv32-p2", "move", 48,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV32_P3, "move-c-sprv32-p3", "move", 48,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV32_P4, "move-c-sprv32-p4", "move", 48,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV32_P5, "move-c-sprv32-p5", "move", 48,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV32_P6, "move-c-sprv32-p6", "move", 48,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV32_P7, "move-c-sprv32-p7", "move", 48,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV32_P8, "move-c-sprv32-p8", "move", 48,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV32_P9, "move-c-sprv32-p9", "move", 48,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV32_P10, "move-c-sprv32-p10", "move", 48,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV32_P11, "move-c-sprv32-p11", "move", 48,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV32_P12, "move-c-sprv32-p12", "move", 48,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV32_P13, "move-c-sprv32-p13", "move", 48,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV32_P14, "move-c-sprv32-p14", "move", 48,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* move ${const32},${Pd} */
+ {
+ CRIS_INSN_MOVE_C_SPRV32_P15, "move-c-sprv32-p15", "move", 48,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* move ${Ps},[${Rd-sfield}${inc}] */
+ {
+ CRIS_INSN_MOVE_SPR_MV0, "move-spr-mv0", "move", 16,
+ { 0, { (1<<MACH_CRISV0) } }
+ },
+/* move ${Ps},[${Rd-sfield}${inc}] */
+ {
+ CRIS_INSN_MOVE_SPR_MV3, "move-spr-mv3", "move", 16,
+ { 0, { (1<<MACH_CRISV3) } }
+ },
+/* move ${Ps},[${Rd-sfield}${inc}] */
+ {
+ CRIS_INSN_MOVE_SPR_MV8, "move-spr-mv8", "move", 16,
+ { 0, { (1<<MACH_CRISV8) } }
+ },
+/* move ${Ps},[${Rd-sfield}${inc}] */
+ {
+ CRIS_INSN_MOVE_SPR_MV10, "move-spr-mv10", "move", 16,
+ { 0, { (1<<MACH_CRISV10) } }
+ },
+/* move ${Ps},[${Rd-sfield}${inc}] */
+ {
+ CRIS_INSN_MOVE_SPR_MV32, "move-spr-mv32", "move", 16,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* sbfs [${Rd-sfield}${inc}] */
+ {
+ CRIS_INSN_SBFS, "sbfs", "sbfs", 16,
+ { 0, { (1<<MACH_CRISV10) } }
+ },
+/* move ${Ss},${Rd-sfield} */
+ {
+ CRIS_INSN_MOVE_SS_R, "move-ss-r", "move", 16,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* move ${Rs},${Sd} */
+ {
+ CRIS_INSN_MOVE_R_SS, "move-r-ss", "move", 16,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* movem ${Rs-dfield},[${Rd-sfield}${inc}] */
+ {
+ CRIS_INSN_MOVEM_R_M, "movem-r-m", "movem", 16,
+ { 0, { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } }
+ },
+/* movem ${Rs-dfield},[${Rd-sfield}${inc}] */
+ {
+ CRIS_INSN_MOVEM_R_M_V32, "movem-r-m-v32", "movem", 16,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* movem [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_MOVEM_M_R, "movem-m-r", "movem", 16,
+ { 0, { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } }
+ },
+/* movem [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_MOVEM_M_PC, "movem-m-pc", "movem", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } }
+ },
+/* movem [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_MOVEM_M_R_V32, "movem-m-r-v32", "movem", 16,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* add.b $Rs,$Rd */
+ {
+ CRIS_INSN_ADD_B_R, "add.b-r", "add.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* add.w $Rs,$Rd */
+ {
+ CRIS_INSN_ADD_W_R, "add.w-r", "add.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* add.d $Rs,$Rd */
+ {
+ CRIS_INSN_ADD_D_R, "add.d-r", "add.d", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* add-m.b [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_ADD_M_B_M, "add-m.b-m", "add-m.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* add-m.w [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_ADD_M_W_M, "add-m.w-m", "add-m.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* add-m.d [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_ADD_M_D_M, "add-m.d-m", "add-m.d", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* add.b ${sconst8}],${Rd} */
+ {
+ CRIS_INSN_ADDCBR, "addcbr", "add.b", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* add.w ${sconst16}],${Rd} */
+ {
+ CRIS_INSN_ADDCWR, "addcwr", "add.w", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* add.d ${const32}],${Rd} */
+ {
+ CRIS_INSN_ADDCDR, "addcdr", "add.d", 48,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* add.d ${sconst32},PC */
+ {
+ CRIS_INSN_ADDCPC, "addcpc", "add.d", 48,
+ { 0|A(UNCOND_CTI), { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } }
+ },
+/* adds.b $Rs,$Rd */
+ {
+ CRIS_INSN_ADDS_B_R, "adds.b-r", "adds.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* adds.w $Rs,$Rd */
+ {
+ CRIS_INSN_ADDS_W_R, "adds.w-r", "adds.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* adds-m.b [${Rs}${inc}],$Rd */
+ {
+ CRIS_INSN_ADDS_M_B_M, "adds-m.b-m", "adds-m.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* adds-m.w [${Rs}${inc}],$Rd */
+ {
+ CRIS_INSN_ADDS_M_W_M, "adds-m.w-m", "adds-m.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* [${Rs}${inc}],$Rd */
+ {
+ CRIS_INSN_ADDSCBR, "addscbr", "[", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* [${Rs}${inc}],$Rd */
+ {
+ CRIS_INSN_ADDSCWR, "addscwr", "[", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* adds.w [PC],PC */
+ {
+ CRIS_INSN_ADDSPCPC, "addspcpc", "adds.w", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } }
+ },
+/* addu.b $Rs,$Rd */
+ {
+ CRIS_INSN_ADDU_B_R, "addu.b-r", "addu.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* addu.w $Rs,$Rd */
+ {
+ CRIS_INSN_ADDU_W_R, "addu.w-r", "addu.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* addu-m.b [${Rs}${inc}],$Rd */
+ {
+ CRIS_INSN_ADDU_M_B_M, "addu-m.b-m", "addu-m.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* addu-m.w [${Rs}${inc}],$Rd */
+ {
+ CRIS_INSN_ADDU_M_W_M, "addu-m.w-m", "addu-m.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* [${Rs}${inc}],$Rd */
+ {
+ CRIS_INSN_ADDUCBR, "adducbr", "[", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* [${Rs}${inc}],$Rd */
+ {
+ CRIS_INSN_ADDUCWR, "adducwr", "[", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* sub.b $Rs,$Rd */
+ {
+ CRIS_INSN_SUB_B_R, "sub.b-r", "sub.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* sub.w $Rs,$Rd */
+ {
+ CRIS_INSN_SUB_W_R, "sub.w-r", "sub.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* sub.d $Rs,$Rd */
+ {
+ CRIS_INSN_SUB_D_R, "sub.d-r", "sub.d", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* sub-m.b [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_SUB_M_B_M, "sub-m.b-m", "sub-m.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* sub-m.w [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_SUB_M_W_M, "sub-m.w-m", "sub-m.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* sub-m.d [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_SUB_M_D_M, "sub-m.d-m", "sub-m.d", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* sub.b ${sconst8}],${Rd} */
+ {
+ CRIS_INSN_SUBCBR, "subcbr", "sub.b", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* sub.w ${sconst16}],${Rd} */
+ {
+ CRIS_INSN_SUBCWR, "subcwr", "sub.w", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* sub.d ${const32}],${Rd} */
+ {
+ CRIS_INSN_SUBCDR, "subcdr", "sub.d", 48,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* subs.b $Rs,$Rd */
+ {
+ CRIS_INSN_SUBS_B_R, "subs.b-r", "subs.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* subs.w $Rs,$Rd */
+ {
+ CRIS_INSN_SUBS_W_R, "subs.w-r", "subs.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* subs-m.b [${Rs}${inc}],$Rd */
+ {
+ CRIS_INSN_SUBS_M_B_M, "subs-m.b-m", "subs-m.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* subs-m.w [${Rs}${inc}],$Rd */
+ {
+ CRIS_INSN_SUBS_M_W_M, "subs-m.w-m", "subs-m.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* [${Rs}${inc}],$Rd */
+ {
+ CRIS_INSN_SUBSCBR, "subscbr", "[", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* [${Rs}${inc}],$Rd */
+ {
+ CRIS_INSN_SUBSCWR, "subscwr", "[", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* subu.b $Rs,$Rd */
+ {
+ CRIS_INSN_SUBU_B_R, "subu.b-r", "subu.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* subu.w $Rs,$Rd */
+ {
+ CRIS_INSN_SUBU_W_R, "subu.w-r", "subu.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* subu-m.b [${Rs}${inc}],$Rd */
+ {
+ CRIS_INSN_SUBU_M_B_M, "subu-m.b-m", "subu-m.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* subu-m.w [${Rs}${inc}],$Rd */
+ {
+ CRIS_INSN_SUBU_M_W_M, "subu-m.w-m", "subu-m.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* [${Rs}${inc}],$Rd */
+ {
+ CRIS_INSN_SUBUCBR, "subucbr", "[", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* [${Rs}${inc}],$Rd */
+ {
+ CRIS_INSN_SUBUCWR, "subucwr", "[", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* addc $Rs,$Rd */
+ {
+ CRIS_INSN_ADDC_R, "addc-r", "addc", 16,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* addc [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_ADDC_M, "addc-m", "addc", 16,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* addc ${const32},${Rd} */
+ {
+ CRIS_INSN_ADDC_C, "addc-c", "addc", 48,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* lapc.d ${const32-pcrel},${Rd} */
+ {
+ CRIS_INSN_LAPC_D, "lapc-d", "lapc.d", 48,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* lapcq ${qo},${Rd} */
+ {
+ CRIS_INSN_LAPCQ, "lapcq", "lapcq", 16,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* addi.b ${Rs-dfield}.m,${Rd-sfield} */
+ {
+ CRIS_INSN_ADDI_B_R, "addi.b-r", "addi.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* addi.w ${Rs-dfield}.m,${Rd-sfield} */
+ {
+ CRIS_INSN_ADDI_W_R, "addi.w-r", "addi.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* addi.d ${Rs-dfield}.m,${Rd-sfield} */
+ {
+ CRIS_INSN_ADDI_D_R, "addi.d-r", "addi.d", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* neg.b $Rs,$Rd */
+ {
+ CRIS_INSN_NEG_B_R, "neg.b-r", "neg.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* neg.w $Rs,$Rd */
+ {
+ CRIS_INSN_NEG_W_R, "neg.w-r", "neg.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* neg.d $Rs,$Rd */
+ {
+ CRIS_INSN_NEG_D_R, "neg.d-r", "neg.d", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* test-m.b [${Rs}${inc}] */
+ {
+ CRIS_INSN_TEST_M_B_M, "test-m.b-m", "test-m.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* test-m.w [${Rs}${inc}] */
+ {
+ CRIS_INSN_TEST_M_W_M, "test-m.w-m", "test-m.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* test-m.d [${Rs}${inc}] */
+ {
+ CRIS_INSN_TEST_M_D_M, "test-m.d-m", "test-m.d", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* move-r-m.b ${Rs-dfield},[${Rd-sfield}${inc}] */
+ {
+ CRIS_INSN_MOVE_R_M_B_M, "move-r-m.b-m", "move-r-m.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* move-r-m.w ${Rs-dfield},[${Rd-sfield}${inc}] */
+ {
+ CRIS_INSN_MOVE_R_M_W_M, "move-r-m.w-m", "move-r-m.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* move-r-m.d ${Rs-dfield},[${Rd-sfield}${inc}] */
+ {
+ CRIS_INSN_MOVE_R_M_D_M, "move-r-m.d-m", "move-r-m.d", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* muls.b $Rs,$Rd */
+ {
+ CRIS_INSN_MULS_B, "muls.b", "muls.b", 16,
+ { 0, { (1<<MACH_CRISV10)|(1<<MACH_CRISV32) } }
+ },
+/* muls.w $Rs,$Rd */
+ {
+ CRIS_INSN_MULS_W, "muls.w", "muls.w", 16,
+ { 0, { (1<<MACH_CRISV10)|(1<<MACH_CRISV32) } }
+ },
+/* muls.d $Rs,$Rd */
+ {
+ CRIS_INSN_MULS_D, "muls.d", "muls.d", 16,
+ { 0, { (1<<MACH_CRISV10)|(1<<MACH_CRISV32) } }
+ },
+/* mulu.b $Rs,$Rd */
+ {
+ CRIS_INSN_MULU_B, "mulu.b", "mulu.b", 16,
+ { 0, { (1<<MACH_CRISV10)|(1<<MACH_CRISV32) } }
+ },
+/* mulu.w $Rs,$Rd */
+ {
+ CRIS_INSN_MULU_W, "mulu.w", "mulu.w", 16,
+ { 0, { (1<<MACH_CRISV10)|(1<<MACH_CRISV32) } }
+ },
+/* mulu.d $Rs,$Rd */
+ {
+ CRIS_INSN_MULU_D, "mulu.d", "mulu.d", 16,
+ { 0, { (1<<MACH_CRISV10)|(1<<MACH_CRISV32) } }
+ },
+/* mcp $Ps,$Rd */
+ {
+ CRIS_INSN_MCP, "mcp", "mcp", 16,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* mstep $Rs,$Rd */
+ {
+ CRIS_INSN_MSTEP, "mstep", "mstep", 16,
+ { 0, { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } }
+ },
+/* dstep $Rs,$Rd */
+ {
+ CRIS_INSN_DSTEP, "dstep", "dstep", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* abs $Rs,$Rd */
+ {
+ CRIS_INSN_ABS, "abs", "abs", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* and.b $Rs,$Rd */
+ {
+ CRIS_INSN_AND_B_R, "and.b-r", "and.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* and.w $Rs,$Rd */
+ {
+ CRIS_INSN_AND_W_R, "and.w-r", "and.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* and.d $Rs,$Rd */
+ {
+ CRIS_INSN_AND_D_R, "and.d-r", "and.d", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* and-m.b [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_AND_M_B_M, "and-m.b-m", "and-m.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* and-m.w [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_AND_M_W_M, "and-m.w-m", "and-m.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* and-m.d [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_AND_M_D_M, "and-m.d-m", "and-m.d", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* and.b ${sconst8}],${Rd} */
+ {
+ CRIS_INSN_ANDCBR, "andcbr", "and.b", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* and.w ${sconst16}],${Rd} */
+ {
+ CRIS_INSN_ANDCWR, "andcwr", "and.w", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* and.d ${const32}],${Rd} */
+ {
+ CRIS_INSN_ANDCDR, "andcdr", "and.d", 48,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* andq $i,$Rd */
+ {
+ CRIS_INSN_ANDQ, "andq", "andq", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* orr.b $Rs,$Rd */
+ {
+ CRIS_INSN_ORR_B_R, "orr.b-r", "orr.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* orr.w $Rs,$Rd */
+ {
+ CRIS_INSN_ORR_W_R, "orr.w-r", "orr.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* orr.d $Rs,$Rd */
+ {
+ CRIS_INSN_ORR_D_R, "orr.d-r", "orr.d", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* or-m.b [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_OR_M_B_M, "or-m.b-m", "or-m.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* or-m.w [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_OR_M_W_M, "or-m.w-m", "or-m.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* or-m.d [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_OR_M_D_M, "or-m.d-m", "or-m.d", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* or.b ${sconst8}],${Rd} */
+ {
+ CRIS_INSN_ORCBR, "orcbr", "or.b", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* or.w ${sconst16}],${Rd} */
+ {
+ CRIS_INSN_ORCWR, "orcwr", "or.w", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* or.d ${const32}],${Rd} */
+ {
+ CRIS_INSN_ORCDR, "orcdr", "or.d", 48,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* orq $i,$Rd */
+ {
+ CRIS_INSN_ORQ, "orq", "orq", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* xor $Rs,$Rd */
+ {
+ CRIS_INSN_XOR, "xor", "xor", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* not ${Rs} */
+ {
+ CRIS_INSN_NOT, "not", "not", 16,
+ { 0, { (1<<MACH_CRISV0)|(1<<MACH_CRISV3) } }
+ },
+/* swap${swapoption} ${Rs} */
+ {
+ CRIS_INSN_SWAP, "swap", "swap", 16,
+ { 0, { (1<<MACH_CRISV8)|(1<<MACH_CRISV10)|(1<<MACH_CRISV32) } }
+ },
+/* asrr.b $Rs,$Rd */
+ {
+ CRIS_INSN_ASRR_B_R, "asrr.b-r", "asrr.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* asrr.w $Rs,$Rd */
+ {
+ CRIS_INSN_ASRR_W_R, "asrr.w-r", "asrr.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* asrr.d $Rs,$Rd */
+ {
+ CRIS_INSN_ASRR_D_R, "asrr.d-r", "asrr.d", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* asrq $c,${Rd} */
+ {
+ CRIS_INSN_ASRQ, "asrq", "asrq", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* lsrr.b $Rs,$Rd */
+ {
+ CRIS_INSN_LSRR_B_R, "lsrr.b-r", "lsrr.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* lsrr.w $Rs,$Rd */
+ {
+ CRIS_INSN_LSRR_W_R, "lsrr.w-r", "lsrr.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* lsrr.d $Rs,$Rd */
+ {
+ CRIS_INSN_LSRR_D_R, "lsrr.d-r", "lsrr.d", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* lsrq $c,${Rd} */
+ {
+ CRIS_INSN_LSRQ, "lsrq", "lsrq", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* lslr.b $Rs,$Rd */
+ {
+ CRIS_INSN_LSLR_B_R, "lslr.b-r", "lslr.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* lslr.w $Rs,$Rd */
+ {
+ CRIS_INSN_LSLR_W_R, "lslr.w-r", "lslr.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* lslr.d $Rs,$Rd */
+ {
+ CRIS_INSN_LSLR_D_R, "lslr.d-r", "lslr.d", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* lslq $c,${Rd} */
+ {
+ CRIS_INSN_LSLQ, "lslq", "lslq", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* $Rs,$Rd */
+ {
+ CRIS_INSN_BTST, "btst", "", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* btstq $c,${Rd} */
+ {
+ CRIS_INSN_BTSTQ, "btstq", "btstq", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* setf ${list-of-flags} */
+ {
+ CRIS_INSN_SETF, "setf", "setf", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* clearf ${list-of-flags} */
+ {
+ CRIS_INSN_CLEARF, "clearf", "clearf", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* rfe */
+ {
+ CRIS_INSN_RFE, "rfe", "rfe", 16,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* sfe */
+ {
+ CRIS_INSN_SFE, "sfe", "sfe", 16,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* rfg */
+ {
+ CRIS_INSN_RFG, "rfg", "rfg", 16,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* rfn */
+ {
+ CRIS_INSN_RFN, "rfn", "rfn", 16,
+ { 0, { (1<<MACH_CRISV32) } }
+ },
+/* halt */
+ {
+ CRIS_INSN_HALT, "halt", "halt", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_CRISV32) } }
+ },
+/* b${cc} ${o-pcrel} */
+ {
+ CRIS_INSN_BCC_B, "bcc-b", "b", 16,
+ { 0|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+ },
+/* ba ${o-pcrel} */
+ {
+ CRIS_INSN_BA_B, "ba-b", "ba", 16,
+ { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+ },
+/* b${cc} ${o-word-pcrel} */
+ {
+ CRIS_INSN_BCC_W, "bcc-w", "b", 32,
+ { 0|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+ },
+/* ba ${o-word-pcrel} */
+ {
+ CRIS_INSN_BA_W, "ba-w", "ba", 32,
+ { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
+ },
+/* jas ${Rs},${Pd} */
+ {
+ CRIS_INSN_JAS_R, "jas-r", "jas", 16,
+ { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_CRISV32) } }
+ },
+/* jump/jsr/jir ${Rs} */
+ {
+ CRIS_INSN_JUMP_R, "jump-r", "jump/jsr/jir", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } }
+ },
+/* jas ${const32},${Pd} */
+ {
+ CRIS_INSN_JAS_C, "jas-c", "jas", 48,
+ { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_CRISV32) } }
+ },
+/* jump/jsr/jir [${Rs}${inc}] */
+ {
+ CRIS_INSN_JUMP_M, "jump-m", "jump/jsr/jir", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } }
+ },
+/* jump/jsr/jir ${const32} */
+ {
+ CRIS_INSN_JUMP_C, "jump-c", "jump/jsr/jir", 48,
+ { 0|A(UNCOND_CTI), { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } }
+ },
+/* jump ${Ps} */
+ {
+ CRIS_INSN_JUMP_P, "jump-p", "jump", 16,
+ { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_CRISV32) } }
+ },
+/* bas ${const32},${Pd} */
+ {
+ CRIS_INSN_BAS_C, "bas-c", "bas", 48,
+ { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_CRISV32) } }
+ },
+/* jasc ${Rs},${Pd} */
+ {
+ CRIS_INSN_JASC_R, "jasc-r", "jasc", 16,
+ { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_CRISV32) } }
+ },
+/* jasc ${const32},${Pd} */
+ {
+ CRIS_INSN_JASC_C, "jasc-c", "jasc", 48,
+ { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_CRISV32) } }
+ },
+/* basc ${const32},${Pd} */
+ {
+ CRIS_INSN_BASC_C, "basc-c", "basc", 48,
+ { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_CRISV32) } }
+ },
+/* break $n */
+ {
+ CRIS_INSN_BREAK, "break", "break", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+ },
+/* bound-r.b ${Rs},${Rd} */
+ {
+ CRIS_INSN_BOUND_R_B_R, "bound-r.b-r", "bound-r.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* bound-r.w ${Rs},${Rd} */
+ {
+ CRIS_INSN_BOUND_R_W_R, "bound-r.w-r", "bound-r.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* bound-r.d ${Rs},${Rd} */
+ {
+ CRIS_INSN_BOUND_R_D_R, "bound-r.d-r", "bound-r.d", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* bound-m.b [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_BOUND_M_B_M, "bound-m.b-m", "bound-m.b", 16,
+ { 0, { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } }
+ },
+/* bound-m.w [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_BOUND_M_W_M, "bound-m.w-m", "bound-m.w", 16,
+ { 0, { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } }
+ },
+/* bound-m.d [${Rs}${inc}],${Rd} */
+ {
+ CRIS_INSN_BOUND_M_D_M, "bound-m.d-m", "bound-m.d", 16,
+ { 0, { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } }
+ },
+/* bound.b [PC+],${Rd} */
+ {
+ CRIS_INSN_BOUND_CB, "bound-cb", "bound.b", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* bound.w [PC+],${Rd} */
+ {
+ CRIS_INSN_BOUND_CW, "bound-cw", "bound.w", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* bound.d [PC+],${Rd} */
+ {
+ CRIS_INSN_BOUND_CD, "bound-cd", "bound.d", 48,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* s${cc} ${Rd-sfield} */
+ {
+ CRIS_INSN_SCC, "scc", "s", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* lz ${Rs},${Rd} */
+ {
+ CRIS_INSN_LZ, "lz", "lz", 16,
+ { 0, { (1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10)|(1<<MACH_CRISV32) } }
+ },
+/* addoq $o,$Rs,ACR */
+ {
+ CRIS_INSN_ADDOQ, "addoq", "addoq", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* bdapq $o,PC */
+ {
+ CRIS_INSN_BDAPQPC, "bdapqpc", "bdapq", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } }
+ },
+/* addo-m.b [${Rs}${inc}],$Rd,ACR */
+ {
+ CRIS_INSN_ADDO_M_B_M, "addo-m.b-m", "addo-m.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* addo-m.w [${Rs}${inc}],$Rd,ACR */
+ {
+ CRIS_INSN_ADDO_M_W_M, "addo-m.w-m", "addo-m.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* addo-m.d [${Rs}${inc}],$Rd,ACR */
+ {
+ CRIS_INSN_ADDO_M_D_M, "addo-m.d-m", "addo-m.d", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* addo.b [PC+],$Rd,ACR */
+ {
+ CRIS_INSN_ADDO_CB, "addo-cb", "addo.b", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* addo.w [PC+],$Rd,ACR */
+ {
+ CRIS_INSN_ADDO_CW, "addo-cw", "addo.w", 32,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* addo.d [PC+],$Rd,ACR */
+ {
+ CRIS_INSN_ADDO_CD, "addo-cd", "addo.d", 48,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* dip [${Rs}${inc}] */
+ {
+ CRIS_INSN_DIP_M, "dip-m", "dip", 16,
+ { 0, { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } }
+ },
+/* dip [PC+] */
+ {
+ CRIS_INSN_DIP_C, "dip-c", "dip", 48,
+ { 0, { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } }
+ },
+/* addi-acr.b ${Rs-dfield}.m,${Rd-sfield},ACR */
+ {
+ CRIS_INSN_ADDI_ACR_B_R, "addi-acr.b-r", "addi-acr.b", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* addi-acr.w ${Rs-dfield}.m,${Rd-sfield},ACR */
+ {
+ CRIS_INSN_ADDI_ACR_W_R, "addi-acr.w-r", "addi-acr.w", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* addi-acr.d ${Rs-dfield}.m,${Rd-sfield},ACR */
+ {
+ CRIS_INSN_ADDI_ACR_D_R, "addi-acr.d-r", "addi-acr.d", 16,
+ { 0, { (1<<MACH_BASE) } }
+ },
+/* biap-pc.b ${Rs-dfield}.m,PC */
+ {
+ CRIS_INSN_BIAP_PC_B_R, "biap-pc.b-r", "biap-pc.b", 16,
+ { 0, { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } }
+ },
+/* biap-pc.w ${Rs-dfield}.m,PC */
+ {
+ CRIS_INSN_BIAP_PC_W_R, "biap-pc.w-r", "biap-pc.w", 16,
+ { 0, { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } }
+ },
+/* biap-pc.d ${Rs-dfield}.m,PC */
+ {
+ CRIS_INSN_BIAP_PC_D_R, "biap-pc.d-r", "biap-pc.d", 16,
+ { 0, { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10) } }
+ },
+/* fidxi [$Rs] */
+ {
+ CRIS_INSN_FIDXI, "fidxi", "fidxi", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_CRISV32) } }
+ },
+/* fidxi [$Rs] */
+ {
+ CRIS_INSN_FTAGI, "ftagi", "fidxi", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_CRISV32) } }
+ },
+/* fidxd [$Rs] */
+ {
+ CRIS_INSN_FIDXD, "fidxd", "fidxd", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_CRISV32) } }
+ },
+/* ftagd [$Rs] */
+ {
+ CRIS_INSN_FTAGD, "ftagd", "ftagd", 16,
+ { 0|A(UNCOND_CTI), { (1<<MACH_CRISV32) } }
+ },
+};
+
+#undef OP
+#undef A
+
+/* Initialize anything needed to be done once, before any cpu_open call. */
+static void init_tables PARAMS ((void));
+
+static void
+init_tables ()
+{
+}
+
+static const CGEN_MACH * lookup_mach_via_bfd_name
+ PARAMS ((const CGEN_MACH *, const char *));
+static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
+static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
+static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
+static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
+static void cris_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
+
+/* Subroutine of cris_cgen_cpu_open to look up a mach via its bfd name. */
+
+static const CGEN_MACH *
+lookup_mach_via_bfd_name (table, name)
+ const CGEN_MACH *table;
+ const char *name;
+{
+ while (table->name)
+ {
+ if (strcmp (name, table->bfd_name) == 0)
+ return table;
+ ++table;
+ }
+ abort ();
+}
+
+/* Subroutine of cris_cgen_cpu_open to build the hardware table. */
+
+static void
+build_hw_table (cd)
+ CGEN_CPU_TABLE *cd;
+{
+ int i;
+ int machs = cd->machs;
+ const CGEN_HW_ENTRY *init = & cris_cgen_hw_table[0];
+ /* MAX_HW is only an upper bound on the number of selected entries.
+ However each entry is indexed by it's enum so there can be holes in
+ the table. */
+ const CGEN_HW_ENTRY **selected =
+ (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
+
+ cd->hw_table.init_entries = init;
+ cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
+ memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
+ /* ??? For now we just use machs to determine which ones we want. */
+ for (i = 0; init[i].name != NULL; ++i)
+ if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
+ & machs)
+ selected[init[i].type] = &init[i];
+ cd->hw_table.entries = selected;
+ cd->hw_table.num_entries = MAX_HW;
+}
+
+/* Subroutine of cris_cgen_cpu_open to build the hardware table. */
+
+static void
+build_ifield_table (cd)
+ CGEN_CPU_TABLE *cd;
+{
+ cd->ifld_table = & cris_cgen_ifld_table[0];
+}
+
+/* Subroutine of cris_cgen_cpu_open to build the hardware table. */
+
+static void
+build_operand_table (cd)
+ CGEN_CPU_TABLE *cd;
+{
+ int i;
+ int machs = cd->machs;
+ const CGEN_OPERAND *init = & cris_cgen_operand_table[0];
+ /* MAX_OPERANDS is only an upper bound on the number of selected entries.
+ However each entry is indexed by it's enum so there can be holes in
+ the table. */
+ const CGEN_OPERAND **selected =
+ (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+
+ cd->operand_table.init_entries = init;
+ cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
+ memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+ /* ??? For now we just use mach to determine which ones we want. */
+ for (i = 0; init[i].name != NULL; ++i)
+ if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
+ & machs)
+ selected[init[i].type] = &init[i];
+ cd->operand_table.entries = selected;
+ cd->operand_table.num_entries = MAX_OPERANDS;
+}
+
+/* Subroutine of cris_cgen_cpu_open to build the hardware table.
+ ??? This could leave out insns not supported by the specified mach/isa,
+ but that would cause errors like "foo only supported by bar" to become
+ "unknown insn", so for now we include all insns and require the app to
+ do the checking later.
+ ??? On the other hand, parsing of such insns may require their hardware or
+ operand elements to be in the table [which they mightn't be]. */
+
+static void
+build_insn_table (cd)
+ CGEN_CPU_TABLE *cd;
+{
+ int i;
+ const CGEN_IBASE *ib = & cris_cgen_insn_table[0];
+ CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
+
+ memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
+ for (i = 0; i < MAX_INSNS; ++i)
+ insns[i].base = &ib[i];
+ cd->insn_table.init_entries = insns;
+ cd->insn_table.entry_size = sizeof (CGEN_IBASE);
+ cd->insn_table.num_init_entries = MAX_INSNS;
+}
+
+/* Subroutine of cris_cgen_cpu_open to rebuild the tables. */
+
+static void
+cris_cgen_rebuild_tables (cd)
+ CGEN_CPU_TABLE *cd;
+{
+ int i;
+ unsigned int isas = cd->isas;
+ unsigned int machs = cd->machs;
+
+ cd->int_insn_p = CGEN_INT_INSN_P;
+
+ /* Data derived from the isa spec. */
+#define UNSET (CGEN_SIZE_UNKNOWN + 1)
+ cd->default_insn_bitsize = UNSET;
+ cd->base_insn_bitsize = UNSET;
+ cd->min_insn_bitsize = 65535; /* some ridiculously big number */
+ cd->max_insn_bitsize = 0;
+ for (i = 0; i < MAX_ISAS; ++i)
+ if (((1 << i) & isas) != 0)
+ {
+ const CGEN_ISA *isa = & cris_cgen_isa_table[i];
+
+ /* Default insn sizes of all selected isas must be
+ equal or we set the result to 0, meaning "unknown". */
+ if (cd->default_insn_bitsize == UNSET)
+ cd->default_insn_bitsize = isa->default_insn_bitsize;
+ else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
+ ; /* this is ok */
+ else
+ cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
+
+ /* Base insn sizes of all selected isas must be equal
+ or we set the result to 0, meaning "unknown". */
+ if (cd->base_insn_bitsize == UNSET)
+ cd->base_insn_bitsize = isa->base_insn_bitsize;
+ else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
+ ; /* this is ok */
+ else
+ cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
+
+ /* Set min,max insn sizes. */
+ if (isa->min_insn_bitsize < cd->min_insn_bitsize)
+ cd->min_insn_bitsize = isa->min_insn_bitsize;
+ if (isa->max_insn_bitsize > cd->max_insn_bitsize)
+ cd->max_insn_bitsize = isa->max_insn_bitsize;
+ }
+
+ /* Data derived from the mach spec. */
+ for (i = 0; i < MAX_MACHS; ++i)
+ if (((1 << i) & machs) != 0)
+ {
+ const CGEN_MACH *mach = & cris_cgen_mach_table[i];
+
+ if (mach->insn_chunk_bitsize != 0)
+ {
+ if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
+ {
+ fprintf (stderr, "cris_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
+ cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
+ abort ();
+ }
+
+ cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
+ }
+ }
+
+ /* Determine which hw elements are used by MACH. */
+ build_hw_table (cd);
+
+ /* Build the ifield table. */
+ build_ifield_table (cd);
+
+ /* Determine which operands are used by MACH/ISA. */
+ build_operand_table (cd);
+
+ /* Build the instruction table. */
+ build_insn_table (cd);
+}
+
+/* Initialize a cpu table and return a descriptor.
+ It's much like opening a file, and must be the first function called.
+ The arguments are a set of (type/value) pairs, terminated with
+ CGEN_CPU_OPEN_END.
+
+ Currently supported values:
+ CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
+ CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
+ CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
+ CGEN_CPU_OPEN_ENDIAN: specify endian choice
+ CGEN_CPU_OPEN_END: terminates arguments
+
+ ??? Simultaneous multiple isas might not make sense, but it's not (yet)
+ precluded.
+
+ ??? We only support ISO C stdargs here, not K&R.
+ Laziness, plus experiment to see if anything requires K&R - eventually
+ K&R will no longer be supported - e.g. GDB is currently trying this. */
+
+CGEN_CPU_DESC
+cris_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
+{
+ CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
+ static int init_p;
+ unsigned int isas = 0; /* 0 = "unspecified" */
+ unsigned int machs = 0; /* 0 = "unspecified" */
+ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
+ va_list ap;
+
+ if (! init_p)
+ {
+ init_tables ();
+ init_p = 1;
+ }
+
+ memset (cd, 0, sizeof (*cd));
+
+ va_start (ap, arg_type);
+ while (arg_type != CGEN_CPU_OPEN_END)
+ {
+ switch (arg_type)
+ {
+ case CGEN_CPU_OPEN_ISAS :
+ isas = va_arg (ap, unsigned int);
+ break;
+ case CGEN_CPU_OPEN_MACHS :
+ machs = va_arg (ap, unsigned int);
+ break;
+ case CGEN_CPU_OPEN_BFDMACH :
+ {
+ const char *name = va_arg (ap, const char *);
+ const CGEN_MACH *mach =
+ lookup_mach_via_bfd_name (cris_cgen_mach_table, name);
+
+ machs |= 1 << mach->num;
+ break;
+ }
+ case CGEN_CPU_OPEN_ENDIAN :
+ endian = va_arg (ap, enum cgen_endian);
+ break;
+ default :
+ fprintf (stderr, "cris_cgen_cpu_open: unsupported argument `%d'\n",
+ arg_type);
+ abort (); /* ??? return NULL? */
+ }
+ arg_type = va_arg (ap, enum cgen_cpu_open_arg);
+ }
+ va_end (ap);
+
+ /* mach unspecified means "all" */
+ if (machs == 0)
+ machs = (1 << MAX_MACHS) - 1;
+ /* base mach is always selected */
+ machs |= 1;
+ /* isa unspecified means "all" */
+ if (isas == 0)
+ isas = (1 << MAX_ISAS) - 1;
+ if (endian == CGEN_ENDIAN_UNKNOWN)
+ {
+ /* ??? If target has only one, could have a default. */
+ fprintf (stderr, "cris_cgen_cpu_open: no endianness specified\n");
+ abort ();
+ }
+
+ cd->isas = isas;
+ cd->machs = machs;
+ cd->endian = endian;
+ /* FIXME: for the sparc case we can determine insn-endianness statically.
+ The worry here is where both data and insn endian can be independently
+ chosen, in which case this function will need another argument.
+ Actually, will want to allow for more arguments in the future anyway. */
+ cd->insn_endian = endian;
+
+ /* Table (re)builder. */
+ cd->rebuild_tables = cris_cgen_rebuild_tables;
+ cris_cgen_rebuild_tables (cd);
+
+ /* Default to not allowing signed overflow. */
+ cd->signed_overflow_ok_p = 0;
+
+ return (CGEN_CPU_DESC) cd;
+}
+
+/* Cover fn to cris_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
+ MACH_NAME is the bfd name of the mach. */
+
+CGEN_CPU_DESC
+cris_cgen_cpu_open_1 (mach_name, endian)
+ const char *mach_name;
+ enum cgen_endian endian;
+{
+ return cris_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
+ CGEN_CPU_OPEN_ENDIAN, endian,
+ CGEN_CPU_OPEN_END);
+}
+
+/* Close a cpu table.
+ ??? This can live in a machine independent file, but there's currently
+ no place to put this file (there's no libcgen). libopcodes is the wrong
+ place as some simulator ports use this but they don't use libopcodes. */
+
+void
+cris_cgen_cpu_close (cd)
+ CGEN_CPU_DESC cd;
+{
+ unsigned int i;
+ const CGEN_INSN *insns;
+
+ if (cd->macro_insn_table.init_entries)
+ {
+ insns = cd->macro_insn_table.init_entries;
+ for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
+ {
+ if (CGEN_INSN_RX ((insns)))
+ regfree (CGEN_INSN_RX (insns));
+ }
+ }
+
+ if (cd->insn_table.init_entries)
+ {
+ insns = cd->insn_table.init_entries;
+ for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+ {
+ if (CGEN_INSN_RX (insns))
+ regfree (CGEN_INSN_RX (insns));
+ }
+ }
+
+
+
+ if (cd->macro_insn_table.init_entries)
+ free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+
+ if (cd->insn_table.init_entries)
+ free ((CGEN_INSN *) cd->insn_table.init_entries);
+
+ if (cd->hw_table.entries)
+ free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
+
+ if (cd->operand_table.entries)
+ free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
+
+ free (cd);
+}
+
--- /dev/null
+/* CPU data header for cris.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2004 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef CRIS_CPU_H
+#define CRIS_CPU_H
+
+#define CGEN_ARCH cris
+
+/* Given symbol S, return cris_cgen_<S>. */
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define CGEN_SYM(s) cris##_cgen_##s
+#else
+#define CGEN_SYM(s) cris/**/_cgen_/**/s
+#endif
+
+
+/* Selected cpu families. */
+#define HAVE_CPU_CRISV0F
+#define HAVE_CPU_CRISV3F
+#define HAVE_CPU_CRISV8F
+#define HAVE_CPU_CRISV10F
+#define HAVE_CPU_CRISV32F
+
+#define CGEN_INSN_LSB0_P 1
+
+/* Minimum size of any insn (in bytes). */
+#define CGEN_MIN_INSN_SIZE 2
+
+/* Maximum size of any insn (in bytes). */
+#define CGEN_MAX_INSN_SIZE 6
+
+#define CGEN_INT_INSN_P 0
+
+/* Maximum number of syntax elements in an instruction. */
+#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 22
+
+/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
+ e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
+ we can't hash on everything up to the space. */
+#define CGEN_MNEMONIC_OPERANDS
+
+/* Maximum number of fields in an instruction. */
+#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 6
+
+/* Enums. */
+
+/* Enum declaration for . */
+typedef enum gr_names_pcreg {
+ H_GR_REAL_PC_PC = 15, H_GR_REAL_PC_SP = 14, H_GR_REAL_PC_R0 = 0, H_GR_REAL_PC_R1 = 1
+ , H_GR_REAL_PC_R2 = 2, H_GR_REAL_PC_R3 = 3, H_GR_REAL_PC_R4 = 4, H_GR_REAL_PC_R5 = 5
+ , H_GR_REAL_PC_R6 = 6, H_GR_REAL_PC_R7 = 7, H_GR_REAL_PC_R8 = 8, H_GR_REAL_PC_R9 = 9
+ , H_GR_REAL_PC_R10 = 10, H_GR_REAL_PC_R11 = 11, H_GR_REAL_PC_R12 = 12, H_GR_REAL_PC_R13 = 13
+ , H_GR_REAL_PC_R14 = 14
+} GR_NAMES_PCREG;
+
+/* Enum declaration for . */
+typedef enum gr_names_acr {
+ H_GR_ACR = 15, H_GR_SP = 14, H_GR_R0 = 0, H_GR_R1 = 1
+ , H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4, H_GR_R5 = 5
+ , H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8, H_GR_R9 = 9
+ , H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12, H_GR_R13 = 13
+ , H_GR_R14 = 14
+} GR_NAMES_ACR;
+
+/* Enum declaration for . */
+typedef enum gr_names_v32 {
+ H_GR_V32_ACR = 15, H_GR_V32_SP = 14, H_GR_V32_R0 = 0, H_GR_V32_R1 = 1
+ , H_GR_V32_R2 = 2, H_GR_V32_R3 = 3, H_GR_V32_R4 = 4, H_GR_V32_R5 = 5
+ , H_GR_V32_R6 = 6, H_GR_V32_R7 = 7, H_GR_V32_R8 = 8, H_GR_V32_R9 = 9
+ , H_GR_V32_R10 = 10, H_GR_V32_R11 = 11, H_GR_V32_R12 = 12, H_GR_V32_R13 = 13
+ , H_GR_V32_R14 = 14
+} GR_NAMES_V32;
+
+/* Enum declaration for . */
+typedef enum p_names_v10 {
+ H_SR_PRE_V32_CCR = 5, H_SR_PRE_V32_MOF = 7, H_SR_PRE_V32_IBR = 9, H_SR_PRE_V32_IRP = 10
+ , H_SR_PRE_V32_BAR = 12, H_SR_PRE_V32_DCCR = 13, H_SR_PRE_V32_BRP = 14, H_SR_PRE_V32_USP = 15
+ , H_SR_PRE_V32_VR = 1, H_SR_PRE_V32_SRP = 11, H_SR_PRE_V32_P0 = 0, H_SR_PRE_V32_P1 = 1
+ , H_SR_PRE_V32_P2 = 2, H_SR_PRE_V32_P3 = 3, H_SR_PRE_V32_P4 = 4, H_SR_PRE_V32_P5 = 5
+ , H_SR_PRE_V32_P6 = 6, H_SR_PRE_V32_P7 = 7, H_SR_PRE_V32_P8 = 8, H_SR_PRE_V32_P9 = 9
+ , H_SR_PRE_V32_P10 = 10, H_SR_PRE_V32_P11 = 11, H_SR_PRE_V32_P12 = 12, H_SR_PRE_V32_P13 = 13
+ , H_SR_PRE_V32_P14 = 14
+} P_NAMES_V10;
+
+/* Enum declaration for . */
+typedef enum p_names_v32 {
+ H_SR_BZ = 0, H_SR_PID = 2, H_SR_SRS = 3, H_SR_WZ = 4
+ , H_SR_EXS = 5, H_SR_EDA = 6, H_SR_MOF = 7, H_SR_DZ = 8
+ , H_SR_EBP = 9, H_SR_ERP = 10, H_SR_NRP = 12, H_SR_CCS = 13
+ , H_SR_USP = 14, H_SR_SPC = 15, H_SR_VR = 1, H_SR_SRP = 11
+ , H_SR_P0 = 0, H_SR_P1 = 1, H_SR_P2 = 2, H_SR_P3 = 3
+ , H_SR_P4 = 4, H_SR_P5 = 5, H_SR_P6 = 6, H_SR_P7 = 7
+ , H_SR_P8 = 8, H_SR_P9 = 9, H_SR_P10 = 10, H_SR_P11 = 11
+ , H_SR_P12 = 12, H_SR_P13 = 13, H_SR_P14 = 14
+} P_NAMES_V32;
+
+/* Enum declaration for . */
+typedef enum p_names_v32_x {
+ H_SR_V32_BZ = 0, H_SR_V32_PID = 2, H_SR_V32_SRS = 3, H_SR_V32_WZ = 4
+ , H_SR_V32_EXS = 5, H_SR_V32_EDA = 6, H_SR_V32_MOF = 7, H_SR_V32_DZ = 8
+ , H_SR_V32_EBP = 9, H_SR_V32_ERP = 10, H_SR_V32_NRP = 12, H_SR_V32_CCS = 13
+ , H_SR_V32_USP = 14, H_SR_V32_SPC = 15, H_SR_V32_VR = 1, H_SR_V32_SRP = 11
+ , H_SR_V32_P0 = 0, H_SR_V32_P1 = 1, H_SR_V32_P2 = 2, H_SR_V32_P3 = 3
+ , H_SR_V32_P4 = 4, H_SR_V32_P5 = 5, H_SR_V32_P6 = 6, H_SR_V32_P7 = 7
+ , H_SR_V32_P8 = 8, H_SR_V32_P9 = 9, H_SR_V32_P10 = 10, H_SR_V32_P11 = 11
+ , H_SR_V32_P12 = 12, H_SR_V32_P13 = 13, H_SR_V32_P14 = 14
+} P_NAMES_V32_X;
+
+/* Enum declaration for Standard instruction operand size. */
+typedef enum insn_size {
+ SIZE_BYTE, SIZE_WORD, SIZE_DWORD, SIZE_FIXED
+} INSN_SIZE;
+
+/* Enum declaration for Standard instruction addressing modes. */
+typedef enum insn_mode {
+ MODE_QUICK_IMMEDIATE, MODE_REGISTER, MODE_INDIRECT, MODE_AUTOINCREMENT
+} INSN_MODE;
+
+/* Enum declaration for Whether the operand is indirect. */
+typedef enum insn_memoryness_mode {
+ MODEMEMP_NO, MODEMEMP_YES
+} INSN_MEMORYNESS_MODE;
+
+/* Enum declaration for Whether the indirect operand is autoincrement. */
+typedef enum insn_memincness_mode {
+ MODEINCP_NO, MODEINCP_YES
+} INSN_MEMINCNESS_MODE;
+
+/* Enum declaration for Signed instruction operand size. */
+typedef enum insn_signed_size {
+ SIGNED_UNDEF_SIZE_0, SIGNED_UNDEF_SIZE_1, SIGNED_BYTE, SIGNED_WORD
+} INSN_SIGNED_SIZE;
+
+/* Enum declaration for Unsigned instruction operand size. */
+typedef enum insn_unsigned_size {
+ UNSIGNED_BYTE, UNSIGNED_WORD, UNSIGNED_UNDEF_SIZE_2, UNSIGNED_UNDEF_SIZE_3
+} INSN_UNSIGNED_SIZE;
+
+/* Enum declaration for Insns for MODE_QUICK_IMMEDIATE. */
+typedef enum insn_qi_opc {
+ Q_BCC_0, Q_BCC_1, Q_BCC_2, Q_BCC_3
+ , Q_BDAP_0, Q_BDAP_1, Q_BDAP_2, Q_BDAP_3
+ , Q_ADDQ, Q_MOVEQ, Q_SUBQ, Q_CMPQ
+ , Q_ANDQ, Q_ORQ, Q_ASHQ, Q_LSHQ
+} INSN_QI_OPC;
+
+/* Enum declaration for Same as insn-qi-opc, though using only the high two bits of the opcode. */
+typedef enum insn_qihi_opc {
+ QHI_BCC, QHI_BDAP, QHI_OTHER2, QHI_OTHER3
+} INSN_QIHI_OPC;
+
+/* Enum declaration for Insns for MODE_REGISTER and either SIZE_BYTE, SIZE_WORD or SIZE_DWORD. */
+typedef enum insn_r_opc {
+ R_ADDX, R_MOVX, R_SUBX, R_LSL
+ , R_ADDI, R_BIAP, R_NEG, R_BOUND
+ , R_ADD, R_MOVE, R_SUB, R_CMP
+ , R_AND, R_OR, R_ASR, R_LSR
+} INSN_R_OPC;
+
+/* Enum declaration for Insns for MODE_REGISTER and SIZE_FIXED. */
+typedef enum insn_rfix_opc {
+ RFIX_ADDX, RFIX_MOVX, RFIX_SUBX, RFIX_BTST
+ , RFIX_SCC, RFIX_ADDC, RFIX_SETF, RFIX_CLEARF
+ , RFIX_MOVE_R_S, RFIX_MOVE_S_R, RFIX_ABS, RFIX_DSTEP
+ , RFIX_LZ, RFIX_SWAP, RFIX_XOR, RFIX_MSTEP
+} INSN_RFIX_OPC;
+
+/* Enum declaration for Insns for (MODE_INDIRECT or MODE_AUTOINCREMENT) and either SIZE_BYTE, SIZE_WORD or SIZE_DWORD. */
+typedef enum insn_indir_opc {
+ INDIR_ADDX, INDIR_MOVX, INDIR_SUBX, INDIR_CMPX
+ , INDIR_MUL, INDIR_BDAP_M, INDIR_ADDC, INDIR_BOUND
+ , INDIR_ADD, INDIR_MOVE_M_R, INDIR_SUB, INDIR_CMP
+ , INDIR_AND, INDIR_OR, INDIR_TEST, INDIR_MOVE_R_M
+} INSN_INDIR_OPC;
+
+/* Enum declaration for Insns for (MODE_INDIRECT or MODE_AUTOINCREMENT) and SIZE_FIXED. */
+typedef enum insn_infix_opc {
+ INFIX_ADDX, INFIX_MOVX, INFIX_SUBX, INFIX_CMPX
+ , INFIX_JUMP_M, INFIX_DIP, INFIX_JUMP_R, INFIX_BCC_M
+ , INFIX_MOVE_M_S, INFIX_MOVE_S_M, INFIX_BMOD, INFIX_BSTORE
+ , INFIX_RBF, INFIX_SBFS, INFIX_MOVEM_M_R, INFIX_MOVEM_R_M
+} INSN_INFIX_OPC;
+
+/* Attributes. */
+
+/* Enum declaration for machine type selection. */
+typedef enum mach_attr {
+ MACH_BASE, MACH_CRISV0, MACH_CRISV3, MACH_CRISV8
+ , MACH_CRISV10, MACH_CRISV32, MACH_MAX
+} MACH_ATTR;
+
+/* Enum declaration for instruction set selection. */
+typedef enum isa_attr {
+ ISA_CRIS, ISA_MAX
+} ISA_ATTR;
+
+/* Number of architecture variants. */
+#define MAX_ISAS 1
+#define MAX_MACHS ((int) MACH_MAX)
+
+/* Ifield support. */
+
+extern const struct cgen_ifld cris_cgen_ifld_table[];
+
+/* Ifield attribute indices. */
+
+/* Enum declaration for cgen_ifld attrs. */
+typedef enum cgen_ifld_attr {
+ CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
+ , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
+ , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
+} CGEN_IFLD_ATTR;
+
+/* Number of non-boolean elements in cgen_ifld_attr. */
+#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
+
+/* Enum declaration for cris ifield types. */
+typedef enum ifield_type {
+ CRIS_F_NIL, CRIS_F_ANYOF, CRIS_F_OPERAND1, CRIS_F_SIZE
+ , CRIS_F_OPCODE, CRIS_F_MODE, CRIS_F_OPERAND2, CRIS_F_MEMMODE
+ , CRIS_F_MEMBIT, CRIS_F_B5, CRIS_F_OPCODE_HI, CRIS_F_DSTSRC
+ , CRIS_F_U6, CRIS_F_S6, CRIS_F_U5, CRIS_F_U4
+ , CRIS_F_S8, CRIS_F_DISP9_HI, CRIS_F_DISP9_LO, CRIS_F_DISP9
+ , CRIS_F_QO, CRIS_F_INDIR_PC__BYTE, CRIS_F_INDIR_PC__WORD, CRIS_F_INDIR_PC__WORD_PCREL
+ , CRIS_F_INDIR_PC__DWORD, CRIS_F_INDIR_PC__DWORD_PCREL, CRIS_F_MAX
+} IFIELD_TYPE;
+
+#define MAX_IFLD ((int) CRIS_F_MAX)
+
+/* Hardware attribute indices. */
+
+/* Enum declaration for cgen_hw attrs. */
+typedef enum cgen_hw_attr {
+ CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
+ , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
+} CGEN_HW_ATTR;
+
+/* Number of non-boolean elements in cgen_hw_attr. */
+#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
+
+/* Enum declaration for cris hardware types. */
+typedef enum cgen_hw_type {
+ HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
+ , HW_H_IADDR, HW_H_INC, HW_H_CCODE, HW_H_SWAP
+ , HW_H_FLAGBITS, HW_H_V32, HW_H_PC, HW_H_GR
+ , HW_H_GR_X, HW_H_GR_REAL_PC, HW_H_RAW_GR, HW_H_SR
+ , HW_H_SR_X, HW_H_SUPR, HW_H_CBIT, HW_H_CBIT_MOVE
+ , HW_H_CBIT_MOVE_X, HW_H_VBIT, HW_H_VBIT_MOVE, HW_H_VBIT_MOVE_X
+ , HW_H_ZBIT, HW_H_ZBIT_MOVE, HW_H_ZBIT_MOVE_X, HW_H_NBIT
+ , HW_H_NBIT_MOVE, HW_H_NBIT_MOVE_X, HW_H_XBIT, HW_H_IBIT
+ , HW_H_IBIT_X, HW_H_PBIT, HW_H_RBIT, HW_H_UBIT
+ , HW_H_UBIT_X, HW_H_GBIT, HW_H_KERNEL_SP, HW_H_MBIT
+ , HW_H_QBIT, HW_H_SBIT, HW_H_INSN_PREFIXED_P, HW_H_INSN_PREFIXED_P_X
+ , HW_H_PREFIXREG, HW_MAX
+} CGEN_HW_TYPE;
+
+#define MAX_HW ((int) HW_MAX)
+
+/* Operand attribute indices. */
+
+/* Enum declaration for cgen_operand attrs. */
+typedef enum cgen_operand_attr {
+ CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
+ , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
+ , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
+} CGEN_OPERAND_ATTR;
+
+/* Number of non-boolean elements in cgen_operand_attr. */
+#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
+
+/* Enum declaration for cris operand types. */
+typedef enum cgen_operand_type {
+ CRIS_OPERAND_PC, CRIS_OPERAND_CBIT, CRIS_OPERAND_CBIT_MOVE, CRIS_OPERAND_VBIT
+ , CRIS_OPERAND_VBIT_MOVE, CRIS_OPERAND_ZBIT, CRIS_OPERAND_ZBIT_MOVE, CRIS_OPERAND_NBIT
+ , CRIS_OPERAND_NBIT_MOVE, CRIS_OPERAND_XBIT, CRIS_OPERAND_IBIT, CRIS_OPERAND_UBIT
+ , CRIS_OPERAND_PBIT, CRIS_OPERAND_RBIT, CRIS_OPERAND_SBIT, CRIS_OPERAND_MBIT
+ , CRIS_OPERAND_QBIT, CRIS_OPERAND_PREFIX_SET, CRIS_OPERAND_PREFIXREG, CRIS_OPERAND_RS
+ , CRIS_OPERAND_INC, CRIS_OPERAND_PS, CRIS_OPERAND_SS, CRIS_OPERAND_SD
+ , CRIS_OPERAND_I, CRIS_OPERAND_J, CRIS_OPERAND_C, CRIS_OPERAND_QO
+ , CRIS_OPERAND_RD, CRIS_OPERAND_SCONST8, CRIS_OPERAND_UCONST8, CRIS_OPERAND_SCONST16
+ , CRIS_OPERAND_UCONST16, CRIS_OPERAND_CONST32, CRIS_OPERAND_CONST32_PCREL, CRIS_OPERAND_PD
+ , CRIS_OPERAND_O, CRIS_OPERAND_O_PCREL, CRIS_OPERAND_O_WORD_PCREL, CRIS_OPERAND_CC
+ , CRIS_OPERAND_N, CRIS_OPERAND_SWAPOPTION, CRIS_OPERAND_LIST_OF_FLAGS, CRIS_OPERAND_MAX
+} CGEN_OPERAND_TYPE;
+
+/* Number of operands types. */
+#define MAX_OPERANDS 43
+
+/* Maximum number of operands referenced by any insn. */
+#define MAX_OPERAND_INSTANCES 8
+
+/* Insn attribute indices. */
+
+/* Enum declaration for cgen_insn attrs. */
+typedef enum cgen_insn_attr {
+ CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
+ , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
+ , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
+} CGEN_INSN_ATTR;
+
+/* Number of non-boolean elements in cgen_insn_attr. */
+#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
+
+/* cgen.h uses things we just defined. */
+#include "opcode/cgen.h"
+
+/* Attributes. */
+extern const CGEN_ATTR_TABLE cris_cgen_hardware_attr_table[];
+extern const CGEN_ATTR_TABLE cris_cgen_ifield_attr_table[];
+extern const CGEN_ATTR_TABLE cris_cgen_operand_attr_table[];
+extern const CGEN_ATTR_TABLE cris_cgen_insn_attr_table[];
+
+/* Hardware decls. */
+
+extern CGEN_KEYWORD cris_cgen_opval_h_inc;
+extern CGEN_KEYWORD cris_cgen_opval_h_ccode;
+extern CGEN_KEYWORD cris_cgen_opval_h_swap;
+extern CGEN_KEYWORD cris_cgen_opval_h_flagbits;
+extern CGEN_KEYWORD cris_cgen_opval_gr_names_pcreg;
+extern CGEN_KEYWORD cris_cgen_opval_gr_names_pcreg;
+extern CGEN_KEYWORD cris_cgen_opval_gr_names_acr;
+extern CGEN_KEYWORD cris_cgen_opval_p_names_v10;
+extern CGEN_KEYWORD cris_cgen_opval_p_names_v10;
+extern CGEN_KEYWORD cris_cgen_opval_p_names_v10;
+extern CGEN_KEYWORD cris_cgen_opval_p_names_v10;
+extern CGEN_KEYWORD cris_cgen_opval_p_names_v32;
+extern CGEN_KEYWORD cris_cgen_opval_h_supr;
+
+extern const CGEN_HW_ENTRY cris_cgen_hw_table[];
+
+
+
+#endif /* CRIS_CPU_H */
--- /dev/null
+/* Instruction opcode header for cris.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2004 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef CRIS_OPC_H
+#define CRIS_OPC_H
+
+/* Enum declaration for cris instruction types. */
+typedef enum cgen_insn_type {
+ CRIS_INSN_INVALID, CRIS_INSN_NOP, CRIS_INSN_MOVE_B_R, CRIS_INSN_MOVE_W_R
+ , CRIS_INSN_MOVE_D_R, CRIS_INSN_MOVEPCR, CRIS_INSN_MOVEQ, CRIS_INSN_MOVS_B_R
+ , CRIS_INSN_MOVS_W_R, CRIS_INSN_MOVU_B_R, CRIS_INSN_MOVU_W_R, CRIS_INSN_MOVECBR
+ , CRIS_INSN_MOVECWR, CRIS_INSN_MOVECDR, CRIS_INSN_MOVSCBR, CRIS_INSN_MOVSCWR
+ , CRIS_INSN_MOVUCBR, CRIS_INSN_MOVUCWR, CRIS_INSN_ADDQ, CRIS_INSN_SUBQ
+ , CRIS_INSN_CMP_R_B_R, CRIS_INSN_CMP_R_W_R, CRIS_INSN_CMP_R_D_R, CRIS_INSN_CMP_M_B_M
+ , CRIS_INSN_CMP_M_W_M, CRIS_INSN_CMP_M_D_M, CRIS_INSN_CMPCBR, CRIS_INSN_CMPCWR
+ , CRIS_INSN_CMPCDR, CRIS_INSN_CMPQ, CRIS_INSN_CMPS_M_B_M, CRIS_INSN_CMPS_M_W_M
+ , CRIS_INSN_CMPSCBR, CRIS_INSN_CMPSCWR, CRIS_INSN_CMPU_M_B_M, CRIS_INSN_CMPU_M_W_M
+ , CRIS_INSN_CMPUCBR, CRIS_INSN_CMPUCWR, CRIS_INSN_MOVE_M_B_M, CRIS_INSN_MOVE_M_W_M
+ , CRIS_INSN_MOVE_M_D_M, CRIS_INSN_MOVS_M_B_M, CRIS_INSN_MOVS_M_W_M, CRIS_INSN_MOVU_M_B_M
+ , CRIS_INSN_MOVU_M_W_M, CRIS_INSN_MOVE_R_SPRV0, CRIS_INSN_MOVE_R_SPRV3, CRIS_INSN_MOVE_R_SPRV8
+ , CRIS_INSN_MOVE_R_SPRV10, CRIS_INSN_MOVE_R_SPRV32, CRIS_INSN_MOVE_SPR_RV0, CRIS_INSN_MOVE_SPR_RV3
+ , CRIS_INSN_MOVE_SPR_RV8, CRIS_INSN_MOVE_SPR_RV10, CRIS_INSN_MOVE_SPR_RV32, CRIS_INSN_RET_TYPE
+ , CRIS_INSN_MOVE_M_SPRV0, CRIS_INSN_MOVE_M_SPRV3, CRIS_INSN_MOVE_M_SPRV8, CRIS_INSN_MOVE_M_SPRV10
+ , CRIS_INSN_MOVE_M_SPRV32, CRIS_INSN_MOVE_C_SPRV0_P0, CRIS_INSN_MOVE_C_SPRV0_P1, CRIS_INSN_MOVE_C_SPRV0_P4
+ , CRIS_INSN_MOVE_C_SPRV0_P5, CRIS_INSN_MOVE_C_SPRV0_P8, CRIS_INSN_MOVE_C_SPRV0_P9, CRIS_INSN_MOVE_C_SPRV0_P10
+ , CRIS_INSN_MOVE_C_SPRV0_P11, CRIS_INSN_MOVE_C_SPRV0_P12, CRIS_INSN_MOVE_C_SPRV0_P13, CRIS_INSN_MOVE_C_SPRV0_P6
+ , CRIS_INSN_MOVE_C_SPRV0_P7, CRIS_INSN_MOVE_C_SPRV3_P0, CRIS_INSN_MOVE_C_SPRV3_P1, CRIS_INSN_MOVE_C_SPRV3_P4
+ , CRIS_INSN_MOVE_C_SPRV3_P5, CRIS_INSN_MOVE_C_SPRV3_P8, CRIS_INSN_MOVE_C_SPRV3_P9, CRIS_INSN_MOVE_C_SPRV3_P10
+ , CRIS_INSN_MOVE_C_SPRV3_P11, CRIS_INSN_MOVE_C_SPRV3_P12, CRIS_INSN_MOVE_C_SPRV3_P13, CRIS_INSN_MOVE_C_SPRV3_P6
+ , CRIS_INSN_MOVE_C_SPRV3_P7, CRIS_INSN_MOVE_C_SPRV3_P14, CRIS_INSN_MOVE_C_SPRV8_P0, CRIS_INSN_MOVE_C_SPRV8_P1
+ , CRIS_INSN_MOVE_C_SPRV8_P4, CRIS_INSN_MOVE_C_SPRV8_P5, CRIS_INSN_MOVE_C_SPRV8_P8, CRIS_INSN_MOVE_C_SPRV8_P9
+ , CRIS_INSN_MOVE_C_SPRV8_P10, CRIS_INSN_MOVE_C_SPRV8_P11, CRIS_INSN_MOVE_C_SPRV8_P12, CRIS_INSN_MOVE_C_SPRV8_P13
+ , CRIS_INSN_MOVE_C_SPRV8_P14, CRIS_INSN_MOVE_C_SPRV10_P0, CRIS_INSN_MOVE_C_SPRV10_P1, CRIS_INSN_MOVE_C_SPRV10_P4
+ , CRIS_INSN_MOVE_C_SPRV10_P5, CRIS_INSN_MOVE_C_SPRV10_P8, CRIS_INSN_MOVE_C_SPRV10_P9, CRIS_INSN_MOVE_C_SPRV10_P10
+ , CRIS_INSN_MOVE_C_SPRV10_P11, CRIS_INSN_MOVE_C_SPRV10_P12, CRIS_INSN_MOVE_C_SPRV10_P13, CRIS_INSN_MOVE_C_SPRV10_P7
+ , CRIS_INSN_MOVE_C_SPRV10_P14, CRIS_INSN_MOVE_C_SPRV10_P15, CRIS_INSN_MOVE_C_SPRV32_P0, CRIS_INSN_MOVE_C_SPRV32_P1
+ , CRIS_INSN_MOVE_C_SPRV32_P2, CRIS_INSN_MOVE_C_SPRV32_P3, CRIS_INSN_MOVE_C_SPRV32_P4, CRIS_INSN_MOVE_C_SPRV32_P5
+ , CRIS_INSN_MOVE_C_SPRV32_P6, CRIS_INSN_MOVE_C_SPRV32_P7, CRIS_INSN_MOVE_C_SPRV32_P8, CRIS_INSN_MOVE_C_SPRV32_P9
+ , CRIS_INSN_MOVE_C_SPRV32_P10, CRIS_INSN_MOVE_C_SPRV32_P11, CRIS_INSN_MOVE_C_SPRV32_P12, CRIS_INSN_MOVE_C_SPRV32_P13
+ , CRIS_INSN_MOVE_C_SPRV32_P14, CRIS_INSN_MOVE_C_SPRV32_P15, CRIS_INSN_MOVE_SPR_MV0, CRIS_INSN_MOVE_SPR_MV3
+ , CRIS_INSN_MOVE_SPR_MV8, CRIS_INSN_MOVE_SPR_MV10, CRIS_INSN_MOVE_SPR_MV32, CRIS_INSN_SBFS
+ , CRIS_INSN_MOVE_SS_R, CRIS_INSN_MOVE_R_SS, CRIS_INSN_MOVEM_R_M, CRIS_INSN_MOVEM_R_M_V32
+ , CRIS_INSN_MOVEM_M_R, CRIS_INSN_MOVEM_M_PC, CRIS_INSN_MOVEM_M_R_V32, CRIS_INSN_ADD_B_R
+ , CRIS_INSN_ADD_W_R, CRIS_INSN_ADD_D_R, CRIS_INSN_ADD_M_B_M, CRIS_INSN_ADD_M_W_M
+ , CRIS_INSN_ADD_M_D_M, CRIS_INSN_ADDCBR, CRIS_INSN_ADDCWR, CRIS_INSN_ADDCDR
+ , CRIS_INSN_ADDCPC, CRIS_INSN_ADDS_B_R, CRIS_INSN_ADDS_W_R, CRIS_INSN_ADDS_M_B_M
+ , CRIS_INSN_ADDS_M_W_M, CRIS_INSN_ADDSCBR, CRIS_INSN_ADDSCWR, CRIS_INSN_ADDSPCPC
+ , CRIS_INSN_ADDU_B_R, CRIS_INSN_ADDU_W_R, CRIS_INSN_ADDU_M_B_M, CRIS_INSN_ADDU_M_W_M
+ , CRIS_INSN_ADDUCBR, CRIS_INSN_ADDUCWR, CRIS_INSN_SUB_B_R, CRIS_INSN_SUB_W_R
+ , CRIS_INSN_SUB_D_R, CRIS_INSN_SUB_M_B_M, CRIS_INSN_SUB_M_W_M, CRIS_INSN_SUB_M_D_M
+ , CRIS_INSN_SUBCBR, CRIS_INSN_SUBCWR, CRIS_INSN_SUBCDR, CRIS_INSN_SUBS_B_R
+ , CRIS_INSN_SUBS_W_R, CRIS_INSN_SUBS_M_B_M, CRIS_INSN_SUBS_M_W_M, CRIS_INSN_SUBSCBR
+ , CRIS_INSN_SUBSCWR, CRIS_INSN_SUBU_B_R, CRIS_INSN_SUBU_W_R, CRIS_INSN_SUBU_M_B_M
+ , CRIS_INSN_SUBU_M_W_M, CRIS_INSN_SUBUCBR, CRIS_INSN_SUBUCWR, CRIS_INSN_ADDC_R
+ , CRIS_INSN_ADDC_M, CRIS_INSN_ADDC_C, CRIS_INSN_LAPC_D, CRIS_INSN_LAPCQ
+ , CRIS_INSN_ADDI_B_R, CRIS_INSN_ADDI_W_R, CRIS_INSN_ADDI_D_R, CRIS_INSN_NEG_B_R
+ , CRIS_INSN_NEG_W_R, CRIS_INSN_NEG_D_R, CRIS_INSN_TEST_M_B_M, CRIS_INSN_TEST_M_W_M
+ , CRIS_INSN_TEST_M_D_M, CRIS_INSN_MOVE_R_M_B_M, CRIS_INSN_MOVE_R_M_W_M, CRIS_INSN_MOVE_R_M_D_M
+ , CRIS_INSN_MULS_B, CRIS_INSN_MULS_W, CRIS_INSN_MULS_D, CRIS_INSN_MULU_B
+ , CRIS_INSN_MULU_W, CRIS_INSN_MULU_D, CRIS_INSN_MCP, CRIS_INSN_MSTEP
+ , CRIS_INSN_DSTEP, CRIS_INSN_ABS, CRIS_INSN_AND_B_R, CRIS_INSN_AND_W_R
+ , CRIS_INSN_AND_D_R, CRIS_INSN_AND_M_B_M, CRIS_INSN_AND_M_W_M, CRIS_INSN_AND_M_D_M
+ , CRIS_INSN_ANDCBR, CRIS_INSN_ANDCWR, CRIS_INSN_ANDCDR, CRIS_INSN_ANDQ
+ , CRIS_INSN_ORR_B_R, CRIS_INSN_ORR_W_R, CRIS_INSN_ORR_D_R, CRIS_INSN_OR_M_B_M
+ , CRIS_INSN_OR_M_W_M, CRIS_INSN_OR_M_D_M, CRIS_INSN_ORCBR, CRIS_INSN_ORCWR
+ , CRIS_INSN_ORCDR, CRIS_INSN_ORQ, CRIS_INSN_XOR, CRIS_INSN_NOT
+ , CRIS_INSN_SWAP, CRIS_INSN_ASRR_B_R, CRIS_INSN_ASRR_W_R, CRIS_INSN_ASRR_D_R
+ , CRIS_INSN_ASRQ, CRIS_INSN_LSRR_B_R, CRIS_INSN_LSRR_W_R, CRIS_INSN_LSRR_D_R
+ , CRIS_INSN_LSRQ, CRIS_INSN_LSLR_B_R, CRIS_INSN_LSLR_W_R, CRIS_INSN_LSLR_D_R
+ , CRIS_INSN_LSLQ, CRIS_INSN_BTST, CRIS_INSN_BTSTQ, CRIS_INSN_SETF
+ , CRIS_INSN_CLEARF, CRIS_INSN_RFE, CRIS_INSN_SFE, CRIS_INSN_RFG
+ , CRIS_INSN_RFN, CRIS_INSN_HALT, CRIS_INSN_BCC_B, CRIS_INSN_BA_B
+ , CRIS_INSN_BCC_W, CRIS_INSN_BA_W, CRIS_INSN_JAS_R, CRIS_INSN_JUMP_R
+ , CRIS_INSN_JAS_C, CRIS_INSN_JUMP_M, CRIS_INSN_JUMP_C, CRIS_INSN_JUMP_P
+ , CRIS_INSN_BAS_C, CRIS_INSN_JASC_R, CRIS_INSN_JASC_C, CRIS_INSN_BASC_C
+ , CRIS_INSN_BREAK, CRIS_INSN_BOUND_R_B_R, CRIS_INSN_BOUND_R_W_R, CRIS_INSN_BOUND_R_D_R
+ , CRIS_INSN_BOUND_M_B_M, CRIS_INSN_BOUND_M_W_M, CRIS_INSN_BOUND_M_D_M, CRIS_INSN_BOUND_CB
+ , CRIS_INSN_BOUND_CW, CRIS_INSN_BOUND_CD, CRIS_INSN_SCC, CRIS_INSN_LZ
+ , CRIS_INSN_ADDOQ, CRIS_INSN_BDAPQPC, CRIS_INSN_ADDO_M_B_M, CRIS_INSN_ADDO_M_W_M
+ , CRIS_INSN_ADDO_M_D_M, CRIS_INSN_ADDO_CB, CRIS_INSN_ADDO_CW, CRIS_INSN_ADDO_CD
+ , CRIS_INSN_DIP_M, CRIS_INSN_DIP_C, CRIS_INSN_ADDI_ACR_B_R, CRIS_INSN_ADDI_ACR_W_R
+ , CRIS_INSN_ADDI_ACR_D_R, CRIS_INSN_BIAP_PC_B_R, CRIS_INSN_BIAP_PC_W_R, CRIS_INSN_BIAP_PC_D_R
+ , CRIS_INSN_FIDXI, CRIS_INSN_FTAGI, CRIS_INSN_FIDXD, CRIS_INSN_FTAGD
+} CGEN_INSN_TYPE;
+
+/* Index of `invalid' insn place holder. */
+#define CGEN_INSN_INVALID CRIS_INSN_INVALID
+
+/* Total number of insns in table. */
+#define MAX_INSNS ((int) CRIS_INSN_FTAGD + 1)
+
+/* This struct records data prior to insertion or after extraction. */
+struct cgen_fields
+{
+ int length;
+ long f_nil;
+ long f_anyof;
+ long f_operand1;
+ long f_size;
+ long f_opcode;
+ long f_mode;
+ long f_operand2;
+ long f_memmode;
+ long f_membit;
+ long f_b5;
+ long f_opcode_hi;
+ long f_dstsrc;
+ long f_u6;
+ long f_s6;
+ long f_u5;
+ long f_u4;
+ long f_s8;
+ long f_disp9_hi;
+ long f_disp9_lo;
+ long f_disp9;
+ long f_qo;
+ long f_indir_pc__byte;
+ long f_indir_pc__word;
+ long f_indir_pc__word_pcrel;
+ long f_indir_pc__dword;
+ long f_indir_pc__dword_pcrel;
+};
+
+#define CGEN_INIT_PARSE(od) \
+{\
+}
+#define CGEN_INIT_INSERT(od) \
+{\
+}
+#define CGEN_INIT_EXTRACT(od) \
+{\
+}
+#define CGEN_INIT_PRINT(od) \
+{\
+}
+
+
+#endif /* CRIS_OPC_H */
--- /dev/null
+/* Collection of junk for CRIS.
+ Copyright (C) 2004, 2005 Free Software Foundation, Inc.
+ Contributed by Axis Communications.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+/* For other arch:s, this file is described as a "collection of junk", so
+ let's collect some nice junk of our own. Keep it; it might be useful
+ some day! */
+
+#ifndef CRIS_SIM_H
+#define CRIS_SIM_H
+
+typedef struct {
+ /* Whether the branch for the current insn was taken. Placed first
+ here, in hope it'll get closer to the main simulator data. */
+ USI branch_taken;
+
+ /* PC of the insn of the branch. */
+ USI old_pc;
+
+ /* Static cycle count for all insns executed so far, including
+ non-context-specific stall cycles, for example when adding to PC. */
+ unsigned64 basic_cycle_count;
+
+ /* Stall cycles for unaligned access of memory operands. FIXME:
+ Should or should not include unaligned [PC+] operands? */
+ unsigned64 unaligned_mem_dword_count;
+
+ /* Context-specific stall cycles. */
+ unsigned64 memsrc_stall_count;
+ unsigned64 memraw_stall_count;
+ unsigned64 movemsrc_stall_count;
+ unsigned64 movemaddr_stall_count;
+ unsigned64 movemdst_stall_count;
+ unsigned64 mulsrc_stall_count;
+ unsigned64 jumpsrc_stall_count;
+ unsigned64 branch_stall_count;
+ unsigned64 jumptarget_stall_count;
+
+ /* What kind of target-specific trace to perform. */
+ int flags;
+
+ /* Just the basic cycle count. */
+#define FLAG_CRIS_MISC_PROFILE_SIMPLE 1
+
+ /* Show unaligned accesses. */
+#define FLAG_CRIS_MISC_PROFILE_UNALIGNED 2
+
+ /* Show schedulable entities. */
+#define FLAG_CRIS_MISC_PROFILE_SCHEDULABLE 4
+
+ /* Show everything. */
+#define FLAG_CRIS_MISC_PROFILE_ALL \
+ (FLAG_CRIS_MISC_PROFILE_SIMPLE \
+ | FLAG_CRIS_MISC_PROFILE_UNALIGNED \
+ | FLAG_CRIS_MISC_PROFILE_SCHEDULABLE)
+
+ /* Emit trace of each insn, xsim style. */
+#define FLAG_CRIS_MISC_PROFILE_XSIM_TRACE 8
+
+#define N_CRISV32_BRANCH_PREDICTORS 256
+ unsigned char branch_predictors[N_CRISV32_BRANCH_PREDICTORS];
+
+} CRIS_MISC_PROFILE;
+
+/* Handler prototypes for functions called from the CGEN description. */
+
+extern USI cris_bmod_handler (SIM_CPU *, UINT, USI);
+extern void cris_flush_simulator_decode_cache (SIM_CPU *, USI);
+extern USI crisv10f_break_handler (SIM_CPU *, USI, USI);
+extern USI crisv32f_break_handler (SIM_CPU *, USI, USI);
+extern USI cris_break_13_handler (SIM_CPU *, USI, USI, USI, USI, USI, USI,
+ USI, USI);
+
+/* Using GNU syntax (not C99) so we can compile this on RH 6.2
+ (egcs-1.1.2/gcc-2.91.66). */
+#define cris_trace_printf(SD, CPU, FMT...) \
+ do \
+ { \
+ if (TRACE_FILE (STATE_TRACE_DATA (SD)) != NULL) \
+ fprintf (TRACE_FILE (CPU_TRACE_DATA (CPU)), FMT); \
+ else \
+ sim_io_printf (SD, FMT); \
+ } \
+ while (0)
+
+#if WITH_PROFILE_MODEL_P
+#define crisv32f_branch_taken(cpu, oldpc, newpc, taken) \
+ do \
+ { \
+ CPU_CRIS_MISC_PROFILE (cpu)->old_pc = oldpc; \
+ CPU_CRIS_MISC_PROFILE (cpu)->branch_taken = taken; \
+ } \
+ while (0)
+#else
+#define crisv32f_branch_taken(cpu, oldpc, newpc, taken)
+#endif
+
+#define crisv10f_branch_taken(cpu, oldpc, newpc, taken)
+
+#define crisv32f_read_supr(cpu, index) \
+ (cgen_rtx_error (current_cpu, \
+ "Read of support register is unimplemented"), \
+ 0)
+
+#define crisv32f_write_supr(cpu, index, val) \
+ cgen_rtx_error (current_cpu, \
+ "Write to support register is unimplemented") \
+
+#define crisv32f_rfg_handler(cpu, pc) \
+ cgen_rtx_error (current_cpu, "RFG isn't implemented")
+
+#define crisv32f_halt_handler(cpu, pc) \
+ (cgen_rtx_error (current_cpu, "HALT isn't implemented"), 0)
+
+#define crisv32f_fidxi_handler(cpu, pc, indx) \
+ (cgen_rtx_error (current_cpu, "FIDXI isn't implemented"), 0)
+
+#define crisv32f_ftagi_handler(cpu, pc, indx) \
+ (cgen_rtx_error (current_cpu, "FTAGI isn't implemented"), 0)
+
+#define crisv32f_fidxd_handler(cpu, pc, indx) \
+ (cgen_rtx_error (current_cpu, "FIDXD isn't implemented"), 0)
+
+#define crisv32f_ftagd_handler(cpu, pc, indx) \
+ (cgen_rtx_error (current_cpu, "FTAGD isn't implemented"), 0)
+
+/* We have nothing special to do when interrupts or NMI are enabled
+ after having been disabled, so empty macros are enough for these
+ hooks. */
+#define crisv32f_interrupts_enabled(cpu)
+#define crisv32f_nmi_enabled(cpu)
+
+/* Better warn for this case here, because everything needed is
+ somewhere within the CPU. Compare to trying to use interrupts and
+ NMI, which would fail earlier, when trying to make nonexistent
+ external components generate those exceptions. */
+#define crisv32f_single_step_enabled(cpu) \
+ ((crisv32f_h_qbit_get (cpu) != 0 \
+ || (crisv32f_h_sr_get (cpu, H_SR_SPC) & ~1) != 0) \
+ ? (cgen_rtx_error (cpu, \
+ "single-stepping isn't implemented"), 0) \
+ : 0)
+
+/* We don't need to track the value of the PID register here. */
+#define crisv32f_write_pid_handler(cpu, val)
+
+/* Neither do we need to know of transitions to user mode. */
+#define crisv32f_usermode_enabled(cpu)
+
+/* House-keeping exported from traps.c */
+extern void cris_set_callbacks (host_callback *);
+
+/* FIXME: Add more junk. */
+#endif
--- /dev/null
+/* CRIS base simulator support code
+ Copyright (C) 2004, 2005 Free Software Foundation, Inc.
+ Contributed by Axis Communications.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+/* The infrastructure is based on that of i960.c. */
+
+#define WANT_CPU
+
+#include "sim-main.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+
+#define MY(f) XCONCAT3(crisv,BASENUM,f)
+
+/* Dispatcher for break insn. */
+
+USI
+MY (f_break_handler) (SIM_CPU *cpu, USI breaknum, USI pc)
+{
+ SIM_DESC sd = CPU_STATE (cpu);
+ USI ret = pc + 2;
+
+ MY (f_h_pc_set) (cpu, ret);
+
+ /* FIXME: Error out if IBR or ERP set. */
+ switch (breaknum)
+ {
+ case 13:
+ MY (f_h_gr_set (cpu, 10,
+ cris_break_13_handler (cpu,
+ MY (f_h_gr_get (cpu, 9)),
+ MY (f_h_gr_get (cpu, 10)),
+ MY (f_h_gr_get (cpu, 11)),
+ MY (f_h_gr_get (cpu, 12)),
+ MY (f_h_gr_get (cpu, 13)),
+ MY (f_h_sr_get (cpu, 7)),
+ MY (f_h_sr_get (cpu, 11)),
+ pc)));
+ break;
+
+ case 14:
+ sim_io_printf (sd, "%x\n", MY (f_h_gr_get (cpu, 3)));
+ break;
+
+ case 15:
+ /* Re-use the Linux exit call. */
+ cris_break_13_handler (cpu, /* TARGET_SYS_exit */ 1, 0,
+ 0, 0, 0, 0, 0, pc);
+
+ default:
+ abort ();
+ }
+
+ return MY (f_h_pc_get) (cpu);
+}
+
+/* Accessor function for simulator internal use.
+ Note the contents of BUF are in target byte order. */
+
+int
+MY (f_fetch_register) (SIM_CPU *current_cpu, int rn,
+ unsigned char *buf, int len ATTRIBUTE_UNUSED)
+{
+ SETTSI (buf, XCONCAT3(crisv,BASENUM,f_h_gr_get) (current_cpu, rn));
+ return -1;
+}
+
+/* Accessor function for simulator internal use.
+ Note the contents of BUF are in target byte order. */
+
+int
+MY (f_store_register) (SIM_CPU *current_cpu, int rn,
+ unsigned char *buf, int len ATTRIBUTE_UNUSED)
+{
+ XCONCAT3(crisv,BASENUM,f_h_gr_set) (current_cpu, rn, GETTSI (buf));
+ return -1;
+}
+\f
+#if WITH_PROFILE_MODEL_P
+
+/* FIXME: Some of these should be inline or macros. Later. */
+
+/* Initialize cycle counting for an insn.
+ FIRST_P is non-zero if this is the first insn in a set of parallel
+ insns. */
+
+void
+MY (f_model_insn_before) (SIM_CPU *current_cpu, int first_p ATTRIBUTE_UNUSED)
+{
+ /* To give the impression that we actually know what PC is, we have to
+ dump register contents *before* the *next* insn, not after the
+ *previous* insn. Uhh... */
+
+ /* FIXME: Move this to separate, overridable function. */
+ if ((CPU_CRIS_MISC_PROFILE (current_cpu)->flags
+ & FLAG_CRIS_MISC_PROFILE_XSIM_TRACE)
+#ifdef GET_H_INSN_PREFIXED_P
+ /* For versions with prefixed insns, trace the combination as
+ one insn. */
+ && !GET_H_INSN_PREFIXED_P ()
+#endif
+ && 1)
+ {
+ int i;
+ char flags[7];
+ SIM_DESC sd = CPU_STATE (current_cpu);
+
+ cris_trace_printf (sd, current_cpu, "%lx ", (unsigned long) (CPU (h_pc)));
+
+ for (i = 0; i < 15; i++)
+ cris_trace_printf (sd, current_cpu, "%lx ",
+ (unsigned long) (XCONCAT3(crisv,BASENUM,
+ f_h_gr_get) (current_cpu,
+ i)));
+ flags[0] = GET_H_IBIT () != 0 ? 'I' : 'i';
+ flags[1] = GET_H_XBIT () != 0 ? 'X' : 'x';
+ flags[2] = GET_H_NBIT () != 0 ? 'N' : 'n';
+ flags[3] = GET_H_ZBIT () != 0 ? 'Z' : 'z';
+ flags[4] = GET_H_VBIT () != 0 ? 'V' : 'v';
+ flags[5] = GET_H_CBIT () != 0 ? 'C' : 'c';
+ flags[6] = 0;
+
+ /* Emit ACR after flags and cycle count for this insn. */
+ if (BASENUM == 32)
+ cris_trace_printf (sd, current_cpu, "%s %d %lx\n", flags,
+ (int)
+ ((CPU_CRIS_MISC_PROFILE (current_cpu)
+ ->basic_cycle_count
+ - CPU_CRIS_PREV_MISC_PROFILE (current_cpu)
+ ->basic_cycle_count)
+ + (CPU_CRIS_MISC_PROFILE (current_cpu)
+ ->unaligned_mem_dword_count
+ - CPU_CRIS_PREV_MISC_PROFILE (current_cpu)
+ ->unaligned_mem_dword_count)),
+ (unsigned long) (XCONCAT3(crisv,BASENUM,
+ f_h_gr_get) (current_cpu,
+ 15)));
+ else
+ cris_trace_printf (sd, current_cpu, "%s %d\n", flags,
+ (int)
+ ((CPU_CRIS_MISC_PROFILE (current_cpu)
+ ->basic_cycle_count
+ - CPU_CRIS_PREV_MISC_PROFILE (current_cpu)
+ ->basic_cycle_count)
+ + (CPU_CRIS_MISC_PROFILE (current_cpu)
+ ->unaligned_mem_dword_count
+ - CPU_CRIS_PREV_MISC_PROFILE (current_cpu)
+ ->unaligned_mem_dword_count)));
+
+ CPU_CRIS_PREV_MISC_PROFILE (current_cpu)[0]
+ = CPU_CRIS_MISC_PROFILE (current_cpu)[0];
+ }
+}
+
+/* Record the cycles computed for an insn.
+ LAST_P is non-zero if this is the last insn in a set of parallel insns,
+ and we update the total cycle count.
+ CYCLES is the cycle count of the insn. */
+
+void
+MY (f_model_insn_after) (SIM_CPU *current_cpu, int last_p ATTRIBUTE_UNUSED,
+ int cycles)
+{
+ PROFILE_DATA *p = CPU_PROFILE_DATA (current_cpu);
+
+ PROFILE_MODEL_TOTAL_CYCLES (p) += cycles;
+ CPU_CRIS_MISC_PROFILE (current_cpu)->basic_cycle_count += cycles;
+ PROFILE_MODEL_CUR_INSN_CYCLES (p) = cycles;
+}
+
+/* Initialize cycle counting for an insn.
+ FIRST_P is non-zero if this is the first insn in a set of parallel
+ insns. */
+
+void
+MY (f_model_init_insn_cycles) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
+ int first_p ATTRIBUTE_UNUSED)
+{
+ abort ();
+}
+
+/* Record the cycles computed for an insn.
+ LAST_P is non-zero if this is the last insn in a set of parallel insns,
+ and we update the total cycle count. */
+
+void
+MY (f_model_update_insn_cycles) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
+ int last_p ATTRIBUTE_UNUSED)
+{
+ abort ();
+}
+
+#if 0
+void
+MY (f_model_record_cycles) (SIM_CPU *current_cpu, unsigned long cycles)
+{
+ abort ();
+}
+
+void
+MY (f_model_mark_get_h_gr) (SIM_CPU *current_cpu, ARGBUF *abuf)
+{
+ abort ();
+}
+
+void
+MY (f_model_mark_set_h_gr) (SIM_CPU *current_cpu, ARGBUF *abuf)
+{
+ abort ();
+}
+#endif
+\f
+/* Create the context for a thread. */
+
+void *
+MY (make_thread_cpu_data) (SIM_CPU *current_cpu, void *context)
+{
+ void *info = xmalloc (current_cpu->thread_cpu_data_size);
+
+ if (context != NULL)
+ memcpy (info,
+ context,
+ current_cpu->thread_cpu_data_size);
+ else
+ memset (info, 0, current_cpu->thread_cpu_data_size),abort();
+ return info;
+}
+
+/* Hook function for per-cpu simulator initialization. */
+
+void
+MY (f_specific_init) (SIM_CPU *current_cpu)
+{
+ current_cpu->make_thread_cpu_data = MY (make_thread_cpu_data);
+ current_cpu->thread_cpu_data_size = sizeof (current_cpu->cpu_data);
+}
+\f
+/* Model function for arbitrary single stall cycles. */
+
+int
+MY (XCONCAT3 (f_model_crisv,BASENUM,
+ _u_stall)) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
+ const IDESC *idesc,
+ int unit_num,
+ int referenced ATTRIBUTE_UNUSED)
+{
+ return idesc->timing->units[unit_num].done;
+}
+
+#ifndef SPECIFIC_U_SKIP4_FN
+
+/* Model function for u-skip4 unit. */
+
+int
+MY (XCONCAT3 (f_model_crisv,BASENUM,
+ _u_skip4)) (SIM_CPU *current_cpu,
+ const IDESC *idesc,
+ int unit_num,
+ int referenced ATTRIBUTE_UNUSED)
+{
+ /* Handle PC not being updated with pbb. FIXME: What if not pbb? */
+ CPU (h_pc) += 4;
+ return idesc->timing->units[unit_num].done;
+}
+
+#endif
+
+#ifndef SPECIFIC_U_EXEC_FN
+
+/* Model function for u-exec unit. */
+
+int
+MY (XCONCAT3 (f_model_crisv,BASENUM,
+ _u_exec)) (SIM_CPU *current_cpu,
+ const IDESC *idesc,
+ int unit_num, int referenced ATTRIBUTE_UNUSED)
+{
+ /* Handle PC not being updated with pbb. FIXME: What if not pbb? */
+ CPU (h_pc) += 2;
+ return idesc->timing->units[unit_num].done;
+}
+#endif
+
+#ifndef SPECIFIC_U_MEM_FN
+
+/* Model function for u-mem unit. */
+
+int
+MY (XCONCAT3 (f_model_crisv,BASENUM,
+ _u_mem)) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
+ const IDESC *idesc,
+ int unit_num,
+ int referenced ATTRIBUTE_UNUSED)
+{
+ return idesc->timing->units[unit_num].done;
+}
+#endif
+
+#ifndef SPECIFIC_U_CONST16_FN
+
+/* Model function for u-const16 unit. */
+
+int
+MY (XCONCAT3 (f_model_crisv,BASENUM,
+ _u_const16)) (SIM_CPU *current_cpu,
+ const IDESC *idesc,
+ int unit_num,
+ int referenced ATTRIBUTE_UNUSED)
+{
+ CPU (h_pc) += 2;
+ return idesc->timing->units[unit_num].done;
+}
+#endif /* SPECIFIC_U_CONST16_FN */
+
+#ifndef SPECIFIC_U_CONST32_FN
+
+/* This will be incorrect for early models, where a dword always take
+ two cycles. */
+#define CRIS_MODEL_MASK_PC_STALL 2
+
+/* Model function for u-const32 unit. */
+
+int
+MY (XCONCAT3 (f_model_crisv,BASENUM,
+ _u_const32)) (SIM_CPU *current_cpu,
+ const IDESC *idesc,
+ int unit_num,
+ int referenced ATTRIBUTE_UNUSED)
+{
+ int unaligned_extra
+ = (((CPU (h_pc) + 2) & CRIS_MODEL_MASK_PC_STALL)
+ == CRIS_MODEL_MASK_PC_STALL);
+
+ /* Handle PC not being updated with pbb. FIXME: What if not pbb? */
+ CPU_CRIS_MISC_PROFILE (current_cpu)->unaligned_mem_dword_count
+ += unaligned_extra;
+
+ CPU (h_pc) += 4;
+ return idesc->timing->units[unit_num].done;
+}
+#endif /* SPECIFIC_U_CONST32_FN */
+
+#ifndef SPECIFIC_U_MOVEM_FN
+
+/* Model function for u-movem unit. */
+
+int
+MY (XCONCAT3 (f_model_crisv,BASENUM,
+ _u_movem)) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
+ const IDESC *idesc ATTRIBUTE_UNUSED,
+ int unit_num ATTRIBUTE_UNUSED,
+ int referenced ATTRIBUTE_UNUSED,
+ INT limreg)
+{
+ /* FIXME: Add cycles for misalignment. */
+
+ if (limreg == -1)
+ abort ();
+
+ /* We don't record movem move cycles in movemsrc_stall_count since
+ those cycles have historically been handled as ordinary cycles. */
+ return limreg + 1;
+}
+#endif /* SPECIFIC_U_MOVEM_FN */
+
+#endif /* WITH_PROFILE_MODEL_P */
--- /dev/null
+/* CRIS v10 simulator support code
+ Copyright (C) 2004, 2005 Free Software Foundation, Inc.
+ Contributed by Axis Communications.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+/* The infrastructure is based on that of i960.c. */
+
+#define WANT_CPU_CRISV10F
+
+#define BASENUM 10
+#include "cris-tmpl.c"
+
+#if WITH_PROFILE_MODEL_P
+
+/* Model function for u-multiply unit. */
+
+int
+MY (XCONCAT3 (f_model_crisv,BASENUM,
+ _u_multiply)) (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
+ const IDESC *idesc ATTRIBUTE_UNUSED,
+ int unit_num ATTRIBUTE_UNUSED,
+ int referenced ATTRIBUTE_UNUSED)
+{
+ return 1;
+}
+
+#endif /* WITH_PROFILE_MODEL_P */
--- /dev/null
+/* CRIS v32 simulator support code
+ Copyright (C) 2004, 2005 Free Software Foundation, Inc.
+ Contributed by Axis Communications.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+/* The infrastructure is based on that of i960.c. */
+
+#define WANT_CPU_CRISV32F
+
+#define SPECIFIC_U_EXEC_FN
+#define SPECIFIC_U_SKIP4_FN
+#define SPECIFIC_U_CONST16_FN
+#define SPECIFIC_U_CONST32_FN
+#define SPECIFIC_U_MEM_FN
+#define SPECIFIC_U_MOVEM_FN
+#define BASENUM 32
+#include "cris-tmpl.c"
+
+#if WITH_PROFILE_MODEL_P
+
+/* Re-use the bit position for the BZ register, since there are no stall
+ cycles for reading or writing it. */
+#define CRIS_BZ_REGNO 16
+#define CRIS_MODF_JUMP_MASK (1 << CRIS_BZ_REGNO)
+/* Likewise for the WZ register, marking memory writes. */
+#define CRIS_WZ_REGNO 20
+#define CRIS_MODF_MEM_WRITE_MASK (1 << CRIS_WZ_REGNO)
+#define CRIS_MOF_REGNO (16 + 7)
+#define CRIS_ALWAYS_CONDITION 14
+
+/* This macro must only be used in context where there's only one
+ dynamic cause for a penalty, except in the u-exec unit. */
+
+#define PENALIZE1(CNT) \
+ do \
+ { \
+ CPU_CRIS_MISC_PROFILE (current_cpu)->CNT++; \
+ model_data->prev_prev_prev_modf_regs \
+ = model_data->prev_prev_modf_regs; \
+ model_data->prev_prev_modf_regs \
+ = model_data->prev_modf_regs; \
+ model_data->prev_modf_regs = 0; \
+ model_data->prev_prev_prev_movem_dest_regs \
+ = model_data->prev_prev_movem_dest_regs; \
+ model_data->prev_prev_movem_dest_regs \
+ = model_data->prev_movem_dest_regs; \
+ model_data->prev_movem_dest_regs = 0; \
+ } \
+ while (0)
+
+
+/* Model function for u-skip4 unit. */
+
+int
+MY (XCONCAT3 (f_model_crisv,BASENUM,
+ _u_skip4)) (SIM_CPU *current_cpu,
+ const IDESC *idesc ATTRIBUTE_UNUSED,
+ int unit_num ATTRIBUTE_UNUSED,
+ int referenced ATTRIBUTE_UNUSED)
+{
+ /* Handle PC not being updated with pbb. FIXME: What if not pbb? */
+ CPU (h_pc) += 4;
+ return 0;
+}
+
+/* Model function for u-exec unit. */
+
+int
+MY (XCONCAT3 (f_model_crisv,BASENUM,
+ _u_exec)) (SIM_CPU *current_cpu,
+ const IDESC *idesc ATTRIBUTE_UNUSED,
+ int unit_num ATTRIBUTE_UNUSED,
+ int referenced ATTRIBUTE_UNUSED,
+ INT destreg_in,
+ INT srcreg,
+ INT destreg_out)
+{
+ MODEL_CRISV32_DATA *model_data
+ = (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
+ UINT modf_regs
+ = ((destreg_out == -1 ? 0 : (1 << destreg_out))
+ | model_data->modf_regs);
+
+ if (srcreg != -1)
+ {
+ if (model_data->prev_movem_dest_regs & (1 << srcreg))
+ {
+ PENALIZE1 (movemdst_stall_count);
+ PENALIZE1 (movemdst_stall_count);
+ PENALIZE1 (movemdst_stall_count);
+ }
+ else if (model_data->prev_prev_movem_dest_regs & (1 << srcreg))
+ {
+ PENALIZE1 (movemdst_stall_count);
+ PENALIZE1 (movemdst_stall_count);
+ }
+ else if (model_data->prev_prev_prev_movem_dest_regs & (1 << srcreg))
+ PENALIZE1 (movemdst_stall_count);
+ }
+
+ if (destreg_in != -1)
+ {
+ if (model_data->prev_movem_dest_regs & (1 << destreg_in))
+ {
+ PENALIZE1 (movemdst_stall_count);
+ PENALIZE1 (movemdst_stall_count);
+ PENALIZE1 (movemdst_stall_count);
+ }
+ else if (model_data->prev_prev_movem_dest_regs & (1 << destreg_in))
+ {
+ PENALIZE1 (movemdst_stall_count);
+ PENALIZE1 (movemdst_stall_count);
+ }
+ else if (model_data->prev_prev_prev_movem_dest_regs & (1 << destreg_in))
+ PENALIZE1 (movemdst_stall_count);
+ }
+
+ model_data->prev_prev_prev_modf_regs
+ = model_data->prev_prev_modf_regs;
+ model_data->prev_prev_modf_regs = model_data->prev_modf_regs;
+ model_data->prev_modf_regs = modf_regs;
+ model_data->modf_regs = 0;
+
+ model_data->prev_prev_prev_movem_dest_regs
+ = model_data->prev_prev_movem_dest_regs;
+ model_data->prev_prev_movem_dest_regs = model_data->prev_movem_dest_regs;
+ model_data->prev_movem_dest_regs = model_data->movem_dest_regs;
+ model_data->movem_dest_regs = 0;
+
+ /* Handle PC not being updated with pbb. FIXME: What if not pbb? */
+ CPU (h_pc) += 2;
+ return 1;
+}
+
+/* Special case used when the destination is a special register. */
+
+int
+MY (XCONCAT3 (f_model_crisv,BASENUM,
+ _u_exec_to_sr)) (SIM_CPU *current_cpu,
+ const IDESC *idesc ATTRIBUTE_UNUSED,
+ int unit_num ATTRIBUTE_UNUSED,
+ int referenced ATTRIBUTE_UNUSED,
+ INT srcreg,
+ INT specreg)
+{
+ int specdest;
+
+ if (specreg != -1)
+ specdest = specreg + 16;
+ else
+ abort ();
+
+ return MY (XCONCAT3 (f_model_crisv,BASENUM,_u_exec))
+ (current_cpu, NULL, 0, 0, -1, srcreg,
+ /* The positions for constant-zero registers BZ and WZ are recycled
+ for jump and memory-write markers. We must take precautions
+ here not to add false markers for them. It might be that the
+ hardware inserts stall cycles for instructions that actually try
+ and write those registers, but we'll burn that bridge when we
+ get to it; we'd have to find other free bits or make new
+ model_data variables. However, it's doubtful that there will
+ ever be a need to be cycle-correct for useless code, at least in
+ this particular simulator, mainly used for GCC testing. */
+ specdest == CRIS_BZ_REGNO || specdest == CRIS_WZ_REGNO
+ ? -1 : specdest);
+}
+
+
+/* Special case for movem. */
+
+int
+MY (XCONCAT3 (f_model_crisv,BASENUM,
+ _u_exec_movem)) (SIM_CPU *current_cpu,
+ const IDESC *idesc ATTRIBUTE_UNUSED,
+ int unit_num ATTRIBUTE_UNUSED,
+ int referenced ATTRIBUTE_UNUSED,
+ INT srcreg,
+ INT destreg_out)
+{
+ return MY (XCONCAT3 (f_model_crisv,BASENUM,_u_exec))
+ (current_cpu, NULL, 0, 0, -1, srcreg, destreg_out);
+}
+
+/* Model function for u-const16 unit. */
+
+int
+MY (XCONCAT3 (f_model_crisv,BASENUM,
+ _u_const16)) (SIM_CPU *current_cpu,
+ const IDESC *idesc ATTRIBUTE_UNUSED,
+ int unit_num ATTRIBUTE_UNUSED,
+ int referenced ATTRIBUTE_UNUSED)
+{
+ MODEL_CRISV32_DATA *model_data
+ = (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
+
+ /* If the previous insn was a jump of some sort and this insn
+ straddles a cache-line, there's a one-cycle penalty.
+ FIXME: Test-cases for normal const16 and others, like branch. */
+ if ((model_data->prev_modf_regs & CRIS_MODF_JUMP_MASK)
+ && (CPU (h_pc) & 0x1e) == 0x1e)
+ PENALIZE1 (jumptarget_stall_count);
+
+ /* Handle PC not being updated with pbb. FIXME: What if not pbb? */
+ CPU (h_pc) += 2;
+
+ return 0;
+}
+
+/* Model function for u-const32 unit. */
+
+int
+MY (XCONCAT3 (f_model_crisv,BASENUM,
+ _u_const32)) (SIM_CPU *current_cpu,
+ const IDESC *idesc ATTRIBUTE_UNUSED,
+ int unit_num ATTRIBUTE_UNUSED,
+ int referenced ATTRIBUTE_UNUSED)
+{
+ MODEL_CRISV32_DATA *model_data
+ = (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
+
+ /* If the previous insn was a jump of some sort and this insn
+ straddles a cache-line, there's a one-cycle penalty. */
+ if ((model_data->prev_modf_regs & CRIS_MODF_JUMP_MASK)
+ && (CPU (h_pc) & 0x1e) == 0x1c)
+ PENALIZE1 (jumptarget_stall_count);
+
+ /* Handle PC not being updated with pbb. FIXME: What if not pbb? */
+ CPU (h_pc) += 4;
+
+ return 0;
+}
+
+/* Model function for u-mem unit. */
+
+int
+MY (XCONCAT3 (f_model_crisv,BASENUM,
+ _u_mem)) (SIM_CPU *current_cpu,
+ const IDESC *idesc ATTRIBUTE_UNUSED,
+ int unit_num ATTRIBUTE_UNUSED,
+ int referenced ATTRIBUTE_UNUSED,
+ INT srcreg)
+{
+ MODEL_CRISV32_DATA *model_data
+ = (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
+
+ if (srcreg == -1)
+ abort ();
+
+ /* If srcreg references a register modified in the previous cycle
+ through other than autoincrement, then there's a penalty: one
+ cycle. */
+ if (model_data->prev_modf_regs & (1 << srcreg))
+ PENALIZE1 (memsrc_stall_count);
+
+ return 0;
+}
+
+/* Model function for u-mem-r unit. */
+
+int
+MY (XCONCAT3 (f_model_crisv,BASENUM,
+ _u_mem_r)) (SIM_CPU *current_cpu,
+ const IDESC *idesc ATTRIBUTE_UNUSED,
+ int unit_num ATTRIBUTE_UNUSED,
+ int referenced ATTRIBUTE_UNUSED)
+{
+ MODEL_CRISV32_DATA *model_data
+ = (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
+
+ /* There's a two-cycle penalty for read after a memory write in any of
+ the two previous cycles, known as a cache read-after-write hazard.
+
+ This model function (the model_data member access) depends on being
+ executed before the u-exec unit. */
+ if ((model_data->prev_modf_regs & CRIS_MODF_MEM_WRITE_MASK)
+ || (model_data->prev_prev_modf_regs & CRIS_MODF_MEM_WRITE_MASK))
+ {
+ PENALIZE1 (memraw_stall_count);
+ PENALIZE1 (memraw_stall_count);
+ }
+
+ return 0;
+}
+
+/* Model function for u-mem-w unit. */
+
+int
+MY (XCONCAT3 (f_model_crisv,BASENUM,
+ _u_mem_w)) (SIM_CPU *current_cpu,
+ const IDESC *idesc ATTRIBUTE_UNUSED,
+ int unit_num ATTRIBUTE_UNUSED,
+ int referenced ATTRIBUTE_UNUSED)
+{
+ MODEL_CRISV32_DATA *model_data
+ = (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
+
+ /* Mark that memory has been written. This model function (the
+ model_data member access) depends on being executed after the
+ u-exec unit. */
+ model_data->prev_modf_regs |= CRIS_MODF_MEM_WRITE_MASK;
+
+ return 0;
+}
+
+/* Model function for u-movem-rtom unit. */
+
+int
+MY (XCONCAT3 (f_model_crisv,BASENUM,
+ _u_movem_rtom)) (SIM_CPU *current_cpu,
+ const IDESC *idesc ATTRIBUTE_UNUSED,
+ int unit_num ATTRIBUTE_UNUSED,
+ int referenced ATTRIBUTE_UNUSED,
+ /* Deliberate order. */
+ INT addrreg, INT limreg)
+{
+ USI addr;
+ MODEL_CRISV32_DATA *model_data
+ = (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
+
+ if (limreg == -1 || addrreg == -1)
+ abort ();
+
+ addr = GET_H_GR (addrreg);
+
+ /* The movem-to-memory instruction must not move a register modified
+ in one of the previous two cycles. Enforce by adding penalty
+ cycles. */
+ if (model_data->prev_modf_regs & ((1 << (limreg + 1)) - 1))
+ {
+ PENALIZE1 (movemsrc_stall_count);
+ PENALIZE1 (movemsrc_stall_count);
+ }
+ else if (model_data->prev_prev_modf_regs & ((1 << (limreg + 1)) - 1))
+ PENALIZE1 (movemsrc_stall_count);
+
+ /* One-cycle penalty for each cache-line straddled. Use the
+ documented expressions. Unfortunately no penalty cycles are
+ eliminated by any penalty cycles above. We file these numbers
+ separately, since they aren't schedulable for all cases. */
+ if ((addr >> 5) == (((addr + 4 * (limreg + 1)) - 1) >> 5))
+ ;
+ else if ((addr >> 5) == (((addr + 4 * (limreg + 1)) - 1) >> 5) - 1)
+ PENALIZE1 (movemaddr_stall_count);
+ else if ((addr >> 5) == (((addr + 4 * (limreg + 1)) - 1) >> 5) - 2)
+ {
+ PENALIZE1 (movemaddr_stall_count);
+ PENALIZE1 (movemaddr_stall_count);
+ }
+ else
+ abort ();
+
+ return 0;
+}
+
+/* Model function for u-movem-mtor unit. */
+
+int
+MY (XCONCAT3 (f_model_crisv,BASENUM,
+ _u_movem_mtor)) (SIM_CPU *current_cpu,
+ const IDESC *idesc ATTRIBUTE_UNUSED,
+ int unit_num ATTRIBUTE_UNUSED,
+ int referenced ATTRIBUTE_UNUSED,
+ /* Deliberate order. */
+ INT addrreg, INT limreg)
+{
+ USI addr;
+ int nregs = limreg + 1;
+ MODEL_CRISV32_DATA *model_data
+ = (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
+
+ if (limreg == -1 || addrreg == -1)
+ abort ();
+
+ addr = GET_H_GR (addrreg);
+
+ /* One-cycle penalty for each cache-line straddled. Use the
+ documented expressions. One cycle is the norm; more cycles are
+ counted as penalties. Unfortunately no penalty cycles here
+ eliminate penalty cycles indicated in ->movem_dest_regs. */
+ if ((addr >> 5) == (((addr + 4 * nregs) - 1) >> 5) - 1)
+ PENALIZE1 (movemaddr_stall_count);
+ else if ((addr >> 5) == (((addr + 4 * nregs) - 1) >> 5) - 2)
+ {
+ PENALIZE1 (movemaddr_stall_count);
+ PENALIZE1 (movemaddr_stall_count);
+ }
+
+ model_data->modf_regs |= ((1 << nregs) - 1);
+ model_data->movem_dest_regs |= ((1 << nregs) - 1);
+ return 0;
+}
+
+
+/* Model function for u-branch unit.
+ FIXME: newpc and cc are always wrong. */
+
+int
+MY (XCONCAT3 (f_model_crisv,BASENUM,_u_branch)) (SIM_CPU *current_cpu,
+ const IDESC *idesc,
+ int unit_num, int referenced)
+{
+ CRIS_MISC_PROFILE *profp = CPU_CRIS_MISC_PROFILE (current_cpu);
+ USI pc = profp->old_pc;
+ MODEL_CRISV32_DATA *model_data
+ = (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
+ int taken = profp->branch_taken;
+ int branch_index = (pc & (N_CRISV32_BRANCH_PREDICTORS - 1)) >> 1;
+ int pred_taken = (profp->branch_predictors[branch_index] & 2) != 0;
+
+ if (taken != pred_taken)
+ {
+ PENALIZE1 (branch_stall_count);
+ PENALIZE1 (branch_stall_count);
+ }
+
+ if (taken)
+ {
+ if (profp->branch_predictors[branch_index] < 3)
+ profp->branch_predictors[branch_index]++;
+
+ return MY (XCONCAT3 (f_model_crisv,BASENUM,_u_jump))
+ (current_cpu, idesc, unit_num, referenced, -1);
+ }
+
+ if (profp->branch_predictors[branch_index] != 0)
+ profp->branch_predictors[branch_index]--;
+
+ return 0;
+}
+
+/* Model function for u-jump-r unit. */
+
+int
+MY (XCONCAT3 (f_model_crisv,BASENUM,
+ _u_jump_r)) (SIM_CPU *current_cpu,
+ const IDESC *idesc ATTRIBUTE_UNUSED,
+ int unit_num ATTRIBUTE_UNUSED,
+ int referenced ATTRIBUTE_UNUSED,
+ int regno)
+{
+ MODEL_CRISV32_DATA *model_data
+ = (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
+
+ if (regno == -1)
+ abort ();
+
+ /* For jump-to-register, the register must not have been modified the
+ last two cycles. Penalty: two cycles from the modifying insn. */
+ if ((1 << regno) & model_data->prev_modf_regs)
+ {
+ PENALIZE1 (jumpsrc_stall_count);
+ PENALIZE1 (jumpsrc_stall_count);
+ }
+ else if ((1 << regno) & model_data->prev_prev_modf_regs)
+ PENALIZE1 (jumpsrc_stall_count);
+
+ return 0;
+}
+
+/* Model function for u-jump-sr unit. */
+
+int
+MY (XCONCAT3 (f_model_crisv,BASENUM,_u_jump_sr)) (SIM_CPU *current_cpu,
+ const IDESC *idesc,
+ int unit_num, int referenced,
+ int sr_regno)
+{
+ int regno;
+
+ MODEL_CRISV32_DATA *model_data
+ = (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
+
+ if (sr_regno == -1)
+ abort ();
+
+ regno = sr_regno + 16;
+
+ /* For jump-to-register, the register must not have been modified the
+ last two cycles. Penalty: two cycles from the modifying insn. */
+ if ((1 << regno) & model_data->prev_modf_regs)
+ {
+ PENALIZE1 (jumpsrc_stall_count);
+ PENALIZE1 (jumpsrc_stall_count);
+ }
+ else if ((1 << regno) & model_data->prev_prev_modf_regs)
+ PENALIZE1 (jumpsrc_stall_count);
+
+ return
+ MY (XCONCAT3 (f_model_crisv,BASENUM,_u_jump)) (current_cpu, idesc,
+ unit_num, referenced, -1);
+}
+
+/* Model function for u-jump unit. */
+
+int
+MY (XCONCAT3 (f_model_crisv,BASENUM,
+ _u_jump)) (SIM_CPU *current_cpu,
+ const IDESC *idesc ATTRIBUTE_UNUSED,
+ int unit_num ATTRIBUTE_UNUSED,
+ int referenced ATTRIBUTE_UNUSED,
+ int out_sr_regno)
+{
+ MODEL_CRISV32_DATA *model_data
+ = (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
+
+ /* Mark that we made a jump. */
+ model_data->modf_regs
+ |= (CRIS_MODF_JUMP_MASK
+ | (out_sr_regno == -1 || out_sr_regno == CRIS_BZ_REGNO
+ ? 0 : (1 << (out_sr_regno + 16))));
+ return 0;
+}
+
+/* Model function for u-multiply unit. */
+
+int
+MY (XCONCAT3 (f_model_crisv,BASENUM,
+ _u_multiply)) (SIM_CPU *current_cpu,
+ const IDESC *idesc ATTRIBUTE_UNUSED,
+ int unit_num ATTRIBUTE_UNUSED,
+ int referenced ATTRIBUTE_UNUSED,
+ int srcreg, int destreg)
+{
+ MODEL_CRISV32_DATA *model_data
+ = (MODEL_CRISV32_DATA *) CPU_MODEL_DATA (current_cpu);
+
+ /* Sanity-check for cases that should never happen. */
+ if (srcreg == -1 || destreg == -1)
+ abort ();
+
+ /* This takes extra cycles when one of the inputs has been modified
+ through other than autoincrement in the previous cycle. Penalty:
+ one cycle. */
+ if (((1 << srcreg) | (1 << destreg)) & model_data->prev_modf_regs)
+ PENALIZE1 (mulsrc_stall_count);
+
+ /* We modified the multiplication destination (marked in u-exec) and
+ the MOF register. */
+ model_data->modf_regs |= (1 << CRIS_MOF_REGNO);
+ return 0;
+}
+
+#endif /* WITH_PROFILE_MODEL_P */
--- /dev/null
+/* Simulator instruction decoder for crisv10f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2004 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU crisv10f
+#define WANT_CPU_CRISV10F
+
+#include "sim-main.h"
+#include "sim-assert.h"
+
+/* The instruction descriptor array.
+ This is computed at runtime. Space for it is not malloc'd to save a
+ teensy bit of cpu in the decoder. Moving it to malloc space is trivial
+ but won't be done until necessary (we don't currently support the runtime
+ addition of instructions nor an SMP machine with different cpus). */
+static IDESC crisv10f_insn_data[CRISV10F_INSN__MAX];
+
+/* Commas between elements are contained in the macros.
+ Some of these are conditionally compiled out. */
+
+static const struct insn_sem crisv10f_insn_sem[] =
+{
+ { VIRTUAL_INSN_X_INVALID, CRISV10F_INSN_X_INVALID, CRISV10F_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_AFTER, CRISV10F_INSN_X_AFTER, CRISV10F_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_BEFORE, CRISV10F_INSN_X_BEFORE, CRISV10F_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_CTI_CHAIN, CRISV10F_INSN_X_CTI_CHAIN, CRISV10F_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_CHAIN, CRISV10F_INSN_X_CHAIN, CRISV10F_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_BEGIN, CRISV10F_INSN_X_BEGIN, CRISV10F_SFMT_EMPTY },
+ { CRIS_INSN_NOP, CRISV10F_INSN_NOP, CRISV10F_SFMT_NOP },
+ { CRIS_INSN_MOVE_B_R, CRISV10F_INSN_MOVE_B_R, CRISV10F_SFMT_MOVE_B_R },
+ { CRIS_INSN_MOVE_W_R, CRISV10F_INSN_MOVE_W_R, CRISV10F_SFMT_MOVE_B_R },
+ { CRIS_INSN_MOVE_D_R, CRISV10F_INSN_MOVE_D_R, CRISV10F_SFMT_MOVE_D_R },
+ { CRIS_INSN_MOVEPCR, CRISV10F_INSN_MOVEPCR, CRISV10F_SFMT_MOVEPCR },
+ { CRIS_INSN_MOVEQ, CRISV10F_INSN_MOVEQ, CRISV10F_SFMT_MOVEQ },
+ { CRIS_INSN_MOVS_B_R, CRISV10F_INSN_MOVS_B_R, CRISV10F_SFMT_MOVS_B_R },
+ { CRIS_INSN_MOVS_W_R, CRISV10F_INSN_MOVS_W_R, CRISV10F_SFMT_MOVS_B_R },
+ { CRIS_INSN_MOVU_B_R, CRISV10F_INSN_MOVU_B_R, CRISV10F_SFMT_MOVS_B_R },
+ { CRIS_INSN_MOVU_W_R, CRISV10F_INSN_MOVU_W_R, CRISV10F_SFMT_MOVS_B_R },
+ { CRIS_INSN_MOVECBR, CRISV10F_INSN_MOVECBR, CRISV10F_SFMT_MOVECBR },
+ { CRIS_INSN_MOVECWR, CRISV10F_INSN_MOVECWR, CRISV10F_SFMT_MOVECWR },
+ { CRIS_INSN_MOVECDR, CRISV10F_INSN_MOVECDR, CRISV10F_SFMT_MOVECDR },
+ { CRIS_INSN_MOVSCBR, CRISV10F_INSN_MOVSCBR, CRISV10F_SFMT_MOVSCBR },
+ { CRIS_INSN_MOVSCWR, CRISV10F_INSN_MOVSCWR, CRISV10F_SFMT_MOVSCWR },
+ { CRIS_INSN_MOVUCBR, CRISV10F_INSN_MOVUCBR, CRISV10F_SFMT_MOVUCBR },
+ { CRIS_INSN_MOVUCWR, CRISV10F_INSN_MOVUCWR, CRISV10F_SFMT_MOVUCWR },
+ { CRIS_INSN_ADDQ, CRISV10F_INSN_ADDQ, CRISV10F_SFMT_ADDQ },
+ { CRIS_INSN_SUBQ, CRISV10F_INSN_SUBQ, CRISV10F_SFMT_ADDQ },
+ { CRIS_INSN_CMP_R_B_R, CRISV10F_INSN_CMP_R_B_R, CRISV10F_SFMT_CMP_R_B_R },
+ { CRIS_INSN_CMP_R_W_R, CRISV10F_INSN_CMP_R_W_R, CRISV10F_SFMT_CMP_R_B_R },
+ { CRIS_INSN_CMP_R_D_R, CRISV10F_INSN_CMP_R_D_R, CRISV10F_SFMT_CMP_R_B_R },
+ { CRIS_INSN_CMP_M_B_M, CRISV10F_INSN_CMP_M_B_M, CRISV10F_SFMT_CMP_M_B_M },
+ { CRIS_INSN_CMP_M_W_M, CRISV10F_INSN_CMP_M_W_M, CRISV10F_SFMT_CMP_M_W_M },
+ { CRIS_INSN_CMP_M_D_M, CRISV10F_INSN_CMP_M_D_M, CRISV10F_SFMT_CMP_M_D_M },
+ { CRIS_INSN_CMPCBR, CRISV10F_INSN_CMPCBR, CRISV10F_SFMT_CMPCBR },
+ { CRIS_INSN_CMPCWR, CRISV10F_INSN_CMPCWR, CRISV10F_SFMT_CMPCWR },
+ { CRIS_INSN_CMPCDR, CRISV10F_INSN_CMPCDR, CRISV10F_SFMT_CMPCDR },
+ { CRIS_INSN_CMPQ, CRISV10F_INSN_CMPQ, CRISV10F_SFMT_CMPQ },
+ { CRIS_INSN_CMPS_M_B_M, CRISV10F_INSN_CMPS_M_B_M, CRISV10F_SFMT_CMP_M_B_M },
+ { CRIS_INSN_CMPS_M_W_M, CRISV10F_INSN_CMPS_M_W_M, CRISV10F_SFMT_CMP_M_W_M },
+ { CRIS_INSN_CMPSCBR, CRISV10F_INSN_CMPSCBR, CRISV10F_SFMT_CMPCBR },
+ { CRIS_INSN_CMPSCWR, CRISV10F_INSN_CMPSCWR, CRISV10F_SFMT_CMPCWR },
+ { CRIS_INSN_CMPU_M_B_M, CRISV10F_INSN_CMPU_M_B_M, CRISV10F_SFMT_CMP_M_B_M },
+ { CRIS_INSN_CMPU_M_W_M, CRISV10F_INSN_CMPU_M_W_M, CRISV10F_SFMT_CMP_M_W_M },
+ { CRIS_INSN_CMPUCBR, CRISV10F_INSN_CMPUCBR, CRISV10F_SFMT_CMPUCBR },
+ { CRIS_INSN_CMPUCWR, CRISV10F_INSN_CMPUCWR, CRISV10F_SFMT_CMPUCWR },
+ { CRIS_INSN_MOVE_M_B_M, CRISV10F_INSN_MOVE_M_B_M, CRISV10F_SFMT_MOVE_M_B_M },
+ { CRIS_INSN_MOVE_M_W_M, CRISV10F_INSN_MOVE_M_W_M, CRISV10F_SFMT_MOVE_M_W_M },
+ { CRIS_INSN_MOVE_M_D_M, CRISV10F_INSN_MOVE_M_D_M, CRISV10F_SFMT_MOVE_M_D_M },
+ { CRIS_INSN_MOVS_M_B_M, CRISV10F_INSN_MOVS_M_B_M, CRISV10F_SFMT_MOVS_M_B_M },
+ { CRIS_INSN_MOVS_M_W_M, CRISV10F_INSN_MOVS_M_W_M, CRISV10F_SFMT_MOVS_M_W_M },
+ { CRIS_INSN_MOVU_M_B_M, CRISV10F_INSN_MOVU_M_B_M, CRISV10F_SFMT_MOVS_M_B_M },
+ { CRIS_INSN_MOVU_M_W_M, CRISV10F_INSN_MOVU_M_W_M, CRISV10F_SFMT_MOVS_M_W_M },
+ { CRIS_INSN_MOVE_R_SPRV10, CRISV10F_INSN_MOVE_R_SPRV10, CRISV10F_SFMT_MOVE_R_SPRV10 },
+ { CRIS_INSN_MOVE_SPR_RV10, CRISV10F_INSN_MOVE_SPR_RV10, CRISV10F_SFMT_MOVE_SPR_RV10 },
+ { CRIS_INSN_RET_TYPE, CRISV10F_INSN_RET_TYPE, CRISV10F_SFMT_RET_TYPE },
+ { CRIS_INSN_MOVE_M_SPRV10, CRISV10F_INSN_MOVE_M_SPRV10, CRISV10F_SFMT_MOVE_M_SPRV10 },
+ { CRIS_INSN_MOVE_C_SPRV10_P0, CRISV10F_INSN_MOVE_C_SPRV10_P0, CRISV10F_SFMT_MOVE_C_SPRV10_P0 },
+ { CRIS_INSN_MOVE_C_SPRV10_P1, CRISV10F_INSN_MOVE_C_SPRV10_P1, CRISV10F_SFMT_MOVE_C_SPRV10_P0 },
+ { CRIS_INSN_MOVE_C_SPRV10_P4, CRISV10F_INSN_MOVE_C_SPRV10_P4, CRISV10F_SFMT_MOVE_C_SPRV10_P4 },
+ { CRIS_INSN_MOVE_C_SPRV10_P5, CRISV10F_INSN_MOVE_C_SPRV10_P5, CRISV10F_SFMT_MOVE_C_SPRV10_P4 },
+ { CRIS_INSN_MOVE_C_SPRV10_P8, CRISV10F_INSN_MOVE_C_SPRV10_P8, CRISV10F_SFMT_MOVE_C_SPRV10_P8 },
+ { CRIS_INSN_MOVE_C_SPRV10_P9, CRISV10F_INSN_MOVE_C_SPRV10_P9, CRISV10F_SFMT_MOVE_C_SPRV10_P8 },
+ { CRIS_INSN_MOVE_C_SPRV10_P10, CRISV10F_INSN_MOVE_C_SPRV10_P10, CRISV10F_SFMT_MOVE_C_SPRV10_P8 },
+ { CRIS_INSN_MOVE_C_SPRV10_P11, CRISV10F_INSN_MOVE_C_SPRV10_P11, CRISV10F_SFMT_MOVE_C_SPRV10_P8 },
+ { CRIS_INSN_MOVE_C_SPRV10_P12, CRISV10F_INSN_MOVE_C_SPRV10_P12, CRISV10F_SFMT_MOVE_C_SPRV10_P8 },
+ { CRIS_INSN_MOVE_C_SPRV10_P13, CRISV10F_INSN_MOVE_C_SPRV10_P13, CRISV10F_SFMT_MOVE_C_SPRV10_P8 },
+ { CRIS_INSN_MOVE_C_SPRV10_P7, CRISV10F_INSN_MOVE_C_SPRV10_P7, CRISV10F_SFMT_MOVE_C_SPRV10_P8 },
+ { CRIS_INSN_MOVE_C_SPRV10_P14, CRISV10F_INSN_MOVE_C_SPRV10_P14, CRISV10F_SFMT_MOVE_C_SPRV10_P8 },
+ { CRIS_INSN_MOVE_C_SPRV10_P15, CRISV10F_INSN_MOVE_C_SPRV10_P15, CRISV10F_SFMT_MOVE_C_SPRV10_P8 },
+ { CRIS_INSN_MOVE_SPR_MV10, CRISV10F_INSN_MOVE_SPR_MV10, CRISV10F_SFMT_MOVE_SPR_MV10 },
+ { CRIS_INSN_SBFS, CRISV10F_INSN_SBFS, CRISV10F_SFMT_SBFS },
+ { CRIS_INSN_MOVEM_R_M, CRISV10F_INSN_MOVEM_R_M, CRISV10F_SFMT_MOVEM_R_M },
+ { CRIS_INSN_MOVEM_M_R, CRISV10F_INSN_MOVEM_M_R, CRISV10F_SFMT_MOVEM_M_R },
+ { CRIS_INSN_MOVEM_M_PC, CRISV10F_INSN_MOVEM_M_PC, CRISV10F_SFMT_MOVEM_M_PC },
+ { CRIS_INSN_ADD_B_R, CRISV10F_INSN_ADD_B_R, CRISV10F_SFMT_ADD_B_R },
+ { CRIS_INSN_ADD_W_R, CRISV10F_INSN_ADD_W_R, CRISV10F_SFMT_ADD_B_R },
+ { CRIS_INSN_ADD_D_R, CRISV10F_INSN_ADD_D_R, CRISV10F_SFMT_ADD_D_R },
+ { CRIS_INSN_ADD_M_B_M, CRISV10F_INSN_ADD_M_B_M, CRISV10F_SFMT_ADD_M_B_M },
+ { CRIS_INSN_ADD_M_W_M, CRISV10F_INSN_ADD_M_W_M, CRISV10F_SFMT_ADD_M_W_M },
+ { CRIS_INSN_ADD_M_D_M, CRISV10F_INSN_ADD_M_D_M, CRISV10F_SFMT_ADD_M_D_M },
+ { CRIS_INSN_ADDCBR, CRISV10F_INSN_ADDCBR, CRISV10F_SFMT_ADDCBR },
+ { CRIS_INSN_ADDCWR, CRISV10F_INSN_ADDCWR, CRISV10F_SFMT_ADDCWR },
+ { CRIS_INSN_ADDCDR, CRISV10F_INSN_ADDCDR, CRISV10F_SFMT_ADDCDR },
+ { CRIS_INSN_ADDCPC, CRISV10F_INSN_ADDCPC, CRISV10F_SFMT_ADDCPC },
+ { CRIS_INSN_ADDS_B_R, CRISV10F_INSN_ADDS_B_R, CRISV10F_SFMT_ADD_D_R },
+ { CRIS_INSN_ADDS_W_R, CRISV10F_INSN_ADDS_W_R, CRISV10F_SFMT_ADD_D_R },
+ { CRIS_INSN_ADDS_M_B_M, CRISV10F_INSN_ADDS_M_B_M, CRISV10F_SFMT_ADDS_M_B_M },
+ { CRIS_INSN_ADDS_M_W_M, CRISV10F_INSN_ADDS_M_W_M, CRISV10F_SFMT_ADDS_M_W_M },
+ { CRIS_INSN_ADDSCBR, CRISV10F_INSN_ADDSCBR, CRISV10F_SFMT_ADDSCBR },
+ { CRIS_INSN_ADDSCWR, CRISV10F_INSN_ADDSCWR, CRISV10F_SFMT_ADDSCWR },
+ { CRIS_INSN_ADDSPCPC, CRISV10F_INSN_ADDSPCPC, CRISV10F_SFMT_ADDSPCPC },
+ { CRIS_INSN_ADDU_B_R, CRISV10F_INSN_ADDU_B_R, CRISV10F_SFMT_ADD_D_R },
+ { CRIS_INSN_ADDU_W_R, CRISV10F_INSN_ADDU_W_R, CRISV10F_SFMT_ADD_D_R },
+ { CRIS_INSN_ADDU_M_B_M, CRISV10F_INSN_ADDU_M_B_M, CRISV10F_SFMT_ADDS_M_B_M },
+ { CRIS_INSN_ADDU_M_W_M, CRISV10F_INSN_ADDU_M_W_M, CRISV10F_SFMT_ADDS_M_W_M },
+ { CRIS_INSN_ADDUCBR, CRISV10F_INSN_ADDUCBR, CRISV10F_SFMT_ADDSCBR },
+ { CRIS_INSN_ADDUCWR, CRISV10F_INSN_ADDUCWR, CRISV10F_SFMT_ADDSCWR },
+ { CRIS_INSN_SUB_B_R, CRISV10F_INSN_SUB_B_R, CRISV10F_SFMT_ADD_B_R },
+ { CRIS_INSN_SUB_W_R, CRISV10F_INSN_SUB_W_R, CRISV10F_SFMT_ADD_B_R },
+ { CRIS_INSN_SUB_D_R, CRISV10F_INSN_SUB_D_R, CRISV10F_SFMT_ADD_D_R },
+ { CRIS_INSN_SUB_M_B_M, CRISV10F_INSN_SUB_M_B_M, CRISV10F_SFMT_ADD_M_B_M },
+ { CRIS_INSN_SUB_M_W_M, CRISV10F_INSN_SUB_M_W_M, CRISV10F_SFMT_ADD_M_W_M },
+ { CRIS_INSN_SUB_M_D_M, CRISV10F_INSN_SUB_M_D_M, CRISV10F_SFMT_ADD_M_D_M },
+ { CRIS_INSN_SUBCBR, CRISV10F_INSN_SUBCBR, CRISV10F_SFMT_ADDCBR },
+ { CRIS_INSN_SUBCWR, CRISV10F_INSN_SUBCWR, CRISV10F_SFMT_ADDCWR },
+ { CRIS_INSN_SUBCDR, CRISV10F_INSN_SUBCDR, CRISV10F_SFMT_ADDCDR },
+ { CRIS_INSN_SUBS_B_R, CRISV10F_INSN_SUBS_B_R, CRISV10F_SFMT_ADD_D_R },
+ { CRIS_INSN_SUBS_W_R, CRISV10F_INSN_SUBS_W_R, CRISV10F_SFMT_ADD_D_R },
+ { CRIS_INSN_SUBS_M_B_M, CRISV10F_INSN_SUBS_M_B_M, CRISV10F_SFMT_ADDS_M_B_M },
+ { CRIS_INSN_SUBS_M_W_M, CRISV10F_INSN_SUBS_M_W_M, CRISV10F_SFMT_ADDS_M_W_M },
+ { CRIS_INSN_SUBSCBR, CRISV10F_INSN_SUBSCBR, CRISV10F_SFMT_ADDSCBR },
+ { CRIS_INSN_SUBSCWR, CRISV10F_INSN_SUBSCWR, CRISV10F_SFMT_ADDSCWR },
+ { CRIS_INSN_SUBU_B_R, CRISV10F_INSN_SUBU_B_R, CRISV10F_SFMT_ADD_D_R },
+ { CRIS_INSN_SUBU_W_R, CRISV10F_INSN_SUBU_W_R, CRISV10F_SFMT_ADD_D_R },
+ { CRIS_INSN_SUBU_M_B_M, CRISV10F_INSN_SUBU_M_B_M, CRISV10F_SFMT_ADDS_M_B_M },
+ { CRIS_INSN_SUBU_M_W_M, CRISV10F_INSN_SUBU_M_W_M, CRISV10F_SFMT_ADDS_M_W_M },
+ { CRIS_INSN_SUBUCBR, CRISV10F_INSN_SUBUCBR, CRISV10F_SFMT_ADDSCBR },
+ { CRIS_INSN_SUBUCWR, CRISV10F_INSN_SUBUCWR, CRISV10F_SFMT_ADDSCWR },
+ { CRIS_INSN_ADDI_B_R, CRISV10F_INSN_ADDI_B_R, CRISV10F_SFMT_ADDI_B_R },
+ { CRIS_INSN_ADDI_W_R, CRISV10F_INSN_ADDI_W_R, CRISV10F_SFMT_ADDI_B_R },
+ { CRIS_INSN_ADDI_D_R, CRISV10F_INSN_ADDI_D_R, CRISV10F_SFMT_ADDI_B_R },
+ { CRIS_INSN_NEG_B_R, CRISV10F_INSN_NEG_B_R, CRISV10F_SFMT_NEG_B_R },
+ { CRIS_INSN_NEG_W_R, CRISV10F_INSN_NEG_W_R, CRISV10F_SFMT_NEG_B_R },
+ { CRIS_INSN_NEG_D_R, CRISV10F_INSN_NEG_D_R, CRISV10F_SFMT_NEG_D_R },
+ { CRIS_INSN_TEST_M_B_M, CRISV10F_INSN_TEST_M_B_M, CRISV10F_SFMT_TEST_M_B_M },
+ { CRIS_INSN_TEST_M_W_M, CRISV10F_INSN_TEST_M_W_M, CRISV10F_SFMT_TEST_M_W_M },
+ { CRIS_INSN_TEST_M_D_M, CRISV10F_INSN_TEST_M_D_M, CRISV10F_SFMT_TEST_M_D_M },
+ { CRIS_INSN_MOVE_R_M_B_M, CRISV10F_INSN_MOVE_R_M_B_M, CRISV10F_SFMT_MOVE_R_M_B_M },
+ { CRIS_INSN_MOVE_R_M_W_M, CRISV10F_INSN_MOVE_R_M_W_M, CRISV10F_SFMT_MOVE_R_M_W_M },
+ { CRIS_INSN_MOVE_R_M_D_M, CRISV10F_INSN_MOVE_R_M_D_M, CRISV10F_SFMT_MOVE_R_M_D_M },
+ { CRIS_INSN_MULS_B, CRISV10F_INSN_MULS_B, CRISV10F_SFMT_MULS_B },
+ { CRIS_INSN_MULS_W, CRISV10F_INSN_MULS_W, CRISV10F_SFMT_MULS_B },
+ { CRIS_INSN_MULS_D, CRISV10F_INSN_MULS_D, CRISV10F_SFMT_MULS_B },
+ { CRIS_INSN_MULU_B, CRISV10F_INSN_MULU_B, CRISV10F_SFMT_MULS_B },
+ { CRIS_INSN_MULU_W, CRISV10F_INSN_MULU_W, CRISV10F_SFMT_MULS_B },
+ { CRIS_INSN_MULU_D, CRISV10F_INSN_MULU_D, CRISV10F_SFMT_MULS_B },
+ { CRIS_INSN_MSTEP, CRISV10F_INSN_MSTEP, CRISV10F_SFMT_MSTEP },
+ { CRIS_INSN_DSTEP, CRISV10F_INSN_DSTEP, CRISV10F_SFMT_DSTEP },
+ { CRIS_INSN_ABS, CRISV10F_INSN_ABS, CRISV10F_SFMT_MOVS_B_R },
+ { CRIS_INSN_AND_B_R, CRISV10F_INSN_AND_B_R, CRISV10F_SFMT_AND_B_R },
+ { CRIS_INSN_AND_W_R, CRISV10F_INSN_AND_W_R, CRISV10F_SFMT_AND_W_R },
+ { CRIS_INSN_AND_D_R, CRISV10F_INSN_AND_D_R, CRISV10F_SFMT_AND_D_R },
+ { CRIS_INSN_AND_M_B_M, CRISV10F_INSN_AND_M_B_M, CRISV10F_SFMT_AND_M_B_M },
+ { CRIS_INSN_AND_M_W_M, CRISV10F_INSN_AND_M_W_M, CRISV10F_SFMT_AND_M_W_M },
+ { CRIS_INSN_AND_M_D_M, CRISV10F_INSN_AND_M_D_M, CRISV10F_SFMT_AND_M_D_M },
+ { CRIS_INSN_ANDCBR, CRISV10F_INSN_ANDCBR, CRISV10F_SFMT_ANDCBR },
+ { CRIS_INSN_ANDCWR, CRISV10F_INSN_ANDCWR, CRISV10F_SFMT_ANDCWR },
+ { CRIS_INSN_ANDCDR, CRISV10F_INSN_ANDCDR, CRISV10F_SFMT_ANDCDR },
+ { CRIS_INSN_ANDQ, CRISV10F_INSN_ANDQ, CRISV10F_SFMT_ANDQ },
+ { CRIS_INSN_ORR_B_R, CRISV10F_INSN_ORR_B_R, CRISV10F_SFMT_AND_B_R },
+ { CRIS_INSN_ORR_W_R, CRISV10F_INSN_ORR_W_R, CRISV10F_SFMT_AND_W_R },
+ { CRIS_INSN_ORR_D_R, CRISV10F_INSN_ORR_D_R, CRISV10F_SFMT_AND_D_R },
+ { CRIS_INSN_OR_M_B_M, CRISV10F_INSN_OR_M_B_M, CRISV10F_SFMT_AND_M_B_M },
+ { CRIS_INSN_OR_M_W_M, CRISV10F_INSN_OR_M_W_M, CRISV10F_SFMT_AND_M_W_M },
+ { CRIS_INSN_OR_M_D_M, CRISV10F_INSN_OR_M_D_M, CRISV10F_SFMT_AND_M_D_M },
+ { CRIS_INSN_ORCBR, CRISV10F_INSN_ORCBR, CRISV10F_SFMT_ANDCBR },
+ { CRIS_INSN_ORCWR, CRISV10F_INSN_ORCWR, CRISV10F_SFMT_ANDCWR },
+ { CRIS_INSN_ORCDR, CRISV10F_INSN_ORCDR, CRISV10F_SFMT_ANDCDR },
+ { CRIS_INSN_ORQ, CRISV10F_INSN_ORQ, CRISV10F_SFMT_ANDQ },
+ { CRIS_INSN_XOR, CRISV10F_INSN_XOR, CRISV10F_SFMT_DSTEP },
+ { CRIS_INSN_SWAP, CRISV10F_INSN_SWAP, CRISV10F_SFMT_SWAP },
+ { CRIS_INSN_ASRR_B_R, CRISV10F_INSN_ASRR_B_R, CRISV10F_SFMT_ASRR_B_R },
+ { CRIS_INSN_ASRR_W_R, CRISV10F_INSN_ASRR_W_R, CRISV10F_SFMT_ASRR_B_R },
+ { CRIS_INSN_ASRR_D_R, CRISV10F_INSN_ASRR_D_R, CRISV10F_SFMT_AND_D_R },
+ { CRIS_INSN_ASRQ, CRISV10F_INSN_ASRQ, CRISV10F_SFMT_ASRQ },
+ { CRIS_INSN_LSRR_B_R, CRISV10F_INSN_LSRR_B_R, CRISV10F_SFMT_LSRR_B_R },
+ { CRIS_INSN_LSRR_W_R, CRISV10F_INSN_LSRR_W_R, CRISV10F_SFMT_LSRR_B_R },
+ { CRIS_INSN_LSRR_D_R, CRISV10F_INSN_LSRR_D_R, CRISV10F_SFMT_LSRR_D_R },
+ { CRIS_INSN_LSRQ, CRISV10F_INSN_LSRQ, CRISV10F_SFMT_ASRQ },
+ { CRIS_INSN_LSLR_B_R, CRISV10F_INSN_LSLR_B_R, CRISV10F_SFMT_LSRR_B_R },
+ { CRIS_INSN_LSLR_W_R, CRISV10F_INSN_LSLR_W_R, CRISV10F_SFMT_LSRR_B_R },
+ { CRIS_INSN_LSLR_D_R, CRISV10F_INSN_LSLR_D_R, CRISV10F_SFMT_LSRR_D_R },
+ { CRIS_INSN_LSLQ, CRISV10F_INSN_LSLQ, CRISV10F_SFMT_ASRQ },
+ { CRIS_INSN_BTST, CRISV10F_INSN_BTST, CRISV10F_SFMT_BTST },
+ { CRIS_INSN_BTSTQ, CRISV10F_INSN_BTSTQ, CRISV10F_SFMT_BTSTQ },
+ { CRIS_INSN_SETF, CRISV10F_INSN_SETF, CRISV10F_SFMT_SETF },
+ { CRIS_INSN_CLEARF, CRISV10F_INSN_CLEARF, CRISV10F_SFMT_SETF },
+ { CRIS_INSN_BCC_B, CRISV10F_INSN_BCC_B, CRISV10F_SFMT_BCC_B },
+ { CRIS_INSN_BA_B, CRISV10F_INSN_BA_B, CRISV10F_SFMT_BA_B },
+ { CRIS_INSN_BCC_W, CRISV10F_INSN_BCC_W, CRISV10F_SFMT_BCC_W },
+ { CRIS_INSN_BA_W, CRISV10F_INSN_BA_W, CRISV10F_SFMT_BA_W },
+ { CRIS_INSN_JUMP_R, CRISV10F_INSN_JUMP_R, CRISV10F_SFMT_JUMP_R },
+ { CRIS_INSN_JUMP_M, CRISV10F_INSN_JUMP_M, CRISV10F_SFMT_JUMP_M },
+ { CRIS_INSN_JUMP_C, CRISV10F_INSN_JUMP_C, CRISV10F_SFMT_JUMP_C },
+ { CRIS_INSN_BREAK, CRISV10F_INSN_BREAK, CRISV10F_SFMT_BREAK },
+ { CRIS_INSN_BOUND_R_B_R, CRISV10F_INSN_BOUND_R_B_R, CRISV10F_SFMT_DSTEP },
+ { CRIS_INSN_BOUND_R_W_R, CRISV10F_INSN_BOUND_R_W_R, CRISV10F_SFMT_DSTEP },
+ { CRIS_INSN_BOUND_R_D_R, CRISV10F_INSN_BOUND_R_D_R, CRISV10F_SFMT_DSTEP },
+ { CRIS_INSN_BOUND_M_B_M, CRISV10F_INSN_BOUND_M_B_M, CRISV10F_SFMT_BOUND_M_B_M },
+ { CRIS_INSN_BOUND_M_W_M, CRISV10F_INSN_BOUND_M_W_M, CRISV10F_SFMT_BOUND_M_W_M },
+ { CRIS_INSN_BOUND_M_D_M, CRISV10F_INSN_BOUND_M_D_M, CRISV10F_SFMT_BOUND_M_D_M },
+ { CRIS_INSN_BOUND_CB, CRISV10F_INSN_BOUND_CB, CRISV10F_SFMT_BOUND_CB },
+ { CRIS_INSN_BOUND_CW, CRISV10F_INSN_BOUND_CW, CRISV10F_SFMT_BOUND_CW },
+ { CRIS_INSN_BOUND_CD, CRISV10F_INSN_BOUND_CD, CRISV10F_SFMT_BOUND_CD },
+ { CRIS_INSN_SCC, CRISV10F_INSN_SCC, CRISV10F_SFMT_SCC },
+ { CRIS_INSN_LZ, CRISV10F_INSN_LZ, CRISV10F_SFMT_MOVS_B_R },
+ { CRIS_INSN_ADDOQ, CRISV10F_INSN_ADDOQ, CRISV10F_SFMT_ADDOQ },
+ { CRIS_INSN_BDAPQPC, CRISV10F_INSN_BDAPQPC, CRISV10F_SFMT_BDAPQPC },
+ { CRIS_INSN_ADDO_M_B_M, CRISV10F_INSN_ADDO_M_B_M, CRISV10F_SFMT_ADDO_M_B_M },
+ { CRIS_INSN_ADDO_M_W_M, CRISV10F_INSN_ADDO_M_W_M, CRISV10F_SFMT_ADDO_M_W_M },
+ { CRIS_INSN_ADDO_M_D_M, CRISV10F_INSN_ADDO_M_D_M, CRISV10F_SFMT_ADDO_M_D_M },
+ { CRIS_INSN_ADDO_CB, CRISV10F_INSN_ADDO_CB, CRISV10F_SFMT_ADDO_CB },
+ { CRIS_INSN_ADDO_CW, CRISV10F_INSN_ADDO_CW, CRISV10F_SFMT_ADDO_CW },
+ { CRIS_INSN_ADDO_CD, CRISV10F_INSN_ADDO_CD, CRISV10F_SFMT_ADDO_CD },
+ { CRIS_INSN_DIP_M, CRISV10F_INSN_DIP_M, CRISV10F_SFMT_DIP_M },
+ { CRIS_INSN_DIP_C, CRISV10F_INSN_DIP_C, CRISV10F_SFMT_DIP_C },
+ { CRIS_INSN_ADDI_ACR_B_R, CRISV10F_INSN_ADDI_ACR_B_R, CRISV10F_SFMT_ADDI_ACR_B_R },
+ { CRIS_INSN_ADDI_ACR_W_R, CRISV10F_INSN_ADDI_ACR_W_R, CRISV10F_SFMT_ADDI_ACR_B_R },
+ { CRIS_INSN_ADDI_ACR_D_R, CRISV10F_INSN_ADDI_ACR_D_R, CRISV10F_SFMT_ADDI_ACR_B_R },
+ { CRIS_INSN_BIAP_PC_B_R, CRISV10F_INSN_BIAP_PC_B_R, CRISV10F_SFMT_BIAP_PC_B_R },
+ { CRIS_INSN_BIAP_PC_W_R, CRISV10F_INSN_BIAP_PC_W_R, CRISV10F_SFMT_BIAP_PC_B_R },
+ { CRIS_INSN_BIAP_PC_D_R, CRISV10F_INSN_BIAP_PC_D_R, CRISV10F_SFMT_BIAP_PC_B_R },
+};
+
+static const struct insn_sem crisv10f_insn_sem_invalid = {
+ VIRTUAL_INSN_X_INVALID, CRISV10F_INSN_X_INVALID, CRISV10F_SFMT_EMPTY
+};
+
+/* Initialize an IDESC from the compile-time computable parts. */
+
+static INLINE void
+init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
+{
+ const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
+
+ id->num = t->index;
+ id->sfmt = t->sfmt;
+ if ((int) t->type <= 0)
+ id->idata = & cgen_virtual_insn_table[- (int) t->type];
+ else
+ id->idata = & insn_table[t->type];
+ id->attrs = CGEN_INSN_ATTRS (id->idata);
+ /* Oh my god, a magic number. */
+ id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
+
+#if WITH_PROFILE_MODEL_P
+ id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
+ {
+ SIM_DESC sd = CPU_STATE (cpu);
+ SIM_ASSERT (t->index == id->timing->num);
+ }
+#endif
+
+ /* Semantic pointers are initialized elsewhere. */
+}
+
+/* Initialize the instruction descriptor table. */
+
+void
+crisv10f_init_idesc_table (SIM_CPU *cpu)
+{
+ IDESC *id,*tabend;
+ const struct insn_sem *t,*tend;
+ int tabsize = CRISV10F_INSN__MAX;
+ IDESC *table = crisv10f_insn_data;
+
+ memset (table, 0, tabsize * sizeof (IDESC));
+
+ /* First set all entries to the `invalid insn'. */
+ t = & crisv10f_insn_sem_invalid;
+ for (id = table, tabend = table + tabsize; id < tabend; ++id)
+ init_idesc (cpu, id, t);
+
+ /* Now fill in the values for the chosen cpu. */
+ for (t = crisv10f_insn_sem, tend = t + sizeof (crisv10f_insn_sem) / sizeof (*t);
+ t != tend; ++t)
+ {
+ init_idesc (cpu, & table[t->index], t);
+ }
+
+ /* Link the IDESC table into the cpu. */
+ CPU_IDESC (cpu) = table;
+}
+
+/* Given an instruction, return a pointer to its IDESC entry. */
+
+const IDESC *
+crisv10f_decode (SIM_CPU *current_cpu, IADDR pc,
+ CGEN_INSN_INT base_insn,
+ ARGBUF *abuf)
+{
+ /* Result of decoder. */
+ CRISV10F_INSN_TYPE itype;
+
+ {
+ CGEN_INSN_INT insn = base_insn;
+
+ {
+ unsigned int val = (((insn >> 4) & (255 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ {
+ unsigned int val = (((insn >> 12) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 15 : itype = CRISV10F_INSN_BCC_B; goto extract_sfmt_bcc_b;
+ case 14 : itype = CRISV10F_INSN_BA_B; goto extract_sfmt_ba_b;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 16 : /* fall through */
+ case 17 : /* fall through */
+ case 18 : /* fall through */
+ case 19 : /* fall through */
+ case 20 : /* fall through */
+ case 21 : /* fall through */
+ case 22 : /* fall through */
+ case 23 : /* fall through */
+ case 24 : /* fall through */
+ case 25 : /* fall through */
+ case 26 : /* fall through */
+ case 27 : /* fall through */
+ case 28 : /* fall through */
+ case 29 : /* fall through */
+ case 30 : /* fall through */
+ case 31 :
+ {
+ unsigned int val = (((insn >> 12) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_ADDOQ; goto extract_sfmt_addoq;
+ case 15 : itype = CRISV10F_INSN_BDAPQPC; goto extract_sfmt_bdapqpc;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : itype = CRISV10F_INSN_ADDQ; goto extract_sfmt_addq;
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : itype = CRISV10F_INSN_MOVEQ; goto extract_sfmt_moveq;
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : itype = CRISV10F_INSN_SUBQ; goto extract_sfmt_addq;
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 : itype = CRISV10F_INSN_CMPQ; goto extract_sfmt_cmpq;
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : itype = CRISV10F_INSN_ANDQ; goto extract_sfmt_andq;
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : itype = CRISV10F_INSN_ORQ; goto extract_sfmt_andq;
+ case 56 : /* fall through */
+ case 57 : itype = CRISV10F_INSN_BTSTQ; goto extract_sfmt_btstq;
+ case 58 : /* fall through */
+ case 59 : itype = CRISV10F_INSN_ASRQ; goto extract_sfmt_asrq;
+ case 60 : /* fall through */
+ case 61 : itype = CRISV10F_INSN_LSLQ; goto extract_sfmt_asrq;
+ case 62 : /* fall through */
+ case 63 : itype = CRISV10F_INSN_LSRQ; goto extract_sfmt_asrq;
+ case 64 : itype = CRISV10F_INSN_ADDU_B_R; goto extract_sfmt_add_d_r;
+ case 65 : itype = CRISV10F_INSN_ADDU_W_R; goto extract_sfmt_add_d_r;
+ case 66 : itype = CRISV10F_INSN_ADDS_B_R; goto extract_sfmt_add_d_r;
+ case 67 : itype = CRISV10F_INSN_ADDS_W_R; goto extract_sfmt_add_d_r;
+ case 68 : itype = CRISV10F_INSN_MOVU_B_R; goto extract_sfmt_movs_b_r;
+ case 69 : itype = CRISV10F_INSN_MOVU_W_R; goto extract_sfmt_movs_b_r;
+ case 70 : itype = CRISV10F_INSN_MOVS_B_R; goto extract_sfmt_movs_b_r;
+ case 71 : itype = CRISV10F_INSN_MOVS_W_R; goto extract_sfmt_movs_b_r;
+ case 72 : itype = CRISV10F_INSN_SUBU_B_R; goto extract_sfmt_add_d_r;
+ case 73 : itype = CRISV10F_INSN_SUBU_W_R; goto extract_sfmt_add_d_r;
+ case 74 : itype = CRISV10F_INSN_SUBS_B_R; goto extract_sfmt_add_d_r;
+ case 75 : itype = CRISV10F_INSN_SUBS_W_R; goto extract_sfmt_add_d_r;
+ case 76 : itype = CRISV10F_INSN_LSLR_B_R; goto extract_sfmt_lsrr_b_r;
+ case 77 : itype = CRISV10F_INSN_LSLR_W_R; goto extract_sfmt_lsrr_b_r;
+ case 78 : itype = CRISV10F_INSN_LSLR_D_R; goto extract_sfmt_lsrr_d_r;
+ case 79 : itype = CRISV10F_INSN_BTST; goto extract_sfmt_btst;
+ case 80 :
+ {
+ unsigned int val = (((insn >> 8) & (7 << 4)) | ((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 16 : /* fall through */
+ case 17 : /* fall through */
+ case 18 : /* fall through */
+ case 19 : /* fall through */
+ case 20 : /* fall through */
+ case 21 : /* fall through */
+ case 22 : /* fall through */
+ case 23 : /* fall through */
+ case 24 : /* fall through */
+ case 25 : /* fall through */
+ case 26 : /* fall through */
+ case 27 : /* fall through */
+ case 28 : /* fall through */
+ case 29 : /* fall through */
+ case 30 : /* fall through */
+ case 31 : /* fall through */
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 : /* fall through */
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 : /* fall through */
+ case 64 : /* fall through */
+ case 65 : /* fall through */
+ case 66 : /* fall through */
+ case 67 : /* fall through */
+ case 68 : /* fall through */
+ case 69 : /* fall through */
+ case 70 : /* fall through */
+ case 71 : /* fall through */
+ case 72 : /* fall through */
+ case 73 : /* fall through */
+ case 74 : /* fall through */
+ case 75 : /* fall through */
+ case 76 : /* fall through */
+ case 77 : /* fall through */
+ case 78 : /* fall through */
+ case 79 : /* fall through */
+ case 80 : /* fall through */
+ case 81 : /* fall through */
+ case 82 : /* fall through */
+ case 83 : /* fall through */
+ case 84 : /* fall through */
+ case 85 : /* fall through */
+ case 86 : /* fall through */
+ case 87 : /* fall through */
+ case 88 : /* fall through */
+ case 89 : /* fall through */
+ case 90 : /* fall through */
+ case 91 : /* fall through */
+ case 92 : /* fall through */
+ case 93 : /* fall through */
+ case 94 : /* fall through */
+ case 95 : /* fall through */
+ case 96 : /* fall through */
+ case 97 : /* fall through */
+ case 98 : /* fall through */
+ case 99 : /* fall through */
+ case 100 : /* fall through */
+ case 101 : /* fall through */
+ case 102 : /* fall through */
+ case 103 : /* fall through */
+ case 104 : /* fall through */
+ case 105 : /* fall through */
+ case 106 : /* fall through */
+ case 107 : /* fall through */
+ case 108 : /* fall through */
+ case 109 : /* fall through */
+ case 110 : /* fall through */
+ case 111 : /* fall through */
+ case 112 : /* fall through */
+ case 113 : /* fall through */
+ case 114 : /* fall through */
+ case 115 : /* fall through */
+ case 116 : /* fall through */
+ case 117 : /* fall through */
+ case 118 : /* fall through */
+ case 119 : /* fall through */
+ case 120 : /* fall through */
+ case 121 : /* fall through */
+ case 122 : /* fall through */
+ case 123 : /* fall through */
+ case 124 : /* fall through */
+ case 125 : /* fall through */
+ case 126 : /* fall through */
+ case 127 : itype = CRISV10F_INSN_ADDI_B_R; goto extract_sfmt_addi_b_r;
+ case 15 :
+ {
+ unsigned int val = (((insn >> 15) & (1 << 0)));
+ switch (val)
+ {
+ case 0 : itype = CRISV10F_INSN_NOP; goto extract_sfmt_nop;
+ case 1 : itype = CRISV10F_INSN_ADDI_B_R; goto extract_sfmt_addi_b_r;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 81 : itype = CRISV10F_INSN_ADDI_W_R; goto extract_sfmt_addi_b_r;
+ case 82 : itype = CRISV10F_INSN_ADDI_D_R; goto extract_sfmt_addi_b_r;
+ case 83 : itype = CRISV10F_INSN_SCC; goto extract_sfmt_scc;
+ case 84 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_ADDI_ACR_B_R; goto extract_sfmt_addi_acr_b_r;
+ case 15 : itype = CRISV10F_INSN_BIAP_PC_B_R; goto extract_sfmt_biap_pc_b_r;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 85 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_ADDI_ACR_W_R; goto extract_sfmt_addi_acr_b_r;
+ case 15 : itype = CRISV10F_INSN_BIAP_PC_W_R; goto extract_sfmt_biap_pc_b_r;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 86 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_ADDI_ACR_D_R; goto extract_sfmt_addi_acr_b_r;
+ case 15 : itype = CRISV10F_INSN_BIAP_PC_D_R; goto extract_sfmt_biap_pc_b_r;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 88 : itype = CRISV10F_INSN_NEG_B_R; goto extract_sfmt_neg_b_r;
+ case 89 : itype = CRISV10F_INSN_NEG_W_R; goto extract_sfmt_neg_b_r;
+ case 90 : itype = CRISV10F_INSN_NEG_D_R; goto extract_sfmt_neg_d_r;
+ case 91 : itype = CRISV10F_INSN_SETF; goto extract_sfmt_setf;
+ case 92 : itype = CRISV10F_INSN_BOUND_R_B_R; goto extract_sfmt_dstep;
+ case 93 : itype = CRISV10F_INSN_BOUND_R_W_R; goto extract_sfmt_dstep;
+ case 94 : itype = CRISV10F_INSN_BOUND_R_D_R; goto extract_sfmt_dstep;
+ case 95 : itype = CRISV10F_INSN_CLEARF; goto extract_sfmt_setf;
+ case 96 : itype = CRISV10F_INSN_ADD_B_R; goto extract_sfmt_add_b_r;
+ case 97 : itype = CRISV10F_INSN_ADD_W_R; goto extract_sfmt_add_b_r;
+ case 98 : itype = CRISV10F_INSN_ADD_D_R; goto extract_sfmt_add_d_r;
+ case 99 : itype = CRISV10F_INSN_MOVE_R_SPRV10; goto extract_sfmt_move_r_sprv10;
+ case 100 : itype = CRISV10F_INSN_MOVE_B_R; goto extract_sfmt_move_b_r;
+ case 101 : itype = CRISV10F_INSN_MOVE_W_R; goto extract_sfmt_move_b_r;
+ case 102 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_MOVE_D_R; goto extract_sfmt_move_d_r;
+ case 15 : itype = CRISV10F_INSN_MOVEPCR; goto extract_sfmt_movepcr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 103 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_MOVE_SPR_RV10; goto extract_sfmt_move_spr_rv10;
+ case 15 : itype = CRISV10F_INSN_RET_TYPE; goto extract_sfmt_ret_type;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 104 : itype = CRISV10F_INSN_SUB_B_R; goto extract_sfmt_add_b_r;
+ case 105 : itype = CRISV10F_INSN_SUB_W_R; goto extract_sfmt_add_b_r;
+ case 106 : itype = CRISV10F_INSN_SUB_D_R; goto extract_sfmt_add_d_r;
+ case 107 : itype = CRISV10F_INSN_ABS; goto extract_sfmt_movs_b_r;
+ case 108 : itype = CRISV10F_INSN_CMP_R_B_R; goto extract_sfmt_cmp_r_b_r;
+ case 109 : itype = CRISV10F_INSN_CMP_R_W_R; goto extract_sfmt_cmp_r_b_r;
+ case 110 : itype = CRISV10F_INSN_CMP_R_D_R; goto extract_sfmt_cmp_r_b_r;
+ case 111 : itype = CRISV10F_INSN_DSTEP; goto extract_sfmt_dstep;
+ case 112 : itype = CRISV10F_INSN_AND_B_R; goto extract_sfmt_and_b_r;
+ case 113 : itype = CRISV10F_INSN_AND_W_R; goto extract_sfmt_and_w_r;
+ case 114 : itype = CRISV10F_INSN_AND_D_R; goto extract_sfmt_and_d_r;
+ case 115 : itype = CRISV10F_INSN_LZ; goto extract_sfmt_movs_b_r;
+ case 116 : itype = CRISV10F_INSN_ORR_B_R; goto extract_sfmt_and_b_r;
+ case 117 : itype = CRISV10F_INSN_ORR_W_R; goto extract_sfmt_and_w_r;
+ case 118 : itype = CRISV10F_INSN_ORR_D_R; goto extract_sfmt_and_d_r;
+ case 119 : itype = CRISV10F_INSN_SWAP; goto extract_sfmt_swap;
+ case 120 : itype = CRISV10F_INSN_ASRR_B_R; goto extract_sfmt_asrr_b_r;
+ case 121 : itype = CRISV10F_INSN_ASRR_W_R; goto extract_sfmt_asrr_b_r;
+ case 122 : itype = CRISV10F_INSN_ASRR_D_R; goto extract_sfmt_and_d_r;
+ case 123 : itype = CRISV10F_INSN_XOR; goto extract_sfmt_dstep;
+ case 124 : itype = CRISV10F_INSN_LSRR_B_R; goto extract_sfmt_lsrr_b_r;
+ case 125 : itype = CRISV10F_INSN_LSRR_W_R; goto extract_sfmt_lsrr_b_r;
+ case 126 : itype = CRISV10F_INSN_LSRR_D_R; goto extract_sfmt_lsrr_d_r;
+ case 127 : itype = CRISV10F_INSN_MSTEP; goto extract_sfmt_mstep;
+ case 128 : itype = CRISV10F_INSN_ADDU_M_B_M; goto extract_sfmt_adds_m_b_m;
+ case 129 : itype = CRISV10F_INSN_ADDU_M_W_M; goto extract_sfmt_adds_m_w_m;
+ case 130 : itype = CRISV10F_INSN_ADDS_M_B_M; goto extract_sfmt_adds_m_b_m;
+ case 131 :
+ {
+ unsigned int val = (((insn >> 8) & (7 << 4)) | ((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 : /* fall through */
+ case 16 : /* fall through */
+ case 17 : /* fall through */
+ case 18 : /* fall through */
+ case 19 : /* fall through */
+ case 20 : /* fall through */
+ case 21 : /* fall through */
+ case 22 : /* fall through */
+ case 23 : /* fall through */
+ case 24 : /* fall through */
+ case 25 : /* fall through */
+ case 26 : /* fall through */
+ case 27 : /* fall through */
+ case 28 : /* fall through */
+ case 29 : /* fall through */
+ case 30 : /* fall through */
+ case 31 : /* fall through */
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : /* fall through */
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : /* fall through */
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : /* fall through */
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 : /* fall through */
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : /* fall through */
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : /* fall through */
+ case 56 : /* fall through */
+ case 57 : /* fall through */
+ case 58 : /* fall through */
+ case 59 : /* fall through */
+ case 60 : /* fall through */
+ case 61 : /* fall through */
+ case 62 : /* fall through */
+ case 63 : /* fall through */
+ case 64 : /* fall through */
+ case 65 : /* fall through */
+ case 66 : /* fall through */
+ case 67 : /* fall through */
+ case 68 : /* fall through */
+ case 69 : /* fall through */
+ case 70 : /* fall through */
+ case 71 : /* fall through */
+ case 72 : /* fall through */
+ case 73 : /* fall through */
+ case 74 : /* fall through */
+ case 75 : /* fall through */
+ case 76 : /* fall through */
+ case 77 : /* fall through */
+ case 78 : /* fall through */
+ case 79 : /* fall through */
+ case 80 : /* fall through */
+ case 81 : /* fall through */
+ case 82 : /* fall through */
+ case 83 : /* fall through */
+ case 84 : /* fall through */
+ case 85 : /* fall through */
+ case 86 : /* fall through */
+ case 87 : /* fall through */
+ case 88 : /* fall through */
+ case 89 : /* fall through */
+ case 90 : /* fall through */
+ case 91 : /* fall through */
+ case 92 : /* fall through */
+ case 93 : /* fall through */
+ case 94 : /* fall through */
+ case 95 : /* fall through */
+ case 96 : /* fall through */
+ case 97 : /* fall through */
+ case 98 : /* fall through */
+ case 99 : /* fall through */
+ case 100 : /* fall through */
+ case 101 : /* fall through */
+ case 102 : /* fall through */
+ case 103 : /* fall through */
+ case 104 : /* fall through */
+ case 105 : /* fall through */
+ case 106 : /* fall through */
+ case 107 : /* fall through */
+ case 108 : /* fall through */
+ case 109 : /* fall through */
+ case 110 : /* fall through */
+ case 111 : /* fall through */
+ case 112 : /* fall through */
+ case 113 : /* fall through */
+ case 114 : /* fall through */
+ case 115 : /* fall through */
+ case 116 : /* fall through */
+ case 117 : /* fall through */
+ case 118 : /* fall through */
+ case 119 : /* fall through */
+ case 120 : /* fall through */
+ case 121 : /* fall through */
+ case 122 : /* fall through */
+ case 123 : /* fall through */
+ case 124 : /* fall through */
+ case 125 : /* fall through */
+ case 126 : itype = CRISV10F_INSN_ADDS_M_W_M; goto extract_sfmt_adds_m_w_m;
+ case 127 :
+ {
+ unsigned int val = (((insn >> 15) & (1 << 0)));
+ switch (val)
+ {
+ case 0 : itype = CRISV10F_INSN_ADDS_M_W_M; goto extract_sfmt_adds_m_w_m;
+ case 1 : itype = CRISV10F_INSN_ADDSPCPC; goto extract_sfmt_addspcpc;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 132 : itype = CRISV10F_INSN_MOVU_M_B_M; goto extract_sfmt_movs_m_b_m;
+ case 133 : itype = CRISV10F_INSN_MOVU_M_W_M; goto extract_sfmt_movs_m_w_m;
+ case 134 : itype = CRISV10F_INSN_MOVS_M_B_M; goto extract_sfmt_movs_m_b_m;
+ case 135 : itype = CRISV10F_INSN_MOVS_M_W_M; goto extract_sfmt_movs_m_w_m;
+ case 136 : itype = CRISV10F_INSN_SUBU_M_B_M; goto extract_sfmt_adds_m_b_m;
+ case 137 : itype = CRISV10F_INSN_SUBU_M_W_M; goto extract_sfmt_adds_m_w_m;
+ case 138 : itype = CRISV10F_INSN_SUBS_M_B_M; goto extract_sfmt_adds_m_b_m;
+ case 139 : itype = CRISV10F_INSN_SUBS_M_W_M; goto extract_sfmt_adds_m_w_m;
+ case 140 : itype = CRISV10F_INSN_CMPU_M_B_M; goto extract_sfmt_cmp_m_b_m;
+ case 141 : itype = CRISV10F_INSN_CMPU_M_W_M; goto extract_sfmt_cmp_m_w_m;
+ case 142 : itype = CRISV10F_INSN_CMPS_M_B_M; goto extract_sfmt_cmp_m_b_m;
+ case 143 : itype = CRISV10F_INSN_CMPS_M_W_M; goto extract_sfmt_cmp_m_w_m;
+ case 144 : itype = CRISV10F_INSN_MULU_B; goto extract_sfmt_muls_b;
+ case 145 : itype = CRISV10F_INSN_MULU_W; goto extract_sfmt_muls_b;
+ case 146 : itype = CRISV10F_INSN_MULU_D; goto extract_sfmt_muls_b;
+ case 147 :
+ {
+ unsigned int val = (((insn >> 12) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 15 : itype = CRISV10F_INSN_JUMP_M; goto extract_sfmt_jump_m;
+ case 14 : itype = CRISV10F_INSN_BREAK; goto extract_sfmt_break;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 148 : itype = CRISV10F_INSN_ADDO_M_B_M; goto extract_sfmt_addo_m_b_m;
+ case 149 : itype = CRISV10F_INSN_ADDO_M_W_M; goto extract_sfmt_addo_m_w_m;
+ case 150 : itype = CRISV10F_INSN_ADDO_M_D_M; goto extract_sfmt_addo_m_d_m;
+ case 151 : itype = CRISV10F_INSN_DIP_M; goto extract_sfmt_dip_m;
+ case 155 : itype = CRISV10F_INSN_JUMP_R; goto extract_sfmt_jump_r;
+ case 156 : itype = CRISV10F_INSN_BOUND_M_B_M; goto extract_sfmt_bound_m_b_m;
+ case 157 : itype = CRISV10F_INSN_BOUND_M_W_M; goto extract_sfmt_bound_m_w_m;
+ case 158 : itype = CRISV10F_INSN_BOUND_M_D_M; goto extract_sfmt_bound_m_d_m;
+ case 160 : itype = CRISV10F_INSN_ADD_M_B_M; goto extract_sfmt_add_m_b_m;
+ case 161 : itype = CRISV10F_INSN_ADD_M_W_M; goto extract_sfmt_add_m_w_m;
+ case 162 : itype = CRISV10F_INSN_ADD_M_D_M; goto extract_sfmt_add_m_d_m;
+ case 163 : itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10;
+ case 164 : itype = CRISV10F_INSN_MOVE_M_B_M; goto extract_sfmt_move_m_b_m;
+ case 165 : itype = CRISV10F_INSN_MOVE_M_W_M; goto extract_sfmt_move_m_w_m;
+ case 166 : itype = CRISV10F_INSN_MOVE_M_D_M; goto extract_sfmt_move_m_d_m;
+ case 167 : /* fall through */
+ case 231 : itype = CRISV10F_INSN_MOVE_SPR_MV10; goto extract_sfmt_move_spr_mv10;
+ case 168 : itype = CRISV10F_INSN_SUB_M_B_M; goto extract_sfmt_add_m_b_m;
+ case 169 : itype = CRISV10F_INSN_SUB_M_W_M; goto extract_sfmt_add_m_w_m;
+ case 170 : itype = CRISV10F_INSN_SUB_M_D_M; goto extract_sfmt_add_m_d_m;
+ case 172 : itype = CRISV10F_INSN_CMP_M_B_M; goto extract_sfmt_cmp_m_b_m;
+ case 173 : itype = CRISV10F_INSN_CMP_M_W_M; goto extract_sfmt_cmp_m_w_m;
+ case 174 : itype = CRISV10F_INSN_CMP_M_D_M; goto extract_sfmt_cmp_m_d_m;
+ case 176 : itype = CRISV10F_INSN_AND_M_B_M; goto extract_sfmt_and_m_b_m;
+ case 177 : itype = CRISV10F_INSN_AND_M_W_M; goto extract_sfmt_and_m_w_m;
+ case 178 : itype = CRISV10F_INSN_AND_M_D_M; goto extract_sfmt_and_m_d_m;
+ case 180 : itype = CRISV10F_INSN_OR_M_B_M; goto extract_sfmt_and_m_b_m;
+ case 181 : itype = CRISV10F_INSN_OR_M_W_M; goto extract_sfmt_and_m_w_m;
+ case 182 : itype = CRISV10F_INSN_OR_M_D_M; goto extract_sfmt_and_m_d_m;
+ case 183 : /* fall through */
+ case 247 : itype = CRISV10F_INSN_SBFS; goto extract_sfmt_sbfs;
+ case 184 : /* fall through */
+ case 248 : itype = CRISV10F_INSN_TEST_M_B_M; goto extract_sfmt_test_m_b_m;
+ case 185 : /* fall through */
+ case 249 : itype = CRISV10F_INSN_TEST_M_W_M; goto extract_sfmt_test_m_w_m;
+ case 186 : /* fall through */
+ case 250 : itype = CRISV10F_INSN_TEST_M_D_M; goto extract_sfmt_test_m_d_m;
+ case 187 : /* fall through */
+ case 251 :
+ {
+ unsigned int val = (((insn >> 12) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_MOVEM_M_R; goto extract_sfmt_movem_m_r;
+ case 15 : itype = CRISV10F_INSN_MOVEM_M_PC; goto extract_sfmt_movem_m_pc;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 188 : /* fall through */
+ case 252 : itype = CRISV10F_INSN_MOVE_R_M_B_M; goto extract_sfmt_move_r_m_b_m;
+ case 189 : /* fall through */
+ case 253 : itype = CRISV10F_INSN_MOVE_R_M_W_M; goto extract_sfmt_move_r_m_w_m;
+ case 190 : /* fall through */
+ case 254 : itype = CRISV10F_INSN_MOVE_R_M_D_M; goto extract_sfmt_move_r_m_d_m;
+ case 191 : /* fall through */
+ case 255 : itype = CRISV10F_INSN_MOVEM_R_M; goto extract_sfmt_movem_r_m;
+ case 192 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_ADDU_M_B_M; goto extract_sfmt_adds_m_b_m;
+ case 15 : itype = CRISV10F_INSN_ADDUCBR; goto extract_sfmt_addscbr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 193 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_ADDU_M_W_M; goto extract_sfmt_adds_m_w_m;
+ case 15 : itype = CRISV10F_INSN_ADDUCWR; goto extract_sfmt_addscwr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 194 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_ADDS_M_B_M; goto extract_sfmt_adds_m_b_m;
+ case 15 : itype = CRISV10F_INSN_ADDSCBR; goto extract_sfmt_addscbr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 195 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_ADDS_M_W_M; goto extract_sfmt_adds_m_w_m;
+ case 15 : itype = CRISV10F_INSN_ADDSCWR; goto extract_sfmt_addscwr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 196 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_MOVU_M_B_M; goto extract_sfmt_movs_m_b_m;
+ case 15 : itype = CRISV10F_INSN_MOVUCBR; goto extract_sfmt_movucbr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 197 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_MOVU_M_W_M; goto extract_sfmt_movs_m_w_m;
+ case 15 : itype = CRISV10F_INSN_MOVUCWR; goto extract_sfmt_movucwr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 198 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_MOVS_M_B_M; goto extract_sfmt_movs_m_b_m;
+ case 15 : itype = CRISV10F_INSN_MOVSCBR; goto extract_sfmt_movscbr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 199 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_MOVS_M_W_M; goto extract_sfmt_movs_m_w_m;
+ case 15 : itype = CRISV10F_INSN_MOVSCWR; goto extract_sfmt_movscwr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 200 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_SUBU_M_B_M; goto extract_sfmt_adds_m_b_m;
+ case 15 : itype = CRISV10F_INSN_SUBUCBR; goto extract_sfmt_addscbr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 201 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_SUBU_M_W_M; goto extract_sfmt_adds_m_w_m;
+ case 15 : itype = CRISV10F_INSN_SUBUCWR; goto extract_sfmt_addscwr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 202 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_SUBS_M_B_M; goto extract_sfmt_adds_m_b_m;
+ case 15 : itype = CRISV10F_INSN_SUBSCBR; goto extract_sfmt_addscbr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 203 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_SUBS_M_W_M; goto extract_sfmt_adds_m_w_m;
+ case 15 : itype = CRISV10F_INSN_SUBSCWR; goto extract_sfmt_addscwr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 204 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_CMPU_M_B_M; goto extract_sfmt_cmp_m_b_m;
+ case 15 : itype = CRISV10F_INSN_CMPUCBR; goto extract_sfmt_cmpucbr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 205 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_CMPU_M_W_M; goto extract_sfmt_cmp_m_w_m;
+ case 15 : itype = CRISV10F_INSN_CMPUCWR; goto extract_sfmt_cmpucwr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 206 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_CMPS_M_B_M; goto extract_sfmt_cmp_m_b_m;
+ case 15 : itype = CRISV10F_INSN_CMPSCBR; goto extract_sfmt_cmpcbr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 207 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_CMPS_M_W_M; goto extract_sfmt_cmp_m_w_m;
+ case 15 : itype = CRISV10F_INSN_CMPSCWR; goto extract_sfmt_cmpcwr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 208 : itype = CRISV10F_INSN_MULS_B; goto extract_sfmt_muls_b;
+ case 209 : itype = CRISV10F_INSN_MULS_W; goto extract_sfmt_muls_b;
+ case 210 : itype = CRISV10F_INSN_MULS_D; goto extract_sfmt_muls_b;
+ case 211 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_JUMP_M; goto extract_sfmt_jump_m;
+ case 15 : itype = CRISV10F_INSN_JUMP_C; goto extract_sfmt_jump_c;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 212 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_ADDO_M_B_M; goto extract_sfmt_addo_m_b_m;
+ case 15 : itype = CRISV10F_INSN_ADDO_CB; goto extract_sfmt_addo_cb;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 213 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_ADDO_M_W_M; goto extract_sfmt_addo_m_w_m;
+ case 15 : itype = CRISV10F_INSN_ADDO_CW; goto extract_sfmt_addo_cw;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 214 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_ADDO_M_D_M; goto extract_sfmt_addo_m_d_m;
+ case 15 : itype = CRISV10F_INSN_ADDO_CD; goto extract_sfmt_addo_cd;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 215 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_DIP_M; goto extract_sfmt_dip_m;
+ case 15 : itype = CRISV10F_INSN_DIP_C; goto extract_sfmt_dip_c;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 220 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_BOUND_M_B_M; goto extract_sfmt_bound_m_b_m;
+ case 15 : itype = CRISV10F_INSN_BOUND_CB; goto extract_sfmt_bound_cb;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 221 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_BOUND_M_W_M; goto extract_sfmt_bound_m_w_m;
+ case 15 : itype = CRISV10F_INSN_BOUND_CW; goto extract_sfmt_bound_cw;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 222 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_BOUND_M_D_M; goto extract_sfmt_bound_m_d_m;
+ case 15 : itype = CRISV10F_INSN_BOUND_CD; goto extract_sfmt_bound_cd;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 223 :
+ {
+ unsigned int val = (((insn >> 12) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 15 : itype = CRISV10F_INSN_BCC_W; goto extract_sfmt_bcc_w;
+ case 14 : itype = CRISV10F_INSN_BA_W; goto extract_sfmt_ba_w;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 224 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_ADD_M_B_M; goto extract_sfmt_add_m_b_m;
+ case 15 : itype = CRISV10F_INSN_ADDCBR; goto extract_sfmt_addcbr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 225 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_ADD_M_W_M; goto extract_sfmt_add_m_w_m;
+ case 15 : itype = CRISV10F_INSN_ADDCWR; goto extract_sfmt_addcwr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 226 :
+ {
+ unsigned int val = (((insn >> 12) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_ADD_M_D_M; goto extract_sfmt_add_m_d_m;
+ case 15 : itype = CRISV10F_INSN_ADDCDR; goto extract_sfmt_addcdr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 15 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_ADD_M_D_M; goto extract_sfmt_add_m_d_m;
+ case 15 : itype = CRISV10F_INSN_ADDCPC; goto extract_sfmt_addcpc;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 227 :
+ {
+ unsigned int val = (((insn >> 12) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10;
+ case 15 : itype = CRISV10F_INSN_MOVE_C_SPRV10_P0; goto extract_sfmt_move_c_sprv10_p0;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10;
+ case 15 : itype = CRISV10F_INSN_MOVE_C_SPRV10_P1; goto extract_sfmt_move_c_sprv10_p0;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 6 : itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10;
+ case 4 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10;
+ case 15 : itype = CRISV10F_INSN_MOVE_C_SPRV10_P4; goto extract_sfmt_move_c_sprv10_p4;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 5 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10;
+ case 15 : itype = CRISV10F_INSN_MOVE_C_SPRV10_P5; goto extract_sfmt_move_c_sprv10_p4;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 7 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10;
+ case 15 : itype = CRISV10F_INSN_MOVE_C_SPRV10_P7; goto extract_sfmt_move_c_sprv10_p8;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 8 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10;
+ case 15 : itype = CRISV10F_INSN_MOVE_C_SPRV10_P8; goto extract_sfmt_move_c_sprv10_p8;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 9 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10;
+ case 15 : itype = CRISV10F_INSN_MOVE_C_SPRV10_P9; goto extract_sfmt_move_c_sprv10_p8;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 10 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10;
+ case 15 : itype = CRISV10F_INSN_MOVE_C_SPRV10_P10; goto extract_sfmt_move_c_sprv10_p8;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 11 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10;
+ case 15 : itype = CRISV10F_INSN_MOVE_C_SPRV10_P11; goto extract_sfmt_move_c_sprv10_p8;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 12 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10;
+ case 15 : itype = CRISV10F_INSN_MOVE_C_SPRV10_P12; goto extract_sfmt_move_c_sprv10_p8;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 13 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10;
+ case 15 : itype = CRISV10F_INSN_MOVE_C_SPRV10_P13; goto extract_sfmt_move_c_sprv10_p8;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 14 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10;
+ case 15 : itype = CRISV10F_INSN_MOVE_C_SPRV10_P14; goto extract_sfmt_move_c_sprv10_p8;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 15 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_MOVE_M_SPRV10; goto extract_sfmt_move_m_sprv10;
+ case 15 : itype = CRISV10F_INSN_MOVE_C_SPRV10_P15; goto extract_sfmt_move_c_sprv10_p8;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 228 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_MOVE_M_B_M; goto extract_sfmt_move_m_b_m;
+ case 15 : itype = CRISV10F_INSN_MOVECBR; goto extract_sfmt_movecbr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 229 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_MOVE_M_W_M; goto extract_sfmt_move_m_w_m;
+ case 15 : itype = CRISV10F_INSN_MOVECWR; goto extract_sfmt_movecwr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 230 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_MOVE_M_D_M; goto extract_sfmt_move_m_d_m;
+ case 15 : itype = CRISV10F_INSN_MOVECDR; goto extract_sfmt_movecdr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 232 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_SUB_M_B_M; goto extract_sfmt_add_m_b_m;
+ case 15 : itype = CRISV10F_INSN_SUBCBR; goto extract_sfmt_addcbr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 233 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_SUB_M_W_M; goto extract_sfmt_add_m_w_m;
+ case 15 : itype = CRISV10F_INSN_SUBCWR; goto extract_sfmt_addcwr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 234 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_SUB_M_D_M; goto extract_sfmt_add_m_d_m;
+ case 15 : itype = CRISV10F_INSN_SUBCDR; goto extract_sfmt_addcdr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 236 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_CMP_M_B_M; goto extract_sfmt_cmp_m_b_m;
+ case 15 : itype = CRISV10F_INSN_CMPCBR; goto extract_sfmt_cmpcbr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 237 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_CMP_M_W_M; goto extract_sfmt_cmp_m_w_m;
+ case 15 : itype = CRISV10F_INSN_CMPCWR; goto extract_sfmt_cmpcwr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 238 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_CMP_M_D_M; goto extract_sfmt_cmp_m_d_m;
+ case 15 : itype = CRISV10F_INSN_CMPCDR; goto extract_sfmt_cmpcdr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 240 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_AND_M_B_M; goto extract_sfmt_and_m_b_m;
+ case 15 : itype = CRISV10F_INSN_ANDCBR; goto extract_sfmt_andcbr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 241 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_AND_M_W_M; goto extract_sfmt_and_m_w_m;
+ case 15 : itype = CRISV10F_INSN_ANDCWR; goto extract_sfmt_andcwr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 242 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_AND_M_D_M; goto extract_sfmt_and_m_d_m;
+ case 15 : itype = CRISV10F_INSN_ANDCDR; goto extract_sfmt_andcdr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 244 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_OR_M_B_M; goto extract_sfmt_and_m_b_m;
+ case 15 : itype = CRISV10F_INSN_ORCBR; goto extract_sfmt_andcbr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 245 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_OR_M_W_M; goto extract_sfmt_and_m_w_m;
+ case 15 : itype = CRISV10F_INSN_ORCWR; goto extract_sfmt_andcwr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 246 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV10F_INSN_OR_M_D_M; goto extract_sfmt_and_m_d_m;
+ case 15 : itype = CRISV10F_INSN_ORCDR; goto extract_sfmt_andcdr;
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = CRISV10F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ }
+
+ /* The instruction has been decoded, now extract the fields. */
+
+ extract_sfmt_empty:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_nop:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_b_r:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_b_r", "f_operand1 0x%x", 'x', f_operand1, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_d_r:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_d_r", "f_operand1 0x%x", 'x', f_operand1, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movepcr:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_moveq.f
+ UINT f_operand2;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movepcr", "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_moveq:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_moveq.f
+ UINT f_operand2;
+ INT f_s6;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_s6 = EXTRACT_LSB0_INT (insn, 16, 5, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_s6) = f_s6;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_moveq", "f_s6 0x%x", 'x', f_s6, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movs_b_r:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movs_b_r", "f_operand1 0x%x", 'x', f_operand1, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movecbr:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ INT f_indir_pc__byte;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__byte) = f_indir_pc__byte;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movecbr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__byte 0x%x", 'x', f_indir_pc__byte, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movecwr:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ INT f_indir_pc__word;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__word) = f_indir_pc__word;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movecwr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__word 0x%x", 'x', f_indir_pc__word, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movecdr:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ INT f_indir_pc__dword;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUSI (current_cpu, pc + 2);
+ f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_indir_pc__dword) = f_indir_pc__dword;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movecdr", "f_indir_pc__dword 0x%x", 'x', f_indir_pc__dword, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movscbr:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ UINT f_operand2;
+ INT f_indir_pc__byte;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_indir_pc__byte) = f_indir_pc__byte;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movscbr", "f_indir_pc__byte 0x%x", 'x', f_indir_pc__byte, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movscwr:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ UINT f_operand2;
+ INT f_indir_pc__word;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_indir_pc__word) = f_indir_pc__word;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movscwr", "f_indir_pc__word 0x%x", 'x', f_indir_pc__word, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movucbr:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ UINT f_operand2;
+ INT f_indir_pc__byte;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_indir_pc__byte) = f_indir_pc__byte;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movucbr", "f_indir_pc__byte 0x%x", 'x', f_indir_pc__byte, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movucwr:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ UINT f_operand2;
+ INT f_indir_pc__word;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_indir_pc__word) = f_indir_pc__word;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movucwr", "f_indir_pc__word 0x%x", 'x', f_indir_pc__word, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addq:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addq.f
+ UINT f_operand2;
+ UINT f_u6;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_u6 = EXTRACT_LSB0_UINT (insn, 16, 5, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addq", "f_operand2 0x%x", 'x', f_operand2, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_r_b_r:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_r_b_r", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_m_b_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_m_b_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_m_w_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_m_w_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_m_d_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_m_d_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmpcbr:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ INT f_indir_pc__byte;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__byte) = f_indir_pc__byte;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpcbr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__byte 0x%x", 'x', f_indir_pc__byte, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmpcwr:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ INT f_indir_pc__word;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__word) = f_indir_pc__word;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpcwr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__word 0x%x", 'x', f_indir_pc__word, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmpcdr:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ INT f_indir_pc__dword;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUSI (current_cpu, pc + 2);
+ f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__dword) = f_indir_pc__dword;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpcdr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__dword 0x%x", 'x', f_indir_pc__dword, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmpq:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_andq.f
+ UINT f_operand2;
+ INT f_s6;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_s6 = EXTRACT_LSB0_INT (insn, 16, 5, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_s6) = f_s6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpq", "f_operand2 0x%x", 'x', f_operand2, "f_s6 0x%x", 'x', f_s6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmpucbr:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ INT f_indir_pc__byte;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__byte) = f_indir_pc__byte;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpucbr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__byte 0x%x", 'x', f_indir_pc__byte, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmpucwr:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ INT f_indir_pc__word;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__word) = f_indir_pc__word;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpucwr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__word 0x%x", 'x', f_indir_pc__word, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_m_b_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_operand2) = f_operand2;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_m_b_m", "f_operand1 0x%x", 'x', f_operand1, "f_operand2 0x%x", 'x', f_operand2, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ FLD (out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd) = ((ANDIF (GET_H_INSN_PREFIXED_P (), (! (FLD (f_memmode))))) ? (FLD (f_operand1)) : (FLD (f_operand2)));
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_m_w_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_operand2) = f_operand2;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_m_w_m", "f_operand1 0x%x", 'x', f_operand1, "f_operand2 0x%x", 'x', f_operand2, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ FLD (out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd) = ((ANDIF (GET_H_INSN_PREFIXED_P (), (! (FLD (f_memmode))))) ? (FLD (f_operand1)) : (FLD (f_operand2)));
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_m_d_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_operand2) = f_operand2;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_m_d_m", "f_operand1 0x%x", 'x', f_operand1, "f_operand2 0x%x", 'x', f_operand2, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ FLD (out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd) = ((ANDIF (GET_H_INSN_PREFIXED_P (), (! (FLD (f_memmode))))) ? (FLD (f_operand1)) : (FLD (f_operand2)));
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movs_m_b_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movs_m_b_m", "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rd) = f_operand2;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movs_m_w_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movs_m_w_m", "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rd) = f_operand2;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_r_sprv10:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_r_sprv10", "f_operand1 0x%x", 'x', f_operand1, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Pd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_spr_rv10:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_spr_rv10.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_spr_rv10", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Ps) = f_operand2;
+ FLD (out_h_gr_SI_index_of__DFLT_Rs) = FLD (f_operand1);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ret_type:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_spr_rv10.f
+ UINT f_operand2;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ret_type", "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Ps) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_m_sprv10:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_operand2) = f_operand2;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_m_sprv10", "f_operand1 0x%x", 'x', f_operand1, "f_operand2 0x%x", 'x', f_operand2, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Pd) = f_operand2;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_c_sprv10_p0:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p0.f
+ UINT f_operand2;
+ INT f_indir_pc__byte;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_indir_pc__byte) = f_indir_pc__byte;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_c_sprv10_p0", "f_indir_pc__byte 0x%x", 'x', f_indir_pc__byte, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_Pd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_c_sprv10_p4:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p4.f
+ UINT f_operand2;
+ INT f_indir_pc__word;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_indir_pc__word) = f_indir_pc__word;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_c_sprv10_p4", "f_indir_pc__word 0x%x", 'x', f_indir_pc__word, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_Pd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_c_sprv10_p8:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ INT f_indir_pc__dword;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUSI (current_cpu, pc + 2);
+ f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_indir_pc__dword) = f_indir_pc__dword;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_c_sprv10_p8", "f_indir_pc__dword 0x%x", 'x', f_indir_pc__dword, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_Pd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_spr_mv10:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_spr_mv10", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Ps) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sbfs:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sbfs", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movem_r_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_movem_r_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movem_r_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (in_h_gr_SI_0) = 0;
+ FLD (in_h_gr_SI_1) = 1;
+ FLD (in_h_gr_SI_10) = 10;
+ FLD (in_h_gr_SI_11) = 11;
+ FLD (in_h_gr_SI_12) = 12;
+ FLD (in_h_gr_SI_13) = 13;
+ FLD (in_h_gr_SI_14) = 14;
+ FLD (in_h_gr_SI_15) = 15;
+ FLD (in_h_gr_SI_2) = 2;
+ FLD (in_h_gr_SI_3) = 3;
+ FLD (in_h_gr_SI_4) = 4;
+ FLD (in_h_gr_SI_5) = 5;
+ FLD (in_h_gr_SI_6) = 6;
+ FLD (in_h_gr_SI_7) = 7;
+ FLD (in_h_gr_SI_8) = 8;
+ FLD (in_h_gr_SI_9) = 9;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movem_m_r:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_movem_m_r.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movem_m_r", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ FLD (out_h_gr_SI_0) = 0;
+ FLD (out_h_gr_SI_1) = 1;
+ FLD (out_h_gr_SI_10) = 10;
+ FLD (out_h_gr_SI_11) = 11;
+ FLD (out_h_gr_SI_12) = 12;
+ FLD (out_h_gr_SI_13) = 13;
+ FLD (out_h_gr_SI_14) = 14;
+ FLD (out_h_gr_SI_2) = 2;
+ FLD (out_h_gr_SI_3) = 3;
+ FLD (out_h_gr_SI_4) = 4;
+ FLD (out_h_gr_SI_5) = 5;
+ FLD (out_h_gr_SI_6) = 6;
+ FLD (out_h_gr_SI_7) = 7;
+ FLD (out_h_gr_SI_8) = 8;
+ FLD (out_h_gr_SI_9) = 9;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movem_m_pc:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_movem_m_r.f
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movem_m_pc", "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ FLD (out_h_gr_SI_0) = 0;
+ FLD (out_h_gr_SI_1) = 1;
+ FLD (out_h_gr_SI_10) = 10;
+ FLD (out_h_gr_SI_11) = 11;
+ FLD (out_h_gr_SI_12) = 12;
+ FLD (out_h_gr_SI_13) = 13;
+ FLD (out_h_gr_SI_14) = 14;
+ FLD (out_h_gr_SI_2) = 2;
+ FLD (out_h_gr_SI_3) = 3;
+ FLD (out_h_gr_SI_4) = 4;
+ FLD (out_h_gr_SI_5) = 5;
+ FLD (out_h_gr_SI_6) = 6;
+ FLD (out_h_gr_SI_7) = 7;
+ FLD (out_h_gr_SI_8) = 8;
+ FLD (out_h_gr_SI_9) = 9;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_b_r:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_b_r", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_d_r:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_d_r", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_m_b_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_m_b_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ FLD (out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd) = ((ANDIF (GET_H_INSN_PREFIXED_P (), (! (FLD (f_memmode))))) ? (FLD (f_operand1)) : (FLD (f_operand2)));
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_m_w_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_m_w_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ FLD (out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd) = ((ANDIF (GET_H_INSN_PREFIXED_P (), (! (FLD (f_memmode))))) ? (FLD (f_operand1)) : (FLD (f_operand2)));
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_m_d_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_m_d_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ FLD (out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd) = ((ANDIF (GET_H_INSN_PREFIXED_P (), (! (FLD (f_memmode))))) ? (FLD (f_operand1)) : (FLD (f_operand2)));
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addcbr:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ INT f_indir_pc__byte;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__byte) = f_indir_pc__byte;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addcbr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__byte 0x%x", 'x', f_indir_pc__byte, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addcwr:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ INT f_indir_pc__word;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__word) = f_indir_pc__word;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addcwr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__word 0x%x", 'x', f_indir_pc__word, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addcdr:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ INT f_indir_pc__dword;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUSI (current_cpu, pc + 2);
+ f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__dword) = f_indir_pc__dword;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addcdr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__dword 0x%x", 'x', f_indir_pc__dword, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addcpc:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ INT f_indir_pc__dword;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUSI (current_cpu, pc + 2);
+ f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_indir_pc__dword) = f_indir_pc__dword;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addcpc", "f_indir_pc__dword 0x%x", 'x', f_indir_pc__dword, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adds_m_b_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adds_m_b_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ FLD (out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd) = ((ANDIF (GET_H_INSN_PREFIXED_P (), (! (FLD (f_memmode))))) ? (FLD (f_operand1)) : (FLD (f_operand2)));
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adds_m_w_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adds_m_w_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ FLD (out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd) = ((ANDIF (GET_H_INSN_PREFIXED_P (), (! (FLD (f_memmode))))) ? (FLD (f_operand1)) : (FLD (f_operand2)));
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addscbr:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ INT f_indir_pc__byte;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__byte) = f_indir_pc__byte;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addscbr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__byte 0x%x", 'x', f_indir_pc__byte, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addscwr:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ INT f_indir_pc__word;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__word) = f_indir_pc__word;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addscwr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__word 0x%x", 'x', f_indir_pc__word, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addspcpc:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addspcpc", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addi_b_r:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi_b_r", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_neg_b_r:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_neg_b_r", "f_operand1 0x%x", 'x', f_operand1, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_neg_d_r:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_neg_d_r", "f_operand1 0x%x", 'x', f_operand1, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_test_m_b_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_test_m_b_m", "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_test_m_w_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_test_m_w_m", "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_test_m_d_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_test_m_d_m", "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_r_m_b_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_r_m_b_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_r_m_w_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_r_m_w_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_r_m_d_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_r_m_d_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_muls_b:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_muls_b", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rd) = f_operand2;
+ FLD (out_h_sr_SI_7) = 7;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mstep:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mstep", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_dstep:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_dstep", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_b_r:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_b_r", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_w_r:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_w_r", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_d_r:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_d_r", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_m_b_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_m_b_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ FLD (out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd) = ((ANDIF (GET_H_INSN_PREFIXED_P (), (! (FLD (f_memmode))))) ? (FLD (f_operand1)) : (FLD (f_operand2)));
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_m_w_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_m_w_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ FLD (out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd) = ((ANDIF (GET_H_INSN_PREFIXED_P (), (! (FLD (f_memmode))))) ? (FLD (f_operand1)) : (FLD (f_operand2)));
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_m_d_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_m_d_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ FLD (out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd) = ((ANDIF (GET_H_INSN_PREFIXED_P (), (! (FLD (f_memmode))))) ? (FLD (f_operand1)) : (FLD (f_operand2)));
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_andcbr:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ INT f_indir_pc__byte;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__byte) = f_indir_pc__byte;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andcbr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__byte 0x%x", 'x', f_indir_pc__byte, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_andcwr:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ INT f_indir_pc__word;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__word) = f_indir_pc__word;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andcwr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__word 0x%x", 'x', f_indir_pc__word, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_andcdr:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ INT f_indir_pc__dword;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUSI (current_cpu, pc + 2);
+ f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__dword) = f_indir_pc__dword;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andcdr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__dword 0x%x", 'x', f_indir_pc__dword, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_andq:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_andq.f
+ UINT f_operand2;
+ INT f_s6;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_s6 = EXTRACT_LSB0_INT (insn, 16, 5, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_s6) = f_s6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andq", "f_operand2 0x%x", 'x', f_operand2, "f_s6 0x%x", 'x', f_s6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_swap:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_swap", "f_operand1 0x%x", 'x', f_operand1, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asrr_b_r:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asrr_b_r", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asrq:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_asrq.f
+ UINT f_operand2;
+ UINT f_u5;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_u5 = EXTRACT_LSB0_UINT (insn, 16, 4, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_u5) = f_u5;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asrq", "f_operand2 0x%x", 'x', f_operand2, "f_u5 0x%x", 'x', f_u5, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lsrr_b_r:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lsrr_b_r", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lsrr_d_r:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lsrr_d_r", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_btst:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_btstq:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_asrq.f
+ UINT f_operand2;
+ UINT f_u5;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_u5 = EXTRACT_LSB0_UINT (insn, 16, 4, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_u5) = f_u5;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btstq", "f_operand2 0x%x", 'x', f_operand2, "f_u5 0x%x", 'x', f_u5, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_setf:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_setf.f
+ UINT f_operand2;
+ UINT f_operand1;
+ UINT f_dstsrc;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+ f_dstsrc = ((((f_operand1) | (((f_operand2) << (4))))) & (255));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstsrc) = f_dstsrc;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setf", "f_dstsrc 0x%x", 'x', f_dstsrc, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bcc_b:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bcc_b.f
+ UINT f_operand2;
+ UINT f_disp9_lo;
+ INT f_disp9_hi;
+ INT f_disp9;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7);
+ f_disp9_hi = EXTRACT_LSB0_INT (insn, 16, 0, 1);
+{
+ SI tmp_abslo;
+ SI tmp_absval;
+ tmp_abslo = ((f_disp9_lo) << (1));
+ tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));
+ f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_NON_V32 ()) ? (0) : (2))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (i_o_pcrel) = f_disp9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcc_b", "f_operand2 0x%x", 'x', f_operand2, "o_pcrel 0x%x", 'x', f_disp9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ba_b:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bcc_b.f
+ UINT f_disp9_lo;
+ INT f_disp9_hi;
+ INT f_disp9;
+
+ f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7);
+ f_disp9_hi = EXTRACT_LSB0_INT (insn, 16, 0, 1);
+{
+ SI tmp_abslo;
+ SI tmp_absval;
+ tmp_abslo = ((f_disp9_lo) << (1));
+ tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));
+ f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_NON_V32 ()) ? (0) : (2))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_o_pcrel) = f_disp9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ba_b", "o_pcrel 0x%x", 'x', f_disp9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bcc_w:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bcc_w.f
+ SI f_indir_pc__word_pcrel;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_NON_V32 ()) ? (0) : (4))))));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (i_o_word_pcrel) = f_indir_pc__word_pcrel;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcc_w", "f_operand2 0x%x", 'x', f_operand2, "o_word_pcrel 0x%x", 'x', f_indir_pc__word_pcrel, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ba_w:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bcc_w.f
+ SI f_indir_pc__word_pcrel;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_NON_V32 ()) ? (0) : (4))))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_o_word_pcrel) = f_indir_pc__word_pcrel;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ba_w", "o_word_pcrel 0x%x", 'x', f_indir_pc__word_pcrel, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jump_r:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jump_r", "f_operand1 0x%x", 'x', f_operand1, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Pd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jump_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jump_m", "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Pd) = f_operand2;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jump_c:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ INT f_indir_pc__dword;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUSI (current_cpu, pc + 2);
+ f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_indir_pc__dword) = f_indir_pc__dword;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jump_c", "f_indir_pc__dword 0x%x", 'x', f_indir_pc__dword, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_Pd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_break:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_break.f
+ UINT f_u4;
+
+ f_u4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u4) = f_u4;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_break", "f_u4 0x%x", 'x', f_u4, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bound_m_b_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bound_m_b_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rd) = f_operand2;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bound_m_w_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bound_m_w_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rd) = f_operand2;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bound_m_d_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bound_m_d_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rd) = f_operand2;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bound_cb:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ INT f_indir_pc__byte;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__byte) = f_indir_pc__byte;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bound_cb", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__byte 0x%x", 'x', f_indir_pc__byte, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bound_cw:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ INT f_indir_pc__word;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__word) = f_indir_pc__word;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bound_cw", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__word 0x%x", 'x', f_indir_pc__word, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bound_cd:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ INT f_indir_pc__dword;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUSI (current_cpu, pc + 2);
+ f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__dword) = f_indir_pc__dword;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bound_cd", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__dword 0x%x", 'x', f_indir_pc__dword, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_scc:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_scc", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addoq:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addoq.f
+ UINT f_operand2;
+ INT f_s8;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_s8 = EXTRACT_LSB0_INT (insn, 16, 7, 8);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_s8) = f_s8;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addoq", "f_operand2 0x%x", 'x', f_operand2, "f_s8 0x%x", 'x', f_s8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bdapqpc:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addoq.f
+ INT f_s8;
+
+ f_s8 = EXTRACT_LSB0_INT (insn, 16, 7, 8);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_s8) = f_s8;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bdapqpc", "f_s8 0x%x", 'x', f_s8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addo_m_b_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addo_m_b_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addo_m_w_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addo_m_w_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addo_m_d_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addo_m_d_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addo_cb:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ INT f_indir_pc__byte;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__byte) = f_indir_pc__byte;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addo_cb", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__byte 0x%x", 'x', f_indir_pc__byte, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addo_cw:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ INT f_indir_pc__word;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__word) = f_indir_pc__word;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addo_cw", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__word 0x%x", 'x', f_indir_pc__word, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addo_cd:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ INT f_indir_pc__dword;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUSI (current_cpu, pc + 2);
+ f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__dword) = f_indir_pc__dword;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addo_cd", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__dword 0x%x", 'x', f_indir_pc__dword, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_dip_m:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_dip_m", "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_dip_c:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ INT f_indir_pc__dword;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUSI (current_cpu, pc + 2);
+ f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_indir_pc__dword) = f_indir_pc__dword;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_dip_c", "f_indir_pc__dword 0x%x", 'x', f_indir_pc__dword, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addi_acr_b_r:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi_acr_b_r", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_biap_pc_b_r:
+ {
+ const IDESC *idesc = &crisv10f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addoq.f
+ UINT f_operand2;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_biap_pc_b_r", "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+}
--- /dev/null
+/* Decode header for crisv10f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2004 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef CRISV10F_DECODE_H
+#define CRISV10F_DECODE_H
+
+extern const IDESC *crisv10f_decode (SIM_CPU *, IADDR,
+ CGEN_INSN_INT,
+ ARGBUF *);
+extern void crisv10f_init_idesc_table (SIM_CPU *);
+extern void crisv10f_sem_init_idesc_table (SIM_CPU *);
+extern void crisv10f_semf_init_idesc_table (SIM_CPU *);
+
+/* Enum declaration for instructions in cpu family crisv10f. */
+typedef enum crisv10f_insn_type {
+ CRISV10F_INSN_X_INVALID, CRISV10F_INSN_X_AFTER, CRISV10F_INSN_X_BEFORE, CRISV10F_INSN_X_CTI_CHAIN
+ , CRISV10F_INSN_X_CHAIN, CRISV10F_INSN_X_BEGIN, CRISV10F_INSN_NOP, CRISV10F_INSN_MOVE_B_R
+ , CRISV10F_INSN_MOVE_W_R, CRISV10F_INSN_MOVE_D_R, CRISV10F_INSN_MOVEPCR, CRISV10F_INSN_MOVEQ
+ , CRISV10F_INSN_MOVS_B_R, CRISV10F_INSN_MOVS_W_R, CRISV10F_INSN_MOVU_B_R, CRISV10F_INSN_MOVU_W_R
+ , CRISV10F_INSN_MOVECBR, CRISV10F_INSN_MOVECWR, CRISV10F_INSN_MOVECDR, CRISV10F_INSN_MOVSCBR
+ , CRISV10F_INSN_MOVSCWR, CRISV10F_INSN_MOVUCBR, CRISV10F_INSN_MOVUCWR, CRISV10F_INSN_ADDQ
+ , CRISV10F_INSN_SUBQ, CRISV10F_INSN_CMP_R_B_R, CRISV10F_INSN_CMP_R_W_R, CRISV10F_INSN_CMP_R_D_R
+ , CRISV10F_INSN_CMP_M_B_M, CRISV10F_INSN_CMP_M_W_M, CRISV10F_INSN_CMP_M_D_M, CRISV10F_INSN_CMPCBR
+ , CRISV10F_INSN_CMPCWR, CRISV10F_INSN_CMPCDR, CRISV10F_INSN_CMPQ, CRISV10F_INSN_CMPS_M_B_M
+ , CRISV10F_INSN_CMPS_M_W_M, CRISV10F_INSN_CMPSCBR, CRISV10F_INSN_CMPSCWR, CRISV10F_INSN_CMPU_M_B_M
+ , CRISV10F_INSN_CMPU_M_W_M, CRISV10F_INSN_CMPUCBR, CRISV10F_INSN_CMPUCWR, CRISV10F_INSN_MOVE_M_B_M
+ , CRISV10F_INSN_MOVE_M_W_M, CRISV10F_INSN_MOVE_M_D_M, CRISV10F_INSN_MOVS_M_B_M, CRISV10F_INSN_MOVS_M_W_M
+ , CRISV10F_INSN_MOVU_M_B_M, CRISV10F_INSN_MOVU_M_W_M, CRISV10F_INSN_MOVE_R_SPRV10, CRISV10F_INSN_MOVE_SPR_RV10
+ , CRISV10F_INSN_RET_TYPE, CRISV10F_INSN_MOVE_M_SPRV10, CRISV10F_INSN_MOVE_C_SPRV10_P0, CRISV10F_INSN_MOVE_C_SPRV10_P1
+ , CRISV10F_INSN_MOVE_C_SPRV10_P4, CRISV10F_INSN_MOVE_C_SPRV10_P5, CRISV10F_INSN_MOVE_C_SPRV10_P8, CRISV10F_INSN_MOVE_C_SPRV10_P9
+ , CRISV10F_INSN_MOVE_C_SPRV10_P10, CRISV10F_INSN_MOVE_C_SPRV10_P11, CRISV10F_INSN_MOVE_C_SPRV10_P12, CRISV10F_INSN_MOVE_C_SPRV10_P13
+ , CRISV10F_INSN_MOVE_C_SPRV10_P7, CRISV10F_INSN_MOVE_C_SPRV10_P14, CRISV10F_INSN_MOVE_C_SPRV10_P15, CRISV10F_INSN_MOVE_SPR_MV10
+ , CRISV10F_INSN_SBFS, CRISV10F_INSN_MOVEM_R_M, CRISV10F_INSN_MOVEM_M_R, CRISV10F_INSN_MOVEM_M_PC
+ , CRISV10F_INSN_ADD_B_R, CRISV10F_INSN_ADD_W_R, CRISV10F_INSN_ADD_D_R, CRISV10F_INSN_ADD_M_B_M
+ , CRISV10F_INSN_ADD_M_W_M, CRISV10F_INSN_ADD_M_D_M, CRISV10F_INSN_ADDCBR, CRISV10F_INSN_ADDCWR
+ , CRISV10F_INSN_ADDCDR, CRISV10F_INSN_ADDCPC, CRISV10F_INSN_ADDS_B_R, CRISV10F_INSN_ADDS_W_R
+ , CRISV10F_INSN_ADDS_M_B_M, CRISV10F_INSN_ADDS_M_W_M, CRISV10F_INSN_ADDSCBR, CRISV10F_INSN_ADDSCWR
+ , CRISV10F_INSN_ADDSPCPC, CRISV10F_INSN_ADDU_B_R, CRISV10F_INSN_ADDU_W_R, CRISV10F_INSN_ADDU_M_B_M
+ , CRISV10F_INSN_ADDU_M_W_M, CRISV10F_INSN_ADDUCBR, CRISV10F_INSN_ADDUCWR, CRISV10F_INSN_SUB_B_R
+ , CRISV10F_INSN_SUB_W_R, CRISV10F_INSN_SUB_D_R, CRISV10F_INSN_SUB_M_B_M, CRISV10F_INSN_SUB_M_W_M
+ , CRISV10F_INSN_SUB_M_D_M, CRISV10F_INSN_SUBCBR, CRISV10F_INSN_SUBCWR, CRISV10F_INSN_SUBCDR
+ , CRISV10F_INSN_SUBS_B_R, CRISV10F_INSN_SUBS_W_R, CRISV10F_INSN_SUBS_M_B_M, CRISV10F_INSN_SUBS_M_W_M
+ , CRISV10F_INSN_SUBSCBR, CRISV10F_INSN_SUBSCWR, CRISV10F_INSN_SUBU_B_R, CRISV10F_INSN_SUBU_W_R
+ , CRISV10F_INSN_SUBU_M_B_M, CRISV10F_INSN_SUBU_M_W_M, CRISV10F_INSN_SUBUCBR, CRISV10F_INSN_SUBUCWR
+ , CRISV10F_INSN_ADDI_B_R, CRISV10F_INSN_ADDI_W_R, CRISV10F_INSN_ADDI_D_R, CRISV10F_INSN_NEG_B_R
+ , CRISV10F_INSN_NEG_W_R, CRISV10F_INSN_NEG_D_R, CRISV10F_INSN_TEST_M_B_M, CRISV10F_INSN_TEST_M_W_M
+ , CRISV10F_INSN_TEST_M_D_M, CRISV10F_INSN_MOVE_R_M_B_M, CRISV10F_INSN_MOVE_R_M_W_M, CRISV10F_INSN_MOVE_R_M_D_M
+ , CRISV10F_INSN_MULS_B, CRISV10F_INSN_MULS_W, CRISV10F_INSN_MULS_D, CRISV10F_INSN_MULU_B
+ , CRISV10F_INSN_MULU_W, CRISV10F_INSN_MULU_D, CRISV10F_INSN_MSTEP, CRISV10F_INSN_DSTEP
+ , CRISV10F_INSN_ABS, CRISV10F_INSN_AND_B_R, CRISV10F_INSN_AND_W_R, CRISV10F_INSN_AND_D_R
+ , CRISV10F_INSN_AND_M_B_M, CRISV10F_INSN_AND_M_W_M, CRISV10F_INSN_AND_M_D_M, CRISV10F_INSN_ANDCBR
+ , CRISV10F_INSN_ANDCWR, CRISV10F_INSN_ANDCDR, CRISV10F_INSN_ANDQ, CRISV10F_INSN_ORR_B_R
+ , CRISV10F_INSN_ORR_W_R, CRISV10F_INSN_ORR_D_R, CRISV10F_INSN_OR_M_B_M, CRISV10F_INSN_OR_M_W_M
+ , CRISV10F_INSN_OR_M_D_M, CRISV10F_INSN_ORCBR, CRISV10F_INSN_ORCWR, CRISV10F_INSN_ORCDR
+ , CRISV10F_INSN_ORQ, CRISV10F_INSN_XOR, CRISV10F_INSN_SWAP, CRISV10F_INSN_ASRR_B_R
+ , CRISV10F_INSN_ASRR_W_R, CRISV10F_INSN_ASRR_D_R, CRISV10F_INSN_ASRQ, CRISV10F_INSN_LSRR_B_R
+ , CRISV10F_INSN_LSRR_W_R, CRISV10F_INSN_LSRR_D_R, CRISV10F_INSN_LSRQ, CRISV10F_INSN_LSLR_B_R
+ , CRISV10F_INSN_LSLR_W_R, CRISV10F_INSN_LSLR_D_R, CRISV10F_INSN_LSLQ, CRISV10F_INSN_BTST
+ , CRISV10F_INSN_BTSTQ, CRISV10F_INSN_SETF, CRISV10F_INSN_CLEARF, CRISV10F_INSN_BCC_B
+ , CRISV10F_INSN_BA_B, CRISV10F_INSN_BCC_W, CRISV10F_INSN_BA_W, CRISV10F_INSN_JUMP_R
+ , CRISV10F_INSN_JUMP_M, CRISV10F_INSN_JUMP_C, CRISV10F_INSN_BREAK, CRISV10F_INSN_BOUND_R_B_R
+ , CRISV10F_INSN_BOUND_R_W_R, CRISV10F_INSN_BOUND_R_D_R, CRISV10F_INSN_BOUND_M_B_M, CRISV10F_INSN_BOUND_M_W_M
+ , CRISV10F_INSN_BOUND_M_D_M, CRISV10F_INSN_BOUND_CB, CRISV10F_INSN_BOUND_CW, CRISV10F_INSN_BOUND_CD
+ , CRISV10F_INSN_SCC, CRISV10F_INSN_LZ, CRISV10F_INSN_ADDOQ, CRISV10F_INSN_BDAPQPC
+ , CRISV10F_INSN_ADDO_M_B_M, CRISV10F_INSN_ADDO_M_W_M, CRISV10F_INSN_ADDO_M_D_M, CRISV10F_INSN_ADDO_CB
+ , CRISV10F_INSN_ADDO_CW, CRISV10F_INSN_ADDO_CD, CRISV10F_INSN_DIP_M, CRISV10F_INSN_DIP_C
+ , CRISV10F_INSN_ADDI_ACR_B_R, CRISV10F_INSN_ADDI_ACR_W_R, CRISV10F_INSN_ADDI_ACR_D_R, CRISV10F_INSN_BIAP_PC_B_R
+ , CRISV10F_INSN_BIAP_PC_W_R, CRISV10F_INSN_BIAP_PC_D_R, CRISV10F_INSN__MAX
+} CRISV10F_INSN_TYPE;
+
+/* Enum declaration for semantic formats in cpu family crisv10f. */
+typedef enum crisv10f_sfmt_type {
+ CRISV10F_SFMT_EMPTY, CRISV10F_SFMT_NOP, CRISV10F_SFMT_MOVE_B_R, CRISV10F_SFMT_MOVE_D_R
+ , CRISV10F_SFMT_MOVEPCR, CRISV10F_SFMT_MOVEQ, CRISV10F_SFMT_MOVS_B_R, CRISV10F_SFMT_MOVECBR
+ , CRISV10F_SFMT_MOVECWR, CRISV10F_SFMT_MOVECDR, CRISV10F_SFMT_MOVSCBR, CRISV10F_SFMT_MOVSCWR
+ , CRISV10F_SFMT_MOVUCBR, CRISV10F_SFMT_MOVUCWR, CRISV10F_SFMT_ADDQ, CRISV10F_SFMT_CMP_R_B_R
+ , CRISV10F_SFMT_CMP_M_B_M, CRISV10F_SFMT_CMP_M_W_M, CRISV10F_SFMT_CMP_M_D_M, CRISV10F_SFMT_CMPCBR
+ , CRISV10F_SFMT_CMPCWR, CRISV10F_SFMT_CMPCDR, CRISV10F_SFMT_CMPQ, CRISV10F_SFMT_CMPUCBR
+ , CRISV10F_SFMT_CMPUCWR, CRISV10F_SFMT_MOVE_M_B_M, CRISV10F_SFMT_MOVE_M_W_M, CRISV10F_SFMT_MOVE_M_D_M
+ , CRISV10F_SFMT_MOVS_M_B_M, CRISV10F_SFMT_MOVS_M_W_M, CRISV10F_SFMT_MOVE_R_SPRV10, CRISV10F_SFMT_MOVE_SPR_RV10
+ , CRISV10F_SFMT_RET_TYPE, CRISV10F_SFMT_MOVE_M_SPRV10, CRISV10F_SFMT_MOVE_C_SPRV10_P0, CRISV10F_SFMT_MOVE_C_SPRV10_P4
+ , CRISV10F_SFMT_MOVE_C_SPRV10_P8, CRISV10F_SFMT_MOVE_SPR_MV10, CRISV10F_SFMT_SBFS, CRISV10F_SFMT_MOVEM_R_M
+ , CRISV10F_SFMT_MOVEM_M_R, CRISV10F_SFMT_MOVEM_M_PC, CRISV10F_SFMT_ADD_B_R, CRISV10F_SFMT_ADD_D_R
+ , CRISV10F_SFMT_ADD_M_B_M, CRISV10F_SFMT_ADD_M_W_M, CRISV10F_SFMT_ADD_M_D_M, CRISV10F_SFMT_ADDCBR
+ , CRISV10F_SFMT_ADDCWR, CRISV10F_SFMT_ADDCDR, CRISV10F_SFMT_ADDCPC, CRISV10F_SFMT_ADDS_M_B_M
+ , CRISV10F_SFMT_ADDS_M_W_M, CRISV10F_SFMT_ADDSCBR, CRISV10F_SFMT_ADDSCWR, CRISV10F_SFMT_ADDSPCPC
+ , CRISV10F_SFMT_ADDI_B_R, CRISV10F_SFMT_NEG_B_R, CRISV10F_SFMT_NEG_D_R, CRISV10F_SFMT_TEST_M_B_M
+ , CRISV10F_SFMT_TEST_M_W_M, CRISV10F_SFMT_TEST_M_D_M, CRISV10F_SFMT_MOVE_R_M_B_M, CRISV10F_SFMT_MOVE_R_M_W_M
+ , CRISV10F_SFMT_MOVE_R_M_D_M, CRISV10F_SFMT_MULS_B, CRISV10F_SFMT_MSTEP, CRISV10F_SFMT_DSTEP
+ , CRISV10F_SFMT_AND_B_R, CRISV10F_SFMT_AND_W_R, CRISV10F_SFMT_AND_D_R, CRISV10F_SFMT_AND_M_B_M
+ , CRISV10F_SFMT_AND_M_W_M, CRISV10F_SFMT_AND_M_D_M, CRISV10F_SFMT_ANDCBR, CRISV10F_SFMT_ANDCWR
+ , CRISV10F_SFMT_ANDCDR, CRISV10F_SFMT_ANDQ, CRISV10F_SFMT_SWAP, CRISV10F_SFMT_ASRR_B_R
+ , CRISV10F_SFMT_ASRQ, CRISV10F_SFMT_LSRR_B_R, CRISV10F_SFMT_LSRR_D_R, CRISV10F_SFMT_BTST
+ , CRISV10F_SFMT_BTSTQ, CRISV10F_SFMT_SETF, CRISV10F_SFMT_BCC_B, CRISV10F_SFMT_BA_B
+ , CRISV10F_SFMT_BCC_W, CRISV10F_SFMT_BA_W, CRISV10F_SFMT_JUMP_R, CRISV10F_SFMT_JUMP_M
+ , CRISV10F_SFMT_JUMP_C, CRISV10F_SFMT_BREAK, CRISV10F_SFMT_BOUND_M_B_M, CRISV10F_SFMT_BOUND_M_W_M
+ , CRISV10F_SFMT_BOUND_M_D_M, CRISV10F_SFMT_BOUND_CB, CRISV10F_SFMT_BOUND_CW, CRISV10F_SFMT_BOUND_CD
+ , CRISV10F_SFMT_SCC, CRISV10F_SFMT_ADDOQ, CRISV10F_SFMT_BDAPQPC, CRISV10F_SFMT_ADDO_M_B_M
+ , CRISV10F_SFMT_ADDO_M_W_M, CRISV10F_SFMT_ADDO_M_D_M, CRISV10F_SFMT_ADDO_CB, CRISV10F_SFMT_ADDO_CW
+ , CRISV10F_SFMT_ADDO_CD, CRISV10F_SFMT_DIP_M, CRISV10F_SFMT_DIP_C, CRISV10F_SFMT_ADDI_ACR_B_R
+ , CRISV10F_SFMT_BIAP_PC_B_R
+} CRISV10F_SFMT_TYPE;
+
+/* Function unit handlers (user written). */
+
+extern int crisv10f_model_crisv10_u_movem (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rd*/);
+extern int crisv10f_model_crisv10_u_multiply (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int crisv10f_model_crisv10_u_skip4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int crisv10f_model_crisv10_u_stall (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int crisv10f_model_crisv10_u_const32 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int crisv10f_model_crisv10_u_const16 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int crisv10f_model_crisv10_u_mem (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int crisv10f_model_crisv10_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+
+/* Profiling before/after handlers (user written) */
+
+extern void crisv10f_model_insn_before (SIM_CPU *, int /*first_p*/);
+extern void crisv10f_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
+
+#endif /* CRISV10F_DECODE_H */
--- /dev/null
+/* Simulator instruction decoder for crisv32f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2004 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU crisv32f
+#define WANT_CPU_CRISV32F
+
+#include "sim-main.h"
+#include "sim-assert.h"
+
+/* The instruction descriptor array.
+ This is computed at runtime. Space for it is not malloc'd to save a
+ teensy bit of cpu in the decoder. Moving it to malloc space is trivial
+ but won't be done until necessary (we don't currently support the runtime
+ addition of instructions nor an SMP machine with different cpus). */
+static IDESC crisv32f_insn_data[CRISV32F_INSN__MAX];
+
+/* Commas between elements are contained in the macros.
+ Some of these are conditionally compiled out. */
+
+static const struct insn_sem crisv32f_insn_sem[] =
+{
+ { VIRTUAL_INSN_X_INVALID, CRISV32F_INSN_X_INVALID, CRISV32F_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_AFTER, CRISV32F_INSN_X_AFTER, CRISV32F_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_BEFORE, CRISV32F_INSN_X_BEFORE, CRISV32F_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_CTI_CHAIN, CRISV32F_INSN_X_CTI_CHAIN, CRISV32F_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_CHAIN, CRISV32F_INSN_X_CHAIN, CRISV32F_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_BEGIN, CRISV32F_INSN_X_BEGIN, CRISV32F_SFMT_EMPTY },
+ { CRIS_INSN_MOVE_B_R, CRISV32F_INSN_MOVE_B_R, CRISV32F_SFMT_MOVE_B_R },
+ { CRIS_INSN_MOVE_W_R, CRISV32F_INSN_MOVE_W_R, CRISV32F_SFMT_MOVE_B_R },
+ { CRIS_INSN_MOVE_D_R, CRISV32F_INSN_MOVE_D_R, CRISV32F_SFMT_MOVE_D_R },
+ { CRIS_INSN_MOVEQ, CRISV32F_INSN_MOVEQ, CRISV32F_SFMT_MOVEQ },
+ { CRIS_INSN_MOVS_B_R, CRISV32F_INSN_MOVS_B_R, CRISV32F_SFMT_MOVS_B_R },
+ { CRIS_INSN_MOVS_W_R, CRISV32F_INSN_MOVS_W_R, CRISV32F_SFMT_MOVS_B_R },
+ { CRIS_INSN_MOVU_B_R, CRISV32F_INSN_MOVU_B_R, CRISV32F_SFMT_MOVS_B_R },
+ { CRIS_INSN_MOVU_W_R, CRISV32F_INSN_MOVU_W_R, CRISV32F_SFMT_MOVS_B_R },
+ { CRIS_INSN_MOVECBR, CRISV32F_INSN_MOVECBR, CRISV32F_SFMT_MOVECBR },
+ { CRIS_INSN_MOVECWR, CRISV32F_INSN_MOVECWR, CRISV32F_SFMT_MOVECWR },
+ { CRIS_INSN_MOVECDR, CRISV32F_INSN_MOVECDR, CRISV32F_SFMT_MOVECDR },
+ { CRIS_INSN_MOVSCBR, CRISV32F_INSN_MOVSCBR, CRISV32F_SFMT_MOVSCBR },
+ { CRIS_INSN_MOVSCWR, CRISV32F_INSN_MOVSCWR, CRISV32F_SFMT_MOVSCWR },
+ { CRIS_INSN_MOVUCBR, CRISV32F_INSN_MOVUCBR, CRISV32F_SFMT_MOVUCBR },
+ { CRIS_INSN_MOVUCWR, CRISV32F_INSN_MOVUCWR, CRISV32F_SFMT_MOVUCWR },
+ { CRIS_INSN_ADDQ, CRISV32F_INSN_ADDQ, CRISV32F_SFMT_ADDQ },
+ { CRIS_INSN_SUBQ, CRISV32F_INSN_SUBQ, CRISV32F_SFMT_ADDQ },
+ { CRIS_INSN_CMP_R_B_R, CRISV32F_INSN_CMP_R_B_R, CRISV32F_SFMT_CMP_R_B_R },
+ { CRIS_INSN_CMP_R_W_R, CRISV32F_INSN_CMP_R_W_R, CRISV32F_SFMT_CMP_R_B_R },
+ { CRIS_INSN_CMP_R_D_R, CRISV32F_INSN_CMP_R_D_R, CRISV32F_SFMT_CMP_R_B_R },
+ { CRIS_INSN_CMP_M_B_M, CRISV32F_INSN_CMP_M_B_M, CRISV32F_SFMT_CMP_M_B_M },
+ { CRIS_INSN_CMP_M_W_M, CRISV32F_INSN_CMP_M_W_M, CRISV32F_SFMT_CMP_M_W_M },
+ { CRIS_INSN_CMP_M_D_M, CRISV32F_INSN_CMP_M_D_M, CRISV32F_SFMT_CMP_M_D_M },
+ { CRIS_INSN_CMPCBR, CRISV32F_INSN_CMPCBR, CRISV32F_SFMT_CMPCBR },
+ { CRIS_INSN_CMPCWR, CRISV32F_INSN_CMPCWR, CRISV32F_SFMT_CMPCWR },
+ { CRIS_INSN_CMPCDR, CRISV32F_INSN_CMPCDR, CRISV32F_SFMT_CMPCDR },
+ { CRIS_INSN_CMPQ, CRISV32F_INSN_CMPQ, CRISV32F_SFMT_CMPQ },
+ { CRIS_INSN_CMPS_M_B_M, CRISV32F_INSN_CMPS_M_B_M, CRISV32F_SFMT_CMP_M_B_M },
+ { CRIS_INSN_CMPS_M_W_M, CRISV32F_INSN_CMPS_M_W_M, CRISV32F_SFMT_CMP_M_W_M },
+ { CRIS_INSN_CMPSCBR, CRISV32F_INSN_CMPSCBR, CRISV32F_SFMT_CMPCBR },
+ { CRIS_INSN_CMPSCWR, CRISV32F_INSN_CMPSCWR, CRISV32F_SFMT_CMPCWR },
+ { CRIS_INSN_CMPU_M_B_M, CRISV32F_INSN_CMPU_M_B_M, CRISV32F_SFMT_CMP_M_B_M },
+ { CRIS_INSN_CMPU_M_W_M, CRISV32F_INSN_CMPU_M_W_M, CRISV32F_SFMT_CMP_M_W_M },
+ { CRIS_INSN_CMPUCBR, CRISV32F_INSN_CMPUCBR, CRISV32F_SFMT_CMPUCBR },
+ { CRIS_INSN_CMPUCWR, CRISV32F_INSN_CMPUCWR, CRISV32F_SFMT_CMPUCWR },
+ { CRIS_INSN_MOVE_M_B_M, CRISV32F_INSN_MOVE_M_B_M, CRISV32F_SFMT_MOVE_M_B_M },
+ { CRIS_INSN_MOVE_M_W_M, CRISV32F_INSN_MOVE_M_W_M, CRISV32F_SFMT_MOVE_M_W_M },
+ { CRIS_INSN_MOVE_M_D_M, CRISV32F_INSN_MOVE_M_D_M, CRISV32F_SFMT_MOVE_M_D_M },
+ { CRIS_INSN_MOVS_M_B_M, CRISV32F_INSN_MOVS_M_B_M, CRISV32F_SFMT_MOVS_M_B_M },
+ { CRIS_INSN_MOVS_M_W_M, CRISV32F_INSN_MOVS_M_W_M, CRISV32F_SFMT_MOVS_M_W_M },
+ { CRIS_INSN_MOVU_M_B_M, CRISV32F_INSN_MOVU_M_B_M, CRISV32F_SFMT_MOVS_M_B_M },
+ { CRIS_INSN_MOVU_M_W_M, CRISV32F_INSN_MOVU_M_W_M, CRISV32F_SFMT_MOVS_M_W_M },
+ { CRIS_INSN_MOVE_R_SPRV32, CRISV32F_INSN_MOVE_R_SPRV32, CRISV32F_SFMT_MOVE_R_SPRV32 },
+ { CRIS_INSN_MOVE_SPR_RV32, CRISV32F_INSN_MOVE_SPR_RV32, CRISV32F_SFMT_MOVE_SPR_RV32 },
+ { CRIS_INSN_MOVE_M_SPRV32, CRISV32F_INSN_MOVE_M_SPRV32, CRISV32F_SFMT_MOVE_M_SPRV32 },
+ { CRIS_INSN_MOVE_C_SPRV32_P0, CRISV32F_INSN_MOVE_C_SPRV32_P0, CRISV32F_SFMT_MOVE_C_SPRV32_P0 },
+ { CRIS_INSN_MOVE_C_SPRV32_P1, CRISV32F_INSN_MOVE_C_SPRV32_P1, CRISV32F_SFMT_MOVE_C_SPRV32_P0 },
+ { CRIS_INSN_MOVE_C_SPRV32_P2, CRISV32F_INSN_MOVE_C_SPRV32_P2, CRISV32F_SFMT_MOVE_C_SPRV32_P0 },
+ { CRIS_INSN_MOVE_C_SPRV32_P3, CRISV32F_INSN_MOVE_C_SPRV32_P3, CRISV32F_SFMT_MOVE_C_SPRV32_P0 },
+ { CRIS_INSN_MOVE_C_SPRV32_P4, CRISV32F_INSN_MOVE_C_SPRV32_P4, CRISV32F_SFMT_MOVE_C_SPRV32_P0 },
+ { CRIS_INSN_MOVE_C_SPRV32_P5, CRISV32F_INSN_MOVE_C_SPRV32_P5, CRISV32F_SFMT_MOVE_C_SPRV32_P0 },
+ { CRIS_INSN_MOVE_C_SPRV32_P6, CRISV32F_INSN_MOVE_C_SPRV32_P6, CRISV32F_SFMT_MOVE_C_SPRV32_P0 },
+ { CRIS_INSN_MOVE_C_SPRV32_P7, CRISV32F_INSN_MOVE_C_SPRV32_P7, CRISV32F_SFMT_MOVE_C_SPRV32_P0 },
+ { CRIS_INSN_MOVE_C_SPRV32_P8, CRISV32F_INSN_MOVE_C_SPRV32_P8, CRISV32F_SFMT_MOVE_C_SPRV32_P0 },
+ { CRIS_INSN_MOVE_C_SPRV32_P9, CRISV32F_INSN_MOVE_C_SPRV32_P9, CRISV32F_SFMT_MOVE_C_SPRV32_P0 },
+ { CRIS_INSN_MOVE_C_SPRV32_P10, CRISV32F_INSN_MOVE_C_SPRV32_P10, CRISV32F_SFMT_MOVE_C_SPRV32_P0 },
+ { CRIS_INSN_MOVE_C_SPRV32_P11, CRISV32F_INSN_MOVE_C_SPRV32_P11, CRISV32F_SFMT_MOVE_C_SPRV32_P0 },
+ { CRIS_INSN_MOVE_C_SPRV32_P12, CRISV32F_INSN_MOVE_C_SPRV32_P12, CRISV32F_SFMT_MOVE_C_SPRV32_P0 },
+ { CRIS_INSN_MOVE_C_SPRV32_P13, CRISV32F_INSN_MOVE_C_SPRV32_P13, CRISV32F_SFMT_MOVE_C_SPRV32_P0 },
+ { CRIS_INSN_MOVE_C_SPRV32_P14, CRISV32F_INSN_MOVE_C_SPRV32_P14, CRISV32F_SFMT_MOVE_C_SPRV32_P0 },
+ { CRIS_INSN_MOVE_C_SPRV32_P15, CRISV32F_INSN_MOVE_C_SPRV32_P15, CRISV32F_SFMT_MOVE_C_SPRV32_P0 },
+ { CRIS_INSN_MOVE_SPR_MV32, CRISV32F_INSN_MOVE_SPR_MV32, CRISV32F_SFMT_MOVE_SPR_MV32 },
+ { CRIS_INSN_MOVE_SS_R, CRISV32F_INSN_MOVE_SS_R, CRISV32F_SFMT_MOVE_SS_R },
+ { CRIS_INSN_MOVE_R_SS, CRISV32F_INSN_MOVE_R_SS, CRISV32F_SFMT_MOVE_R_SS },
+ { CRIS_INSN_MOVEM_R_M_V32, CRISV32F_INSN_MOVEM_R_M_V32, CRISV32F_SFMT_MOVEM_R_M_V32 },
+ { CRIS_INSN_MOVEM_M_R_V32, CRISV32F_INSN_MOVEM_M_R_V32, CRISV32F_SFMT_MOVEM_M_R_V32 },
+ { CRIS_INSN_ADD_B_R, CRISV32F_INSN_ADD_B_R, CRISV32F_SFMT_ADD_B_R },
+ { CRIS_INSN_ADD_W_R, CRISV32F_INSN_ADD_W_R, CRISV32F_SFMT_ADD_B_R },
+ { CRIS_INSN_ADD_D_R, CRISV32F_INSN_ADD_D_R, CRISV32F_SFMT_ADD_D_R },
+ { CRIS_INSN_ADD_M_B_M, CRISV32F_INSN_ADD_M_B_M, CRISV32F_SFMT_ADD_M_B_M },
+ { CRIS_INSN_ADD_M_W_M, CRISV32F_INSN_ADD_M_W_M, CRISV32F_SFMT_ADD_M_W_M },
+ { CRIS_INSN_ADD_M_D_M, CRISV32F_INSN_ADD_M_D_M, CRISV32F_SFMT_ADD_M_D_M },
+ { CRIS_INSN_ADDCBR, CRISV32F_INSN_ADDCBR, CRISV32F_SFMT_ADDCBR },
+ { CRIS_INSN_ADDCWR, CRISV32F_INSN_ADDCWR, CRISV32F_SFMT_ADDCWR },
+ { CRIS_INSN_ADDCDR, CRISV32F_INSN_ADDCDR, CRISV32F_SFMT_ADDCDR },
+ { CRIS_INSN_ADDS_B_R, CRISV32F_INSN_ADDS_B_R, CRISV32F_SFMT_ADD_D_R },
+ { CRIS_INSN_ADDS_W_R, CRISV32F_INSN_ADDS_W_R, CRISV32F_SFMT_ADD_D_R },
+ { CRIS_INSN_ADDS_M_B_M, CRISV32F_INSN_ADDS_M_B_M, CRISV32F_SFMT_ADDS_M_B_M },
+ { CRIS_INSN_ADDS_M_W_M, CRISV32F_INSN_ADDS_M_W_M, CRISV32F_SFMT_ADDS_M_W_M },
+ { CRIS_INSN_ADDSCBR, CRISV32F_INSN_ADDSCBR, CRISV32F_SFMT_ADDSCBR },
+ { CRIS_INSN_ADDSCWR, CRISV32F_INSN_ADDSCWR, CRISV32F_SFMT_ADDSCWR },
+ { CRIS_INSN_ADDU_B_R, CRISV32F_INSN_ADDU_B_R, CRISV32F_SFMT_ADD_D_R },
+ { CRIS_INSN_ADDU_W_R, CRISV32F_INSN_ADDU_W_R, CRISV32F_SFMT_ADD_D_R },
+ { CRIS_INSN_ADDU_M_B_M, CRISV32F_INSN_ADDU_M_B_M, CRISV32F_SFMT_ADDS_M_B_M },
+ { CRIS_INSN_ADDU_M_W_M, CRISV32F_INSN_ADDU_M_W_M, CRISV32F_SFMT_ADDS_M_W_M },
+ { CRIS_INSN_ADDUCBR, CRISV32F_INSN_ADDUCBR, CRISV32F_SFMT_ADDSCBR },
+ { CRIS_INSN_ADDUCWR, CRISV32F_INSN_ADDUCWR, CRISV32F_SFMT_ADDSCWR },
+ { CRIS_INSN_SUB_B_R, CRISV32F_INSN_SUB_B_R, CRISV32F_SFMT_ADD_B_R },
+ { CRIS_INSN_SUB_W_R, CRISV32F_INSN_SUB_W_R, CRISV32F_SFMT_ADD_B_R },
+ { CRIS_INSN_SUB_D_R, CRISV32F_INSN_SUB_D_R, CRISV32F_SFMT_ADD_D_R },
+ { CRIS_INSN_SUB_M_B_M, CRISV32F_INSN_SUB_M_B_M, CRISV32F_SFMT_ADD_M_B_M },
+ { CRIS_INSN_SUB_M_W_M, CRISV32F_INSN_SUB_M_W_M, CRISV32F_SFMT_ADD_M_W_M },
+ { CRIS_INSN_SUB_M_D_M, CRISV32F_INSN_SUB_M_D_M, CRISV32F_SFMT_ADD_M_D_M },
+ { CRIS_INSN_SUBCBR, CRISV32F_INSN_SUBCBR, CRISV32F_SFMT_ADDCBR },
+ { CRIS_INSN_SUBCWR, CRISV32F_INSN_SUBCWR, CRISV32F_SFMT_ADDCWR },
+ { CRIS_INSN_SUBCDR, CRISV32F_INSN_SUBCDR, CRISV32F_SFMT_ADDCDR },
+ { CRIS_INSN_SUBS_B_R, CRISV32F_INSN_SUBS_B_R, CRISV32F_SFMT_ADD_D_R },
+ { CRIS_INSN_SUBS_W_R, CRISV32F_INSN_SUBS_W_R, CRISV32F_SFMT_ADD_D_R },
+ { CRIS_INSN_SUBS_M_B_M, CRISV32F_INSN_SUBS_M_B_M, CRISV32F_SFMT_ADDS_M_B_M },
+ { CRIS_INSN_SUBS_M_W_M, CRISV32F_INSN_SUBS_M_W_M, CRISV32F_SFMT_ADDS_M_W_M },
+ { CRIS_INSN_SUBSCBR, CRISV32F_INSN_SUBSCBR, CRISV32F_SFMT_ADDSCBR },
+ { CRIS_INSN_SUBSCWR, CRISV32F_INSN_SUBSCWR, CRISV32F_SFMT_ADDSCWR },
+ { CRIS_INSN_SUBU_B_R, CRISV32F_INSN_SUBU_B_R, CRISV32F_SFMT_ADD_D_R },
+ { CRIS_INSN_SUBU_W_R, CRISV32F_INSN_SUBU_W_R, CRISV32F_SFMT_ADD_D_R },
+ { CRIS_INSN_SUBU_M_B_M, CRISV32F_INSN_SUBU_M_B_M, CRISV32F_SFMT_ADDS_M_B_M },
+ { CRIS_INSN_SUBU_M_W_M, CRISV32F_INSN_SUBU_M_W_M, CRISV32F_SFMT_ADDS_M_W_M },
+ { CRIS_INSN_SUBUCBR, CRISV32F_INSN_SUBUCBR, CRISV32F_SFMT_ADDSCBR },
+ { CRIS_INSN_SUBUCWR, CRISV32F_INSN_SUBUCWR, CRISV32F_SFMT_ADDSCWR },
+ { CRIS_INSN_ADDC_R, CRISV32F_INSN_ADDC_R, CRISV32F_SFMT_ADD_D_R },
+ { CRIS_INSN_ADDC_M, CRISV32F_INSN_ADDC_M, CRISV32F_SFMT_ADDC_M },
+ { CRIS_INSN_ADDC_C, CRISV32F_INSN_ADDC_C, CRISV32F_SFMT_ADDCDR },
+ { CRIS_INSN_LAPC_D, CRISV32F_INSN_LAPC_D, CRISV32F_SFMT_LAPC_D },
+ { CRIS_INSN_LAPCQ, CRISV32F_INSN_LAPCQ, CRISV32F_SFMT_LAPCQ },
+ { CRIS_INSN_ADDI_B_R, CRISV32F_INSN_ADDI_B_R, CRISV32F_SFMT_ADDI_B_R },
+ { CRIS_INSN_ADDI_W_R, CRISV32F_INSN_ADDI_W_R, CRISV32F_SFMT_ADDI_B_R },
+ { CRIS_INSN_ADDI_D_R, CRISV32F_INSN_ADDI_D_R, CRISV32F_SFMT_ADDI_B_R },
+ { CRIS_INSN_NEG_B_R, CRISV32F_INSN_NEG_B_R, CRISV32F_SFMT_NEG_B_R },
+ { CRIS_INSN_NEG_W_R, CRISV32F_INSN_NEG_W_R, CRISV32F_SFMT_NEG_B_R },
+ { CRIS_INSN_NEG_D_R, CRISV32F_INSN_NEG_D_R, CRISV32F_SFMT_NEG_D_R },
+ { CRIS_INSN_TEST_M_B_M, CRISV32F_INSN_TEST_M_B_M, CRISV32F_SFMT_TEST_M_B_M },
+ { CRIS_INSN_TEST_M_W_M, CRISV32F_INSN_TEST_M_W_M, CRISV32F_SFMT_TEST_M_W_M },
+ { CRIS_INSN_TEST_M_D_M, CRISV32F_INSN_TEST_M_D_M, CRISV32F_SFMT_TEST_M_D_M },
+ { CRIS_INSN_MOVE_R_M_B_M, CRISV32F_INSN_MOVE_R_M_B_M, CRISV32F_SFMT_MOVE_R_M_B_M },
+ { CRIS_INSN_MOVE_R_M_W_M, CRISV32F_INSN_MOVE_R_M_W_M, CRISV32F_SFMT_MOVE_R_M_W_M },
+ { CRIS_INSN_MOVE_R_M_D_M, CRISV32F_INSN_MOVE_R_M_D_M, CRISV32F_SFMT_MOVE_R_M_D_M },
+ { CRIS_INSN_MULS_B, CRISV32F_INSN_MULS_B, CRISV32F_SFMT_MULS_B },
+ { CRIS_INSN_MULS_W, CRISV32F_INSN_MULS_W, CRISV32F_SFMT_MULS_B },
+ { CRIS_INSN_MULS_D, CRISV32F_INSN_MULS_D, CRISV32F_SFMT_MULS_B },
+ { CRIS_INSN_MULU_B, CRISV32F_INSN_MULU_B, CRISV32F_SFMT_MULS_B },
+ { CRIS_INSN_MULU_W, CRISV32F_INSN_MULU_W, CRISV32F_SFMT_MULS_B },
+ { CRIS_INSN_MULU_D, CRISV32F_INSN_MULU_D, CRISV32F_SFMT_MULS_B },
+ { CRIS_INSN_MCP, CRISV32F_INSN_MCP, CRISV32F_SFMT_MCP },
+ { CRIS_INSN_DSTEP, CRISV32F_INSN_DSTEP, CRISV32F_SFMT_DSTEP },
+ { CRIS_INSN_ABS, CRISV32F_INSN_ABS, CRISV32F_SFMT_MOVS_B_R },
+ { CRIS_INSN_AND_B_R, CRISV32F_INSN_AND_B_R, CRISV32F_SFMT_AND_B_R },
+ { CRIS_INSN_AND_W_R, CRISV32F_INSN_AND_W_R, CRISV32F_SFMT_AND_W_R },
+ { CRIS_INSN_AND_D_R, CRISV32F_INSN_AND_D_R, CRISV32F_SFMT_AND_D_R },
+ { CRIS_INSN_AND_M_B_M, CRISV32F_INSN_AND_M_B_M, CRISV32F_SFMT_AND_M_B_M },
+ { CRIS_INSN_AND_M_W_M, CRISV32F_INSN_AND_M_W_M, CRISV32F_SFMT_AND_M_W_M },
+ { CRIS_INSN_AND_M_D_M, CRISV32F_INSN_AND_M_D_M, CRISV32F_SFMT_AND_M_D_M },
+ { CRIS_INSN_ANDCBR, CRISV32F_INSN_ANDCBR, CRISV32F_SFMT_ANDCBR },
+ { CRIS_INSN_ANDCWR, CRISV32F_INSN_ANDCWR, CRISV32F_SFMT_ANDCWR },
+ { CRIS_INSN_ANDCDR, CRISV32F_INSN_ANDCDR, CRISV32F_SFMT_ANDCDR },
+ { CRIS_INSN_ANDQ, CRISV32F_INSN_ANDQ, CRISV32F_SFMT_ANDQ },
+ { CRIS_INSN_ORR_B_R, CRISV32F_INSN_ORR_B_R, CRISV32F_SFMT_AND_B_R },
+ { CRIS_INSN_ORR_W_R, CRISV32F_INSN_ORR_W_R, CRISV32F_SFMT_AND_W_R },
+ { CRIS_INSN_ORR_D_R, CRISV32F_INSN_ORR_D_R, CRISV32F_SFMT_AND_D_R },
+ { CRIS_INSN_OR_M_B_M, CRISV32F_INSN_OR_M_B_M, CRISV32F_SFMT_AND_M_B_M },
+ { CRIS_INSN_OR_M_W_M, CRISV32F_INSN_OR_M_W_M, CRISV32F_SFMT_AND_M_W_M },
+ { CRIS_INSN_OR_M_D_M, CRISV32F_INSN_OR_M_D_M, CRISV32F_SFMT_AND_M_D_M },
+ { CRIS_INSN_ORCBR, CRISV32F_INSN_ORCBR, CRISV32F_SFMT_ANDCBR },
+ { CRIS_INSN_ORCWR, CRISV32F_INSN_ORCWR, CRISV32F_SFMT_ANDCWR },
+ { CRIS_INSN_ORCDR, CRISV32F_INSN_ORCDR, CRISV32F_SFMT_ANDCDR },
+ { CRIS_INSN_ORQ, CRISV32F_INSN_ORQ, CRISV32F_SFMT_ANDQ },
+ { CRIS_INSN_XOR, CRISV32F_INSN_XOR, CRISV32F_SFMT_DSTEP },
+ { CRIS_INSN_SWAP, CRISV32F_INSN_SWAP, CRISV32F_SFMT_SWAP },
+ { CRIS_INSN_ASRR_B_R, CRISV32F_INSN_ASRR_B_R, CRISV32F_SFMT_ASRR_B_R },
+ { CRIS_INSN_ASRR_W_R, CRISV32F_INSN_ASRR_W_R, CRISV32F_SFMT_ASRR_B_R },
+ { CRIS_INSN_ASRR_D_R, CRISV32F_INSN_ASRR_D_R, CRISV32F_SFMT_AND_D_R },
+ { CRIS_INSN_ASRQ, CRISV32F_INSN_ASRQ, CRISV32F_SFMT_ASRQ },
+ { CRIS_INSN_LSRR_B_R, CRISV32F_INSN_LSRR_B_R, CRISV32F_SFMT_LSRR_B_R },
+ { CRIS_INSN_LSRR_W_R, CRISV32F_INSN_LSRR_W_R, CRISV32F_SFMT_LSRR_B_R },
+ { CRIS_INSN_LSRR_D_R, CRISV32F_INSN_LSRR_D_R, CRISV32F_SFMT_LSRR_D_R },
+ { CRIS_INSN_LSRQ, CRISV32F_INSN_LSRQ, CRISV32F_SFMT_ASRQ },
+ { CRIS_INSN_LSLR_B_R, CRISV32F_INSN_LSLR_B_R, CRISV32F_SFMT_LSRR_B_R },
+ { CRIS_INSN_LSLR_W_R, CRISV32F_INSN_LSLR_W_R, CRISV32F_SFMT_LSRR_B_R },
+ { CRIS_INSN_LSLR_D_R, CRISV32F_INSN_LSLR_D_R, CRISV32F_SFMT_LSRR_D_R },
+ { CRIS_INSN_LSLQ, CRISV32F_INSN_LSLQ, CRISV32F_SFMT_ASRQ },
+ { CRIS_INSN_BTST, CRISV32F_INSN_BTST, CRISV32F_SFMT_BTST },
+ { CRIS_INSN_BTSTQ, CRISV32F_INSN_BTSTQ, CRISV32F_SFMT_BTSTQ },
+ { CRIS_INSN_SETF, CRISV32F_INSN_SETF, CRISV32F_SFMT_SETF },
+ { CRIS_INSN_CLEARF, CRISV32F_INSN_CLEARF, CRISV32F_SFMT_SETF },
+ { CRIS_INSN_RFE, CRISV32F_INSN_RFE, CRISV32F_SFMT_RFE },
+ { CRIS_INSN_SFE, CRISV32F_INSN_SFE, CRISV32F_SFMT_SFE },
+ { CRIS_INSN_RFG, CRISV32F_INSN_RFG, CRISV32F_SFMT_RFG },
+ { CRIS_INSN_RFN, CRISV32F_INSN_RFN, CRISV32F_SFMT_RFN },
+ { CRIS_INSN_HALT, CRISV32F_INSN_HALT, CRISV32F_SFMT_HALT },
+ { CRIS_INSN_BCC_B, CRISV32F_INSN_BCC_B, CRISV32F_SFMT_BCC_B },
+ { CRIS_INSN_BA_B, CRISV32F_INSN_BA_B, CRISV32F_SFMT_BA_B },
+ { CRIS_INSN_BCC_W, CRISV32F_INSN_BCC_W, CRISV32F_SFMT_BCC_W },
+ { CRIS_INSN_BA_W, CRISV32F_INSN_BA_W, CRISV32F_SFMT_BA_W },
+ { CRIS_INSN_JAS_R, CRISV32F_INSN_JAS_R, CRISV32F_SFMT_JAS_R },
+ { CRIS_INSN_JAS_C, CRISV32F_INSN_JAS_C, CRISV32F_SFMT_JAS_C },
+ { CRIS_INSN_JUMP_P, CRISV32F_INSN_JUMP_P, CRISV32F_SFMT_JUMP_P },
+ { CRIS_INSN_BAS_C, CRISV32F_INSN_BAS_C, CRISV32F_SFMT_BAS_C },
+ { CRIS_INSN_JASC_R, CRISV32F_INSN_JASC_R, CRISV32F_SFMT_JASC_R },
+ { CRIS_INSN_JASC_C, CRISV32F_INSN_JASC_C, CRISV32F_SFMT_JAS_C },
+ { CRIS_INSN_BASC_C, CRISV32F_INSN_BASC_C, CRISV32F_SFMT_BAS_C },
+ { CRIS_INSN_BREAK, CRISV32F_INSN_BREAK, CRISV32F_SFMT_BREAK },
+ { CRIS_INSN_BOUND_R_B_R, CRISV32F_INSN_BOUND_R_B_R, CRISV32F_SFMT_DSTEP },
+ { CRIS_INSN_BOUND_R_W_R, CRISV32F_INSN_BOUND_R_W_R, CRISV32F_SFMT_DSTEP },
+ { CRIS_INSN_BOUND_R_D_R, CRISV32F_INSN_BOUND_R_D_R, CRISV32F_SFMT_DSTEP },
+ { CRIS_INSN_BOUND_CB, CRISV32F_INSN_BOUND_CB, CRISV32F_SFMT_BOUND_CB },
+ { CRIS_INSN_BOUND_CW, CRISV32F_INSN_BOUND_CW, CRISV32F_SFMT_BOUND_CW },
+ { CRIS_INSN_BOUND_CD, CRISV32F_INSN_BOUND_CD, CRISV32F_SFMT_BOUND_CD },
+ { CRIS_INSN_SCC, CRISV32F_INSN_SCC, CRISV32F_SFMT_SCC },
+ { CRIS_INSN_LZ, CRISV32F_INSN_LZ, CRISV32F_SFMT_MOVS_B_R },
+ { CRIS_INSN_ADDOQ, CRISV32F_INSN_ADDOQ, CRISV32F_SFMT_ADDOQ },
+ { CRIS_INSN_ADDO_M_B_M, CRISV32F_INSN_ADDO_M_B_M, CRISV32F_SFMT_ADDO_M_B_M },
+ { CRIS_INSN_ADDO_M_W_M, CRISV32F_INSN_ADDO_M_W_M, CRISV32F_SFMT_ADDO_M_W_M },
+ { CRIS_INSN_ADDO_M_D_M, CRISV32F_INSN_ADDO_M_D_M, CRISV32F_SFMT_ADDO_M_D_M },
+ { CRIS_INSN_ADDO_CB, CRISV32F_INSN_ADDO_CB, CRISV32F_SFMT_ADDO_CB },
+ { CRIS_INSN_ADDO_CW, CRISV32F_INSN_ADDO_CW, CRISV32F_SFMT_ADDO_CW },
+ { CRIS_INSN_ADDO_CD, CRISV32F_INSN_ADDO_CD, CRISV32F_SFMT_ADDO_CD },
+ { CRIS_INSN_ADDI_ACR_B_R, CRISV32F_INSN_ADDI_ACR_B_R, CRISV32F_SFMT_ADDI_ACR_B_R },
+ { CRIS_INSN_ADDI_ACR_W_R, CRISV32F_INSN_ADDI_ACR_W_R, CRISV32F_SFMT_ADDI_ACR_B_R },
+ { CRIS_INSN_ADDI_ACR_D_R, CRISV32F_INSN_ADDI_ACR_D_R, CRISV32F_SFMT_ADDI_ACR_B_R },
+ { CRIS_INSN_FIDXI, CRISV32F_INSN_FIDXI, CRISV32F_SFMT_FIDXI },
+ { CRIS_INSN_FTAGI, CRISV32F_INSN_FTAGI, CRISV32F_SFMT_FIDXI },
+ { CRIS_INSN_FIDXD, CRISV32F_INSN_FIDXD, CRISV32F_SFMT_FIDXI },
+ { CRIS_INSN_FTAGD, CRISV32F_INSN_FTAGD, CRISV32F_SFMT_FIDXI },
+};
+
+static const struct insn_sem crisv32f_insn_sem_invalid = {
+ VIRTUAL_INSN_X_INVALID, CRISV32F_INSN_X_INVALID, CRISV32F_SFMT_EMPTY
+};
+
+/* Initialize an IDESC from the compile-time computable parts. */
+
+static INLINE void
+init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
+{
+ const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
+
+ id->num = t->index;
+ id->sfmt = t->sfmt;
+ if ((int) t->type <= 0)
+ id->idata = & cgen_virtual_insn_table[- (int) t->type];
+ else
+ id->idata = & insn_table[t->type];
+ id->attrs = CGEN_INSN_ATTRS (id->idata);
+ /* Oh my god, a magic number. */
+ id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
+
+#if WITH_PROFILE_MODEL_P
+ id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
+ {
+ SIM_DESC sd = CPU_STATE (cpu);
+ SIM_ASSERT (t->index == id->timing->num);
+ }
+#endif
+
+ /* Semantic pointers are initialized elsewhere. */
+}
+
+/* Initialize the instruction descriptor table. */
+
+void
+crisv32f_init_idesc_table (SIM_CPU *cpu)
+{
+ IDESC *id,*tabend;
+ const struct insn_sem *t,*tend;
+ int tabsize = CRISV32F_INSN__MAX;
+ IDESC *table = crisv32f_insn_data;
+
+ memset (table, 0, tabsize * sizeof (IDESC));
+
+ /* First set all entries to the `invalid insn'. */
+ t = & crisv32f_insn_sem_invalid;
+ for (id = table, tabend = table + tabsize; id < tabend; ++id)
+ init_idesc (cpu, id, t);
+
+ /* Now fill in the values for the chosen cpu. */
+ for (t = crisv32f_insn_sem, tend = t + sizeof (crisv32f_insn_sem) / sizeof (*t);
+ t != tend; ++t)
+ {
+ init_idesc (cpu, & table[t->index], t);
+ }
+
+ /* Link the IDESC table into the cpu. */
+ CPU_IDESC (cpu) = table;
+}
+
+/* Given an instruction, return a pointer to its IDESC entry. */
+
+const IDESC *
+crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
+ CGEN_INSN_INT base_insn,
+ ARGBUF *abuf)
+{
+ /* Result of decoder. */
+ CRISV32F_INSN_TYPE itype;
+
+ {
+ CGEN_INSN_INT insn = base_insn;
+
+ {
+ unsigned int val = (((insn >> 4) & (255 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : /* fall through */
+ case 15 :
+ {
+ unsigned int val = (((insn >> 12) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 15 : itype = CRISV32F_INSN_BCC_B; goto extract_sfmt_bcc_b;
+ case 14 : itype = CRISV32F_INSN_BA_B; goto extract_sfmt_ba_b;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 16 : /* fall through */
+ case 17 : /* fall through */
+ case 18 : /* fall through */
+ case 19 : /* fall through */
+ case 20 : /* fall through */
+ case 21 : /* fall through */
+ case 22 : /* fall through */
+ case 23 : /* fall through */
+ case 24 : /* fall through */
+ case 25 : /* fall through */
+ case 26 : /* fall through */
+ case 27 : /* fall through */
+ case 28 : /* fall through */
+ case 29 : /* fall through */
+ case 30 : /* fall through */
+ case 31 : itype = CRISV32F_INSN_ADDOQ; goto extract_sfmt_addoq;
+ case 32 : /* fall through */
+ case 33 : /* fall through */
+ case 34 : /* fall through */
+ case 35 : itype = CRISV32F_INSN_ADDQ; goto extract_sfmt_addq;
+ case 36 : /* fall through */
+ case 37 : /* fall through */
+ case 38 : /* fall through */
+ case 39 : itype = CRISV32F_INSN_MOVEQ; goto extract_sfmt_moveq;
+ case 40 : /* fall through */
+ case 41 : /* fall through */
+ case 42 : /* fall through */
+ case 43 : itype = CRISV32F_INSN_SUBQ; goto extract_sfmt_addq;
+ case 44 : /* fall through */
+ case 45 : /* fall through */
+ case 46 : /* fall through */
+ case 47 : itype = CRISV32F_INSN_CMPQ; goto extract_sfmt_cmpq;
+ case 48 : /* fall through */
+ case 49 : /* fall through */
+ case 50 : /* fall through */
+ case 51 : itype = CRISV32F_INSN_ANDQ; goto extract_sfmt_andq;
+ case 52 : /* fall through */
+ case 53 : /* fall through */
+ case 54 : /* fall through */
+ case 55 : itype = CRISV32F_INSN_ORQ; goto extract_sfmt_andq;
+ case 56 : /* fall through */
+ case 57 : itype = CRISV32F_INSN_BTSTQ; goto extract_sfmt_btstq;
+ case 58 : /* fall through */
+ case 59 : itype = CRISV32F_INSN_ASRQ; goto extract_sfmt_asrq;
+ case 60 : /* fall through */
+ case 61 : itype = CRISV32F_INSN_LSLQ; goto extract_sfmt_asrq;
+ case 62 : /* fall through */
+ case 63 : itype = CRISV32F_INSN_LSRQ; goto extract_sfmt_asrq;
+ case 64 : itype = CRISV32F_INSN_ADDU_B_R; goto extract_sfmt_add_d_r;
+ case 65 : itype = CRISV32F_INSN_ADDU_W_R; goto extract_sfmt_add_d_r;
+ case 66 : itype = CRISV32F_INSN_ADDS_B_R; goto extract_sfmt_add_d_r;
+ case 67 : itype = CRISV32F_INSN_ADDS_W_R; goto extract_sfmt_add_d_r;
+ case 68 : itype = CRISV32F_INSN_MOVU_B_R; goto extract_sfmt_movs_b_r;
+ case 69 : itype = CRISV32F_INSN_MOVU_W_R; goto extract_sfmt_movs_b_r;
+ case 70 : itype = CRISV32F_INSN_MOVS_B_R; goto extract_sfmt_movs_b_r;
+ case 71 : itype = CRISV32F_INSN_MOVS_W_R; goto extract_sfmt_movs_b_r;
+ case 72 : itype = CRISV32F_INSN_SUBU_B_R; goto extract_sfmt_add_d_r;
+ case 73 : itype = CRISV32F_INSN_SUBU_W_R; goto extract_sfmt_add_d_r;
+ case 74 : itype = CRISV32F_INSN_SUBS_B_R; goto extract_sfmt_add_d_r;
+ case 75 : itype = CRISV32F_INSN_SUBS_W_R; goto extract_sfmt_add_d_r;
+ case 76 : itype = CRISV32F_INSN_LSLR_B_R; goto extract_sfmt_lsrr_b_r;
+ case 77 : itype = CRISV32F_INSN_LSLR_W_R; goto extract_sfmt_lsrr_b_r;
+ case 78 : itype = CRISV32F_INSN_LSLR_D_R; goto extract_sfmt_lsrr_d_r;
+ case 79 : itype = CRISV32F_INSN_BTST; goto extract_sfmt_btst;
+ case 80 : itype = CRISV32F_INSN_ADDI_B_R; goto extract_sfmt_addi_b_r;
+ case 81 : itype = CRISV32F_INSN_ADDI_W_R; goto extract_sfmt_addi_b_r;
+ case 82 : itype = CRISV32F_INSN_ADDI_D_R; goto extract_sfmt_addi_b_r;
+ case 83 : itype = CRISV32F_INSN_SCC; goto extract_sfmt_scc;
+ case 84 : itype = CRISV32F_INSN_ADDI_ACR_B_R; goto extract_sfmt_addi_acr_b_r;
+ case 85 : itype = CRISV32F_INSN_ADDI_ACR_W_R; goto extract_sfmt_addi_acr_b_r;
+ case 86 : itype = CRISV32F_INSN_ADDI_ACR_D_R; goto extract_sfmt_addi_acr_b_r;
+ case 87 : itype = CRISV32F_INSN_ADDC_R; goto extract_sfmt_add_d_r;
+ case 88 : itype = CRISV32F_INSN_NEG_B_R; goto extract_sfmt_neg_b_r;
+ case 89 : itype = CRISV32F_INSN_NEG_W_R; goto extract_sfmt_neg_b_r;
+ case 90 : itype = CRISV32F_INSN_NEG_D_R; goto extract_sfmt_neg_d_r;
+ case 91 : itype = CRISV32F_INSN_SETF; goto extract_sfmt_setf;
+ case 92 : itype = CRISV32F_INSN_BOUND_R_B_R; goto extract_sfmt_dstep;
+ case 93 : itype = CRISV32F_INSN_BOUND_R_W_R; goto extract_sfmt_dstep;
+ case 94 : itype = CRISV32F_INSN_BOUND_R_D_R; goto extract_sfmt_dstep;
+ case 95 : itype = CRISV32F_INSN_CLEARF; goto extract_sfmt_setf;
+ case 96 : itype = CRISV32F_INSN_ADD_B_R; goto extract_sfmt_add_b_r;
+ case 97 : itype = CRISV32F_INSN_ADD_W_R; goto extract_sfmt_add_b_r;
+ case 98 : itype = CRISV32F_INSN_ADD_D_R; goto extract_sfmt_add_d_r;
+ case 99 : itype = CRISV32F_INSN_MOVE_R_SPRV32; goto extract_sfmt_move_r_sprv32;
+ case 100 : itype = CRISV32F_INSN_MOVE_B_R; goto extract_sfmt_move_b_r;
+ case 101 : itype = CRISV32F_INSN_MOVE_W_R; goto extract_sfmt_move_b_r;
+ case 102 : itype = CRISV32F_INSN_MOVE_D_R; goto extract_sfmt_move_d_r;
+ case 103 : itype = CRISV32F_INSN_MOVE_SPR_RV32; goto extract_sfmt_move_spr_rv32;
+ case 104 : itype = CRISV32F_INSN_SUB_B_R; goto extract_sfmt_add_b_r;
+ case 105 : itype = CRISV32F_INSN_SUB_W_R; goto extract_sfmt_add_b_r;
+ case 106 : itype = CRISV32F_INSN_SUB_D_R; goto extract_sfmt_add_d_r;
+ case 107 : itype = CRISV32F_INSN_ABS; goto extract_sfmt_movs_b_r;
+ case 108 : itype = CRISV32F_INSN_CMP_R_B_R; goto extract_sfmt_cmp_r_b_r;
+ case 109 : itype = CRISV32F_INSN_CMP_R_W_R; goto extract_sfmt_cmp_r_b_r;
+ case 110 : itype = CRISV32F_INSN_CMP_R_D_R; goto extract_sfmt_cmp_r_b_r;
+ case 111 : itype = CRISV32F_INSN_DSTEP; goto extract_sfmt_dstep;
+ case 112 : itype = CRISV32F_INSN_AND_B_R; goto extract_sfmt_and_b_r;
+ case 113 : itype = CRISV32F_INSN_AND_W_R; goto extract_sfmt_and_w_r;
+ case 114 : itype = CRISV32F_INSN_AND_D_R; goto extract_sfmt_and_d_r;
+ case 115 : itype = CRISV32F_INSN_LZ; goto extract_sfmt_movs_b_r;
+ case 116 : itype = CRISV32F_INSN_ORR_B_R; goto extract_sfmt_and_b_r;
+ case 117 : itype = CRISV32F_INSN_ORR_W_R; goto extract_sfmt_and_w_r;
+ case 118 : itype = CRISV32F_INSN_ORR_D_R; goto extract_sfmt_and_d_r;
+ case 119 : itype = CRISV32F_INSN_SWAP; goto extract_sfmt_swap;
+ case 120 : itype = CRISV32F_INSN_ASRR_B_R; goto extract_sfmt_asrr_b_r;
+ case 121 : itype = CRISV32F_INSN_ASRR_W_R; goto extract_sfmt_asrr_b_r;
+ case 122 : itype = CRISV32F_INSN_ASRR_D_R; goto extract_sfmt_and_d_r;
+ case 123 : itype = CRISV32F_INSN_XOR; goto extract_sfmt_dstep;
+ case 124 : itype = CRISV32F_INSN_LSRR_B_R; goto extract_sfmt_lsrr_b_r;
+ case 125 : itype = CRISV32F_INSN_LSRR_W_R; goto extract_sfmt_lsrr_b_r;
+ case 126 : itype = CRISV32F_INSN_LSRR_D_R; goto extract_sfmt_lsrr_d_r;
+ case 127 : itype = CRISV32F_INSN_MCP; goto extract_sfmt_mcp;
+ case 128 : itype = CRISV32F_INSN_ADDU_M_B_M; goto extract_sfmt_adds_m_b_m;
+ case 129 : itype = CRISV32F_INSN_ADDU_M_W_M; goto extract_sfmt_adds_m_w_m;
+ case 130 : itype = CRISV32F_INSN_ADDS_M_B_M; goto extract_sfmt_adds_m_b_m;
+ case 131 : itype = CRISV32F_INSN_ADDS_M_W_M; goto extract_sfmt_adds_m_w_m;
+ case 132 : itype = CRISV32F_INSN_MOVU_M_B_M; goto extract_sfmt_movs_m_b_m;
+ case 133 : itype = CRISV32F_INSN_MOVU_M_W_M; goto extract_sfmt_movs_m_w_m;
+ case 134 : itype = CRISV32F_INSN_MOVS_M_B_M; goto extract_sfmt_movs_m_b_m;
+ case 135 : itype = CRISV32F_INSN_MOVS_M_W_M; goto extract_sfmt_movs_m_w_m;
+ case 136 : itype = CRISV32F_INSN_SUBU_M_B_M; goto extract_sfmt_adds_m_b_m;
+ case 137 : itype = CRISV32F_INSN_SUBU_M_W_M; goto extract_sfmt_adds_m_w_m;
+ case 138 : itype = CRISV32F_INSN_SUBS_M_B_M; goto extract_sfmt_adds_m_b_m;
+ case 139 : itype = CRISV32F_INSN_SUBS_M_W_M; goto extract_sfmt_adds_m_w_m;
+ case 140 : itype = CRISV32F_INSN_CMPU_M_B_M; goto extract_sfmt_cmp_m_b_m;
+ case 141 : itype = CRISV32F_INSN_CMPU_M_W_M; goto extract_sfmt_cmp_m_w_m;
+ case 142 : itype = CRISV32F_INSN_CMPS_M_B_M; goto extract_sfmt_cmp_m_b_m;
+ case 143 : itype = CRISV32F_INSN_CMPS_M_W_M; goto extract_sfmt_cmp_m_w_m;
+ case 144 : itype = CRISV32F_INSN_MULU_B; goto extract_sfmt_muls_b;
+ case 145 : itype = CRISV32F_INSN_MULU_W; goto extract_sfmt_muls_b;
+ case 146 : itype = CRISV32F_INSN_MULU_D; goto extract_sfmt_muls_b;
+ case 147 :
+ {
+ unsigned int val = (((insn >> 12) & (15 << 0)));
+ switch (val)
+ {
+ case 2 : itype = CRISV32F_INSN_RFE; goto extract_sfmt_rfe;
+ case 3 : itype = CRISV32F_INSN_SFE; goto extract_sfmt_sfe;
+ case 4 : itype = CRISV32F_INSN_RFG; goto extract_sfmt_rfg;
+ case 5 : itype = CRISV32F_INSN_RFN; goto extract_sfmt_rfn;
+ case 14 : itype = CRISV32F_INSN_BREAK; goto extract_sfmt_break;
+ case 15 : itype = CRISV32F_INSN_HALT; goto extract_sfmt_halt;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 148 : itype = CRISV32F_INSN_ADDO_M_B_M; goto extract_sfmt_addo_m_b_m;
+ case 149 : itype = CRISV32F_INSN_ADDO_M_W_M; goto extract_sfmt_addo_m_w_m;
+ case 150 : itype = CRISV32F_INSN_ADDO_M_D_M; goto extract_sfmt_addo_m_d_m;
+ case 151 : itype = CRISV32F_INSN_LAPCQ; goto extract_sfmt_lapcq;
+ case 154 : itype = CRISV32F_INSN_ADDC_M; goto extract_sfmt_addc_m;
+ case 155 : itype = CRISV32F_INSN_JAS_R; goto extract_sfmt_jas_r;
+ case 159 : itype = CRISV32F_INSN_JUMP_P; goto extract_sfmt_jump_p;
+ case 160 : itype = CRISV32F_INSN_ADD_M_B_M; goto extract_sfmt_add_m_b_m;
+ case 161 : itype = CRISV32F_INSN_ADD_M_W_M; goto extract_sfmt_add_m_w_m;
+ case 162 : itype = CRISV32F_INSN_ADD_M_D_M; goto extract_sfmt_add_m_d_m;
+ case 163 : itype = CRISV32F_INSN_MOVE_M_SPRV32; goto extract_sfmt_move_m_sprv32;
+ case 164 : itype = CRISV32F_INSN_MOVE_M_B_M; goto extract_sfmt_move_m_b_m;
+ case 165 : itype = CRISV32F_INSN_MOVE_M_W_M; goto extract_sfmt_move_m_w_m;
+ case 166 : itype = CRISV32F_INSN_MOVE_M_D_M; goto extract_sfmt_move_m_d_m;
+ case 167 : /* fall through */
+ case 231 : itype = CRISV32F_INSN_MOVE_SPR_MV32; goto extract_sfmt_move_spr_mv32;
+ case 168 : itype = CRISV32F_INSN_SUB_M_B_M; goto extract_sfmt_add_m_b_m;
+ case 169 : itype = CRISV32F_INSN_SUB_M_W_M; goto extract_sfmt_add_m_w_m;
+ case 170 : itype = CRISV32F_INSN_SUB_M_D_M; goto extract_sfmt_add_m_d_m;
+ case 171 :
+ {
+ unsigned int val = (((insn >> 12) & (1 << 0)));
+ switch (val)
+ {
+ case 0 : itype = CRISV32F_INSN_FIDXD; goto extract_sfmt_fidxi;
+ case 1 : itype = CRISV32F_INSN_FTAGD; goto extract_sfmt_fidxi;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 172 : itype = CRISV32F_INSN_CMP_M_B_M; goto extract_sfmt_cmp_m_b_m;
+ case 173 : itype = CRISV32F_INSN_CMP_M_W_M; goto extract_sfmt_cmp_m_w_m;
+ case 174 : itype = CRISV32F_INSN_CMP_M_D_M; goto extract_sfmt_cmp_m_d_m;
+ case 176 : itype = CRISV32F_INSN_AND_M_B_M; goto extract_sfmt_and_m_b_m;
+ case 177 : itype = CRISV32F_INSN_AND_M_W_M; goto extract_sfmt_and_m_w_m;
+ case 178 : itype = CRISV32F_INSN_AND_M_D_M; goto extract_sfmt_and_m_d_m;
+ case 179 : itype = CRISV32F_INSN_JASC_R; goto extract_sfmt_jasc_r;
+ case 180 : itype = CRISV32F_INSN_OR_M_B_M; goto extract_sfmt_and_m_b_m;
+ case 181 : itype = CRISV32F_INSN_OR_M_W_M; goto extract_sfmt_and_m_w_m;
+ case 182 : itype = CRISV32F_INSN_OR_M_D_M; goto extract_sfmt_and_m_d_m;
+ case 183 : itype = CRISV32F_INSN_MOVE_R_SS; goto extract_sfmt_move_r_ss;
+ case 184 : /* fall through */
+ case 248 : itype = CRISV32F_INSN_TEST_M_B_M; goto extract_sfmt_test_m_b_m;
+ case 185 : /* fall through */
+ case 249 : itype = CRISV32F_INSN_TEST_M_W_M; goto extract_sfmt_test_m_w_m;
+ case 186 : /* fall through */
+ case 250 : itype = CRISV32F_INSN_TEST_M_D_M; goto extract_sfmt_test_m_d_m;
+ case 187 : /* fall through */
+ case 251 : itype = CRISV32F_INSN_MOVEM_M_R_V32; goto extract_sfmt_movem_m_r_v32;
+ case 188 : /* fall through */
+ case 252 : itype = CRISV32F_INSN_MOVE_R_M_B_M; goto extract_sfmt_move_r_m_b_m;
+ case 189 : /* fall through */
+ case 253 : itype = CRISV32F_INSN_MOVE_R_M_W_M; goto extract_sfmt_move_r_m_w_m;
+ case 190 : /* fall through */
+ case 254 : itype = CRISV32F_INSN_MOVE_R_M_D_M; goto extract_sfmt_move_r_m_d_m;
+ case 191 : /* fall through */
+ case 255 : itype = CRISV32F_INSN_MOVEM_R_M_V32; goto extract_sfmt_movem_r_m_v32;
+ case 192 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_ADDU_M_B_M; goto extract_sfmt_adds_m_b_m;
+ case 15 : itype = CRISV32F_INSN_ADDUCBR; goto extract_sfmt_addscbr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 193 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_ADDU_M_W_M; goto extract_sfmt_adds_m_w_m;
+ case 15 : itype = CRISV32F_INSN_ADDUCWR; goto extract_sfmt_addscwr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 194 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_ADDS_M_B_M; goto extract_sfmt_adds_m_b_m;
+ case 15 : itype = CRISV32F_INSN_ADDSCBR; goto extract_sfmt_addscbr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 195 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_ADDS_M_W_M; goto extract_sfmt_adds_m_w_m;
+ case 15 : itype = CRISV32F_INSN_ADDSCWR; goto extract_sfmt_addscwr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 196 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_MOVU_M_B_M; goto extract_sfmt_movs_m_b_m;
+ case 15 : itype = CRISV32F_INSN_MOVUCBR; goto extract_sfmt_movucbr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 197 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_MOVU_M_W_M; goto extract_sfmt_movs_m_w_m;
+ case 15 : itype = CRISV32F_INSN_MOVUCWR; goto extract_sfmt_movucwr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 198 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_MOVS_M_B_M; goto extract_sfmt_movs_m_b_m;
+ case 15 : itype = CRISV32F_INSN_MOVSCBR; goto extract_sfmt_movscbr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 199 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_MOVS_M_W_M; goto extract_sfmt_movs_m_w_m;
+ case 15 : itype = CRISV32F_INSN_MOVSCWR; goto extract_sfmt_movscwr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 200 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_SUBU_M_B_M; goto extract_sfmt_adds_m_b_m;
+ case 15 : itype = CRISV32F_INSN_SUBUCBR; goto extract_sfmt_addscbr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 201 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_SUBU_M_W_M; goto extract_sfmt_adds_m_w_m;
+ case 15 : itype = CRISV32F_INSN_SUBUCWR; goto extract_sfmt_addscwr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 202 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_SUBS_M_B_M; goto extract_sfmt_adds_m_b_m;
+ case 15 : itype = CRISV32F_INSN_SUBSCBR; goto extract_sfmt_addscbr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 203 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_SUBS_M_W_M; goto extract_sfmt_adds_m_w_m;
+ case 15 : itype = CRISV32F_INSN_SUBSCWR; goto extract_sfmt_addscwr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 204 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_CMPU_M_B_M; goto extract_sfmt_cmp_m_b_m;
+ case 15 : itype = CRISV32F_INSN_CMPUCBR; goto extract_sfmt_cmpucbr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 205 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_CMPU_M_W_M; goto extract_sfmt_cmp_m_w_m;
+ case 15 : itype = CRISV32F_INSN_CMPUCWR; goto extract_sfmt_cmpucwr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 206 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_CMPS_M_B_M; goto extract_sfmt_cmp_m_b_m;
+ case 15 : itype = CRISV32F_INSN_CMPSCBR; goto extract_sfmt_cmpcbr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 207 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_CMPS_M_W_M; goto extract_sfmt_cmp_m_w_m;
+ case 15 : itype = CRISV32F_INSN_CMPSCWR; goto extract_sfmt_cmpcwr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 208 : itype = CRISV32F_INSN_MULS_B; goto extract_sfmt_muls_b;
+ case 209 : itype = CRISV32F_INSN_MULS_W; goto extract_sfmt_muls_b;
+ case 210 : itype = CRISV32F_INSN_MULS_D; goto extract_sfmt_muls_b;
+ case 211 :
+ {
+ unsigned int val = (((insn >> 12) & (1 << 0)));
+ switch (val)
+ {
+ case 0 : itype = CRISV32F_INSN_FIDXI; goto extract_sfmt_fidxi;
+ case 1 : itype = CRISV32F_INSN_FTAGI; goto extract_sfmt_fidxi;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 212 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_ADDO_M_B_M; goto extract_sfmt_addo_m_b_m;
+ case 15 : itype = CRISV32F_INSN_ADDO_CB; goto extract_sfmt_addo_cb;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 213 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_ADDO_M_W_M; goto extract_sfmt_addo_m_w_m;
+ case 15 : itype = CRISV32F_INSN_ADDO_CW; goto extract_sfmt_addo_cw;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 214 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_ADDO_M_D_M; goto extract_sfmt_addo_m_d_m;
+ case 15 : itype = CRISV32F_INSN_ADDO_CD; goto extract_sfmt_addo_cd;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 215 : itype = CRISV32F_INSN_LAPC_D; goto extract_sfmt_lapc_d;
+ case 218 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_ADDC_M; goto extract_sfmt_addc_m;
+ case 15 : itype = CRISV32F_INSN_ADDC_C; goto extract_sfmt_addcdr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 219 : itype = CRISV32F_INSN_JAS_C; goto extract_sfmt_jas_c;
+ case 220 : itype = CRISV32F_INSN_BOUND_CB; goto extract_sfmt_bound_cb;
+ case 221 : itype = CRISV32F_INSN_BOUND_CW; goto extract_sfmt_bound_cw;
+ case 222 : itype = CRISV32F_INSN_BOUND_CD; goto extract_sfmt_bound_cd;
+ case 223 :
+ {
+ unsigned int val = (((insn >> 12) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 15 : itype = CRISV32F_INSN_BCC_W; goto extract_sfmt_bcc_w;
+ case 14 : itype = CRISV32F_INSN_BA_W; goto extract_sfmt_ba_w;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 224 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_ADD_M_B_M; goto extract_sfmt_add_m_b_m;
+ case 15 : itype = CRISV32F_INSN_ADDCBR; goto extract_sfmt_addcbr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 225 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_ADD_M_W_M; goto extract_sfmt_add_m_w_m;
+ case 15 : itype = CRISV32F_INSN_ADDCWR; goto extract_sfmt_addcwr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 226 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_ADD_M_D_M; goto extract_sfmt_add_m_d_m;
+ case 15 : itype = CRISV32F_INSN_ADDCDR; goto extract_sfmt_addcdr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 227 :
+ {
+ unsigned int val = (((insn >> 12) & (15 << 0)));
+ switch (val)
+ {
+ case 0 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_MOVE_M_SPRV32; goto extract_sfmt_move_m_sprv32;
+ case 15 : itype = CRISV32F_INSN_MOVE_C_SPRV32_P0; goto extract_sfmt_move_c_sprv32_p0;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 1 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_MOVE_M_SPRV32; goto extract_sfmt_move_m_sprv32;
+ case 15 : itype = CRISV32F_INSN_MOVE_C_SPRV32_P1; goto extract_sfmt_move_c_sprv32_p0;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 2 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_MOVE_M_SPRV32; goto extract_sfmt_move_m_sprv32;
+ case 15 : itype = CRISV32F_INSN_MOVE_C_SPRV32_P2; goto extract_sfmt_move_c_sprv32_p0;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 3 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_MOVE_M_SPRV32; goto extract_sfmt_move_m_sprv32;
+ case 15 : itype = CRISV32F_INSN_MOVE_C_SPRV32_P3; goto extract_sfmt_move_c_sprv32_p0;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 4 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_MOVE_M_SPRV32; goto extract_sfmt_move_m_sprv32;
+ case 15 : itype = CRISV32F_INSN_MOVE_C_SPRV32_P4; goto extract_sfmt_move_c_sprv32_p0;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 5 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_MOVE_M_SPRV32; goto extract_sfmt_move_m_sprv32;
+ case 15 : itype = CRISV32F_INSN_MOVE_C_SPRV32_P5; goto extract_sfmt_move_c_sprv32_p0;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 6 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_MOVE_M_SPRV32; goto extract_sfmt_move_m_sprv32;
+ case 15 : itype = CRISV32F_INSN_MOVE_C_SPRV32_P6; goto extract_sfmt_move_c_sprv32_p0;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 7 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_MOVE_M_SPRV32; goto extract_sfmt_move_m_sprv32;
+ case 15 : itype = CRISV32F_INSN_MOVE_C_SPRV32_P7; goto extract_sfmt_move_c_sprv32_p0;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 8 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_MOVE_M_SPRV32; goto extract_sfmt_move_m_sprv32;
+ case 15 : itype = CRISV32F_INSN_MOVE_C_SPRV32_P8; goto extract_sfmt_move_c_sprv32_p0;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 9 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_MOVE_M_SPRV32; goto extract_sfmt_move_m_sprv32;
+ case 15 : itype = CRISV32F_INSN_MOVE_C_SPRV32_P9; goto extract_sfmt_move_c_sprv32_p0;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 10 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_MOVE_M_SPRV32; goto extract_sfmt_move_m_sprv32;
+ case 15 : itype = CRISV32F_INSN_MOVE_C_SPRV32_P10; goto extract_sfmt_move_c_sprv32_p0;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 11 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_MOVE_M_SPRV32; goto extract_sfmt_move_m_sprv32;
+ case 15 : itype = CRISV32F_INSN_MOVE_C_SPRV32_P11; goto extract_sfmt_move_c_sprv32_p0;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 12 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_MOVE_M_SPRV32; goto extract_sfmt_move_m_sprv32;
+ case 15 : itype = CRISV32F_INSN_MOVE_C_SPRV32_P12; goto extract_sfmt_move_c_sprv32_p0;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 13 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_MOVE_M_SPRV32; goto extract_sfmt_move_m_sprv32;
+ case 15 : itype = CRISV32F_INSN_MOVE_C_SPRV32_P13; goto extract_sfmt_move_c_sprv32_p0;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 14 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_MOVE_M_SPRV32; goto extract_sfmt_move_m_sprv32;
+ case 15 : itype = CRISV32F_INSN_MOVE_C_SPRV32_P14; goto extract_sfmt_move_c_sprv32_p0;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 15 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_MOVE_M_SPRV32; goto extract_sfmt_move_m_sprv32;
+ case 15 : itype = CRISV32F_INSN_MOVE_C_SPRV32_P15; goto extract_sfmt_move_c_sprv32_p0;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 228 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_MOVE_M_B_M; goto extract_sfmt_move_m_b_m;
+ case 15 : itype = CRISV32F_INSN_MOVECBR; goto extract_sfmt_movecbr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 229 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_MOVE_M_W_M; goto extract_sfmt_move_m_w_m;
+ case 15 : itype = CRISV32F_INSN_MOVECWR; goto extract_sfmt_movecwr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 230 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_MOVE_M_D_M; goto extract_sfmt_move_m_d_m;
+ case 15 : itype = CRISV32F_INSN_MOVECDR; goto extract_sfmt_movecdr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 232 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_SUB_M_B_M; goto extract_sfmt_add_m_b_m;
+ case 15 : itype = CRISV32F_INSN_SUBCBR; goto extract_sfmt_addcbr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 233 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_SUB_M_W_M; goto extract_sfmt_add_m_w_m;
+ case 15 : itype = CRISV32F_INSN_SUBCWR; goto extract_sfmt_addcwr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 234 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_SUB_M_D_M; goto extract_sfmt_add_m_d_m;
+ case 15 : itype = CRISV32F_INSN_SUBCDR; goto extract_sfmt_addcdr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 235 : itype = CRISV32F_INSN_BAS_C; goto extract_sfmt_bas_c;
+ case 236 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_CMP_M_B_M; goto extract_sfmt_cmp_m_b_m;
+ case 15 : itype = CRISV32F_INSN_CMPCBR; goto extract_sfmt_cmpcbr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 237 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_CMP_M_W_M; goto extract_sfmt_cmp_m_w_m;
+ case 15 : itype = CRISV32F_INSN_CMPCWR; goto extract_sfmt_cmpcwr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 238 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_CMP_M_D_M; goto extract_sfmt_cmp_m_d_m;
+ case 15 : itype = CRISV32F_INSN_CMPCDR; goto extract_sfmt_cmpcdr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 239 : itype = CRISV32F_INSN_BASC_C; goto extract_sfmt_bas_c;
+ case 240 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_AND_M_B_M; goto extract_sfmt_and_m_b_m;
+ case 15 : itype = CRISV32F_INSN_ANDCBR; goto extract_sfmt_andcbr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 241 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_AND_M_W_M; goto extract_sfmt_and_m_w_m;
+ case 15 : itype = CRISV32F_INSN_ANDCWR; goto extract_sfmt_andcwr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 242 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_AND_M_D_M; goto extract_sfmt_and_m_d_m;
+ case 15 : itype = CRISV32F_INSN_ANDCDR; goto extract_sfmt_andcdr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 243 : itype = CRISV32F_INSN_JASC_C; goto extract_sfmt_jas_c;
+ case 244 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_OR_M_B_M; goto extract_sfmt_and_m_b_m;
+ case 15 : itype = CRISV32F_INSN_ORCBR; goto extract_sfmt_andcbr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 245 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_OR_M_W_M; goto extract_sfmt_and_m_w_m;
+ case 15 : itype = CRISV32F_INSN_ORCWR; goto extract_sfmt_andcwr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 246 :
+ {
+ unsigned int val = (((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : /* fall through */
+ case 1 : /* fall through */
+ case 2 : /* fall through */
+ case 3 : /* fall through */
+ case 4 : /* fall through */
+ case 5 : /* fall through */
+ case 6 : /* fall through */
+ case 7 : /* fall through */
+ case 8 : /* fall through */
+ case 9 : /* fall through */
+ case 10 : /* fall through */
+ case 11 : /* fall through */
+ case 12 : /* fall through */
+ case 13 : /* fall through */
+ case 14 : itype = CRISV32F_INSN_OR_M_D_M; goto extract_sfmt_and_m_d_m;
+ case 15 : itype = CRISV32F_INSN_ORCDR; goto extract_sfmt_andcdr;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 247 : itype = CRISV32F_INSN_MOVE_SS_R; goto extract_sfmt_move_ss_r;
+ default : itype = CRISV32F_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ }
+
+ /* The instruction has been decoded, now extract the fields. */
+
+ extract_sfmt_empty:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_b_r:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_b_r", "f_operand1 0x%x", 'x', f_operand1, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_d_r:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_d_r", "f_operand1 0x%x", 'x', f_operand1, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_moveq:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_moveq.f
+ UINT f_operand2;
+ INT f_s6;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_s6 = EXTRACT_LSB0_INT (insn, 16, 5, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_s6) = f_s6;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_moveq", "f_s6 0x%x", 'x', f_s6, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movs_b_r:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movs_b_r", "f_operand1 0x%x", 'x', f_operand1, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movecbr:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ INT f_indir_pc__byte;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__byte) = f_indir_pc__byte;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movecbr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__byte 0x%x", 'x', f_indir_pc__byte, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movecwr:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ INT f_indir_pc__word;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__word) = f_indir_pc__word;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movecwr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__word 0x%x", 'x', f_indir_pc__word, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movecdr:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ INT f_indir_pc__dword;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUSI (current_cpu, pc + 2);
+ f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_indir_pc__dword) = f_indir_pc__dword;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movecdr", "f_indir_pc__dword 0x%x", 'x', f_indir_pc__dword, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movscbr:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ UINT f_operand2;
+ INT f_indir_pc__byte;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_indir_pc__byte) = f_indir_pc__byte;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movscbr", "f_indir_pc__byte 0x%x", 'x', f_indir_pc__byte, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movscwr:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ UINT f_operand2;
+ INT f_indir_pc__word;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_indir_pc__word) = f_indir_pc__word;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movscwr", "f_indir_pc__word 0x%x", 'x', f_indir_pc__word, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movucbr:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ UINT f_operand2;
+ INT f_indir_pc__byte;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_indir_pc__byte) = f_indir_pc__byte;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movucbr", "f_indir_pc__byte 0x%x", 'x', f_indir_pc__byte, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movucwr:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ UINT f_operand2;
+ INT f_indir_pc__word;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_indir_pc__word) = f_indir_pc__word;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movucwr", "f_indir_pc__word 0x%x", 'x', f_indir_pc__word, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addq:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addq.f
+ UINT f_operand2;
+ UINT f_u6;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_u6 = EXTRACT_LSB0_UINT (insn, 16, 5, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addq", "f_operand2 0x%x", 'x', f_operand2, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_r_b_r:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_r_b_r", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_m_b_m:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_m_b_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_m_w_m:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_m_w_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmp_m_d_m:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp_m_d_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmpcbr:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ INT f_indir_pc__byte;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__byte) = f_indir_pc__byte;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpcbr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__byte 0x%x", 'x', f_indir_pc__byte, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmpcwr:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ INT f_indir_pc__word;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__word) = f_indir_pc__word;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpcwr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__word 0x%x", 'x', f_indir_pc__word, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmpcdr:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ INT f_indir_pc__dword;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUSI (current_cpu, pc + 2);
+ f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__dword) = f_indir_pc__dword;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpcdr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__dword 0x%x", 'x', f_indir_pc__dword, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmpq:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_andq.f
+ UINT f_operand2;
+ INT f_s6;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_s6 = EXTRACT_LSB0_INT (insn, 16, 5, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_s6) = f_s6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpq", "f_operand2 0x%x", 'x', f_operand2, "f_s6 0x%x", 'x', f_s6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmpucbr:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ INT f_indir_pc__byte;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__byte) = f_indir_pc__byte;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpucbr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__byte 0x%x", 'x', f_indir_pc__byte, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmpucwr:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ INT f_indir_pc__word;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__word) = f_indir_pc__word;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpucwr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__word 0x%x", 'x', f_indir_pc__word, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_m_b_m:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_operand2) = f_operand2;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_m_b_m", "f_operand1 0x%x", 'x', f_operand1, "f_operand2 0x%x", 'x', f_operand2, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ FLD (out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd) = ((ANDIF (GET_H_INSN_PREFIXED_P (), (! (FLD (f_memmode))))) ? (FLD (f_operand1)) : (FLD (f_operand2)));
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_m_w_m:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_operand2) = f_operand2;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_m_w_m", "f_operand1 0x%x", 'x', f_operand1, "f_operand2 0x%x", 'x', f_operand2, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ FLD (out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd) = ((ANDIF (GET_H_INSN_PREFIXED_P (), (! (FLD (f_memmode))))) ? (FLD (f_operand1)) : (FLD (f_operand2)));
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_m_d_m:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_operand2) = f_operand2;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_m_d_m", "f_operand1 0x%x", 'x', f_operand1, "f_operand2 0x%x", 'x', f_operand2, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ FLD (out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd) = ((ANDIF (GET_H_INSN_PREFIXED_P (), (! (FLD (f_memmode))))) ? (FLD (f_operand1)) : (FLD (f_operand2)));
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movs_m_b_m:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movs_m_b_m", "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rd) = f_operand2;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movs_m_w_m:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movs_m_w_m", "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rd) = f_operand2;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_r_sprv32:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_r_sprv32", "f_operand1 0x%x", 'x', f_operand1, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Pd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_spr_rv32:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_spr_rv32", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Ps) = f_operand2;
+ FLD (out_h_gr_SI_index_of__DFLT_Rs) = FLD (f_operand1);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_m_sprv32:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_operand2) = f_operand2;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_m_sprv32", "f_operand1 0x%x", 'x', f_operand1, "f_operand2 0x%x", 'x', f_operand2, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Pd) = f_operand2;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_c_sprv32_p0:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ INT f_indir_pc__dword;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUSI (current_cpu, pc + 2);
+ f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_indir_pc__dword) = f_indir_pc__dword;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_c_sprv32_p0", "f_indir_pc__dword 0x%x", 'x', f_indir_pc__dword, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_Pd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_spr_mv32:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_spr_mv32", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Ps) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_ss_r:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_ss_r", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_r_ss:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_r_ss", "f_operand1 0x%x", 'x', f_operand1, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movem_r_m_v32:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_movem_r_m_v32.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movem_r_m_v32", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (in_h_gr_SI_0) = 0;
+ FLD (in_h_gr_SI_1) = 1;
+ FLD (in_h_gr_SI_10) = 10;
+ FLD (in_h_gr_SI_11) = 11;
+ FLD (in_h_gr_SI_12) = 12;
+ FLD (in_h_gr_SI_13) = 13;
+ FLD (in_h_gr_SI_14) = 14;
+ FLD (in_h_gr_SI_15) = 15;
+ FLD (in_h_gr_SI_2) = 2;
+ FLD (in_h_gr_SI_3) = 3;
+ FLD (in_h_gr_SI_4) = 4;
+ FLD (in_h_gr_SI_5) = 5;
+ FLD (in_h_gr_SI_6) = 6;
+ FLD (in_h_gr_SI_7) = 7;
+ FLD (in_h_gr_SI_8) = 8;
+ FLD (in_h_gr_SI_9) = 9;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movem_m_r_v32:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_movem_m_r_v32.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movem_m_r_v32", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ FLD (out_h_gr_SI_0) = 0;
+ FLD (out_h_gr_SI_1) = 1;
+ FLD (out_h_gr_SI_10) = 10;
+ FLD (out_h_gr_SI_11) = 11;
+ FLD (out_h_gr_SI_12) = 12;
+ FLD (out_h_gr_SI_13) = 13;
+ FLD (out_h_gr_SI_14) = 14;
+ FLD (out_h_gr_SI_15) = 15;
+ FLD (out_h_gr_SI_2) = 2;
+ FLD (out_h_gr_SI_3) = 3;
+ FLD (out_h_gr_SI_4) = 4;
+ FLD (out_h_gr_SI_5) = 5;
+ FLD (out_h_gr_SI_6) = 6;
+ FLD (out_h_gr_SI_7) = 7;
+ FLD (out_h_gr_SI_8) = 8;
+ FLD (out_h_gr_SI_9) = 9;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_b_r:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_b_r", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_d_r:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_d_r", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_m_b_m:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_m_b_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ FLD (out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd) = ((ANDIF (GET_H_INSN_PREFIXED_P (), (! (FLD (f_memmode))))) ? (FLD (f_operand1)) : (FLD (f_operand2)));
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_m_w_m:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_m_w_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ FLD (out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd) = ((ANDIF (GET_H_INSN_PREFIXED_P (), (! (FLD (f_memmode))))) ? (FLD (f_operand1)) : (FLD (f_operand2)));
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_m_d_m:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_m_d_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ FLD (out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd) = ((ANDIF (GET_H_INSN_PREFIXED_P (), (! (FLD (f_memmode))))) ? (FLD (f_operand1)) : (FLD (f_operand2)));
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addcbr:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ INT f_indir_pc__byte;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__byte) = f_indir_pc__byte;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addcbr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__byte 0x%x", 'x', f_indir_pc__byte, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addcwr:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ INT f_indir_pc__word;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__word) = f_indir_pc__word;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addcwr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__word 0x%x", 'x', f_indir_pc__word, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addcdr:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ INT f_indir_pc__dword;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUSI (current_cpu, pc + 2);
+ f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__dword) = f_indir_pc__dword;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addcdr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__dword 0x%x", 'x', f_indir_pc__dword, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adds_m_b_m:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adds_m_b_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ FLD (out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd) = ((ANDIF (GET_H_INSN_PREFIXED_P (), (! (FLD (f_memmode))))) ? (FLD (f_operand1)) : (FLD (f_operand2)));
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_adds_m_w_m:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_adds_m_w_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ FLD (out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd) = ((ANDIF (GET_H_INSN_PREFIXED_P (), (! (FLD (f_memmode))))) ? (FLD (f_operand1)) : (FLD (f_operand2)));
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addscbr:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ INT f_indir_pc__byte;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__byte) = f_indir_pc__byte;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addscbr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__byte 0x%x", 'x', f_indir_pc__byte, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addscwr:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ INT f_indir_pc__word;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__word) = f_indir_pc__word;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addscwr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__word 0x%x", 'x', f_indir_pc__word, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addc_m:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addc_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lapc_d:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_lapc_d.f
+ SI f_indir_pc__dword_pcrel;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUSI (current_cpu, pc + 2);
+ f_indir_pc__dword_pcrel = ((pc) + ((0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0))));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (i_const32_pcrel) = f_indir_pc__dword_pcrel;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lapc_d", "f_operand2 0x%x", 'x', f_operand2, "const32_pcrel 0x%x", 'x', f_indir_pc__dword_pcrel, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lapcq:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_lapcq.f
+ UINT f_operand2;
+ SI f_qo;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_qo = ((pc) + (((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (1))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (i_qo) = f_qo;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lapcq", "f_operand2 0x%x", 'x', f_operand2, "qo 0x%x", 'x', f_qo, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addi_b_r:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi_b_r", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_neg_b_r:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_neg_b_r", "f_operand1 0x%x", 'x', f_operand1, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_neg_d_r:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_neg_d_r", "f_operand1 0x%x", 'x', f_operand1, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_test_m_b_m:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_test_m_b_m", "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_test_m_w_m:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_test_m_w_m", "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_test_m_d_m:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_test_m_d_m", "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_r_m_b_m:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_r_m_b_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_r_m_w_m:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_r_m_w_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_move_r_m_d_m:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_move_r_m_d_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_muls_b:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_muls_b", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rd) = f_operand2;
+ FLD (out_h_sr_SI_7) = 7;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mcp:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mcp", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Ps) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_h_gr_SI_index_of__DFLT_Rs) = FLD (f_operand1);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_dstep:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_dstep", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_b_r:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_b_r", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_w_r:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_w_r", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_d_r:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_d_r", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_m_b_m:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_m_b_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ FLD (out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd) = ((ANDIF (GET_H_INSN_PREFIXED_P (), (! (FLD (f_memmode))))) ? (FLD (f_operand1)) : (FLD (f_operand2)));
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_m_w_m:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_m_w_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ FLD (out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd) = ((ANDIF (GET_H_INSN_PREFIXED_P (), (! (FLD (f_memmode))))) ? (FLD (f_operand1)) : (FLD (f_operand2)));
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_m_d_m:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_m_d_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ FLD (out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd) = ((ANDIF (GET_H_INSN_PREFIXED_P (), (! (FLD (f_memmode))))) ? (FLD (f_operand1)) : (FLD (f_operand2)));
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_andcbr:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ INT f_indir_pc__byte;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__byte) = f_indir_pc__byte;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andcbr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__byte 0x%x", 'x', f_indir_pc__byte, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_andcwr:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ INT f_indir_pc__word;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__word) = f_indir_pc__word;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andcwr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__word 0x%x", 'x', f_indir_pc__word, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_andcdr:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ INT f_indir_pc__dword;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUSI (current_cpu, pc + 2);
+ f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__dword) = f_indir_pc__dword;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andcdr", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__dword 0x%x", 'x', f_indir_pc__dword, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_andq:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_andq.f
+ UINT f_operand2;
+ INT f_s6;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_s6 = EXTRACT_LSB0_INT (insn, 16, 5, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_s6) = f_s6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andq", "f_operand2 0x%x", 'x', f_operand2, "f_s6 0x%x", 'x', f_s6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_swap:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_swap", "f_operand1 0x%x", 'x', f_operand1, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asrr_b_r:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asrr_b_r", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_asrq:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_asrq.f
+ UINT f_operand2;
+ UINT f_u5;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_u5 = EXTRACT_LSB0_UINT (insn, 16, 4, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_u5) = f_u5;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_asrq", "f_operand2 0x%x", 'x', f_operand2, "f_u5 0x%x", 'x', f_u5, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lsrr_b_r:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lsrr_b_r", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lsrr_d_r:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lsrr_d_r", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_h_gr_SI_index_of__DFLT_Rd) = FLD (f_operand2);
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_btst:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_btstq:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_asrq.f
+ UINT f_operand2;
+ UINT f_u5;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_u5 = EXTRACT_LSB0_UINT (insn, 16, 4, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_u5) = f_u5;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btstq", "f_operand2 0x%x", 'x', f_operand2, "f_u5 0x%x", 'x', f_u5, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_setf:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_setf.f
+ UINT f_operand2;
+ UINT f_operand1;
+ UINT f_dstsrc;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+ f_dstsrc = ((((f_operand1) | (((f_operand2) << (4))))) & (255));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstsrc) = f_dstsrc;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setf", "f_dstsrc 0x%x", 'x', f_dstsrc, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_rfe:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+#define FLD(f) abuf->fields.sfmt_rfe.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rfe", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_h_sr_SI_13) = 13;
+ FLD (out_h_sr_SI_13) = 13;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sfe:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+#define FLD(f) abuf->fields.sfmt_rfe.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sfe", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_h_sr_SI_13) = 13;
+ FLD (out_h_sr_SI_13) = 13;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_rfg:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rfg", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_rfn:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+#define FLD(f) abuf->fields.sfmt_rfe.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rfn", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_h_sr_SI_13) = 13;
+ FLD (out_h_sr_SI_13) = 13;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_halt:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_halt", (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bcc_b:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bcc_b.f
+ UINT f_operand2;
+ UINT f_disp9_lo;
+ INT f_disp9_hi;
+ INT f_disp9;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7);
+ f_disp9_hi = EXTRACT_LSB0_INT (insn, 16, 0, 1);
+{
+ SI tmp_abslo;
+ SI tmp_absval;
+ tmp_abslo = ((f_disp9_lo) << (1));
+ tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));
+ f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_V32 ()) ? (0) : (2))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (i_o_pcrel) = f_disp9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcc_b", "f_operand2 0x%x", 'x', f_operand2, "o_pcrel 0x%x", 'x', f_disp9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ba_b:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bcc_b.f
+ UINT f_disp9_lo;
+ INT f_disp9_hi;
+ INT f_disp9;
+
+ f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7);
+ f_disp9_hi = EXTRACT_LSB0_INT (insn, 16, 0, 1);
+{
+ SI tmp_abslo;
+ SI tmp_absval;
+ tmp_abslo = ((f_disp9_lo) << (1));
+ tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));
+ f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_V32 ()) ? (0) : (2))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_o_pcrel) = f_disp9;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ba_b", "o_pcrel 0x%x", 'x', f_disp9, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bcc_w:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bcc_w.f
+ SI f_indir_pc__word_pcrel;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_V32 ()) ? (0) : (4))))));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (i_o_word_pcrel) = f_indir_pc__word_pcrel;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcc_w", "f_operand2 0x%x", 'x', f_operand2, "o_word_pcrel 0x%x", 'x', f_indir_pc__word_pcrel, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ba_w:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bcc_w.f
+ SI f_indir_pc__word_pcrel;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_V32 ()) ? (0) : (4))))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_o_word_pcrel) = f_indir_pc__word_pcrel;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ba_w", "o_word_pcrel 0x%x", 'x', f_indir_pc__word_pcrel, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jas_r:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jas_r", "f_operand1 0x%x", 'x', f_operand1, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Pd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jas_c:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ INT f_indir_pc__dword;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUSI (current_cpu, pc + 2);
+ f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_indir_pc__dword) = f_indir_pc__dword;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jas_c", "f_indir_pc__dword 0x%x", 'x', f_indir_pc__dword, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_Pd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jump_p:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ UINT f_operand2;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jump_p", "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Ps) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bas_c:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bas_c.f
+ SI f_indir_pc__dword_pcrel;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUSI (current_cpu, pc + 2);
+ f_indir_pc__dword_pcrel = ((pc) + ((0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0))));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (i_const32_pcrel) = f_indir_pc__dword_pcrel;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bas_c", "f_operand2 0x%x", 'x', f_operand2, "const32_pcrel 0x%x", 'x', f_indir_pc__dword_pcrel, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_Pd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jasc_r:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ FLD (f_operand2) = f_operand2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jasc_r", "f_operand1 0x%x", 'x', f_operand1, "f_operand2 0x%x", 'x', f_operand2, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Pd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_break:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_break.f
+ UINT f_u4;
+
+ f_u4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_u4) = f_u4;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_break", "f_u4 0x%x", 'x', f_u4, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bound_cb:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ INT f_indir_pc__byte;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__byte) = f_indir_pc__byte;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bound_cb", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__byte 0x%x", 'x', f_indir_pc__byte, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bound_cw:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ INT f_indir_pc__word;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__word) = f_indir_pc__word;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bound_cw", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__word 0x%x", 'x', f_indir_pc__word, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bound_cd:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ INT f_indir_pc__dword;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUSI (current_cpu, pc + 2);
+ f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__dword) = f_indir_pc__dword;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bound_cd", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__dword 0x%x", 'x', f_indir_pc__dword, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (out_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_scc:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_scc", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addoq:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addoq.f
+ UINT f_operand2;
+ INT f_s8;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_s8 = EXTRACT_LSB0_INT (insn, 16, 7, 8);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_s8) = f_s8;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addoq", "f_operand2 0x%x", 'x', f_operand2, "f_s8 0x%x", 'x', f_s8, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addo_m_b_m:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addo_m_b_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addo_m_w_m:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addo_m_w_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addo_m_d_m:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ UINT f_operand2;
+ UINT f_memmode;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ FLD (f_memmode) = f_memmode;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addo_m_d_m", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, "f_memmode 0x%x", 'x', f_memmode, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ FLD (out_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addo_cb:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ INT f_indir_pc__byte;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__byte) = f_indir_pc__byte;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addo_cb", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__byte 0x%x", 'x', f_indir_pc__byte, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addo_cw:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ INT f_indir_pc__word;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUHI (current_cpu, pc + 2);
+ f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 16, 15, 16) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__word) = f_indir_pc__word;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addo_cw", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__word 0x%x", 'x', f_indir_pc__word, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addo_cd:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ INT f_indir_pc__dword;
+ UINT f_operand2;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+
+ word_1 = GETIMEMUSI (current_cpu, pc + 2);
+ f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0));
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_indir_pc__dword) = f_indir_pc__dword;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addo_cd", "f_operand2 0x%x", 'x', f_operand2, "f_indir_pc__dword 0x%x", 'x', f_indir_pc__dword, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addi_acr_b_r:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ UINT f_operand2;
+ UINT f_operand1;
+
+ f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4);
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand2) = f_operand2;
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi_acr_b_r", "f_operand2 0x%x", 'x', f_operand2, "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rd) = f_operand2;
+ FLD (in_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fidxi:
+ {
+ const IDESC *idesc = &crisv32f_insn_data[itype];
+ CGEN_INSN_INT insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ UINT f_operand1;
+
+ f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_operand1) = f_operand1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fidxi", "f_operand1 0x%x", 'x', f_operand1, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_Rs) = f_operand1;
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+}
--- /dev/null
+/* Decode header for crisv32f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2004 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef CRISV32F_DECODE_H
+#define CRISV32F_DECODE_H
+
+extern const IDESC *crisv32f_decode (SIM_CPU *, IADDR,
+ CGEN_INSN_INT,
+ ARGBUF *);
+extern void crisv32f_init_idesc_table (SIM_CPU *);
+extern void crisv32f_sem_init_idesc_table (SIM_CPU *);
+extern void crisv32f_semf_init_idesc_table (SIM_CPU *);
+
+/* Enum declaration for instructions in cpu family crisv32f. */
+typedef enum crisv32f_insn_type {
+ CRISV32F_INSN_X_INVALID, CRISV32F_INSN_X_AFTER, CRISV32F_INSN_X_BEFORE, CRISV32F_INSN_X_CTI_CHAIN
+ , CRISV32F_INSN_X_CHAIN, CRISV32F_INSN_X_BEGIN, CRISV32F_INSN_MOVE_B_R, CRISV32F_INSN_MOVE_W_R
+ , CRISV32F_INSN_MOVE_D_R, CRISV32F_INSN_MOVEQ, CRISV32F_INSN_MOVS_B_R, CRISV32F_INSN_MOVS_W_R
+ , CRISV32F_INSN_MOVU_B_R, CRISV32F_INSN_MOVU_W_R, CRISV32F_INSN_MOVECBR, CRISV32F_INSN_MOVECWR
+ , CRISV32F_INSN_MOVECDR, CRISV32F_INSN_MOVSCBR, CRISV32F_INSN_MOVSCWR, CRISV32F_INSN_MOVUCBR
+ , CRISV32F_INSN_MOVUCWR, CRISV32F_INSN_ADDQ, CRISV32F_INSN_SUBQ, CRISV32F_INSN_CMP_R_B_R
+ , CRISV32F_INSN_CMP_R_W_R, CRISV32F_INSN_CMP_R_D_R, CRISV32F_INSN_CMP_M_B_M, CRISV32F_INSN_CMP_M_W_M
+ , CRISV32F_INSN_CMP_M_D_M, CRISV32F_INSN_CMPCBR, CRISV32F_INSN_CMPCWR, CRISV32F_INSN_CMPCDR
+ , CRISV32F_INSN_CMPQ, CRISV32F_INSN_CMPS_M_B_M, CRISV32F_INSN_CMPS_M_W_M, CRISV32F_INSN_CMPSCBR
+ , CRISV32F_INSN_CMPSCWR, CRISV32F_INSN_CMPU_M_B_M, CRISV32F_INSN_CMPU_M_W_M, CRISV32F_INSN_CMPUCBR
+ , CRISV32F_INSN_CMPUCWR, CRISV32F_INSN_MOVE_M_B_M, CRISV32F_INSN_MOVE_M_W_M, CRISV32F_INSN_MOVE_M_D_M
+ , CRISV32F_INSN_MOVS_M_B_M, CRISV32F_INSN_MOVS_M_W_M, CRISV32F_INSN_MOVU_M_B_M, CRISV32F_INSN_MOVU_M_W_M
+ , CRISV32F_INSN_MOVE_R_SPRV32, CRISV32F_INSN_MOVE_SPR_RV32, CRISV32F_INSN_MOVE_M_SPRV32, CRISV32F_INSN_MOVE_C_SPRV32_P0
+ , CRISV32F_INSN_MOVE_C_SPRV32_P1, CRISV32F_INSN_MOVE_C_SPRV32_P2, CRISV32F_INSN_MOVE_C_SPRV32_P3, CRISV32F_INSN_MOVE_C_SPRV32_P4
+ , CRISV32F_INSN_MOVE_C_SPRV32_P5, CRISV32F_INSN_MOVE_C_SPRV32_P6, CRISV32F_INSN_MOVE_C_SPRV32_P7, CRISV32F_INSN_MOVE_C_SPRV32_P8
+ , CRISV32F_INSN_MOVE_C_SPRV32_P9, CRISV32F_INSN_MOVE_C_SPRV32_P10, CRISV32F_INSN_MOVE_C_SPRV32_P11, CRISV32F_INSN_MOVE_C_SPRV32_P12
+ , CRISV32F_INSN_MOVE_C_SPRV32_P13, CRISV32F_INSN_MOVE_C_SPRV32_P14, CRISV32F_INSN_MOVE_C_SPRV32_P15, CRISV32F_INSN_MOVE_SPR_MV32
+ , CRISV32F_INSN_MOVE_SS_R, CRISV32F_INSN_MOVE_R_SS, CRISV32F_INSN_MOVEM_R_M_V32, CRISV32F_INSN_MOVEM_M_R_V32
+ , CRISV32F_INSN_ADD_B_R, CRISV32F_INSN_ADD_W_R, CRISV32F_INSN_ADD_D_R, CRISV32F_INSN_ADD_M_B_M
+ , CRISV32F_INSN_ADD_M_W_M, CRISV32F_INSN_ADD_M_D_M, CRISV32F_INSN_ADDCBR, CRISV32F_INSN_ADDCWR
+ , CRISV32F_INSN_ADDCDR, CRISV32F_INSN_ADDS_B_R, CRISV32F_INSN_ADDS_W_R, CRISV32F_INSN_ADDS_M_B_M
+ , CRISV32F_INSN_ADDS_M_W_M, CRISV32F_INSN_ADDSCBR, CRISV32F_INSN_ADDSCWR, CRISV32F_INSN_ADDU_B_R
+ , CRISV32F_INSN_ADDU_W_R, CRISV32F_INSN_ADDU_M_B_M, CRISV32F_INSN_ADDU_M_W_M, CRISV32F_INSN_ADDUCBR
+ , CRISV32F_INSN_ADDUCWR, CRISV32F_INSN_SUB_B_R, CRISV32F_INSN_SUB_W_R, CRISV32F_INSN_SUB_D_R
+ , CRISV32F_INSN_SUB_M_B_M, CRISV32F_INSN_SUB_M_W_M, CRISV32F_INSN_SUB_M_D_M, CRISV32F_INSN_SUBCBR
+ , CRISV32F_INSN_SUBCWR, CRISV32F_INSN_SUBCDR, CRISV32F_INSN_SUBS_B_R, CRISV32F_INSN_SUBS_W_R
+ , CRISV32F_INSN_SUBS_M_B_M, CRISV32F_INSN_SUBS_M_W_M, CRISV32F_INSN_SUBSCBR, CRISV32F_INSN_SUBSCWR
+ , CRISV32F_INSN_SUBU_B_R, CRISV32F_INSN_SUBU_W_R, CRISV32F_INSN_SUBU_M_B_M, CRISV32F_INSN_SUBU_M_W_M
+ , CRISV32F_INSN_SUBUCBR, CRISV32F_INSN_SUBUCWR, CRISV32F_INSN_ADDC_R, CRISV32F_INSN_ADDC_M
+ , CRISV32F_INSN_ADDC_C, CRISV32F_INSN_LAPC_D, CRISV32F_INSN_LAPCQ, CRISV32F_INSN_ADDI_B_R
+ , CRISV32F_INSN_ADDI_W_R, CRISV32F_INSN_ADDI_D_R, CRISV32F_INSN_NEG_B_R, CRISV32F_INSN_NEG_W_R
+ , CRISV32F_INSN_NEG_D_R, CRISV32F_INSN_TEST_M_B_M, CRISV32F_INSN_TEST_M_W_M, CRISV32F_INSN_TEST_M_D_M
+ , CRISV32F_INSN_MOVE_R_M_B_M, CRISV32F_INSN_MOVE_R_M_W_M, CRISV32F_INSN_MOVE_R_M_D_M, CRISV32F_INSN_MULS_B
+ , CRISV32F_INSN_MULS_W, CRISV32F_INSN_MULS_D, CRISV32F_INSN_MULU_B, CRISV32F_INSN_MULU_W
+ , CRISV32F_INSN_MULU_D, CRISV32F_INSN_MCP, CRISV32F_INSN_DSTEP, CRISV32F_INSN_ABS
+ , CRISV32F_INSN_AND_B_R, CRISV32F_INSN_AND_W_R, CRISV32F_INSN_AND_D_R, CRISV32F_INSN_AND_M_B_M
+ , CRISV32F_INSN_AND_M_W_M, CRISV32F_INSN_AND_M_D_M, CRISV32F_INSN_ANDCBR, CRISV32F_INSN_ANDCWR
+ , CRISV32F_INSN_ANDCDR, CRISV32F_INSN_ANDQ, CRISV32F_INSN_ORR_B_R, CRISV32F_INSN_ORR_W_R
+ , CRISV32F_INSN_ORR_D_R, CRISV32F_INSN_OR_M_B_M, CRISV32F_INSN_OR_M_W_M, CRISV32F_INSN_OR_M_D_M
+ , CRISV32F_INSN_ORCBR, CRISV32F_INSN_ORCWR, CRISV32F_INSN_ORCDR, CRISV32F_INSN_ORQ
+ , CRISV32F_INSN_XOR, CRISV32F_INSN_SWAP, CRISV32F_INSN_ASRR_B_R, CRISV32F_INSN_ASRR_W_R
+ , CRISV32F_INSN_ASRR_D_R, CRISV32F_INSN_ASRQ, CRISV32F_INSN_LSRR_B_R, CRISV32F_INSN_LSRR_W_R
+ , CRISV32F_INSN_LSRR_D_R, CRISV32F_INSN_LSRQ, CRISV32F_INSN_LSLR_B_R, CRISV32F_INSN_LSLR_W_R
+ , CRISV32F_INSN_LSLR_D_R, CRISV32F_INSN_LSLQ, CRISV32F_INSN_BTST, CRISV32F_INSN_BTSTQ
+ , CRISV32F_INSN_SETF, CRISV32F_INSN_CLEARF, CRISV32F_INSN_RFE, CRISV32F_INSN_SFE
+ , CRISV32F_INSN_RFG, CRISV32F_INSN_RFN, CRISV32F_INSN_HALT, CRISV32F_INSN_BCC_B
+ , CRISV32F_INSN_BA_B, CRISV32F_INSN_BCC_W, CRISV32F_INSN_BA_W, CRISV32F_INSN_JAS_R
+ , CRISV32F_INSN_JAS_C, CRISV32F_INSN_JUMP_P, CRISV32F_INSN_BAS_C, CRISV32F_INSN_JASC_R
+ , CRISV32F_INSN_JASC_C, CRISV32F_INSN_BASC_C, CRISV32F_INSN_BREAK, CRISV32F_INSN_BOUND_R_B_R
+ , CRISV32F_INSN_BOUND_R_W_R, CRISV32F_INSN_BOUND_R_D_R, CRISV32F_INSN_BOUND_CB, CRISV32F_INSN_BOUND_CW
+ , CRISV32F_INSN_BOUND_CD, CRISV32F_INSN_SCC, CRISV32F_INSN_LZ, CRISV32F_INSN_ADDOQ
+ , CRISV32F_INSN_ADDO_M_B_M, CRISV32F_INSN_ADDO_M_W_M, CRISV32F_INSN_ADDO_M_D_M, CRISV32F_INSN_ADDO_CB
+ , CRISV32F_INSN_ADDO_CW, CRISV32F_INSN_ADDO_CD, CRISV32F_INSN_ADDI_ACR_B_R, CRISV32F_INSN_ADDI_ACR_W_R
+ , CRISV32F_INSN_ADDI_ACR_D_R, CRISV32F_INSN_FIDXI, CRISV32F_INSN_FTAGI, CRISV32F_INSN_FIDXD
+ , CRISV32F_INSN_FTAGD, CRISV32F_INSN__MAX
+} CRISV32F_INSN_TYPE;
+
+/* Enum declaration for semantic formats in cpu family crisv32f. */
+typedef enum crisv32f_sfmt_type {
+ CRISV32F_SFMT_EMPTY, CRISV32F_SFMT_MOVE_B_R, CRISV32F_SFMT_MOVE_D_R, CRISV32F_SFMT_MOVEQ
+ , CRISV32F_SFMT_MOVS_B_R, CRISV32F_SFMT_MOVECBR, CRISV32F_SFMT_MOVECWR, CRISV32F_SFMT_MOVECDR
+ , CRISV32F_SFMT_MOVSCBR, CRISV32F_SFMT_MOVSCWR, CRISV32F_SFMT_MOVUCBR, CRISV32F_SFMT_MOVUCWR
+ , CRISV32F_SFMT_ADDQ, CRISV32F_SFMT_CMP_R_B_R, CRISV32F_SFMT_CMP_M_B_M, CRISV32F_SFMT_CMP_M_W_M
+ , CRISV32F_SFMT_CMP_M_D_M, CRISV32F_SFMT_CMPCBR, CRISV32F_SFMT_CMPCWR, CRISV32F_SFMT_CMPCDR
+ , CRISV32F_SFMT_CMPQ, CRISV32F_SFMT_CMPUCBR, CRISV32F_SFMT_CMPUCWR, CRISV32F_SFMT_MOVE_M_B_M
+ , CRISV32F_SFMT_MOVE_M_W_M, CRISV32F_SFMT_MOVE_M_D_M, CRISV32F_SFMT_MOVS_M_B_M, CRISV32F_SFMT_MOVS_M_W_M
+ , CRISV32F_SFMT_MOVE_R_SPRV32, CRISV32F_SFMT_MOVE_SPR_RV32, CRISV32F_SFMT_MOVE_M_SPRV32, CRISV32F_SFMT_MOVE_C_SPRV32_P0
+ , CRISV32F_SFMT_MOVE_SPR_MV32, CRISV32F_SFMT_MOVE_SS_R, CRISV32F_SFMT_MOVE_R_SS, CRISV32F_SFMT_MOVEM_R_M_V32
+ , CRISV32F_SFMT_MOVEM_M_R_V32, CRISV32F_SFMT_ADD_B_R, CRISV32F_SFMT_ADD_D_R, CRISV32F_SFMT_ADD_M_B_M
+ , CRISV32F_SFMT_ADD_M_W_M, CRISV32F_SFMT_ADD_M_D_M, CRISV32F_SFMT_ADDCBR, CRISV32F_SFMT_ADDCWR
+ , CRISV32F_SFMT_ADDCDR, CRISV32F_SFMT_ADDS_M_B_M, CRISV32F_SFMT_ADDS_M_W_M, CRISV32F_SFMT_ADDSCBR
+ , CRISV32F_SFMT_ADDSCWR, CRISV32F_SFMT_ADDC_M, CRISV32F_SFMT_LAPC_D, CRISV32F_SFMT_LAPCQ
+ , CRISV32F_SFMT_ADDI_B_R, CRISV32F_SFMT_NEG_B_R, CRISV32F_SFMT_NEG_D_R, CRISV32F_SFMT_TEST_M_B_M
+ , CRISV32F_SFMT_TEST_M_W_M, CRISV32F_SFMT_TEST_M_D_M, CRISV32F_SFMT_MOVE_R_M_B_M, CRISV32F_SFMT_MOVE_R_M_W_M
+ , CRISV32F_SFMT_MOVE_R_M_D_M, CRISV32F_SFMT_MULS_B, CRISV32F_SFMT_MCP, CRISV32F_SFMT_DSTEP
+ , CRISV32F_SFMT_AND_B_R, CRISV32F_SFMT_AND_W_R, CRISV32F_SFMT_AND_D_R, CRISV32F_SFMT_AND_M_B_M
+ , CRISV32F_SFMT_AND_M_W_M, CRISV32F_SFMT_AND_M_D_M, CRISV32F_SFMT_ANDCBR, CRISV32F_SFMT_ANDCWR
+ , CRISV32F_SFMT_ANDCDR, CRISV32F_SFMT_ANDQ, CRISV32F_SFMT_SWAP, CRISV32F_SFMT_ASRR_B_R
+ , CRISV32F_SFMT_ASRQ, CRISV32F_SFMT_LSRR_B_R, CRISV32F_SFMT_LSRR_D_R, CRISV32F_SFMT_BTST
+ , CRISV32F_SFMT_BTSTQ, CRISV32F_SFMT_SETF, CRISV32F_SFMT_RFE, CRISV32F_SFMT_SFE
+ , CRISV32F_SFMT_RFG, CRISV32F_SFMT_RFN, CRISV32F_SFMT_HALT, CRISV32F_SFMT_BCC_B
+ , CRISV32F_SFMT_BA_B, CRISV32F_SFMT_BCC_W, CRISV32F_SFMT_BA_W, CRISV32F_SFMT_JAS_R
+ , CRISV32F_SFMT_JAS_C, CRISV32F_SFMT_JUMP_P, CRISV32F_SFMT_BAS_C, CRISV32F_SFMT_JASC_R
+ , CRISV32F_SFMT_BREAK, CRISV32F_SFMT_BOUND_CB, CRISV32F_SFMT_BOUND_CW, CRISV32F_SFMT_BOUND_CD
+ , CRISV32F_SFMT_SCC, CRISV32F_SFMT_ADDOQ, CRISV32F_SFMT_ADDO_M_B_M, CRISV32F_SFMT_ADDO_M_W_M
+ , CRISV32F_SFMT_ADDO_M_D_M, CRISV32F_SFMT_ADDO_CB, CRISV32F_SFMT_ADDO_CW, CRISV32F_SFMT_ADDO_CD
+ , CRISV32F_SFMT_ADDI_ACR_B_R, CRISV32F_SFMT_FIDXI
+} CRISV32F_SFMT_TYPE;
+
+/* Function unit handlers (user written). */
+
+extern int crisv32f_model_crisv32_u_exec_to_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Pd*/);
+extern int crisv32f_model_crisv32_u_exec_movem (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Rd*/);
+extern int crisv32f_model_crisv32_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rd*/, INT /*Rs*/, INT /*Rd*/);
+extern int crisv32f_model_crisv32_u_skip4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int crisv32f_model_crisv32_u_const32 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int crisv32f_model_crisv32_u_const16 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int crisv32f_model_crisv32_u_jump (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Pd*/);
+extern int crisv32f_model_crisv32_u_jump_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Ps*/);
+extern int crisv32f_model_crisv32_u_jump_r (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/);
+extern int crisv32f_model_crisv32_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int crisv32f_model_crisv32_u_multiply (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Rd*/);
+extern int crisv32f_model_crisv32_u_movem_mtor (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Rd*/);
+extern int crisv32f_model_crisv32_u_movem_rtom (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Rd*/);
+extern int crisv32f_model_crisv32_u_mem_w (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int crisv32f_model_crisv32_u_mem_r (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int crisv32f_model_crisv32_u_mem (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/);
+
+/* Profiling before/after handlers (user written) */
+
+extern void crisv32f_model_insn_before (SIM_CPU *, int /*first_p*/);
+extern void crisv32f_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
+
+#endif /* CRISV32F_DECODE_H */
--- /dev/null
+/* CRIS device support
+ Copyright (C) 2004, 2005 Free Software Foundation, Inc.
+ Contributed by Axis Communications.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+/* Based on the i960 devices.c (for the purposes, the same as all the
+ others). */
+
+#include "sim-main.h"
+
+#ifdef HAVE_DV_SOCKSER
+#include "dv-sockser.h"
+#endif
+
+/* Placeholder definition. */
+struct _device { char dummy; } cris_devices;
+
+void
+device_error (device *me ATTRIBUTE_UNUSED,
+ char *message ATTRIBUTE_UNUSED,
+ ...)
+{
+ abort ();
+}
+
+int
+device_io_read_buffer (device *me ATTRIBUTE_UNUSED,
+ void *source ATTRIBUTE_UNUSED,
+ int space ATTRIBUTE_UNUSED,
+ address_word addr ATTRIBUTE_UNUSED,
+ unsigned nr_bytes ATTRIBUTE_UNUSED,
+ SIM_DESC sd ATTRIBUTE_UNUSED,
+ SIM_CPU *cpu ATTRIBUTE_UNUSED,
+ sim_cia cia ATTRIBUTE_UNUSED)
+{
+ abort ();
+}
+
+int
+device_io_write_buffer (device *me ATTRIBUTE_UNUSED,
+ const void *source,
+ int space ATTRIBUTE_UNUSED,
+ address_word addr, unsigned nr_bytes,
+ SIM_DESC sd, SIM_CPU *cpu, sim_cia cia)
+{
+ static const unsigned char ok[] = { 4, 0, 0, 0x90};
+ static const unsigned char bad[] = { 8, 0, 0, 0x90};
+
+ if (addr == 0x90000004 && memcmp (source, ok, sizeof ok) == 0)
+ cris_break_13_handler (cpu, 1, 0, 0, 0, 0, 0, 0, cia);
+ else if (addr == 0x90000008
+ && memcmp (source, bad, sizeof bad) == 0)
+ cris_break_13_handler (cpu, 1, 34, 0, 0, 0, 0, 0, cia);
+
+ /* If it wasn't one of those, send an invalid-memory signal. */
+ sim_core_signal (sd, cpu, cia, 0, nr_bytes, addr,
+ write_transfer, sim_core_unmapped_signal);
+}
--- /dev/null
+# Simulator main loop for CRIS. -*- C -*-
+# Copyright (C) 2004, 2005 Free Software Foundation, Inc.
+# Contributed by Axis Communications.
+#
+# This file is part of the GNU simulators.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+# Based on the fr30 file.
+
+# Syntax:
+# /bin/sh mainloop.in command
+#
+# Command is one of:
+#
+# init
+# support
+# extract-{simple,scache,pbb}
+# {full,fast}-exec-{simple,scache,pbb}
+#
+# A target need only provide a "full" version of one of simple,scache,pbb.
+# If the target wants it can also provide a fast version of same.
+# It can't provide more than this, however for illustration's sake the CRIS
+# port provides examples of all.
+
+# ??? After a few more ports are done, revisit.
+# Will eventually need to machine generate a lot of this.
+
+case "x$1" in
+
+xsupport)
+
+cat <<EOF
+/* It seems we don't have a templated header file corresponding to
+ cris-tmpl.c, so we have to get out declarations the hackish way. */
+extern void @cpu@_specific_init (SIM_CPU *current_cpu);
+
+static INLINE const IDESC *
+extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, ARGBUF *abuf,
+ int fast_p)
+{
+ const IDESC *id = @cpu@_decode (current_cpu, pc, insn,
+#if CGEN_INT_INSN_P
+ insn,
+#endif
+ abuf);
+ @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
+ if (! fast_p)
+ {
+ int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
+ int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
+ @cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
+ }
+ return id;
+}
+
+static INLINE SEM_PC
+execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
+{
+ SEM_PC vpc;
+
+ if (fast_p)
+ {
+#if ! WITH_SEM_SWITCH_FAST
+#if WITH_SCACHE
+ vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
+#else
+ vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, &sc->argbuf);
+#endif
+#else
+ abort ();
+#endif /* WITH_SEM_SWITCH_FAST */
+ }
+ else
+ {
+#if ! WITH_SEM_SWITCH_FULL
+ ARGBUF *abuf = &sc->argbuf;
+ const IDESC *idesc = abuf->idesc;
+#if WITH_SCACHE_PBB
+ int virtual_p = CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_VIRTUAL);
+#else
+ int virtual_p = 0;
+#endif
+
+ if (! virtual_p)
+ {
+ /* FIXME: call x-before */
+ if (ARGBUF_PROFILE_P (abuf))
+ PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
+ /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */
+ if (PROFILE_MODEL_P (current_cpu)
+ && ARGBUF_PROFILE_P (abuf))
+ @cpu@_model_insn_before (current_cpu, 1 /*first_p*/);
+ TRACE_INSN_INIT (current_cpu, abuf, 1);
+ TRACE_INSN (current_cpu, idesc->idata,
+ (const struct argbuf *) abuf, abuf->addr);
+ }
+#if WITH_SCACHE
+ vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
+#else
+ vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf);
+#endif
+ if (! virtual_p)
+ {
+ /* FIXME: call x-after */
+ if (PROFILE_MODEL_P (current_cpu)
+ && ARGBUF_PROFILE_P (abuf))
+ {
+ int cycles;
+
+ cycles = (*idesc->timing->model_fn) (current_cpu, sc);
+ @cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
+ }
+ TRACE_INSN_FINI (current_cpu, abuf, 1);
+ }
+#else
+ abort ();
+#endif /* WITH_SEM_SWITCH_FULL */
+ }
+
+ return vpc;
+}
+
+EOF
+
+;;
+
+xinit)
+
+cat <<EOF
+ /* This seemed the only sane location to emit a call to a
+ model-specific init function. It may not work for all simulator
+ types. FIXME: Introduce a model-init hook. */
+
+ /* We use the same condition as the code that's expected to follow, so
+ GCC can consolidate the code with only one conditional. */
+ if (! CPU_IDESC_SEM_INIT_P (current_cpu))
+ @cpu@_specific_init (current_cpu);
+EOF
+
+;;
+
+xextract-simple | xextract-scache)
+
+# Inputs: current_cpu, vpc, sc, FAST_P
+# Outputs: sc filled in
+
+cat <<EOF
+{
+ CGEN_INSN_INT insn = GETIMEMUHI (current_cpu, vpc);
+ extract (current_cpu, vpc, insn, SEM_ARGBUF (sc), FAST_P);
+}
+EOF
+
+;;
+
+xextract-pbb)
+
+# Inputs: current_cpu, pc, sc, max_insns, FAST_P
+# Outputs: sc, pc
+# sc must be left pointing past the last created entry.
+# pc must be left pointing past the last created entry.
+# If the pbb is terminated by a cti insn, SET_CTI_VPC(sc) must be called
+# to record the vpc of the cti insn.
+# SET_INSN_COUNT(n) must be called to record number of real insns.
+
+cat <<EOF
+{
+ const IDESC *idesc;
+ int icount = 0;
+
+ /* Make sure the buffer doesn't overflow for profiled insns if
+ max_insns happens to not be a multiple of 3. */
+ if (!FAST_P)
+ max_insns -= 2 + 3;
+ else
+ /* There might be two real insns handled per loop. */
+ max_insns--;
+
+ while (max_insns > 0)
+ {
+ UHI insn = GETIMEMUHI (current_cpu, pc);
+ int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
+ int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
+ int befaft_p = profile_p || trace_p;
+
+ if (befaft_p)
+ {
+ @cpu@_emit_before (current_cpu, sc, pc, 1);
+ ++sc;
+ sc->argbuf.trace_p = trace_p;
+ sc->argbuf.profile_p = profile_p;
+ --max_insns;
+ }
+
+ idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
+ ++sc;
+ --max_insns;
+ ++icount;
+
+ if (befaft_p)
+ {
+ @cpu@_emit_after (current_cpu, sc, pc);
+ ++sc;
+ --max_insns;
+ }
+
+ pc += idesc->length;
+
+ if (IDESC_CTI_P (idesc))
+ {
+ SET_CTI_VPC (sc - 1);
+
+ /* Delay slot? Ignore for zero-instructions (bcc .+2) since
+ those are treated as exit insns to avoid runaway sessions
+ for invalid programs. */
+ if (insn != 0 && CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_DELAY_SLOT))
+ {
+ UHI insn;
+ trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
+ profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
+ befaft_p = profile_p || trace_p;
+
+ if (befaft_p)
+ {
+ @cpu@_emit_before (current_cpu, sc, pc, 1);
+ ++sc;
+ sc->argbuf.trace_p = trace_p;
+ sc->argbuf.profile_p = profile_p;
+ --max_insns;
+ }
+
+ insn = GETIMEMUHI (current_cpu, pc);
+ idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
+ ++sc;
+ --max_insns;
+ ++icount;
+
+ if (befaft_p)
+ {
+ @cpu@_emit_after (current_cpu, sc, pc);
+ ++sc;
+ --max_insns;
+ }
+ pc += idesc->length;
+ }
+ break;
+ }
+ }
+
+ Finish:
+ SET_INSN_COUNT (icount);
+}
+EOF
+
+;;
+
+xfull-exec-* | xfast-exec-*)
+
+# Inputs: current_cpu, sc, FAST_P
+# Outputs: vpc
+# vpc contains the address of the next insn to execute
+
+cat <<EOF
+{
+#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
+#define DEFINE_SWITCH
+#include "sem@cpu@-switch.c"
+#else
+ vpc = execute (current_cpu, vpc, FAST_P);
+#endif
+}
+EOF
+
+;;
+
+*)
+ echo "Invalid argument to mainloop.in: $1" >&2
+ exit 1
+ ;;
+
+esac
--- /dev/null
+/* Simulator model support for crisv10f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2004 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU crisv10f
+#define WANT_CPU_CRISV10F
+
+#include "sim-main.h"
+
+/* The profiling data is recorded here, but is accessed via the profiling
+ mechanism. After all, this is information for profiling. */
+
+#if WITH_PROFILE_MODEL_P
+
+/* Model handlers for each insn. */
+
+static int
+model_crisv10_nop (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_move_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_move_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_move_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_movepcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_moveq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_moveq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_moveq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_movs_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_movs_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_movu_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_movu_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_movecbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_movecwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_movecdr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_movscbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_movscwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_movucbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_movucwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_addq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_subq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_cmp_r_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_cmp_r_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_cmp_r_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_cmp_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_cmp_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_cmp_m_d_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_cmpcbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_cmpcwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_cmpcdr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_cmpq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_cmps_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_cmps_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_cmpscbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_cmpscwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_cmpu_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_cmpu_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_cmpucbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_cmpucwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_move_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_move_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_move_m_d_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_movs_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_movs_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_movu_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_movu_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_move_r_sprv10 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_move_spr_rv10 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_spr_rv10.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_ret_type (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_spr_rv10.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_move_m_sprv10 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_move_c_sprv10_p0 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p0.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_move_c_sprv10_p1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p0.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_move_c_sprv10_p4 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p4.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_move_c_sprv10_p5 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p4.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_move_c_sprv10_p8 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_move_c_sprv10_p9 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_move_c_sprv10_p10 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_move_c_sprv10_p11 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_move_c_sprv10_p12 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_move_c_sprv10_p13 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_move_c_sprv10_p7 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_move_c_sprv10_p14 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_move_c_sprv10_p15 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_move_spr_mv10 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_sbfs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_movem_r_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movem_r_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv10f_model_crisv10_u_movem (current_cpu, idesc, 0, referenced, in_Rd);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_movem_m_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movem_m_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv10f_model_crisv10_u_movem (current_cpu, idesc, 0, referenced, in_Rd);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_movem_m_pc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movem_m_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_add_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_add_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_add_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_add_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_add_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_add_m_d_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_addcbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_addcwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_addcdr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_addcpc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_stall (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 2, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_adds_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_adds_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_adds_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_adds_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_addscbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_addscwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_addspcpc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_stall (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 2, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_addu_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_addu_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_addu_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_addu_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_adducbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_adducwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_sub_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_sub_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_sub_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_sub_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_sub_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_sub_m_d_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_subcbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_subcwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_subcdr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_subs_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_subs_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_subs_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_subs_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_subscbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_subscwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_subu_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_subu_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_subu_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_subu_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_subucbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_subucwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_addi_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_addi_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_addi_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_neg_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_neg_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_neg_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_test_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_test_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_test_m_d_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_move_r_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_move_r_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_move_r_m_d_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_muls_b (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_multiply (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_muls_w (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_multiply (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_muls_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_multiply (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_mulu_b (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_multiply (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_mulu_w (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_multiply (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_mulu_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_multiply (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_mstep (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_dstep (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_and_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_and_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_and_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_and_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_and_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_and_m_d_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_andcbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_andcwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_andcdr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_andq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_orr_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_orr_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_orr_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_or_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_or_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_or_m_d_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_orcbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_orcwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_orcdr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_orq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_xor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_swap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_asrr_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_asrr_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_asrr_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_asrq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_asrq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_lsrr_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_lsrr_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_lsrr_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_lsrq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_asrq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_lslr_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_lslr_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_lslr_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_lslq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_asrq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_btst (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_btstq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_asrq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_setf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setf.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_clearf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setf.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_bcc_b (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bcc_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_ba_b (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bcc_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_bcc_w (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bcc_w.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_ba_w (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bcc_w.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_jump_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_jump_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_jump_c (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_break (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_break.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_bound_r_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_bound_r_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_bound_r_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_bound_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_bound_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_bound_m_d_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_bound_cb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_bound_cw (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_bound_cd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_scc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_lz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_addoq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addoq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_bdapqpc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addoq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_addo_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_addo_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_addo_m_d_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_addo_cb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_addo_cw (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_addo_cd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_dip_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_mem (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_dip_c (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 1, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_addi_acr_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_addi_acr_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_addi_acr_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_biap_pc_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addoq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_biap_pc_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addoq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv10_biap_pc_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addoq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv10f_model_crisv10_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+/* We assume UNIT_NONE == 0 because the tables don't always terminate
+ entries with it. */
+
+/* Model timing data for `crisv10'. */
+
+static const INSN_TIMING crisv10_timing[] = {
+ { CRISV10F_INSN_X_INVALID, 0, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_X_AFTER, 0, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_X_BEFORE, 0, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_X_CHAIN, 0, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_X_BEGIN, 0, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_NOP, model_crisv10_nop, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVE_B_R, model_crisv10_move_b_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVE_W_R, model_crisv10_move_w_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVE_D_R, model_crisv10_move_d_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVEPCR, model_crisv10_movepcr, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVEQ, model_crisv10_moveq, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVS_B_R, model_crisv10_movs_b_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVS_W_R, model_crisv10_movs_w_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVU_B_R, model_crisv10_movu_b_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVU_W_R, model_crisv10_movu_w_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVECBR, model_crisv10_movecbr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVECWR, model_crisv10_movecwr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVECDR, model_crisv10_movecdr, { { (int) UNIT_CRISV10_U_CONST32, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVSCBR, model_crisv10_movscbr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVSCWR, model_crisv10_movscwr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVUCBR, model_crisv10_movucbr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVUCWR, model_crisv10_movucwr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDQ, model_crisv10_addq, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_SUBQ, model_crisv10_subq, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_CMP_R_B_R, model_crisv10_cmp_r_b_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_CMP_R_W_R, model_crisv10_cmp_r_w_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_CMP_R_D_R, model_crisv10_cmp_r_d_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_CMP_M_B_M, model_crisv10_cmp_m_b_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_CMP_M_W_M, model_crisv10_cmp_m_w_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_CMP_M_D_M, model_crisv10_cmp_m_d_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_CMPCBR, model_crisv10_cmpcbr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_CMPCWR, model_crisv10_cmpcwr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_CMPCDR, model_crisv10_cmpcdr, { { (int) UNIT_CRISV10_U_CONST32, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_CMPQ, model_crisv10_cmpq, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_CMPS_M_B_M, model_crisv10_cmps_m_b_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_CMPS_M_W_M, model_crisv10_cmps_m_w_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_CMPSCBR, model_crisv10_cmpscbr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_CMPSCWR, model_crisv10_cmpscwr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_CMPU_M_B_M, model_crisv10_cmpu_m_b_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_CMPU_M_W_M, model_crisv10_cmpu_m_w_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_CMPUCBR, model_crisv10_cmpucbr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_CMPUCWR, model_crisv10_cmpucwr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVE_M_B_M, model_crisv10_move_m_b_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVE_M_W_M, model_crisv10_move_m_w_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVE_M_D_M, model_crisv10_move_m_d_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVS_M_B_M, model_crisv10_movs_m_b_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVS_M_W_M, model_crisv10_movs_m_w_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVU_M_B_M, model_crisv10_movu_m_b_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVU_M_W_M, model_crisv10_movu_m_w_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVE_R_SPRV10, model_crisv10_move_r_sprv10, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVE_SPR_RV10, model_crisv10_move_spr_rv10, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_RET_TYPE, model_crisv10_ret_type, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVE_M_SPRV10, model_crisv10_move_m_sprv10, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVE_C_SPRV10_P0, model_crisv10_move_c_sprv10_p0, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVE_C_SPRV10_P1, model_crisv10_move_c_sprv10_p1, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVE_C_SPRV10_P4, model_crisv10_move_c_sprv10_p4, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVE_C_SPRV10_P5, model_crisv10_move_c_sprv10_p5, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVE_C_SPRV10_P8, model_crisv10_move_c_sprv10_p8, { { (int) UNIT_CRISV10_U_CONST32, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVE_C_SPRV10_P9, model_crisv10_move_c_sprv10_p9, { { (int) UNIT_CRISV10_U_CONST32, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVE_C_SPRV10_P10, model_crisv10_move_c_sprv10_p10, { { (int) UNIT_CRISV10_U_CONST32, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVE_C_SPRV10_P11, model_crisv10_move_c_sprv10_p11, { { (int) UNIT_CRISV10_U_CONST32, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVE_C_SPRV10_P12, model_crisv10_move_c_sprv10_p12, { { (int) UNIT_CRISV10_U_CONST32, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVE_C_SPRV10_P13, model_crisv10_move_c_sprv10_p13, { { (int) UNIT_CRISV10_U_CONST32, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVE_C_SPRV10_P7, model_crisv10_move_c_sprv10_p7, { { (int) UNIT_CRISV10_U_CONST32, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVE_C_SPRV10_P14, model_crisv10_move_c_sprv10_p14, { { (int) UNIT_CRISV10_U_CONST32, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVE_C_SPRV10_P15, model_crisv10_move_c_sprv10_p15, { { (int) UNIT_CRISV10_U_CONST32, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVE_SPR_MV10, model_crisv10_move_spr_mv10, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_SBFS, model_crisv10_sbfs, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVEM_R_M, model_crisv10_movem_r_m, { { (int) UNIT_CRISV10_U_MOVEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVEM_M_R, model_crisv10_movem_m_r, { { (int) UNIT_CRISV10_U_MOVEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVEM_M_PC, model_crisv10_movem_m_pc, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADD_B_R, model_crisv10_add_b_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADD_W_R, model_crisv10_add_w_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADD_D_R, model_crisv10_add_d_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADD_M_B_M, model_crisv10_add_m_b_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADD_M_W_M, model_crisv10_add_m_w_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADD_M_D_M, model_crisv10_add_m_d_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDCBR, model_crisv10_addcbr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDCWR, model_crisv10_addcwr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDCDR, model_crisv10_addcdr, { { (int) UNIT_CRISV10_U_CONST32, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDCPC, model_crisv10_addcpc, { { (int) UNIT_CRISV10_U_CONST32, 1, 1 }, { (int) UNIT_CRISV10_U_STALL, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDS_B_R, model_crisv10_adds_b_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDS_W_R, model_crisv10_adds_w_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDS_M_B_M, model_crisv10_adds_m_b_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDS_M_W_M, model_crisv10_adds_m_w_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDSCBR, model_crisv10_addscbr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDSCWR, model_crisv10_addscwr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDSPCPC, model_crisv10_addspcpc, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_STALL, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDU_B_R, model_crisv10_addu_b_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDU_W_R, model_crisv10_addu_w_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDU_M_B_M, model_crisv10_addu_m_b_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDU_M_W_M, model_crisv10_addu_m_w_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDUCBR, model_crisv10_adducbr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDUCWR, model_crisv10_adducwr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_SUB_B_R, model_crisv10_sub_b_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_SUB_W_R, model_crisv10_sub_w_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_SUB_D_R, model_crisv10_sub_d_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_SUB_M_B_M, model_crisv10_sub_m_b_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_SUB_M_W_M, model_crisv10_sub_m_w_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_SUB_M_D_M, model_crisv10_sub_m_d_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_SUBCBR, model_crisv10_subcbr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_SUBCWR, model_crisv10_subcwr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_SUBCDR, model_crisv10_subcdr, { { (int) UNIT_CRISV10_U_CONST32, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_SUBS_B_R, model_crisv10_subs_b_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_SUBS_W_R, model_crisv10_subs_w_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_SUBS_M_B_M, model_crisv10_subs_m_b_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_SUBS_M_W_M, model_crisv10_subs_m_w_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_SUBSCBR, model_crisv10_subscbr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_SUBSCWR, model_crisv10_subscwr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_SUBU_B_R, model_crisv10_subu_b_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_SUBU_W_R, model_crisv10_subu_w_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_SUBU_M_B_M, model_crisv10_subu_m_b_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_SUBU_M_W_M, model_crisv10_subu_m_w_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_SUBUCBR, model_crisv10_subucbr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_SUBUCWR, model_crisv10_subucwr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDI_B_R, model_crisv10_addi_b_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDI_W_R, model_crisv10_addi_w_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDI_D_R, model_crisv10_addi_d_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_NEG_B_R, model_crisv10_neg_b_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_NEG_W_R, model_crisv10_neg_w_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_NEG_D_R, model_crisv10_neg_d_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_TEST_M_B_M, model_crisv10_test_m_b_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_TEST_M_W_M, model_crisv10_test_m_w_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_TEST_M_D_M, model_crisv10_test_m_d_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVE_R_M_B_M, model_crisv10_move_r_m_b_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVE_R_M_W_M, model_crisv10_move_r_m_w_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MOVE_R_M_D_M, model_crisv10_move_r_m_d_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MULS_B, model_crisv10_muls_b, { { (int) UNIT_CRISV10_U_MULTIPLY, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MULS_W, model_crisv10_muls_w, { { (int) UNIT_CRISV10_U_MULTIPLY, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MULS_D, model_crisv10_muls_d, { { (int) UNIT_CRISV10_U_MULTIPLY, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MULU_B, model_crisv10_mulu_b, { { (int) UNIT_CRISV10_U_MULTIPLY, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MULU_W, model_crisv10_mulu_w, { { (int) UNIT_CRISV10_U_MULTIPLY, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MULU_D, model_crisv10_mulu_d, { { (int) UNIT_CRISV10_U_MULTIPLY, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_MSTEP, model_crisv10_mstep, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_DSTEP, model_crisv10_dstep, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ABS, model_crisv10_abs, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_AND_B_R, model_crisv10_and_b_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_AND_W_R, model_crisv10_and_w_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_AND_D_R, model_crisv10_and_d_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_AND_M_B_M, model_crisv10_and_m_b_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_AND_M_W_M, model_crisv10_and_m_w_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_AND_M_D_M, model_crisv10_and_m_d_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ANDCBR, model_crisv10_andcbr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ANDCWR, model_crisv10_andcwr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ANDCDR, model_crisv10_andcdr, { { (int) UNIT_CRISV10_U_CONST32, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ANDQ, model_crisv10_andq, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ORR_B_R, model_crisv10_orr_b_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ORR_W_R, model_crisv10_orr_w_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ORR_D_R, model_crisv10_orr_d_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_OR_M_B_M, model_crisv10_or_m_b_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_OR_M_W_M, model_crisv10_or_m_w_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_OR_M_D_M, model_crisv10_or_m_d_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ORCBR, model_crisv10_orcbr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ORCWR, model_crisv10_orcwr, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ORCDR, model_crisv10_orcdr, { { (int) UNIT_CRISV10_U_CONST32, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ORQ, model_crisv10_orq, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_XOR, model_crisv10_xor, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_SWAP, model_crisv10_swap, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ASRR_B_R, model_crisv10_asrr_b_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ASRR_W_R, model_crisv10_asrr_w_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ASRR_D_R, model_crisv10_asrr_d_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ASRQ, model_crisv10_asrq, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_LSRR_B_R, model_crisv10_lsrr_b_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_LSRR_W_R, model_crisv10_lsrr_w_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_LSRR_D_R, model_crisv10_lsrr_d_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_LSRQ, model_crisv10_lsrq, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_LSLR_B_R, model_crisv10_lslr_b_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_LSLR_W_R, model_crisv10_lslr_w_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_LSLR_D_R, model_crisv10_lslr_d_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_LSLQ, model_crisv10_lslq, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_BTST, model_crisv10_btst, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_BTSTQ, model_crisv10_btstq, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_SETF, model_crisv10_setf, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_CLEARF, model_crisv10_clearf, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_BCC_B, model_crisv10_bcc_b, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_BA_B, model_crisv10_ba_b, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_BCC_W, model_crisv10_bcc_w, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_BA_W, model_crisv10_ba_w, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_JUMP_R, model_crisv10_jump_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_JUMP_M, model_crisv10_jump_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_JUMP_C, model_crisv10_jump_c, { { (int) UNIT_CRISV10_U_CONST32, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_BREAK, model_crisv10_break, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_BOUND_R_B_R, model_crisv10_bound_r_b_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_BOUND_R_W_R, model_crisv10_bound_r_w_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_BOUND_R_D_R, model_crisv10_bound_r_d_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_BOUND_M_B_M, model_crisv10_bound_m_b_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_BOUND_M_W_M, model_crisv10_bound_m_w_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_BOUND_M_D_M, model_crisv10_bound_m_d_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_BOUND_CB, model_crisv10_bound_cb, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_BOUND_CW, model_crisv10_bound_cw, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_BOUND_CD, model_crisv10_bound_cd, { { (int) UNIT_CRISV10_U_CONST32, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_SCC, model_crisv10_scc, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_LZ, model_crisv10_lz, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDOQ, model_crisv10_addoq, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_BDAPQPC, model_crisv10_bdapqpc, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDO_M_B_M, model_crisv10_addo_m_b_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDO_M_W_M, model_crisv10_addo_m_w_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDO_M_D_M, model_crisv10_addo_m_d_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDO_CB, model_crisv10_addo_cb, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDO_CW, model_crisv10_addo_cw, { { (int) UNIT_CRISV10_U_CONST16, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDO_CD, model_crisv10_addo_cd, { { (int) UNIT_CRISV10_U_CONST32, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_DIP_M, model_crisv10_dip_m, { { (int) UNIT_CRISV10_U_MEM, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_DIP_C, model_crisv10_dip_c, { { (int) UNIT_CRISV10_U_CONST32, 1, 1 }, { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDI_ACR_B_R, model_crisv10_addi_acr_b_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDI_ACR_W_R, model_crisv10_addi_acr_w_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_ADDI_ACR_D_R, model_crisv10_addi_acr_d_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_BIAP_PC_B_R, model_crisv10_biap_pc_b_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_BIAP_PC_W_R, model_crisv10_biap_pc_w_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+ { CRISV10F_INSN_BIAP_PC_D_R, model_crisv10_biap_pc_d_r, { { (int) UNIT_CRISV10_U_EXEC, 1, 1 } } },
+};
+
+#endif /* WITH_PROFILE_MODEL_P */
+
+static void
+crisv10_model_init (SIM_CPU *cpu)
+{
+ CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_CRISV10_DATA));
+}
+
+#if WITH_PROFILE_MODEL_P
+#define TIMING_DATA(td) td
+#else
+#define TIMING_DATA(td) 0
+#endif
+
+static const MODEL crisv10_models[] =
+{
+ { "crisv10", & crisv10_mach, MODEL_CRISV10, TIMING_DATA (& crisv10_timing[0]), crisv10_model_init },
+ { 0 }
+};
+
+/* The properties of this cpu's implementation. */
+
+static const MACH_IMP_PROPERTIES crisv10f_imp_properties =
+{
+ sizeof (SIM_CPU),
+#if WITH_SCACHE
+ sizeof (SCACHE)
+#else
+ 0
+#endif
+};
+
+
+static void
+crisv10f_prepare_run (SIM_CPU *cpu)
+{
+ if (CPU_IDESC (cpu) == NULL)
+ crisv10f_init_idesc_table (cpu);
+}
+
+static const CGEN_INSN *
+crisv10f_get_idata (SIM_CPU *cpu, int inum)
+{
+ return CPU_IDESC (cpu) [inum].idata;
+}
+
+static void
+crisv10_init_cpu (SIM_CPU *cpu)
+{
+ CPU_REG_FETCH (cpu) = crisv10f_fetch_register;
+ CPU_REG_STORE (cpu) = crisv10f_store_register;
+ CPU_PC_FETCH (cpu) = crisv10f_h_pc_get;
+ CPU_PC_STORE (cpu) = crisv10f_h_pc_set;
+ CPU_GET_IDATA (cpu) = crisv10f_get_idata;
+ CPU_MAX_INSNS (cpu) = CRISV10F_INSN__MAX;
+ CPU_INSN_NAME (cpu) = cgen_insn_name;
+ CPU_FULL_ENGINE_FN (cpu) = crisv10f_engine_run_full;
+#if WITH_FAST
+ CPU_FAST_ENGINE_FN (cpu) = crisv10f_engine_run_fast;
+#else
+ CPU_FAST_ENGINE_FN (cpu) = crisv10f_engine_run_full;
+#endif
+}
+
+const MACH crisv10_mach =
+{
+ "crisv10", "cris", MACH_CRISV10,
+ 32, 32, & crisv10_models[0], & crisv10f_imp_properties,
+ crisv10_init_cpu,
+ crisv10f_prepare_run
+};
+
--- /dev/null
+/* Simulator model support for crisv32f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2004 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU crisv32f
+#define WANT_CPU_CRISV32F
+
+#include "sim-main.h"
+
+/* The profiling data is recorded here, but is accessed via the profiling
+ mechanism. After all, this is information for profiling. */
+
+#if WITH_PROFILE_MODEL_P
+
+/* Model handlers for each insn. */
+
+static int
+model_crisv32_move_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_moveq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_moveq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_movs_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_movs_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_movu_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_movu_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_movecbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_movecwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_movecdr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_movscbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_movscwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_movucbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_movucwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_addq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_subq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_cmp_r_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_cmp_r_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_cmp_r_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_cmp_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_cmp_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_cmp_m_d_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_cmpcbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_cmpcwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_cmpcdr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_cmpq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_cmps_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_cmps_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_cmpscbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_cmpscwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_cmpu_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_cmpu_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_cmpucbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_cmpucwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_m_d_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_movs_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ out_Rd = FLD (out_Rd);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 7)) referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_movs_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ out_Rd = FLD (out_Rd);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 7)) referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_movu_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ out_Rd = FLD (out_Rd);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 7)) referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_movu_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ out_Rd = FLD (out_Rd);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 7)) referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_r_sprv32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT out_Pd = -1;
+ in_Rs = FLD (in_Rs);
+ out_Pd = FLD (out_Pd);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec_to_sr (current_cpu, idesc, 0, referenced, in_Rs, out_Pd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_spr_rv32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_m_sprv32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT out_Pd = -1;
+ in_Rs = FLD (in_Rs);
+ out_Pd = FLD (out_Pd);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec_to_sr (current_cpu, idesc, 2, referenced, in_Rs, out_Pd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_c_sprv32_p0 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT out_Pd = -1;
+ out_Pd = FLD (out_Pd);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec_to_sr (current_cpu, idesc, 1, referenced, in_Rs, out_Pd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_c_sprv32_p1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT out_Pd = -1;
+ out_Pd = FLD (out_Pd);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec_to_sr (current_cpu, idesc, 1, referenced, in_Rs, out_Pd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_c_sprv32_p2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT out_Pd = -1;
+ out_Pd = FLD (out_Pd);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec_to_sr (current_cpu, idesc, 1, referenced, in_Rs, out_Pd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_c_sprv32_p3 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT out_Pd = -1;
+ out_Pd = FLD (out_Pd);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec_to_sr (current_cpu, idesc, 1, referenced, in_Rs, out_Pd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_c_sprv32_p4 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT out_Pd = -1;
+ out_Pd = FLD (out_Pd);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec_to_sr (current_cpu, idesc, 1, referenced, in_Rs, out_Pd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_c_sprv32_p5 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT out_Pd = -1;
+ out_Pd = FLD (out_Pd);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec_to_sr (current_cpu, idesc, 1, referenced, in_Rs, out_Pd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_c_sprv32_p6 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT out_Pd = -1;
+ out_Pd = FLD (out_Pd);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec_to_sr (current_cpu, idesc, 1, referenced, in_Rs, out_Pd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_c_sprv32_p7 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT out_Pd = -1;
+ out_Pd = FLD (out_Pd);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec_to_sr (current_cpu, idesc, 1, referenced, in_Rs, out_Pd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_c_sprv32_p8 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT out_Pd = -1;
+ out_Pd = FLD (out_Pd);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec_to_sr (current_cpu, idesc, 1, referenced, in_Rs, out_Pd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_c_sprv32_p9 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT out_Pd = -1;
+ out_Pd = FLD (out_Pd);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec_to_sr (current_cpu, idesc, 1, referenced, in_Rs, out_Pd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_c_sprv32_p10 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT out_Pd = -1;
+ out_Pd = FLD (out_Pd);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec_to_sr (current_cpu, idesc, 1, referenced, in_Rs, out_Pd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_c_sprv32_p11 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT out_Pd = -1;
+ out_Pd = FLD (out_Pd);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec_to_sr (current_cpu, idesc, 1, referenced, in_Rs, out_Pd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_c_sprv32_p12 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT out_Pd = -1;
+ out_Pd = FLD (out_Pd);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec_to_sr (current_cpu, idesc, 1, referenced, in_Rs, out_Pd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_c_sprv32_p13 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT out_Pd = -1;
+ out_Pd = FLD (out_Pd);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec_to_sr (current_cpu, idesc, 1, referenced, in_Rs, out_Pd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_c_sprv32_p14 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT out_Pd = -1;
+ out_Pd = FLD (out_Pd);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec_to_sr (current_cpu, idesc, 1, referenced, in_Rs, out_Pd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_c_sprv32_p15 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT out_Pd = -1;
+ out_Pd = FLD (out_Pd);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec_to_sr (current_cpu, idesc, 1, referenced, in_Rs, out_Pd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_spr_mv32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_w (current_cpu, idesc, 2, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_ss_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_r_ss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_movem_r_m_v32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movem_r_m_v32.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT in_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_movem_rtom (current_cpu, idesc, 1, referenced, in_Rs, in_Rd);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec_movem (current_cpu, idesc, 2, referenced, in_Rs, out_Rd);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_w (current_cpu, idesc, 3, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_movem_m_r_v32 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movem_m_r_v32.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT in_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_movem_mtor (current_cpu, idesc, 2, referenced, in_Rs, in_Rd);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec_movem (current_cpu, idesc, 3, referenced, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_add_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_add_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_add_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_add_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_add_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_add_m_d_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_addcbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_addcwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_addcdr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_adds_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_adds_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_adds_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_adds_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_addscbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_addscwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_addu_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_addu_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_addu_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_addu_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_adducbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_adducwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_sub_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_sub_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_sub_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_sub_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_sub_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_sub_m_d_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_subcbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_subcwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_subcdr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_subs_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_subs_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_subs_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_subs_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_subscbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_subscwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_subu_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_subu_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_subu_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_subu_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_subucbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_subucwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_addc_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_addc_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_addc_c (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_lapc_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lapc_d.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_lapcq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lapcq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_addi_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_addi_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_addi_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_neg_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_neg_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_neg_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_test_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_test_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_test_m_d_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_r_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_w (current_cpu, idesc, 2, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_r_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_w (current_cpu, idesc, 2, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_move_r_m_d_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_w (current_cpu, idesc, 2, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_muls_b (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT in_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_multiply (current_cpu, idesc, 0, referenced, in_Rs, in_Rd);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_muls_w (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT in_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_multiply (current_cpu, idesc, 0, referenced, in_Rs, in_Rd);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_muls_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT in_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_multiply (current_cpu, idesc, 0, referenced, in_Rs, in_Rd);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_mulu_b (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT in_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_multiply (current_cpu, idesc, 0, referenced, in_Rs, in_Rd);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_mulu_w (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT in_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_multiply (current_cpu, idesc, 0, referenced, in_Rs, in_Rd);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_mulu_d (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ INT in_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_multiply (current_cpu, idesc, 0, referenced, in_Rs, in_Rd);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_mcp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_dstep (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_abs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_and_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_and_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_and_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_and_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_and_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_and_m_d_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_andcbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_andcwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_andcdr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_andq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_orr_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_orr_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_orr_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_or_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_or_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_or_m_d_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_orcbr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_orcwr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_orcdr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_orq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_xor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_swap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_asrr_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_asrr_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_asrr_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_asrq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_asrq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_lsrr_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_lsrr_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_lsrr_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_lsrq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_asrq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_lslr_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_lslr_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_lslr_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_lslq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_asrq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_btst (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_btstq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_asrq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_setf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setf.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_clearf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setf.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_rfe (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_rfe.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_sfe (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_rfe.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_rfg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_rfn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_rfe.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_halt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_bcc_b (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bcc_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_branch (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_ba_b (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bcc_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT out_Pd = -1;
+ cycles += crisv32f_model_crisv32_u_jump (current_cpu, idesc, 0, referenced, out_Pd);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_bcc_w (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bcc_w.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_branch (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_ba_w (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bcc_w.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT out_Pd = -1;
+ cycles += crisv32f_model_crisv32_u_jump (current_cpu, idesc, 1, referenced, out_Pd);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_jas_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_jump_r (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT out_Pd = -1;
+ out_Pd = FLD (out_Pd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_jump (current_cpu, idesc, 1, referenced, out_Pd);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_jas_c (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT out_Pd = -1;
+ out_Pd = FLD (out_Pd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_jump (current_cpu, idesc, 1, referenced, out_Pd);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_jump_p (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Ps = -1;
+ in_Ps = FLD (in_Ps);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_jump_sr (current_cpu, idesc, 0, referenced, in_Ps);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_bas_c (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bas_c.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT out_Pd = -1;
+ out_Pd = FLD (out_Pd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_jump (current_cpu, idesc, 1, referenced, out_Pd);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_jasc_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_jump_r (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_skip4 (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT out_Pd = -1;
+ out_Pd = FLD (out_Pd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_jump (current_cpu, idesc, 2, referenced, out_Pd);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 3, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_jasc_c (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_skip4 (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT out_Pd = -1;
+ out_Pd = FLD (out_Pd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_jump (current_cpu, idesc, 2, referenced, out_Pd);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 3, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_basc_c (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bas_c.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_skip4 (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT out_Pd = -1;
+ out_Pd = FLD (out_Pd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_jump (current_cpu, idesc, 2, referenced, out_Pd);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 3, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_break (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_break.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_bound_r_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_bound_r_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_bound_r_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_bound_cb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_bound_cw (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_bound_cd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_scc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_lz (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ out_Rd = FLD (out_Rd);
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_addoq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addoq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_addo_m_b_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_addo_m_w_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_addo_m_d_m (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rs = -1;
+ in_Rs = FLD (in_Rs);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_mem (current_cpu, idesc, 0, referenced, in_Rs);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_mem_r (current_cpu, idesc, 1, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 2, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_addo_cb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_addo_cw (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const16 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_addo_cd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += crisv32f_model_crisv32_u_const32 (current_cpu, idesc, 0, referenced);
+ }
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ referenced |= 1 << 0;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 1, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_addi_acr_b_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_addi_acr_w_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_addi_acr_d_r (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rd = FLD (in_Rd);
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_fidxi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_ftagi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_fidxd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_crisv32_ftagd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_Rd = -1;
+ INT in_Rs = -1;
+ INT out_Rd = -1;
+ in_Rs = FLD (in_Rs);
+ referenced |= 1 << 1;
+ cycles += crisv32f_model_crisv32_u_exec (current_cpu, idesc, 0, referenced, in_Rd, in_Rs, out_Rd);
+ }
+ return cycles;
+#undef FLD
+}
+
+/* We assume UNIT_NONE == 0 because the tables don't always terminate
+ entries with it. */
+
+/* Model timing data for `crisv32'. */
+
+static const INSN_TIMING crisv32_timing[] = {
+ { CRISV32F_INSN_X_INVALID, 0, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_X_AFTER, 0, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_X_BEFORE, 0, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_X_CHAIN, 0, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_X_BEGIN, 0, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_B_R, model_crisv32_move_b_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_W_R, model_crisv32_move_w_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_D_R, model_crisv32_move_d_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVEQ, model_crisv32_moveq, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVS_B_R, model_crisv32_movs_b_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVS_W_R, model_crisv32_movs_w_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVU_B_R, model_crisv32_movu_b_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVU_W_R, model_crisv32_movu_w_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVECBR, model_crisv32_movecbr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVECWR, model_crisv32_movecwr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVECDR, model_crisv32_movecdr, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVSCBR, model_crisv32_movscbr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVSCWR, model_crisv32_movscwr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVUCBR, model_crisv32_movucbr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVUCWR, model_crisv32_movucwr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDQ, model_crisv32_addq, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_SUBQ, model_crisv32_subq, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_CMP_R_B_R, model_crisv32_cmp_r_b_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_CMP_R_W_R, model_crisv32_cmp_r_w_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_CMP_R_D_R, model_crisv32_cmp_r_d_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_CMP_M_B_M, model_crisv32_cmp_m_b_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_CMP_M_W_M, model_crisv32_cmp_m_w_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_CMP_M_D_M, model_crisv32_cmp_m_d_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_CMPCBR, model_crisv32_cmpcbr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_CMPCWR, model_crisv32_cmpcwr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_CMPCDR, model_crisv32_cmpcdr, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_CMPQ, model_crisv32_cmpq, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_CMPS_M_B_M, model_crisv32_cmps_m_b_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_CMPS_M_W_M, model_crisv32_cmps_m_w_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_CMPSCBR, model_crisv32_cmpscbr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_CMPSCWR, model_crisv32_cmpscwr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_CMPU_M_B_M, model_crisv32_cmpu_m_b_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_CMPU_M_W_M, model_crisv32_cmpu_m_w_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_CMPUCBR, model_crisv32_cmpucbr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_CMPUCWR, model_crisv32_cmpucwr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_M_B_M, model_crisv32_move_m_b_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_M_W_M, model_crisv32_move_m_w_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_M_D_M, model_crisv32_move_m_d_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVS_M_B_M, model_crisv32_movs_m_b_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVS_M_W_M, model_crisv32_movs_m_w_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVU_M_B_M, model_crisv32_movu_m_b_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVU_M_W_M, model_crisv32_movu_m_w_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_R_SPRV32, model_crisv32_move_r_sprv32, { { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_SPR_RV32, model_crisv32_move_spr_rv32, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_M_SPRV32, model_crisv32_move_m_sprv32, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P0, model_crisv32_move_c_sprv32_p0, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P1, model_crisv32_move_c_sprv32_p1, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P2, model_crisv32_move_c_sprv32_p2, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P3, model_crisv32_move_c_sprv32_p3, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P4, model_crisv32_move_c_sprv32_p4, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P5, model_crisv32_move_c_sprv32_p5, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P6, model_crisv32_move_c_sprv32_p6, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P7, model_crisv32_move_c_sprv32_p7, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P8, model_crisv32_move_c_sprv32_p8, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P9, model_crisv32_move_c_sprv32_p9, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P10, model_crisv32_move_c_sprv32_p10, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P11, model_crisv32_move_c_sprv32_p11, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P12, model_crisv32_move_c_sprv32_p12, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P13, model_crisv32_move_c_sprv32_p13, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P14, model_crisv32_move_c_sprv32_p14, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P15, model_crisv32_move_c_sprv32_p15, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_TO_SR, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_SPR_MV32, model_crisv32_move_spr_mv32, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_W, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_SS_R, model_crisv32_move_ss_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_R_SS, model_crisv32_move_r_ss, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVEM_R_M_V32, model_crisv32_movem_r_m_v32, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MOVEM_RTOM, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_MOVEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_W, 1, 1 } } },
+ { CRISV32F_INSN_MOVEM_M_R_V32, model_crisv32_movem_m_r_v32, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_MOVEM_MTOR, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC_MOVEM, 1, 1 } } },
+ { CRISV32F_INSN_ADD_B_R, model_crisv32_add_b_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADD_W_R, model_crisv32_add_w_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADD_D_R, model_crisv32_add_d_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADD_M_B_M, model_crisv32_add_m_b_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADD_M_W_M, model_crisv32_add_m_w_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADD_M_D_M, model_crisv32_add_m_d_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDCBR, model_crisv32_addcbr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDCWR, model_crisv32_addcwr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDCDR, model_crisv32_addcdr, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDS_B_R, model_crisv32_adds_b_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDS_W_R, model_crisv32_adds_w_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDS_M_B_M, model_crisv32_adds_m_b_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDS_M_W_M, model_crisv32_adds_m_w_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDSCBR, model_crisv32_addscbr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDSCWR, model_crisv32_addscwr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDU_B_R, model_crisv32_addu_b_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDU_W_R, model_crisv32_addu_w_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDU_M_B_M, model_crisv32_addu_m_b_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDU_M_W_M, model_crisv32_addu_m_w_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDUCBR, model_crisv32_adducbr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDUCWR, model_crisv32_adducwr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_SUB_B_R, model_crisv32_sub_b_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_SUB_W_R, model_crisv32_sub_w_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_SUB_D_R, model_crisv32_sub_d_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_SUB_M_B_M, model_crisv32_sub_m_b_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_SUB_M_W_M, model_crisv32_sub_m_w_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_SUB_M_D_M, model_crisv32_sub_m_d_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_SUBCBR, model_crisv32_subcbr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_SUBCWR, model_crisv32_subcwr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_SUBCDR, model_crisv32_subcdr, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_SUBS_B_R, model_crisv32_subs_b_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_SUBS_W_R, model_crisv32_subs_w_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_SUBS_M_B_M, model_crisv32_subs_m_b_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_SUBS_M_W_M, model_crisv32_subs_m_w_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_SUBSCBR, model_crisv32_subscbr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_SUBSCWR, model_crisv32_subscwr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_SUBU_B_R, model_crisv32_subu_b_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_SUBU_W_R, model_crisv32_subu_w_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_SUBU_M_B_M, model_crisv32_subu_m_b_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_SUBU_M_W_M, model_crisv32_subu_m_w_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_SUBUCBR, model_crisv32_subucbr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_SUBUCWR, model_crisv32_subucwr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDC_R, model_crisv32_addc_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDC_M, model_crisv32_addc_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDC_C, model_crisv32_addc_c, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_LAPC_D, model_crisv32_lapc_d, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_LAPCQ, model_crisv32_lapcq, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDI_B_R, model_crisv32_addi_b_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDI_W_R, model_crisv32_addi_w_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDI_D_R, model_crisv32_addi_d_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_NEG_B_R, model_crisv32_neg_b_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_NEG_W_R, model_crisv32_neg_w_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_NEG_D_R, model_crisv32_neg_d_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_TEST_M_B_M, model_crisv32_test_m_b_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_TEST_M_W_M, model_crisv32_test_m_w_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_TEST_M_D_M, model_crisv32_test_m_d_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_R_M_B_M, model_crisv32_move_r_m_b_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_W, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_R_M_W_M, model_crisv32_move_r_m_w_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_W, 1, 1 } } },
+ { CRISV32F_INSN_MOVE_R_M_D_M, model_crisv32_move_r_m_d_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_W, 1, 1 } } },
+ { CRISV32F_INSN_MULS_B, model_crisv32_muls_b, { { (int) UNIT_CRISV32_U_MULTIPLY, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MULS_W, model_crisv32_muls_w, { { (int) UNIT_CRISV32_U_MULTIPLY, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MULS_D, model_crisv32_muls_d, { { (int) UNIT_CRISV32_U_MULTIPLY, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MULU_B, model_crisv32_mulu_b, { { (int) UNIT_CRISV32_U_MULTIPLY, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MULU_W, model_crisv32_mulu_w, { { (int) UNIT_CRISV32_U_MULTIPLY, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MULU_D, model_crisv32_mulu_d, { { (int) UNIT_CRISV32_U_MULTIPLY, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_MCP, model_crisv32_mcp, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_DSTEP, model_crisv32_dstep, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ABS, model_crisv32_abs, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_AND_B_R, model_crisv32_and_b_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_AND_W_R, model_crisv32_and_w_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_AND_D_R, model_crisv32_and_d_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_AND_M_B_M, model_crisv32_and_m_b_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_AND_M_W_M, model_crisv32_and_m_w_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_AND_M_D_M, model_crisv32_and_m_d_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ANDCBR, model_crisv32_andcbr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ANDCWR, model_crisv32_andcwr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ANDCDR, model_crisv32_andcdr, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ANDQ, model_crisv32_andq, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ORR_B_R, model_crisv32_orr_b_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ORR_W_R, model_crisv32_orr_w_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ORR_D_R, model_crisv32_orr_d_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_OR_M_B_M, model_crisv32_or_m_b_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_OR_M_W_M, model_crisv32_or_m_w_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_OR_M_D_M, model_crisv32_or_m_d_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ORCBR, model_crisv32_orcbr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ORCWR, model_crisv32_orcwr, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ORCDR, model_crisv32_orcdr, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ORQ, model_crisv32_orq, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_XOR, model_crisv32_xor, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_SWAP, model_crisv32_swap, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ASRR_B_R, model_crisv32_asrr_b_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ASRR_W_R, model_crisv32_asrr_w_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ASRR_D_R, model_crisv32_asrr_d_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ASRQ, model_crisv32_asrq, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_LSRR_B_R, model_crisv32_lsrr_b_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_LSRR_W_R, model_crisv32_lsrr_w_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_LSRR_D_R, model_crisv32_lsrr_d_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_LSRQ, model_crisv32_lsrq, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_LSLR_B_R, model_crisv32_lslr_b_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_LSLR_W_R, model_crisv32_lslr_w_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_LSLR_D_R, model_crisv32_lslr_d_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_LSLQ, model_crisv32_lslq, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_BTST, model_crisv32_btst, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_BTSTQ, model_crisv32_btstq, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_SETF, model_crisv32_setf, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_CLEARF, model_crisv32_clearf, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_RFE, model_crisv32_rfe, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_SFE, model_crisv32_sfe, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_RFG, model_crisv32_rfg, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_RFN, model_crisv32_rfn, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_HALT, model_crisv32_halt, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_BCC_B, model_crisv32_bcc_b, { { (int) UNIT_CRISV32_U_BRANCH, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_BA_B, model_crisv32_ba_b, { { (int) UNIT_CRISV32_U_JUMP, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_BCC_W, model_crisv32_bcc_w, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_BRANCH, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_BA_W, model_crisv32_ba_w, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_JUMP, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_JAS_R, model_crisv32_jas_r, { { (int) UNIT_CRISV32_U_JUMP_R, 1, 1 }, { (int) UNIT_CRISV32_U_JUMP, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_JAS_C, model_crisv32_jas_c, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_JUMP, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_JUMP_P, model_crisv32_jump_p, { { (int) UNIT_CRISV32_U_JUMP_SR, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_BAS_C, model_crisv32_bas_c, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_JUMP, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_JASC_R, model_crisv32_jasc_r, { { (int) UNIT_CRISV32_U_JUMP_R, 1, 1 }, { (int) UNIT_CRISV32_U_SKIP4, 1, 1 }, { (int) UNIT_CRISV32_U_JUMP, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_JASC_C, model_crisv32_jasc_c, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_SKIP4, 1, 1 }, { (int) UNIT_CRISV32_U_JUMP, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_BASC_C, model_crisv32_basc_c, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_SKIP4, 1, 1 }, { (int) UNIT_CRISV32_U_JUMP, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_BREAK, model_crisv32_break, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_BOUND_R_B_R, model_crisv32_bound_r_b_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_BOUND_R_W_R, model_crisv32_bound_r_w_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_BOUND_R_D_R, model_crisv32_bound_r_d_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_BOUND_CB, model_crisv32_bound_cb, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_BOUND_CW, model_crisv32_bound_cw, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_BOUND_CD, model_crisv32_bound_cd, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_SCC, model_crisv32_scc, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_LZ, model_crisv32_lz, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDOQ, model_crisv32_addoq, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDO_M_B_M, model_crisv32_addo_m_b_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDO_M_W_M, model_crisv32_addo_m_w_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDO_M_D_M, model_crisv32_addo_m_d_m, { { (int) UNIT_CRISV32_U_MEM, 1, 1 }, { (int) UNIT_CRISV32_U_MEM_R, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDO_CB, model_crisv32_addo_cb, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDO_CW, model_crisv32_addo_cw, { { (int) UNIT_CRISV32_U_CONST16, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDO_CD, model_crisv32_addo_cd, { { (int) UNIT_CRISV32_U_CONST32, 1, 1 }, { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDI_ACR_B_R, model_crisv32_addi_acr_b_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDI_ACR_W_R, model_crisv32_addi_acr_w_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_ADDI_ACR_D_R, model_crisv32_addi_acr_d_r, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_FIDXI, model_crisv32_fidxi, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_FTAGI, model_crisv32_ftagi, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_FIDXD, model_crisv32_fidxd, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+ { CRISV32F_INSN_FTAGD, model_crisv32_ftagd, { { (int) UNIT_CRISV32_U_EXEC, 1, 1 } } },
+};
+
+#endif /* WITH_PROFILE_MODEL_P */
+
+static void
+crisv32_model_init (SIM_CPU *cpu)
+{
+ CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_CRISV32_DATA));
+}
+
+#if WITH_PROFILE_MODEL_P
+#define TIMING_DATA(td) td
+#else
+#define TIMING_DATA(td) 0
+#endif
+
+static const MODEL crisv32_models[] =
+{
+ { "crisv32", & crisv32_mach, MODEL_CRISV32, TIMING_DATA (& crisv32_timing[0]), crisv32_model_init },
+ { 0 }
+};
+
+/* The properties of this cpu's implementation. */
+
+static const MACH_IMP_PROPERTIES crisv32f_imp_properties =
+{
+ sizeof (SIM_CPU),
+#if WITH_SCACHE
+ sizeof (SCACHE)
+#else
+ 0
+#endif
+};
+
+
+static void
+crisv32f_prepare_run (SIM_CPU *cpu)
+{
+ if (CPU_IDESC (cpu) == NULL)
+ crisv32f_init_idesc_table (cpu);
+}
+
+static const CGEN_INSN *
+crisv32f_get_idata (SIM_CPU *cpu, int inum)
+{
+ return CPU_IDESC (cpu) [inum].idata;
+}
+
+static void
+crisv32_init_cpu (SIM_CPU *cpu)
+{
+ CPU_REG_FETCH (cpu) = crisv32f_fetch_register;
+ CPU_REG_STORE (cpu) = crisv32f_store_register;
+ CPU_PC_FETCH (cpu) = crisv32f_h_pc_get;
+ CPU_PC_STORE (cpu) = crisv32f_h_pc_set;
+ CPU_GET_IDATA (cpu) = crisv32f_get_idata;
+ CPU_MAX_INSNS (cpu) = CRISV32F_INSN__MAX;
+ CPU_INSN_NAME (cpu) = cgen_insn_name;
+ CPU_FULL_ENGINE_FN (cpu) = crisv32f_engine_run_full;
+#if WITH_FAST
+ CPU_FAST_ENGINE_FN (cpu) = crisv32f_engine_run_fast;
+#else
+ CPU_FAST_ENGINE_FN (cpu) = crisv32f_engine_run_full;
+#endif
+}
+
+const MACH crisv32_mach =
+{
+ "crisv32", "crisv32", MACH_CRISV32,
+ 32, 32, & crisv32_models[0], & crisv32f_imp_properties,
+ crisv32_init_cpu,
+ crisv32f_prepare_run
+};
+
--- /dev/null
+/* Simulator instruction semantics for crisv10f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2004 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifdef DEFINE_LABELS
+
+ /* The labels have the case they have because the enum of insn types
+ is all uppercase and in the non-stdc case the insn symbol is built
+ into the enum name. */
+
+ static struct {
+ int index;
+ void *label;
+ } labels[] = {
+ { CRISV10F_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
+ { CRISV10F_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
+ { CRISV10F_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
+ { CRISV10F_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
+ { CRISV10F_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
+ { CRISV10F_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
+ { CRISV10F_INSN_NOP, && case_sem_INSN_NOP },
+ { CRISV10F_INSN_MOVE_B_R, && case_sem_INSN_MOVE_B_R },
+ { CRISV10F_INSN_MOVE_W_R, && case_sem_INSN_MOVE_W_R },
+ { CRISV10F_INSN_MOVE_D_R, && case_sem_INSN_MOVE_D_R },
+ { CRISV10F_INSN_MOVEPCR, && case_sem_INSN_MOVEPCR },
+ { CRISV10F_INSN_MOVEQ, && case_sem_INSN_MOVEQ },
+ { CRISV10F_INSN_MOVS_B_R, && case_sem_INSN_MOVS_B_R },
+ { CRISV10F_INSN_MOVS_W_R, && case_sem_INSN_MOVS_W_R },
+ { CRISV10F_INSN_MOVU_B_R, && case_sem_INSN_MOVU_B_R },
+ { CRISV10F_INSN_MOVU_W_R, && case_sem_INSN_MOVU_W_R },
+ { CRISV10F_INSN_MOVECBR, && case_sem_INSN_MOVECBR },
+ { CRISV10F_INSN_MOVECWR, && case_sem_INSN_MOVECWR },
+ { CRISV10F_INSN_MOVECDR, && case_sem_INSN_MOVECDR },
+ { CRISV10F_INSN_MOVSCBR, && case_sem_INSN_MOVSCBR },
+ { CRISV10F_INSN_MOVSCWR, && case_sem_INSN_MOVSCWR },
+ { CRISV10F_INSN_MOVUCBR, && case_sem_INSN_MOVUCBR },
+ { CRISV10F_INSN_MOVUCWR, && case_sem_INSN_MOVUCWR },
+ { CRISV10F_INSN_ADDQ, && case_sem_INSN_ADDQ },
+ { CRISV10F_INSN_SUBQ, && case_sem_INSN_SUBQ },
+ { CRISV10F_INSN_CMP_R_B_R, && case_sem_INSN_CMP_R_B_R },
+ { CRISV10F_INSN_CMP_R_W_R, && case_sem_INSN_CMP_R_W_R },
+ { CRISV10F_INSN_CMP_R_D_R, && case_sem_INSN_CMP_R_D_R },
+ { CRISV10F_INSN_CMP_M_B_M, && case_sem_INSN_CMP_M_B_M },
+ { CRISV10F_INSN_CMP_M_W_M, && case_sem_INSN_CMP_M_W_M },
+ { CRISV10F_INSN_CMP_M_D_M, && case_sem_INSN_CMP_M_D_M },
+ { CRISV10F_INSN_CMPCBR, && case_sem_INSN_CMPCBR },
+ { CRISV10F_INSN_CMPCWR, && case_sem_INSN_CMPCWR },
+ { CRISV10F_INSN_CMPCDR, && case_sem_INSN_CMPCDR },
+ { CRISV10F_INSN_CMPQ, && case_sem_INSN_CMPQ },
+ { CRISV10F_INSN_CMPS_M_B_M, && case_sem_INSN_CMPS_M_B_M },
+ { CRISV10F_INSN_CMPS_M_W_M, && case_sem_INSN_CMPS_M_W_M },
+ { CRISV10F_INSN_CMPSCBR, && case_sem_INSN_CMPSCBR },
+ { CRISV10F_INSN_CMPSCWR, && case_sem_INSN_CMPSCWR },
+ { CRISV10F_INSN_CMPU_M_B_M, && case_sem_INSN_CMPU_M_B_M },
+ { CRISV10F_INSN_CMPU_M_W_M, && case_sem_INSN_CMPU_M_W_M },
+ { CRISV10F_INSN_CMPUCBR, && case_sem_INSN_CMPUCBR },
+ { CRISV10F_INSN_CMPUCWR, && case_sem_INSN_CMPUCWR },
+ { CRISV10F_INSN_MOVE_M_B_M, && case_sem_INSN_MOVE_M_B_M },
+ { CRISV10F_INSN_MOVE_M_W_M, && case_sem_INSN_MOVE_M_W_M },
+ { CRISV10F_INSN_MOVE_M_D_M, && case_sem_INSN_MOVE_M_D_M },
+ { CRISV10F_INSN_MOVS_M_B_M, && case_sem_INSN_MOVS_M_B_M },
+ { CRISV10F_INSN_MOVS_M_W_M, && case_sem_INSN_MOVS_M_W_M },
+ { CRISV10F_INSN_MOVU_M_B_M, && case_sem_INSN_MOVU_M_B_M },
+ { CRISV10F_INSN_MOVU_M_W_M, && case_sem_INSN_MOVU_M_W_M },
+ { CRISV10F_INSN_MOVE_R_SPRV10, && case_sem_INSN_MOVE_R_SPRV10 },
+ { CRISV10F_INSN_MOVE_SPR_RV10, && case_sem_INSN_MOVE_SPR_RV10 },
+ { CRISV10F_INSN_RET_TYPE, && case_sem_INSN_RET_TYPE },
+ { CRISV10F_INSN_MOVE_M_SPRV10, && case_sem_INSN_MOVE_M_SPRV10 },
+ { CRISV10F_INSN_MOVE_C_SPRV10_P0, && case_sem_INSN_MOVE_C_SPRV10_P0 },
+ { CRISV10F_INSN_MOVE_C_SPRV10_P1, && case_sem_INSN_MOVE_C_SPRV10_P1 },
+ { CRISV10F_INSN_MOVE_C_SPRV10_P4, && case_sem_INSN_MOVE_C_SPRV10_P4 },
+ { CRISV10F_INSN_MOVE_C_SPRV10_P5, && case_sem_INSN_MOVE_C_SPRV10_P5 },
+ { CRISV10F_INSN_MOVE_C_SPRV10_P8, && case_sem_INSN_MOVE_C_SPRV10_P8 },
+ { CRISV10F_INSN_MOVE_C_SPRV10_P9, && case_sem_INSN_MOVE_C_SPRV10_P9 },
+ { CRISV10F_INSN_MOVE_C_SPRV10_P10, && case_sem_INSN_MOVE_C_SPRV10_P10 },
+ { CRISV10F_INSN_MOVE_C_SPRV10_P11, && case_sem_INSN_MOVE_C_SPRV10_P11 },
+ { CRISV10F_INSN_MOVE_C_SPRV10_P12, && case_sem_INSN_MOVE_C_SPRV10_P12 },
+ { CRISV10F_INSN_MOVE_C_SPRV10_P13, && case_sem_INSN_MOVE_C_SPRV10_P13 },
+ { CRISV10F_INSN_MOVE_C_SPRV10_P7, && case_sem_INSN_MOVE_C_SPRV10_P7 },
+ { CRISV10F_INSN_MOVE_C_SPRV10_P14, && case_sem_INSN_MOVE_C_SPRV10_P14 },
+ { CRISV10F_INSN_MOVE_C_SPRV10_P15, && case_sem_INSN_MOVE_C_SPRV10_P15 },
+ { CRISV10F_INSN_MOVE_SPR_MV10, && case_sem_INSN_MOVE_SPR_MV10 },
+ { CRISV10F_INSN_SBFS, && case_sem_INSN_SBFS },
+ { CRISV10F_INSN_MOVEM_R_M, && case_sem_INSN_MOVEM_R_M },
+ { CRISV10F_INSN_MOVEM_M_R, && case_sem_INSN_MOVEM_M_R },
+ { CRISV10F_INSN_MOVEM_M_PC, && case_sem_INSN_MOVEM_M_PC },
+ { CRISV10F_INSN_ADD_B_R, && case_sem_INSN_ADD_B_R },
+ { CRISV10F_INSN_ADD_W_R, && case_sem_INSN_ADD_W_R },
+ { CRISV10F_INSN_ADD_D_R, && case_sem_INSN_ADD_D_R },
+ { CRISV10F_INSN_ADD_M_B_M, && case_sem_INSN_ADD_M_B_M },
+ { CRISV10F_INSN_ADD_M_W_M, && case_sem_INSN_ADD_M_W_M },
+ { CRISV10F_INSN_ADD_M_D_M, && case_sem_INSN_ADD_M_D_M },
+ { CRISV10F_INSN_ADDCBR, && case_sem_INSN_ADDCBR },
+ { CRISV10F_INSN_ADDCWR, && case_sem_INSN_ADDCWR },
+ { CRISV10F_INSN_ADDCDR, && case_sem_INSN_ADDCDR },
+ { CRISV10F_INSN_ADDCPC, && case_sem_INSN_ADDCPC },
+ { CRISV10F_INSN_ADDS_B_R, && case_sem_INSN_ADDS_B_R },
+ { CRISV10F_INSN_ADDS_W_R, && case_sem_INSN_ADDS_W_R },
+ { CRISV10F_INSN_ADDS_M_B_M, && case_sem_INSN_ADDS_M_B_M },
+ { CRISV10F_INSN_ADDS_M_W_M, && case_sem_INSN_ADDS_M_W_M },
+ { CRISV10F_INSN_ADDSCBR, && case_sem_INSN_ADDSCBR },
+ { CRISV10F_INSN_ADDSCWR, && case_sem_INSN_ADDSCWR },
+ { CRISV10F_INSN_ADDSPCPC, && case_sem_INSN_ADDSPCPC },
+ { CRISV10F_INSN_ADDU_B_R, && case_sem_INSN_ADDU_B_R },
+ { CRISV10F_INSN_ADDU_W_R, && case_sem_INSN_ADDU_W_R },
+ { CRISV10F_INSN_ADDU_M_B_M, && case_sem_INSN_ADDU_M_B_M },
+ { CRISV10F_INSN_ADDU_M_W_M, && case_sem_INSN_ADDU_M_W_M },
+ { CRISV10F_INSN_ADDUCBR, && case_sem_INSN_ADDUCBR },
+ { CRISV10F_INSN_ADDUCWR, && case_sem_INSN_ADDUCWR },
+ { CRISV10F_INSN_SUB_B_R, && case_sem_INSN_SUB_B_R },
+ { CRISV10F_INSN_SUB_W_R, && case_sem_INSN_SUB_W_R },
+ { CRISV10F_INSN_SUB_D_R, && case_sem_INSN_SUB_D_R },
+ { CRISV10F_INSN_SUB_M_B_M, && case_sem_INSN_SUB_M_B_M },
+ { CRISV10F_INSN_SUB_M_W_M, && case_sem_INSN_SUB_M_W_M },
+ { CRISV10F_INSN_SUB_M_D_M, && case_sem_INSN_SUB_M_D_M },
+ { CRISV10F_INSN_SUBCBR, && case_sem_INSN_SUBCBR },
+ { CRISV10F_INSN_SUBCWR, && case_sem_INSN_SUBCWR },
+ { CRISV10F_INSN_SUBCDR, && case_sem_INSN_SUBCDR },
+ { CRISV10F_INSN_SUBS_B_R, && case_sem_INSN_SUBS_B_R },
+ { CRISV10F_INSN_SUBS_W_R, && case_sem_INSN_SUBS_W_R },
+ { CRISV10F_INSN_SUBS_M_B_M, && case_sem_INSN_SUBS_M_B_M },
+ { CRISV10F_INSN_SUBS_M_W_M, && case_sem_INSN_SUBS_M_W_M },
+ { CRISV10F_INSN_SUBSCBR, && case_sem_INSN_SUBSCBR },
+ { CRISV10F_INSN_SUBSCWR, && case_sem_INSN_SUBSCWR },
+ { CRISV10F_INSN_SUBU_B_R, && case_sem_INSN_SUBU_B_R },
+ { CRISV10F_INSN_SUBU_W_R, && case_sem_INSN_SUBU_W_R },
+ { CRISV10F_INSN_SUBU_M_B_M, && case_sem_INSN_SUBU_M_B_M },
+ { CRISV10F_INSN_SUBU_M_W_M, && case_sem_INSN_SUBU_M_W_M },
+ { CRISV10F_INSN_SUBUCBR, && case_sem_INSN_SUBUCBR },
+ { CRISV10F_INSN_SUBUCWR, && case_sem_INSN_SUBUCWR },
+ { CRISV10F_INSN_ADDI_B_R, && case_sem_INSN_ADDI_B_R },
+ { CRISV10F_INSN_ADDI_W_R, && case_sem_INSN_ADDI_W_R },
+ { CRISV10F_INSN_ADDI_D_R, && case_sem_INSN_ADDI_D_R },
+ { CRISV10F_INSN_NEG_B_R, && case_sem_INSN_NEG_B_R },
+ { CRISV10F_INSN_NEG_W_R, && case_sem_INSN_NEG_W_R },
+ { CRISV10F_INSN_NEG_D_R, && case_sem_INSN_NEG_D_R },
+ { CRISV10F_INSN_TEST_M_B_M, && case_sem_INSN_TEST_M_B_M },
+ { CRISV10F_INSN_TEST_M_W_M, && case_sem_INSN_TEST_M_W_M },
+ { CRISV10F_INSN_TEST_M_D_M, && case_sem_INSN_TEST_M_D_M },
+ { CRISV10F_INSN_MOVE_R_M_B_M, && case_sem_INSN_MOVE_R_M_B_M },
+ { CRISV10F_INSN_MOVE_R_M_W_M, && case_sem_INSN_MOVE_R_M_W_M },
+ { CRISV10F_INSN_MOVE_R_M_D_M, && case_sem_INSN_MOVE_R_M_D_M },
+ { CRISV10F_INSN_MULS_B, && case_sem_INSN_MULS_B },
+ { CRISV10F_INSN_MULS_W, && case_sem_INSN_MULS_W },
+ { CRISV10F_INSN_MULS_D, && case_sem_INSN_MULS_D },
+ { CRISV10F_INSN_MULU_B, && case_sem_INSN_MULU_B },
+ { CRISV10F_INSN_MULU_W, && case_sem_INSN_MULU_W },
+ { CRISV10F_INSN_MULU_D, && case_sem_INSN_MULU_D },
+ { CRISV10F_INSN_MSTEP, && case_sem_INSN_MSTEP },
+ { CRISV10F_INSN_DSTEP, && case_sem_INSN_DSTEP },
+ { CRISV10F_INSN_ABS, && case_sem_INSN_ABS },
+ { CRISV10F_INSN_AND_B_R, && case_sem_INSN_AND_B_R },
+ { CRISV10F_INSN_AND_W_R, && case_sem_INSN_AND_W_R },
+ { CRISV10F_INSN_AND_D_R, && case_sem_INSN_AND_D_R },
+ { CRISV10F_INSN_AND_M_B_M, && case_sem_INSN_AND_M_B_M },
+ { CRISV10F_INSN_AND_M_W_M, && case_sem_INSN_AND_M_W_M },
+ { CRISV10F_INSN_AND_M_D_M, && case_sem_INSN_AND_M_D_M },
+ { CRISV10F_INSN_ANDCBR, && case_sem_INSN_ANDCBR },
+ { CRISV10F_INSN_ANDCWR, && case_sem_INSN_ANDCWR },
+ { CRISV10F_INSN_ANDCDR, && case_sem_INSN_ANDCDR },
+ { CRISV10F_INSN_ANDQ, && case_sem_INSN_ANDQ },
+ { CRISV10F_INSN_ORR_B_R, && case_sem_INSN_ORR_B_R },
+ { CRISV10F_INSN_ORR_W_R, && case_sem_INSN_ORR_W_R },
+ { CRISV10F_INSN_ORR_D_R, && case_sem_INSN_ORR_D_R },
+ { CRISV10F_INSN_OR_M_B_M, && case_sem_INSN_OR_M_B_M },
+ { CRISV10F_INSN_OR_M_W_M, && case_sem_INSN_OR_M_W_M },
+ { CRISV10F_INSN_OR_M_D_M, && case_sem_INSN_OR_M_D_M },
+ { CRISV10F_INSN_ORCBR, && case_sem_INSN_ORCBR },
+ { CRISV10F_INSN_ORCWR, && case_sem_INSN_ORCWR },
+ { CRISV10F_INSN_ORCDR, && case_sem_INSN_ORCDR },
+ { CRISV10F_INSN_ORQ, && case_sem_INSN_ORQ },
+ { CRISV10F_INSN_XOR, && case_sem_INSN_XOR },
+ { CRISV10F_INSN_SWAP, && case_sem_INSN_SWAP },
+ { CRISV10F_INSN_ASRR_B_R, && case_sem_INSN_ASRR_B_R },
+ { CRISV10F_INSN_ASRR_W_R, && case_sem_INSN_ASRR_W_R },
+ { CRISV10F_INSN_ASRR_D_R, && case_sem_INSN_ASRR_D_R },
+ { CRISV10F_INSN_ASRQ, && case_sem_INSN_ASRQ },
+ { CRISV10F_INSN_LSRR_B_R, && case_sem_INSN_LSRR_B_R },
+ { CRISV10F_INSN_LSRR_W_R, && case_sem_INSN_LSRR_W_R },
+ { CRISV10F_INSN_LSRR_D_R, && case_sem_INSN_LSRR_D_R },
+ { CRISV10F_INSN_LSRQ, && case_sem_INSN_LSRQ },
+ { CRISV10F_INSN_LSLR_B_R, && case_sem_INSN_LSLR_B_R },
+ { CRISV10F_INSN_LSLR_W_R, && case_sem_INSN_LSLR_W_R },
+ { CRISV10F_INSN_LSLR_D_R, && case_sem_INSN_LSLR_D_R },
+ { CRISV10F_INSN_LSLQ, && case_sem_INSN_LSLQ },
+ { CRISV10F_INSN_BTST, && case_sem_INSN_BTST },
+ { CRISV10F_INSN_BTSTQ, && case_sem_INSN_BTSTQ },
+ { CRISV10F_INSN_SETF, && case_sem_INSN_SETF },
+ { CRISV10F_INSN_CLEARF, && case_sem_INSN_CLEARF },
+ { CRISV10F_INSN_BCC_B, && case_sem_INSN_BCC_B },
+ { CRISV10F_INSN_BA_B, && case_sem_INSN_BA_B },
+ { CRISV10F_INSN_BCC_W, && case_sem_INSN_BCC_W },
+ { CRISV10F_INSN_BA_W, && case_sem_INSN_BA_W },
+ { CRISV10F_INSN_JUMP_R, && case_sem_INSN_JUMP_R },
+ { CRISV10F_INSN_JUMP_M, && case_sem_INSN_JUMP_M },
+ { CRISV10F_INSN_JUMP_C, && case_sem_INSN_JUMP_C },
+ { CRISV10F_INSN_BREAK, && case_sem_INSN_BREAK },
+ { CRISV10F_INSN_BOUND_R_B_R, && case_sem_INSN_BOUND_R_B_R },
+ { CRISV10F_INSN_BOUND_R_W_R, && case_sem_INSN_BOUND_R_W_R },
+ { CRISV10F_INSN_BOUND_R_D_R, && case_sem_INSN_BOUND_R_D_R },
+ { CRISV10F_INSN_BOUND_M_B_M, && case_sem_INSN_BOUND_M_B_M },
+ { CRISV10F_INSN_BOUND_M_W_M, && case_sem_INSN_BOUND_M_W_M },
+ { CRISV10F_INSN_BOUND_M_D_M, && case_sem_INSN_BOUND_M_D_M },
+ { CRISV10F_INSN_BOUND_CB, && case_sem_INSN_BOUND_CB },
+ { CRISV10F_INSN_BOUND_CW, && case_sem_INSN_BOUND_CW },
+ { CRISV10F_INSN_BOUND_CD, && case_sem_INSN_BOUND_CD },
+ { CRISV10F_INSN_SCC, && case_sem_INSN_SCC },
+ { CRISV10F_INSN_LZ, && case_sem_INSN_LZ },
+ { CRISV10F_INSN_ADDOQ, && case_sem_INSN_ADDOQ },
+ { CRISV10F_INSN_BDAPQPC, && case_sem_INSN_BDAPQPC },
+ { CRISV10F_INSN_ADDO_M_B_M, && case_sem_INSN_ADDO_M_B_M },
+ { CRISV10F_INSN_ADDO_M_W_M, && case_sem_INSN_ADDO_M_W_M },
+ { CRISV10F_INSN_ADDO_M_D_M, && case_sem_INSN_ADDO_M_D_M },
+ { CRISV10F_INSN_ADDO_CB, && case_sem_INSN_ADDO_CB },
+ { CRISV10F_INSN_ADDO_CW, && case_sem_INSN_ADDO_CW },
+ { CRISV10F_INSN_ADDO_CD, && case_sem_INSN_ADDO_CD },
+ { CRISV10F_INSN_DIP_M, && case_sem_INSN_DIP_M },
+ { CRISV10F_INSN_DIP_C, && case_sem_INSN_DIP_C },
+ { CRISV10F_INSN_ADDI_ACR_B_R, && case_sem_INSN_ADDI_ACR_B_R },
+ { CRISV10F_INSN_ADDI_ACR_W_R, && case_sem_INSN_ADDI_ACR_W_R },
+ { CRISV10F_INSN_ADDI_ACR_D_R, && case_sem_INSN_ADDI_ACR_D_R },
+ { CRISV10F_INSN_BIAP_PC_B_R, && case_sem_INSN_BIAP_PC_B_R },
+ { CRISV10F_INSN_BIAP_PC_W_R, && case_sem_INSN_BIAP_PC_W_R },
+ { CRISV10F_INSN_BIAP_PC_D_R, && case_sem_INSN_BIAP_PC_D_R },
+ { 0, 0 }
+ };
+ int i;
+
+ for (i = 0; labels[i].label != 0; ++i)
+ {
+#if FAST_P
+ CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
+#else
+ CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
+#endif
+ }
+
+#undef DEFINE_LABELS
+#endif /* DEFINE_LABELS */
+
+#ifdef DEFINE_SWITCH
+
+/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
+ off frills like tracing and profiling. */
+/* FIXME: A better way would be to have TRACE_RESULT check for something
+ that can cause it to be optimized out. Another way would be to emit
+ special handlers into the instruction "stream". */
+
+#if FAST_P
+#undef TRACE_RESULT
+#define TRACE_RESULT(cpu, abuf, name, type, val)
+#endif
+
+#undef GET_ATTR
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
+#else
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
+#endif
+
+{
+
+#if WITH_SCACHE_PBB
+
+/* Branch to next handler without going around main loop. */
+#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
+SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
+
+#else /* ! WITH_SCACHE_PBB */
+
+#define NEXT(vpc) BREAK (sem)
+#ifdef __GNUC__
+#if FAST_P
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
+#else
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
+#endif
+#else
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
+#endif
+
+#endif /* ! WITH_SCACHE_PBB */
+
+ {
+
+ CASE (sem, INSN_X_INVALID) : /* --invalid-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+ /* Update the recorded pc in the cpu state struct.
+ Only necessary for WITH_SCACHE case, but to avoid the
+ conditional compilation .... */
+ SET_H_PC (pc);
+ /* Virtual insns have zero size. Overwrite vpc with address of next insn
+ using the default-insn-bitsize spec. When executing insns in parallel
+ we may want to queue the fault and continue execution. */
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+ vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_AFTER) : /* --after-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_CRISV10F
+ crisv10f_pbb_after (current_cpu, sem_arg);
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_BEFORE) : /* --before-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_CRISV10F
+ crisv10f_pbb_before (current_cpu, sem_arg);
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_CRISV10F
+#ifdef DEFINE_SWITCH
+ vpc = crisv10f_pbb_cti_chain (current_cpu, sem_arg,
+ pbb_br_type, pbb_br_npc);
+ BREAK (sem);
+#else
+ /* FIXME: Allow provision of explicit ifmt spec in insn spec. */
+ vpc = crisv10f_pbb_cti_chain (current_cpu, sem_arg,
+ CPU_PBB_BR_TYPE (current_cpu),
+ CPU_PBB_BR_NPC (current_cpu));
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_CHAIN) : /* --chain-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_CRISV10F
+ vpc = crisv10f_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+ BREAK (sem);
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_BEGIN) : /* --begin-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_CRISV10F
+#if defined DEFINE_SWITCH || defined FAST_P
+ /* In the switch case FAST_P is a constant, allowing several optimizations
+ in any called inline functions. */
+ vpc = crisv10f_pbb_begin (current_cpu, FAST_P);
+#else
+#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
+ vpc = crisv10f_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#else
+ vpc = crisv10f_pbb_begin (current_cpu, 0);
+#endif
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NOP) : /* nop */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_B_R) : /* move.b move.m ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_newval;
+ tmp_newval = GET_H_GR (FLD (f_operand1));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_W_R) : /* move.w move.m ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_newval;
+ tmp_newval = GET_H_GR (FLD (f_operand1));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_D_R) : /* move.d move.m ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_newval;
+ tmp_newval = GET_H_GR (FLD (f_operand1));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVEPCR) : /* move.d PC,${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_moveq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_pcval;
+ tmp_pcval = ADDSI (pc, 2);
+ {
+ SI opval = tmp_pcval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_pcval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_pcval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVEQ) : /* moveq $i,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_moveq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_newval;
+ tmp_newval = FLD (f_s6);
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+SET_H_NBIT_MOVE (LTSI (tmp_newval, 0));
+SET_H_ZBIT_MOVE (ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))));
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVS_B_R) : /* movs.b movs.m ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_newval;
+ tmp_newval = GET_H_GR (FLD (f_operand1));
+ {
+ SI opval = EXTQISI (tmp_newval);
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVS_W_R) : /* movs.w movs.m ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_newval;
+ tmp_newval = GET_H_GR (FLD (f_operand1));
+ {
+ SI opval = EXTHISI (tmp_newval);
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVU_B_R) : /* movu.b movu.m ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_newval;
+ tmp_newval = GET_H_GR (FLD (f_operand1));
+ {
+ SI opval = ZEXTQISI (tmp_newval);
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVU_W_R) : /* movu.w movu.m ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_newval;
+ tmp_newval = GET_H_GR (FLD (f_operand1));
+ {
+ SI opval = ZEXTHISI (tmp_newval);
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVECBR) : /* move.b ${sconst8},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_newval;
+ tmp_newval = FLD (f_indir_pc__byte);
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVECWR) : /* move.w ${sconst16},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_newval;
+ tmp_newval = FLD (f_indir_pc__word);
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVECDR) : /* move.d ${const32},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ SI tmp_newval;
+ tmp_newval = FLD (f_indir_pc__dword);
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVSCBR) : /* movs.b ${sconst8},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_newval;
+ tmp_newval = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVSCWR) : /* movs.w ${sconst16},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_newval;
+ tmp_newval = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVUCBR) : /* movu.b ${uconst8},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_newval;
+ tmp_newval = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVUCWR) : /* movu.w ${uconst16},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_newval;
+ tmp_newval = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDQ) : /* addq $j,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = FLD (f_u6);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBQ) : /* subq $j,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = FLD (f_u6);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_R_B_R) : /* cmp-r.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_R_W_R) : /* cmp-r.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_R_D_R) : /* cmp-r.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_M_B_M) : /* cmp-m.b [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_M_W_M) : /* cmp-m.w [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_M_D_M) : /* cmp-m.d [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPCBR) : /* cmp.b $sconst8,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = TRUNCSIQI (FLD (f_indir_pc__byte));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPCWR) : /* cmp.w $sconst16,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = TRUNCSIHI (FLD (f_indir_pc__word));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPCDR) : /* cmp.d $const32,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = FLD (f_indir_pc__dword);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPQ) : /* cmpq $i,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_andq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = FLD (f_s6);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPS_M_B_M) : /* cmps-m.b [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPS_M_W_M) : /* cmps-m.w [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPSCBR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPSCWR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPU_M_B_M) : /* cmpu-m.b [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPU_M_W_M) : /* cmpu-m.w [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPUCBR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPUCWR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_M_B_M) : /* move-m.b [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = ({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmp, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmp, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_M_W_M) : /* move-m.w [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = ({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmp, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmp, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_M_D_M) : /* move-m.d [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmp, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVS_M_B_M) : /* movs-m.b [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = EXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (FLD (f_operand2), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTSI (tmp_tmp, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVS_M_W_M) : /* movs-m.w [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = EXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (FLD (f_operand2), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTSI (tmp_tmp, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVU_M_B_M) : /* movu-m.b [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = ZEXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (FLD (f_operand2), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTSI (tmp_tmp, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVU_M_W_M) : /* movu-m.w [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = ZEXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (FLD (f_operand2), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTSI (tmp_tmp, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_R_SPRV10) : /* move ${Rs},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ SI tmp_rno;
+ tmp_tmp = GET_H_GR (FLD (f_operand1));
+ tmp_rno = FLD (f_operand2);
+if (ORIF (ORIF (EQSI (tmp_rno, 0), EQSI (tmp_rno, 1)), ORIF (EQSI (tmp_rno, 4), EQSI (tmp_rno, 8)))) {
+cgen_rtx_error (current_cpu, "move-r-spr: trying to set a read-only special register");
+}
+ else {
+ {
+ SI opval = tmp_tmp;
+ SET_H_SR (FLD (f_operand2), opval);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_SPR_RV10) : /* move ${Ps},${Rd-sfield} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_spr_rv10.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_grno;
+ SI tmp_prno;
+ SI tmp_newval;
+ tmp_prno = FLD (f_operand2);
+ tmp_newval = GET_H_SR (FLD (f_operand2));
+if (EQSI (tmp_prno, 0)) {
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+ else if (EQSI (tmp_prno, 1)) {
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+ else if (EQSI (tmp_prno, 4)) {
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+ else if (EQSI (tmp_prno, 5)) {
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand1));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+ else if (EQSI (tmp_prno, 8)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 9)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 10)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 11)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 12)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 13)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 7)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 14)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 15)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else {
+cgen_rtx_error (current_cpu, "move-spr-r from unimplemented register");
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RET_TYPE) : /* ret/reti/retb */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_spr_rv10.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_retaddr;
+ tmp_retaddr = GET_H_SR (FLD (f_operand2));
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = tmp_retaddr;
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_M_SPRV10) : /* move [${Rs}${inc}],${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_rno;
+ SI tmp_newval;
+ tmp_rno = FLD (f_operand2);
+if (EQSI (tmp_rno, 0)) {
+ tmp_newval = EXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+}
+ else if (EQSI (tmp_rno, 1)) {
+ tmp_newval = EXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+}
+ else if (EQSI (tmp_rno, 4)) {
+ tmp_newval = EXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+}
+ else if (EQSI (tmp_rno, 5)) {
+ tmp_newval = EXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+}
+ else if (EQSI (tmp_rno, 8)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 9)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 10)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 11)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 12)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 13)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 7)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 14)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 15)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else {
+cgen_rtx_error (current_cpu, "Trying to set unimplemented special register");
+}
+ {
+ SI opval = tmp_newval;
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV10_P0) : /* move ${sconst8},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p0.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__byte);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV10_P1) : /* move ${sconst8},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p0.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__byte);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV10_P4) : /* move ${sconst16},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p4.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__word);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV10_P5) : /* move ${sconst16},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p4.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__word);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV10_P8) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV10_P9) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV10_P10) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV10_P11) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV10_P12) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV10_P13) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV10_P7) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV10_P14) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV10_P15) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_SPR_MV10) : /* move ${Ps},[${Rd-sfield}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_rno;
+ tmp_rno = FLD (f_operand2);
+if (EQSI (tmp_rno, 0)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ QI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ QI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 1)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ QI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ QI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 4)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ HI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMHI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ HI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMHI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 5)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ HI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMHI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ HI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMHI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 8)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 9)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 10)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 11)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 12)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 13)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 7)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 14)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 15)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+cgen_rtx_error (current_cpu, "write from unimplemented special register");
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SBFS) : /* sbfs [${Rd-sfield}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+cgen_rtx_error (current_cpu, "SBFS isn't implemented");
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVEM_R_M) : /* movem ${Rs-dfield},[${Rd-sfield}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movem_r_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+{
+ SI tmp_dummy;
+ tmp_dummy = GET_H_GR (FLD (f_operand2));
+}
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+{
+if (GESI (FLD (f_operand2), 15)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 15));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 14)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 14));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 13)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 13));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 12)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 12));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 11)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 11));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 10)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 10));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 9)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 9));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 8)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 8));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 7)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 7));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 6)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 6));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 5)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 5));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 4)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 4));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 3)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 3));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 2)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 2));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 1)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 1));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 0)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 0));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 23);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+}
+if (NEBI (tmp_postinc, 0)) {
+ {
+ SI opval = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (tmp_addr) : (CPU (h_prefixreg_pre_v32)));
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVEM_M_R) : /* movem [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movem_m_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+{
+ SI tmp_dummy;
+ tmp_dummy = GET_H_GR (FLD (f_operand2));
+}
+{
+if (GESI (FLD (f_operand2), 14)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 14), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 13)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 13), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 12)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 12), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 11)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 11), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 10)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 10), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 9)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 9), opval);
+ written |= (1 << 22);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 8)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 8), opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 7)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 7), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 6)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 6), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 5)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 5), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 4)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 4), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 3)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 3), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 2)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 2), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 1)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 0)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 0), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+}
+if (NEBI (tmp_postinc, 0)) {
+ {
+ SI opval = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (tmp_addr) : (CPU (h_prefixreg_pre_v32)));
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVEM_M_PC) : /* movem [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movem_m_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+{
+ {
+ USI opval = GETMEMSI (current_cpu, pc, tmp_addr);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 14), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 13), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 12), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 11), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 10), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 9), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 8), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 7), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 6), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 5), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 4), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 3), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 1), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (NEBI (tmp_postinc, 0)) {
+ {
+ SI opval = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (tmp_addr) : (CPU (h_prefixreg_pre_v32)));
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 5);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_B_R) : /* add.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_W_R) : /* add.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_D_R) : /* add.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_M_B_M) : /* add-m.b [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_M_W_M) : /* add-m.w [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_M_D_M) : /* add-m.d [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDCBR) : /* add.b ${sconst8}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = FLD (f_indir_pc__byte);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDCWR) : /* add.w ${sconst16}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = FLD (f_indir_pc__word);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDCDR) : /* add.d ${const32}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = FLD (f_indir_pc__dword);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDCPC) : /* add.d ${sconst32},PC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ SI tmp_newpc;
+ SI tmp_oldpc;
+ SI tmp_offs;
+ tmp_offs = FLD (f_indir_pc__dword);
+ tmp_oldpc = ADDSI (pc, 6);
+ tmp_newpc = ADDSI (tmp_oldpc, tmp_offs);
+ {
+ USI opval = tmp_newpc;
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_offs, 0), LTSI (tmp_oldpc, 0)), ORIF (ANDIF (LTSI (tmp_oldpc, 0), GESI (tmp_newpc, 0)), ANDIF (LTSI (tmp_offs, 0), GESI (tmp_newpc, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newpc, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newpc, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_offs, 0), LTSI (tmp_oldpc, 0)), GESI (tmp_newpc, 0)), ANDIF (ANDIF (GESI (tmp_offs, 0), GESI (tmp_oldpc, 0)), LTSI (tmp_newpc, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_B_R) : /* adds.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_W_R) : /* adds.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_M_B_M) : /* adds-m.b [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_M_W_M) : /* adds-m.w [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDSCBR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDSCWR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDSPCPC) : /* adds.w [PC],PC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_newpc;
+ SI tmp_oldpc;
+ HI tmp_offs;
+if (NOTBI (GET_H_INSN_PREFIXED_P ())) {
+cgen_rtx_error (current_cpu, "Unexpected adds.w [PC],PC without prefix");
+}
+ tmp_offs = GETMEMHI (current_cpu, pc, CPU (h_prefixreg_pre_v32));
+ tmp_oldpc = ADDSI (pc, 2);
+ tmp_newpc = ADDSI (tmp_oldpc, tmp_offs);
+ {
+ USI opval = tmp_newpc;
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (EXTHISI (tmp_offs), 0), LTSI (tmp_oldpc, 0)), ORIF (ANDIF (LTSI (tmp_oldpc, 0), GESI (tmp_newpc, 0)), ANDIF (LTSI (EXTHISI (tmp_offs), 0), GESI (tmp_newpc, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newpc, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newpc, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (EXTHISI (tmp_offs), 0), LTSI (tmp_oldpc, 0)), GESI (tmp_newpc, 0)), ANDIF (ANDIF (GESI (EXTHISI (tmp_offs), 0), GESI (tmp_oldpc, 0)), LTSI (tmp_newpc, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDU_B_R) : /* addu.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDU_W_R) : /* addu.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDU_M_B_M) : /* addu-m.b [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDU_M_W_M) : /* addu-m.w [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDUCBR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDUCWR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_B_R) : /* sub.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_W_R) : /* sub.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_D_R) : /* sub.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_M_B_M) : /* sub-m.b [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_M_W_M) : /* sub-m.w [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_M_D_M) : /* sub-m.d [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBCBR) : /* sub.b ${sconst8}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = FLD (f_indir_pc__byte);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBCWR) : /* sub.w ${sconst16}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = FLD (f_indir_pc__word);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBCDR) : /* sub.d ${const32}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = FLD (f_indir_pc__dword);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_B_R) : /* subs.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_W_R) : /* subs.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_M_B_M) : /* subs-m.b [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_M_W_M) : /* subs-m.w [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBSCBR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBSCWR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBU_B_R) : /* subu.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBU_W_R) : /* subu.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBU_M_B_M) : /* subu-m.b [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBU_M_W_M) : /* subu-m.w [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBUCBR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBUCWR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDI_B_R) : /* addi.b ${Rs-dfield}.m,${Rd-sfield} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 1));
+ SET_H_GR (FLD (f_operand1), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDI_W_R) : /* addi.w ${Rs-dfield}.m,${Rd-sfield} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 2));
+ SET_H_GR (FLD (f_operand1), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDI_D_R) : /* addi.d ${Rs-dfield}.m,${Rd-sfield} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 4));
+ SET_H_GR (FLD (f_operand1), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NEG_B_R) : /* neg.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = 0;
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NEG_W_R) : /* neg.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = 0;
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NEG_D_R) : /* neg.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = 0;
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TEST_M_B_M) : /* test-m.b [${Rs}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpd;
+ tmp_tmpd = ({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = 0;
+ tmp_tmpopd = tmp_tmpd;
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TEST_M_W_M) : /* test-m.w [${Rs}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpd;
+ tmp_tmpd = ({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = 0;
+ tmp_tmpopd = tmp_tmpd;
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TEST_M_D_M) : /* test-m.d [${Rs}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = 0;
+ tmp_tmpopd = tmp_tmpd;
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_R_M_B_M) : /* move-r-m.b ${Rs-dfield},[${Rd-sfield}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpd;
+ tmp_tmpd = GET_H_GR (FLD (f_operand2));
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ QI opval = tmp_tmpd;
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ QI opval = tmp_tmpd;
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_R_M_W_M) : /* move-r-m.w ${Rs-dfield},[${Rd-sfield}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpd;
+ tmp_tmpd = GET_H_GR (FLD (f_operand2));
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ HI opval = tmp_tmpd;
+ SETMEMHI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ HI opval = tmp_tmpd;
+ SETMEMHI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_R_M_D_M) : /* move-r-m.d ${Rs-dfield},[${Rd-sfield}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = GET_H_GR (FLD (f_operand2));
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+if (ANDIF (GET_H_V32_NON_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = tmp_tmpd;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = tmp_tmpd;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULS_B) : /* muls.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_src1;
+ DI tmp_src2;
+ DI tmp_tmpr;
+ tmp_src1 = EXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
+ tmp_src2 = EXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand2))));
+ tmp_tmpr = MULDI (tmp_src1, tmp_src2);
+ {
+ SI opval = TRUNCDISI (tmp_tmpr);
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ {
+ SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
+ SET_H_SR (((UINT) 7), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTDI (tmp_tmpr, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULS_W) : /* muls.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_src1;
+ DI tmp_src2;
+ DI tmp_tmpr;
+ tmp_src1 = EXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
+ tmp_src2 = EXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand2))));
+ tmp_tmpr = MULDI (tmp_src1, tmp_src2);
+ {
+ SI opval = TRUNCDISI (tmp_tmpr);
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ {
+ SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
+ SET_H_SR (((UINT) 7), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTDI (tmp_tmpr, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULS_D) : /* muls.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_src1;
+ DI tmp_src2;
+ DI tmp_tmpr;
+ tmp_src1 = EXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand1))));
+ tmp_src2 = EXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand2))));
+ tmp_tmpr = MULDI (tmp_src1, tmp_src2);
+ {
+ SI opval = TRUNCDISI (tmp_tmpr);
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ {
+ SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
+ SET_H_SR (((UINT) 7), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTDI (tmp_tmpr, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULU_B) : /* mulu.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_src1;
+ DI tmp_src2;
+ DI tmp_tmpr;
+ tmp_src1 = ZEXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
+ tmp_src2 = ZEXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand2))));
+ tmp_tmpr = MULDI (tmp_src1, tmp_src2);
+ {
+ SI opval = TRUNCDISI (tmp_tmpr);
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ {
+ SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
+ SET_H_SR (((UINT) 7), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTDI (tmp_tmpr, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULU_W) : /* mulu.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_src1;
+ DI tmp_src2;
+ DI tmp_tmpr;
+ tmp_src1 = ZEXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
+ tmp_src2 = ZEXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand2))));
+ tmp_tmpr = MULDI (tmp_src1, tmp_src2);
+ {
+ SI opval = TRUNCDISI (tmp_tmpr);
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ {
+ SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
+ SET_H_SR (((UINT) 7), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTDI (tmp_tmpr, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULU_D) : /* mulu.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_src1;
+ DI tmp_src2;
+ DI tmp_tmpr;
+ tmp_src1 = ZEXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand1))));
+ tmp_src2 = ZEXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand2))));
+ tmp_tmpr = MULDI (tmp_src1, tmp_src2);
+ {
+ SI opval = TRUNCDISI (tmp_tmpr);
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ {
+ SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
+ SET_H_SR (((UINT) 7), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = ANDIF (GET_H_V32_NON_V32 (), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTDI (tmp_tmpr, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MSTEP) : /* mstep $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_tmps;
+ tmp_tmps = GET_H_GR (FLD (f_operand1));
+ tmp_tmpd = ADDSI (SLLSI (GET_H_GR (FLD (f_operand2)), 1), ((CPU (h_nbit)) ? (tmp_tmps) : (0)));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DSTEP) : /* dstep $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ SI tmp_tmps;
+ SI tmp_tmpd;
+ tmp_tmps = GET_H_GR (FLD (f_operand1));
+ tmp_tmp = SLLSI (GET_H_GR (FLD (f_operand2)), 1);
+ tmp_tmpd = ((GEUSI (tmp_tmp, tmp_tmps)) ? (SUBSI (tmp_tmp, tmp_tmps)) : (tmp_tmp));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ABS) : /* abs $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ABSSI (GET_H_GR (FLD (f_operand1)));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_B_R) : /* and.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpd;
+ tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_W_R) : /* and.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpd;
+ tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_D_R) : /* and.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_M_B_M) : /* and-m.b [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpd;
+ tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), ({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_M_W_M) : /* and-m.w [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpd;
+ tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), ({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_M_D_M) : /* and-m.d [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ANDCBR) : /* and.b ${sconst8}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_tmpd;
+ tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__byte));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ANDCWR) : /* and.w ${sconst16}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_tmpd;
+ tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__word));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ANDCDR) : /* and.d ${const32}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ANDQ) : /* andq $i,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_andq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), FLD (f_s6));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORR_B_R) : /* orr.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpd;
+ tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORR_W_R) : /* orr.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpd;
+ tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORR_D_R) : /* orr.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR_M_B_M) : /* or-m.b [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpd;
+ tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), ({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR_M_W_M) : /* or-m.w [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpd;
+ tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), ({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR_M_D_M) : /* or-m.d [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORCBR) : /* or.b ${sconst8}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_tmpd;
+ tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__byte));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORCWR) : /* or.w ${sconst16}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_tmpd;
+ tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__word));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORCDR) : /* or.d ${const32}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORQ) : /* orq $i,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_andq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), FLD (f_s6));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XOR) : /* xor $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = XORSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SWAP) : /* swap${swapoption} ${Rs} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmps;
+ SI tmp_tmpd;
+ tmp_tmps = GET_H_GR (FLD (f_operand1));
+ tmp_tmpd = ({ SI tmp_tmpcode;
+ SI tmp_tmpval;
+ SI tmp_tmpres;
+ tmp_tmpcode = FLD (f_operand2);
+; tmp_tmpval = tmp_tmps;
+; if (EQSI (tmp_tmpcode, 0)) {
+ tmp_tmpres = (cgen_rtx_error (current_cpu, "SWAP without swap modifier isn't implemented"), 0);
+}
+ else if (EQSI (tmp_tmpcode, 1)) {
+ tmp_tmpres = ({ SI tmp_tmpr;
+ tmp_tmpr = tmp_tmpval;
+; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
+}
+ else if (EQSI (tmp_tmpcode, 2)) {
+ tmp_tmpres = ({ SI tmp_tmpb;
+ tmp_tmpb = tmp_tmpval;
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
+}
+ else if (EQSI (tmp_tmpcode, 3)) {
+ tmp_tmpres = ({ SI tmp_tmpr;
+ tmp_tmpr = ({ SI tmp_tmpb;
+ tmp_tmpb = tmp_tmpval;
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
+; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
+}
+ else if (EQSI (tmp_tmpcode, 4)) {
+ tmp_tmpres = ({ SI tmp_tmpb;
+ tmp_tmpb = tmp_tmpval;
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
+}
+ else if (EQSI (tmp_tmpcode, 5)) {
+ tmp_tmpres = ({ SI tmp_tmpr;
+ tmp_tmpr = ({ SI tmp_tmpb;
+ tmp_tmpb = tmp_tmpval;
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
+; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
+}
+ else if (EQSI (tmp_tmpcode, 6)) {
+ tmp_tmpres = ({ SI tmp_tmpb;
+ tmp_tmpb = ({ SI tmp_tmpb;
+ tmp_tmpb = tmp_tmpval;
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
+}
+ else if (EQSI (tmp_tmpcode, 7)) {
+ tmp_tmpres = ({ SI tmp_tmpr;
+ tmp_tmpr = ({ SI tmp_tmpb;
+ tmp_tmpb = ({ SI tmp_tmpb;
+ tmp_tmpb = tmp_tmpval;
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
+; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
+}
+ else if (EQSI (tmp_tmpcode, 8)) {
+ tmp_tmpres = INVSI (tmp_tmpval);
+}
+ else if (EQSI (tmp_tmpcode, 9)) {
+ tmp_tmpres = ({ SI tmp_tmpr;
+ tmp_tmpr = INVSI (tmp_tmpval);
+; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
+}
+ else if (EQSI (tmp_tmpcode, 10)) {
+ tmp_tmpres = ({ SI tmp_tmpb;
+ tmp_tmpb = INVSI (tmp_tmpval);
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
+}
+ else if (EQSI (tmp_tmpcode, 11)) {
+ tmp_tmpres = ({ SI tmp_tmpr;
+ tmp_tmpr = ({ SI tmp_tmpb;
+ tmp_tmpb = INVSI (tmp_tmpval);
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
+; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
+}
+ else if (EQSI (tmp_tmpcode, 12)) {
+ tmp_tmpres = ({ SI tmp_tmpb;
+ tmp_tmpb = INVSI (tmp_tmpval);
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
+}
+ else if (EQSI (tmp_tmpcode, 13)) {
+ tmp_tmpres = ({ SI tmp_tmpr;
+ tmp_tmpr = ({ SI tmp_tmpb;
+ tmp_tmpb = INVSI (tmp_tmpval);
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
+; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
+}
+ else if (EQSI (tmp_tmpcode, 14)) {
+ tmp_tmpres = ({ SI tmp_tmpb;
+ tmp_tmpb = ({ SI tmp_tmpb;
+ tmp_tmpb = INVSI (tmp_tmpval);
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
+}
+ else if (EQSI (tmp_tmpcode, 15)) {
+ tmp_tmpres = ({ SI tmp_tmpr;
+ tmp_tmpr = ({ SI tmp_tmpb;
+ tmp_tmpb = ({ SI tmp_tmpb;
+ tmp_tmpb = INVSI (tmp_tmpval);
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
+; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
+}
+; tmp_tmpres; });
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand1), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRR_B_R) : /* asrr.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpd;
+ SI tmp_cnt1;
+ SI tmp_cnt2;
+ tmp_cnt1 = GET_H_GR (FLD (f_operand1));
+ tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
+ tmp_tmpd = SRASI (EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRR_W_R) : /* asrr.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpd;
+ SI tmp_cnt1;
+ SI tmp_cnt2;
+ tmp_cnt1 = GET_H_GR (FLD (f_operand1));
+ tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
+ tmp_tmpd = SRASI (EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRR_D_R) : /* asrr.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_cnt1;
+ SI tmp_cnt2;
+ tmp_cnt1 = GET_H_GR (FLD (f_operand1));
+ tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
+ tmp_tmpd = SRASI (EXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRQ) : /* asrq $c,${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_asrq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = SRASI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSRR_B_R) : /* lsrr.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_cnt;
+ tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
+ tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSRR_W_R) : /* lsrr.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_cnt;
+ tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
+ tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSRR_D_R) : /* lsrr.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_cnt;
+ tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
+ tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSRQ) : /* lsrq $c,${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_asrq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = SRLSI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSLR_B_R) : /* lslr.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_cnt;
+ tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
+ tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSLR_W_R) : /* lslr.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_cnt;
+ tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
+ tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_PC (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSLR_D_R) : /* lslr.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_cnt;
+ tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
+ tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSLQ) : /* lslq $c,${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_asrq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BTST) : /* $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_cnt;
+ tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), SUBSI (31, ANDSI (GET_H_GR (FLD (f_operand1)), 31)));
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BTSTQ) : /* btstq $c,${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_asrq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), SUBSI (31, FLD (f_u5)));
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SETF) : /* setf ${list-of-flags} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_setf.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = FLD (f_dstsrc);
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 0)), 0)) {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 1);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 1)), 0)) {
+ {
+ BI opval = 1;
+ CPU (h_vbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 2)), 0)) {
+ {
+ BI opval = 1;
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 3)), 0)) {
+ {
+ BI opval = 1;
+ CPU (h_nbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
+ {
+ BI opval = 1;
+ CPU (h_xbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 5)), 0)) {
+ {
+ BI opval = 1;
+ SET_H_IBIT (opval);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "ibit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 6)), 0)) {
+ {
+ BI opval = 1;
+ SET_H_UBIT (opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "ubit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) {
+ {
+ BI opval = 1;
+ CPU (h_pbit) = opval;
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "pbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+if (EQSI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CLEARF) : /* clearf ${list-of-flags} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_setf.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = FLD (f_dstsrc);
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 0)), 0)) {
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 1);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 1)), 0)) {
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 2)), 0)) {
+ {
+ BI opval = 0;
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 3)), 0)) {
+ {
+ BI opval = 0;
+ CPU (h_nbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 5)), 0)) {
+ {
+ BI opval = 0;
+ SET_H_IBIT (opval);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "ibit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 6)), 0)) {
+ {
+ BI opval = 0;
+ SET_H_UBIT (opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "ubit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) {
+ {
+ BI opval = 0;
+ CPU (h_pbit) = opval;
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "pbit", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCC_B) : /* b${cc} ${o-pcrel} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bcc_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_truthval;
+ tmp_truthval = ({ SI tmp_tmpcond;
+ BI tmp_condres;
+ tmp_tmpcond = FLD (f_operand2);
+; if (EQSI (tmp_tmpcond, 0)) {
+ tmp_condres = NOTBI (CPU (h_cbit));
+}
+ else if (EQSI (tmp_tmpcond, 1)) {
+ tmp_condres = CPU (h_cbit);
+}
+ else if (EQSI (tmp_tmpcond, 2)) {
+ tmp_condres = NOTBI (CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 3)) {
+ tmp_condres = CPU (h_zbit);
+}
+ else if (EQSI (tmp_tmpcond, 4)) {
+ tmp_condres = NOTBI (CPU (h_vbit));
+}
+ else if (EQSI (tmp_tmpcond, 5)) {
+ tmp_condres = CPU (h_vbit);
+}
+ else if (EQSI (tmp_tmpcond, 6)) {
+ tmp_condres = NOTBI (CPU (h_nbit));
+}
+ else if (EQSI (tmp_tmpcond, 7)) {
+ tmp_condres = CPU (h_nbit);
+}
+ else if (EQSI (tmp_tmpcond, 8)) {
+ tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 9)) {
+ tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
+}
+ else if (EQSI (tmp_tmpcond, 10)) {
+ tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
+}
+ else if (EQSI (tmp_tmpcond, 11)) {
+ tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
+}
+ else if (EQSI (tmp_tmpcond, 12)) {
+ tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
+}
+ else if (EQSI (tmp_tmpcond, 13)) {
+ tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 14)) {
+ tmp_condres = 1;
+}
+ else if (EQSI (tmp_tmpcond, 15)) {
+ tmp_condres = CPU (h_pbit);
+}
+; tmp_condres; });
+crisv10f_branch_taken (current_cpu, pc, FLD (i_o_pcrel), tmp_truthval);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+if (tmp_truthval) {
+{
+ {
+ USI opval = FLD (i_o_pcrel);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BA_B) : /* ba ${o-pcrel} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bcc_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_o_pcrel);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCC_W) : /* b${cc} ${o-word-pcrel} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bcc_w.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ BI tmp_truthval;
+ tmp_truthval = ({ SI tmp_tmpcond;
+ BI tmp_condres;
+ tmp_tmpcond = FLD (f_operand2);
+; if (EQSI (tmp_tmpcond, 0)) {
+ tmp_condres = NOTBI (CPU (h_cbit));
+}
+ else if (EQSI (tmp_tmpcond, 1)) {
+ tmp_condres = CPU (h_cbit);
+}
+ else if (EQSI (tmp_tmpcond, 2)) {
+ tmp_condres = NOTBI (CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 3)) {
+ tmp_condres = CPU (h_zbit);
+}
+ else if (EQSI (tmp_tmpcond, 4)) {
+ tmp_condres = NOTBI (CPU (h_vbit));
+}
+ else if (EQSI (tmp_tmpcond, 5)) {
+ tmp_condres = CPU (h_vbit);
+}
+ else if (EQSI (tmp_tmpcond, 6)) {
+ tmp_condres = NOTBI (CPU (h_nbit));
+}
+ else if (EQSI (tmp_tmpcond, 7)) {
+ tmp_condres = CPU (h_nbit);
+}
+ else if (EQSI (tmp_tmpcond, 8)) {
+ tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 9)) {
+ tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
+}
+ else if (EQSI (tmp_tmpcond, 10)) {
+ tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
+}
+ else if (EQSI (tmp_tmpcond, 11)) {
+ tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
+}
+ else if (EQSI (tmp_tmpcond, 12)) {
+ tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
+}
+ else if (EQSI (tmp_tmpcond, 13)) {
+ tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 14)) {
+ tmp_condres = 1;
+}
+ else if (EQSI (tmp_tmpcond, 15)) {
+ tmp_condres = CPU (h_pbit);
+}
+; tmp_condres; });
+crisv10f_branch_taken (current_cpu, pc, FLD (i_o_word_pcrel), tmp_truthval);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+if (tmp_truthval) {
+{
+ {
+ USI opval = FLD (i_o_word_pcrel);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BA_W) : /* ba ${o-word-pcrel} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bcc_w.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_o_word_pcrel);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JUMP_R) : /* jump/jsr/jir ${Rs} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+ {
+ USI opval = GET_H_GR (FLD (f_operand1));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JUMP_M) : /* jump/jsr/jir [${Rs}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_m_sprv10.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (pc, 2);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+ {
+ USI opval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JUMP_C) : /* jump/jsr/jir ${const32} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = ADDSI (pc, 6);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+ {
+ USI opval = FLD (f_indir_pc__dword);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BREAK) : /* break $n */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_break.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+ {
+ USI opval = crisv10f_break_handler (current_cpu, FLD (f_u4), pc);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BOUND_R_B_R) : /* bound-r.b ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BOUND_R_W_R) : /* bound-r.w ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BOUND_R_D_R) : /* bound-r.d ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = TRUNCSISI (GET_H_GR (FLD (f_operand1)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BOUND_M_B_M) : /* bound-m.b [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
+if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BOUND_M_W_M) : /* bound-m.w [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
+if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BOUND_M_D_M) : /* bound-m.d [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
+if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BOUND_CB) : /* bound.b [PC+],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BOUND_CW) : /* bound.w [PC+],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTSISI (FLD (f_indir_pc__word));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BOUND_CD) : /* bound.d [PC+],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = FLD (f_indir_pc__dword);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SCC) : /* s${cc} ${Rd-sfield} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_truthval;
+ tmp_truthval = ({ SI tmp_tmpcond;
+ BI tmp_condres;
+ tmp_tmpcond = FLD (f_operand2);
+; if (EQSI (tmp_tmpcond, 0)) {
+ tmp_condres = NOTBI (CPU (h_cbit));
+}
+ else if (EQSI (tmp_tmpcond, 1)) {
+ tmp_condres = CPU (h_cbit);
+}
+ else if (EQSI (tmp_tmpcond, 2)) {
+ tmp_condres = NOTBI (CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 3)) {
+ tmp_condres = CPU (h_zbit);
+}
+ else if (EQSI (tmp_tmpcond, 4)) {
+ tmp_condres = NOTBI (CPU (h_vbit));
+}
+ else if (EQSI (tmp_tmpcond, 5)) {
+ tmp_condres = CPU (h_vbit);
+}
+ else if (EQSI (tmp_tmpcond, 6)) {
+ tmp_condres = NOTBI (CPU (h_nbit));
+}
+ else if (EQSI (tmp_tmpcond, 7)) {
+ tmp_condres = CPU (h_nbit);
+}
+ else if (EQSI (tmp_tmpcond, 8)) {
+ tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 9)) {
+ tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
+}
+ else if (EQSI (tmp_tmpcond, 10)) {
+ tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
+}
+ else if (EQSI (tmp_tmpcond, 11)) {
+ tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
+}
+ else if (EQSI (tmp_tmpcond, 12)) {
+ tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
+}
+ else if (EQSI (tmp_tmpcond, 13)) {
+ tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 14)) {
+ tmp_condres = 1;
+}
+ else if (EQSI (tmp_tmpcond, 15)) {
+ tmp_condres = CPU (h_pbit);
+}
+; tmp_condres; });
+ {
+ SI opval = ZEXTBISI (tmp_truthval);
+ SET_H_GR (FLD (f_operand1), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LZ) : /* lz ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (FLD (f_operand1));
+ tmp_tmpd = 0;
+{
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+}
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDOQ) : /* addoq $o,$Rs,ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addoq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), FLD (f_s8));
+ CPU (h_prefixreg_pre_v32) = opval;
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BDAPQPC) : /* bdapq $o,PC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addoq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (ADDSI (pc, 2), FLD (f_s8));
+ CPU (h_prefixreg_pre_v32) = opval;
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+cris_flush_simulator_decode_cache (current_cpu, pc);
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDO_M_B_M) : /* addo-m.b [${Rs}${inc}],$Rd,ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmps;
+ tmp_tmps = ({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTQISI (tmp_tmps));
+ CPU (h_prefixreg_pre_v32) = opval;
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDO_M_W_M) : /* addo-m.w [${Rs}${inc}],$Rd,ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmps;
+ tmp_tmps = ({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTHISI (tmp_tmps));
+ CPU (h_prefixreg_pre_v32) = opval;
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDO_M_D_M) : /* addo-m.d [${Rs}${inc}],$Rd,ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmps;
+ tmp_tmps = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), tmp_tmps);
+ CPU (h_prefixreg_pre_v32) = opval;
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDO_CB) : /* addo.b [PC+],$Rd,ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte))));
+ CPU (h_prefixreg_pre_v32) = opval;
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDO_CW) : /* addo.w [PC+],$Rd,ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word))));
+ CPU (h_prefixreg_pre_v32) = opval;
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDO_CD) : /* addo.d [PC+],$Rd,ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
+ CPU (h_prefixreg_pre_v32) = opval;
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DIP_M) : /* dip [${Rs}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_spr_mv10.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmps;
+ tmp_tmps = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (CPU (h_prefixreg_pre_v32)));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 5);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ {
+ SI opval = tmp_tmps;
+ CPU (h_prefixreg_pre_v32) = opval;
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DIP_C) : /* dip [PC+] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv10_p8.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ CPU (h_prefixreg_pre_v32) = opval;
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDI_ACR_B_R) : /* addi-acr.b ${Rs-dfield}.m,${Rd-sfield},ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 1));
+ CPU (h_prefixreg_pre_v32) = opval;
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDI_ACR_W_R) : /* addi-acr.w ${Rs-dfield}.m,${Rd-sfield},ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 2));
+ CPU (h_prefixreg_pre_v32) = opval;
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDI_ACR_D_R) : /* addi-acr.d ${Rs-dfield}.m,${Rd-sfield},ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_b_r.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 4));
+ CPU (h_prefixreg_pre_v32) = opval;
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BIAP_PC_B_R) : /* biap-pc.b ${Rs-dfield}.m,PC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addoq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (ADDSI (pc, 4), MULSI (GET_H_GR (FLD (f_operand2)), 1));
+ CPU (h_prefixreg_pre_v32) = opval;
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BIAP_PC_W_R) : /* biap-pc.w ${Rs-dfield}.m,PC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addoq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (ADDSI (pc, 4), MULSI (GET_H_GR (FLD (f_operand2)), 2));
+ CPU (h_prefixreg_pre_v32) = opval;
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BIAP_PC_D_R) : /* biap-pc.d ${Rs-dfield}.m,PC */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addoq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (ADDSI (pc, 4), MULSI (GET_H_GR (FLD (f_operand2)), 4));
+ CPU (h_prefixreg_pre_v32) = opval;
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+
+ }
+ ENDSWITCH (sem) /* End of semantic switch. */
+
+ /* At this point `vpc' contains the next insn to execute. */
+}
+
+#undef DEFINE_SWITCH
+#endif /* DEFINE_SWITCH */
--- /dev/null
+/* Simulator instruction semantics for crisv32f.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2004 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifdef DEFINE_LABELS
+
+ /* The labels have the case they have because the enum of insn types
+ is all uppercase and in the non-stdc case the insn symbol is built
+ into the enum name. */
+
+ static struct {
+ int index;
+ void *label;
+ } labels[] = {
+ { CRISV32F_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
+ { CRISV32F_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
+ { CRISV32F_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
+ { CRISV32F_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
+ { CRISV32F_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
+ { CRISV32F_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
+ { CRISV32F_INSN_MOVE_B_R, && case_sem_INSN_MOVE_B_R },
+ { CRISV32F_INSN_MOVE_W_R, && case_sem_INSN_MOVE_W_R },
+ { CRISV32F_INSN_MOVE_D_R, && case_sem_INSN_MOVE_D_R },
+ { CRISV32F_INSN_MOVEQ, && case_sem_INSN_MOVEQ },
+ { CRISV32F_INSN_MOVS_B_R, && case_sem_INSN_MOVS_B_R },
+ { CRISV32F_INSN_MOVS_W_R, && case_sem_INSN_MOVS_W_R },
+ { CRISV32F_INSN_MOVU_B_R, && case_sem_INSN_MOVU_B_R },
+ { CRISV32F_INSN_MOVU_W_R, && case_sem_INSN_MOVU_W_R },
+ { CRISV32F_INSN_MOVECBR, && case_sem_INSN_MOVECBR },
+ { CRISV32F_INSN_MOVECWR, && case_sem_INSN_MOVECWR },
+ { CRISV32F_INSN_MOVECDR, && case_sem_INSN_MOVECDR },
+ { CRISV32F_INSN_MOVSCBR, && case_sem_INSN_MOVSCBR },
+ { CRISV32F_INSN_MOVSCWR, && case_sem_INSN_MOVSCWR },
+ { CRISV32F_INSN_MOVUCBR, && case_sem_INSN_MOVUCBR },
+ { CRISV32F_INSN_MOVUCWR, && case_sem_INSN_MOVUCWR },
+ { CRISV32F_INSN_ADDQ, && case_sem_INSN_ADDQ },
+ { CRISV32F_INSN_SUBQ, && case_sem_INSN_SUBQ },
+ { CRISV32F_INSN_CMP_R_B_R, && case_sem_INSN_CMP_R_B_R },
+ { CRISV32F_INSN_CMP_R_W_R, && case_sem_INSN_CMP_R_W_R },
+ { CRISV32F_INSN_CMP_R_D_R, && case_sem_INSN_CMP_R_D_R },
+ { CRISV32F_INSN_CMP_M_B_M, && case_sem_INSN_CMP_M_B_M },
+ { CRISV32F_INSN_CMP_M_W_M, && case_sem_INSN_CMP_M_W_M },
+ { CRISV32F_INSN_CMP_M_D_M, && case_sem_INSN_CMP_M_D_M },
+ { CRISV32F_INSN_CMPCBR, && case_sem_INSN_CMPCBR },
+ { CRISV32F_INSN_CMPCWR, && case_sem_INSN_CMPCWR },
+ { CRISV32F_INSN_CMPCDR, && case_sem_INSN_CMPCDR },
+ { CRISV32F_INSN_CMPQ, && case_sem_INSN_CMPQ },
+ { CRISV32F_INSN_CMPS_M_B_M, && case_sem_INSN_CMPS_M_B_M },
+ { CRISV32F_INSN_CMPS_M_W_M, && case_sem_INSN_CMPS_M_W_M },
+ { CRISV32F_INSN_CMPSCBR, && case_sem_INSN_CMPSCBR },
+ { CRISV32F_INSN_CMPSCWR, && case_sem_INSN_CMPSCWR },
+ { CRISV32F_INSN_CMPU_M_B_M, && case_sem_INSN_CMPU_M_B_M },
+ { CRISV32F_INSN_CMPU_M_W_M, && case_sem_INSN_CMPU_M_W_M },
+ { CRISV32F_INSN_CMPUCBR, && case_sem_INSN_CMPUCBR },
+ { CRISV32F_INSN_CMPUCWR, && case_sem_INSN_CMPUCWR },
+ { CRISV32F_INSN_MOVE_M_B_M, && case_sem_INSN_MOVE_M_B_M },
+ { CRISV32F_INSN_MOVE_M_W_M, && case_sem_INSN_MOVE_M_W_M },
+ { CRISV32F_INSN_MOVE_M_D_M, && case_sem_INSN_MOVE_M_D_M },
+ { CRISV32F_INSN_MOVS_M_B_M, && case_sem_INSN_MOVS_M_B_M },
+ { CRISV32F_INSN_MOVS_M_W_M, && case_sem_INSN_MOVS_M_W_M },
+ { CRISV32F_INSN_MOVU_M_B_M, && case_sem_INSN_MOVU_M_B_M },
+ { CRISV32F_INSN_MOVU_M_W_M, && case_sem_INSN_MOVU_M_W_M },
+ { CRISV32F_INSN_MOVE_R_SPRV32, && case_sem_INSN_MOVE_R_SPRV32 },
+ { CRISV32F_INSN_MOVE_SPR_RV32, && case_sem_INSN_MOVE_SPR_RV32 },
+ { CRISV32F_INSN_MOVE_M_SPRV32, && case_sem_INSN_MOVE_M_SPRV32 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P0, && case_sem_INSN_MOVE_C_SPRV32_P0 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P1, && case_sem_INSN_MOVE_C_SPRV32_P1 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P2, && case_sem_INSN_MOVE_C_SPRV32_P2 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P3, && case_sem_INSN_MOVE_C_SPRV32_P3 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P4, && case_sem_INSN_MOVE_C_SPRV32_P4 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P5, && case_sem_INSN_MOVE_C_SPRV32_P5 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P6, && case_sem_INSN_MOVE_C_SPRV32_P6 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P7, && case_sem_INSN_MOVE_C_SPRV32_P7 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P8, && case_sem_INSN_MOVE_C_SPRV32_P8 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P9, && case_sem_INSN_MOVE_C_SPRV32_P9 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P10, && case_sem_INSN_MOVE_C_SPRV32_P10 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P11, && case_sem_INSN_MOVE_C_SPRV32_P11 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P12, && case_sem_INSN_MOVE_C_SPRV32_P12 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P13, && case_sem_INSN_MOVE_C_SPRV32_P13 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P14, && case_sem_INSN_MOVE_C_SPRV32_P14 },
+ { CRISV32F_INSN_MOVE_C_SPRV32_P15, && case_sem_INSN_MOVE_C_SPRV32_P15 },
+ { CRISV32F_INSN_MOVE_SPR_MV32, && case_sem_INSN_MOVE_SPR_MV32 },
+ { CRISV32F_INSN_MOVE_SS_R, && case_sem_INSN_MOVE_SS_R },
+ { CRISV32F_INSN_MOVE_R_SS, && case_sem_INSN_MOVE_R_SS },
+ { CRISV32F_INSN_MOVEM_R_M_V32, && case_sem_INSN_MOVEM_R_M_V32 },
+ { CRISV32F_INSN_MOVEM_M_R_V32, && case_sem_INSN_MOVEM_M_R_V32 },
+ { CRISV32F_INSN_ADD_B_R, && case_sem_INSN_ADD_B_R },
+ { CRISV32F_INSN_ADD_W_R, && case_sem_INSN_ADD_W_R },
+ { CRISV32F_INSN_ADD_D_R, && case_sem_INSN_ADD_D_R },
+ { CRISV32F_INSN_ADD_M_B_M, && case_sem_INSN_ADD_M_B_M },
+ { CRISV32F_INSN_ADD_M_W_M, && case_sem_INSN_ADD_M_W_M },
+ { CRISV32F_INSN_ADD_M_D_M, && case_sem_INSN_ADD_M_D_M },
+ { CRISV32F_INSN_ADDCBR, && case_sem_INSN_ADDCBR },
+ { CRISV32F_INSN_ADDCWR, && case_sem_INSN_ADDCWR },
+ { CRISV32F_INSN_ADDCDR, && case_sem_INSN_ADDCDR },
+ { CRISV32F_INSN_ADDS_B_R, && case_sem_INSN_ADDS_B_R },
+ { CRISV32F_INSN_ADDS_W_R, && case_sem_INSN_ADDS_W_R },
+ { CRISV32F_INSN_ADDS_M_B_M, && case_sem_INSN_ADDS_M_B_M },
+ { CRISV32F_INSN_ADDS_M_W_M, && case_sem_INSN_ADDS_M_W_M },
+ { CRISV32F_INSN_ADDSCBR, && case_sem_INSN_ADDSCBR },
+ { CRISV32F_INSN_ADDSCWR, && case_sem_INSN_ADDSCWR },
+ { CRISV32F_INSN_ADDU_B_R, && case_sem_INSN_ADDU_B_R },
+ { CRISV32F_INSN_ADDU_W_R, && case_sem_INSN_ADDU_W_R },
+ { CRISV32F_INSN_ADDU_M_B_M, && case_sem_INSN_ADDU_M_B_M },
+ { CRISV32F_INSN_ADDU_M_W_M, && case_sem_INSN_ADDU_M_W_M },
+ { CRISV32F_INSN_ADDUCBR, && case_sem_INSN_ADDUCBR },
+ { CRISV32F_INSN_ADDUCWR, && case_sem_INSN_ADDUCWR },
+ { CRISV32F_INSN_SUB_B_R, && case_sem_INSN_SUB_B_R },
+ { CRISV32F_INSN_SUB_W_R, && case_sem_INSN_SUB_W_R },
+ { CRISV32F_INSN_SUB_D_R, && case_sem_INSN_SUB_D_R },
+ { CRISV32F_INSN_SUB_M_B_M, && case_sem_INSN_SUB_M_B_M },
+ { CRISV32F_INSN_SUB_M_W_M, && case_sem_INSN_SUB_M_W_M },
+ { CRISV32F_INSN_SUB_M_D_M, && case_sem_INSN_SUB_M_D_M },
+ { CRISV32F_INSN_SUBCBR, && case_sem_INSN_SUBCBR },
+ { CRISV32F_INSN_SUBCWR, && case_sem_INSN_SUBCWR },
+ { CRISV32F_INSN_SUBCDR, && case_sem_INSN_SUBCDR },
+ { CRISV32F_INSN_SUBS_B_R, && case_sem_INSN_SUBS_B_R },
+ { CRISV32F_INSN_SUBS_W_R, && case_sem_INSN_SUBS_W_R },
+ { CRISV32F_INSN_SUBS_M_B_M, && case_sem_INSN_SUBS_M_B_M },
+ { CRISV32F_INSN_SUBS_M_W_M, && case_sem_INSN_SUBS_M_W_M },
+ { CRISV32F_INSN_SUBSCBR, && case_sem_INSN_SUBSCBR },
+ { CRISV32F_INSN_SUBSCWR, && case_sem_INSN_SUBSCWR },
+ { CRISV32F_INSN_SUBU_B_R, && case_sem_INSN_SUBU_B_R },
+ { CRISV32F_INSN_SUBU_W_R, && case_sem_INSN_SUBU_W_R },
+ { CRISV32F_INSN_SUBU_M_B_M, && case_sem_INSN_SUBU_M_B_M },
+ { CRISV32F_INSN_SUBU_M_W_M, && case_sem_INSN_SUBU_M_W_M },
+ { CRISV32F_INSN_SUBUCBR, && case_sem_INSN_SUBUCBR },
+ { CRISV32F_INSN_SUBUCWR, && case_sem_INSN_SUBUCWR },
+ { CRISV32F_INSN_ADDC_R, && case_sem_INSN_ADDC_R },
+ { CRISV32F_INSN_ADDC_M, && case_sem_INSN_ADDC_M },
+ { CRISV32F_INSN_ADDC_C, && case_sem_INSN_ADDC_C },
+ { CRISV32F_INSN_LAPC_D, && case_sem_INSN_LAPC_D },
+ { CRISV32F_INSN_LAPCQ, && case_sem_INSN_LAPCQ },
+ { CRISV32F_INSN_ADDI_B_R, && case_sem_INSN_ADDI_B_R },
+ { CRISV32F_INSN_ADDI_W_R, && case_sem_INSN_ADDI_W_R },
+ { CRISV32F_INSN_ADDI_D_R, && case_sem_INSN_ADDI_D_R },
+ { CRISV32F_INSN_NEG_B_R, && case_sem_INSN_NEG_B_R },
+ { CRISV32F_INSN_NEG_W_R, && case_sem_INSN_NEG_W_R },
+ { CRISV32F_INSN_NEG_D_R, && case_sem_INSN_NEG_D_R },
+ { CRISV32F_INSN_TEST_M_B_M, && case_sem_INSN_TEST_M_B_M },
+ { CRISV32F_INSN_TEST_M_W_M, && case_sem_INSN_TEST_M_W_M },
+ { CRISV32F_INSN_TEST_M_D_M, && case_sem_INSN_TEST_M_D_M },
+ { CRISV32F_INSN_MOVE_R_M_B_M, && case_sem_INSN_MOVE_R_M_B_M },
+ { CRISV32F_INSN_MOVE_R_M_W_M, && case_sem_INSN_MOVE_R_M_W_M },
+ { CRISV32F_INSN_MOVE_R_M_D_M, && case_sem_INSN_MOVE_R_M_D_M },
+ { CRISV32F_INSN_MULS_B, && case_sem_INSN_MULS_B },
+ { CRISV32F_INSN_MULS_W, && case_sem_INSN_MULS_W },
+ { CRISV32F_INSN_MULS_D, && case_sem_INSN_MULS_D },
+ { CRISV32F_INSN_MULU_B, && case_sem_INSN_MULU_B },
+ { CRISV32F_INSN_MULU_W, && case_sem_INSN_MULU_W },
+ { CRISV32F_INSN_MULU_D, && case_sem_INSN_MULU_D },
+ { CRISV32F_INSN_MCP, && case_sem_INSN_MCP },
+ { CRISV32F_INSN_DSTEP, && case_sem_INSN_DSTEP },
+ { CRISV32F_INSN_ABS, && case_sem_INSN_ABS },
+ { CRISV32F_INSN_AND_B_R, && case_sem_INSN_AND_B_R },
+ { CRISV32F_INSN_AND_W_R, && case_sem_INSN_AND_W_R },
+ { CRISV32F_INSN_AND_D_R, && case_sem_INSN_AND_D_R },
+ { CRISV32F_INSN_AND_M_B_M, && case_sem_INSN_AND_M_B_M },
+ { CRISV32F_INSN_AND_M_W_M, && case_sem_INSN_AND_M_W_M },
+ { CRISV32F_INSN_AND_M_D_M, && case_sem_INSN_AND_M_D_M },
+ { CRISV32F_INSN_ANDCBR, && case_sem_INSN_ANDCBR },
+ { CRISV32F_INSN_ANDCWR, && case_sem_INSN_ANDCWR },
+ { CRISV32F_INSN_ANDCDR, && case_sem_INSN_ANDCDR },
+ { CRISV32F_INSN_ANDQ, && case_sem_INSN_ANDQ },
+ { CRISV32F_INSN_ORR_B_R, && case_sem_INSN_ORR_B_R },
+ { CRISV32F_INSN_ORR_W_R, && case_sem_INSN_ORR_W_R },
+ { CRISV32F_INSN_ORR_D_R, && case_sem_INSN_ORR_D_R },
+ { CRISV32F_INSN_OR_M_B_M, && case_sem_INSN_OR_M_B_M },
+ { CRISV32F_INSN_OR_M_W_M, && case_sem_INSN_OR_M_W_M },
+ { CRISV32F_INSN_OR_M_D_M, && case_sem_INSN_OR_M_D_M },
+ { CRISV32F_INSN_ORCBR, && case_sem_INSN_ORCBR },
+ { CRISV32F_INSN_ORCWR, && case_sem_INSN_ORCWR },
+ { CRISV32F_INSN_ORCDR, && case_sem_INSN_ORCDR },
+ { CRISV32F_INSN_ORQ, && case_sem_INSN_ORQ },
+ { CRISV32F_INSN_XOR, && case_sem_INSN_XOR },
+ { CRISV32F_INSN_SWAP, && case_sem_INSN_SWAP },
+ { CRISV32F_INSN_ASRR_B_R, && case_sem_INSN_ASRR_B_R },
+ { CRISV32F_INSN_ASRR_W_R, && case_sem_INSN_ASRR_W_R },
+ { CRISV32F_INSN_ASRR_D_R, && case_sem_INSN_ASRR_D_R },
+ { CRISV32F_INSN_ASRQ, && case_sem_INSN_ASRQ },
+ { CRISV32F_INSN_LSRR_B_R, && case_sem_INSN_LSRR_B_R },
+ { CRISV32F_INSN_LSRR_W_R, && case_sem_INSN_LSRR_W_R },
+ { CRISV32F_INSN_LSRR_D_R, && case_sem_INSN_LSRR_D_R },
+ { CRISV32F_INSN_LSRQ, && case_sem_INSN_LSRQ },
+ { CRISV32F_INSN_LSLR_B_R, && case_sem_INSN_LSLR_B_R },
+ { CRISV32F_INSN_LSLR_W_R, && case_sem_INSN_LSLR_W_R },
+ { CRISV32F_INSN_LSLR_D_R, && case_sem_INSN_LSLR_D_R },
+ { CRISV32F_INSN_LSLQ, && case_sem_INSN_LSLQ },
+ { CRISV32F_INSN_BTST, && case_sem_INSN_BTST },
+ { CRISV32F_INSN_BTSTQ, && case_sem_INSN_BTSTQ },
+ { CRISV32F_INSN_SETF, && case_sem_INSN_SETF },
+ { CRISV32F_INSN_CLEARF, && case_sem_INSN_CLEARF },
+ { CRISV32F_INSN_RFE, && case_sem_INSN_RFE },
+ { CRISV32F_INSN_SFE, && case_sem_INSN_SFE },
+ { CRISV32F_INSN_RFG, && case_sem_INSN_RFG },
+ { CRISV32F_INSN_RFN, && case_sem_INSN_RFN },
+ { CRISV32F_INSN_HALT, && case_sem_INSN_HALT },
+ { CRISV32F_INSN_BCC_B, && case_sem_INSN_BCC_B },
+ { CRISV32F_INSN_BA_B, && case_sem_INSN_BA_B },
+ { CRISV32F_INSN_BCC_W, && case_sem_INSN_BCC_W },
+ { CRISV32F_INSN_BA_W, && case_sem_INSN_BA_W },
+ { CRISV32F_INSN_JAS_R, && case_sem_INSN_JAS_R },
+ { CRISV32F_INSN_JAS_C, && case_sem_INSN_JAS_C },
+ { CRISV32F_INSN_JUMP_P, && case_sem_INSN_JUMP_P },
+ { CRISV32F_INSN_BAS_C, && case_sem_INSN_BAS_C },
+ { CRISV32F_INSN_JASC_R, && case_sem_INSN_JASC_R },
+ { CRISV32F_INSN_JASC_C, && case_sem_INSN_JASC_C },
+ { CRISV32F_INSN_BASC_C, && case_sem_INSN_BASC_C },
+ { CRISV32F_INSN_BREAK, && case_sem_INSN_BREAK },
+ { CRISV32F_INSN_BOUND_R_B_R, && case_sem_INSN_BOUND_R_B_R },
+ { CRISV32F_INSN_BOUND_R_W_R, && case_sem_INSN_BOUND_R_W_R },
+ { CRISV32F_INSN_BOUND_R_D_R, && case_sem_INSN_BOUND_R_D_R },
+ { CRISV32F_INSN_BOUND_CB, && case_sem_INSN_BOUND_CB },
+ { CRISV32F_INSN_BOUND_CW, && case_sem_INSN_BOUND_CW },
+ { CRISV32F_INSN_BOUND_CD, && case_sem_INSN_BOUND_CD },
+ { CRISV32F_INSN_SCC, && case_sem_INSN_SCC },
+ { CRISV32F_INSN_LZ, && case_sem_INSN_LZ },
+ { CRISV32F_INSN_ADDOQ, && case_sem_INSN_ADDOQ },
+ { CRISV32F_INSN_ADDO_M_B_M, && case_sem_INSN_ADDO_M_B_M },
+ { CRISV32F_INSN_ADDO_M_W_M, && case_sem_INSN_ADDO_M_W_M },
+ { CRISV32F_INSN_ADDO_M_D_M, && case_sem_INSN_ADDO_M_D_M },
+ { CRISV32F_INSN_ADDO_CB, && case_sem_INSN_ADDO_CB },
+ { CRISV32F_INSN_ADDO_CW, && case_sem_INSN_ADDO_CW },
+ { CRISV32F_INSN_ADDO_CD, && case_sem_INSN_ADDO_CD },
+ { CRISV32F_INSN_ADDI_ACR_B_R, && case_sem_INSN_ADDI_ACR_B_R },
+ { CRISV32F_INSN_ADDI_ACR_W_R, && case_sem_INSN_ADDI_ACR_W_R },
+ { CRISV32F_INSN_ADDI_ACR_D_R, && case_sem_INSN_ADDI_ACR_D_R },
+ { CRISV32F_INSN_FIDXI, && case_sem_INSN_FIDXI },
+ { CRISV32F_INSN_FTAGI, && case_sem_INSN_FTAGI },
+ { CRISV32F_INSN_FIDXD, && case_sem_INSN_FIDXD },
+ { CRISV32F_INSN_FTAGD, && case_sem_INSN_FTAGD },
+ { 0, 0 }
+ };
+ int i;
+
+ for (i = 0; labels[i].label != 0; ++i)
+ {
+#if FAST_P
+ CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
+#else
+ CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
+#endif
+ }
+
+#undef DEFINE_LABELS
+#endif /* DEFINE_LABELS */
+
+#ifdef DEFINE_SWITCH
+
+/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
+ off frills like tracing and profiling. */
+/* FIXME: A better way would be to have TRACE_RESULT check for something
+ that can cause it to be optimized out. Another way would be to emit
+ special handlers into the instruction "stream". */
+
+#if FAST_P
+#undef TRACE_RESULT
+#define TRACE_RESULT(cpu, abuf, name, type, val)
+#endif
+
+#undef GET_ATTR
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
+#else
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
+#endif
+
+{
+
+#if WITH_SCACHE_PBB
+
+/* Branch to next handler without going around main loop. */
+#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
+SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
+
+#else /* ! WITH_SCACHE_PBB */
+
+#define NEXT(vpc) BREAK (sem)
+#ifdef __GNUC__
+#if FAST_P
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
+#else
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
+#endif
+#else
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
+#endif
+
+#endif /* ! WITH_SCACHE_PBB */
+
+ {
+
+ CASE (sem, INSN_X_INVALID) : /* --invalid-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+ /* Update the recorded pc in the cpu state struct.
+ Only necessary for WITH_SCACHE case, but to avoid the
+ conditional compilation .... */
+ SET_H_PC (pc);
+ /* Virtual insns have zero size. Overwrite vpc with address of next insn
+ using the default-insn-bitsize spec. When executing insns in parallel
+ we may want to queue the fault and continue execution. */
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+ vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_AFTER) : /* --after-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_CRISV32F
+ crisv32f_pbb_after (current_cpu, sem_arg);
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_BEFORE) : /* --before-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_CRISV32F
+ crisv32f_pbb_before (current_cpu, sem_arg);
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_CRISV32F
+#ifdef DEFINE_SWITCH
+ vpc = crisv32f_pbb_cti_chain (current_cpu, sem_arg,
+ pbb_br_type, pbb_br_npc);
+ BREAK (sem);
+#else
+ /* FIXME: Allow provision of explicit ifmt spec in insn spec. */
+ vpc = crisv32f_pbb_cti_chain (current_cpu, sem_arg,
+ CPU_PBB_BR_TYPE (current_cpu),
+ CPU_PBB_BR_NPC (current_cpu));
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_CHAIN) : /* --chain-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_CRISV32F
+ vpc = crisv32f_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+ BREAK (sem);
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_BEGIN) : /* --begin-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_CRISV32F
+#if defined DEFINE_SWITCH || defined FAST_P
+ /* In the switch case FAST_P is a constant, allowing several optimizations
+ in any called inline functions. */
+ vpc = crisv32f_pbb_begin (current_cpu, FAST_P);
+#else
+#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
+ vpc = crisv32f_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#else
+ vpc = crisv32f_pbb_begin (current_cpu, 0);
+#endif
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_B_R) : /* move.b move.m ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_newval;
+ tmp_newval = GET_H_GR (FLD (f_operand1));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_W_R) : /* move.w move.m ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_newval;
+ tmp_newval = GET_H_GR (FLD (f_operand1));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_D_R) : /* move.d move.m ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_newval;
+ tmp_newval = GET_H_GR (FLD (f_operand1));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVEQ) : /* moveq $i,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_moveq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_newval;
+ tmp_newval = FLD (f_s6);
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+SET_H_NBIT_MOVE (LTSI (tmp_newval, 0));
+SET_H_ZBIT_MOVE (ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))));
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVS_B_R) : /* movs.b movs.m ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_newval;
+ tmp_newval = GET_H_GR (FLD (f_operand1));
+ {
+ SI opval = EXTQISI (tmp_newval);
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVS_W_R) : /* movs.w movs.m ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_newval;
+ tmp_newval = GET_H_GR (FLD (f_operand1));
+ {
+ SI opval = EXTHISI (tmp_newval);
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVU_B_R) : /* movu.b movu.m ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_newval;
+ tmp_newval = GET_H_GR (FLD (f_operand1));
+ {
+ SI opval = ZEXTQISI (tmp_newval);
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVU_W_R) : /* movu.w movu.m ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_newval;
+ tmp_newval = GET_H_GR (FLD (f_operand1));
+ {
+ SI opval = ZEXTHISI (tmp_newval);
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVECBR) : /* move.b ${sconst8},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_newval;
+ tmp_newval = FLD (f_indir_pc__byte);
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVECWR) : /* move.w ${sconst16},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_newval;
+ tmp_newval = FLD (f_indir_pc__word);
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVECDR) : /* move.d ${const32},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ SI tmp_newval;
+ tmp_newval = FLD (f_indir_pc__dword);
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVSCBR) : /* movs.b ${sconst8},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_newval;
+ tmp_newval = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVSCWR) : /* movs.w ${sconst16},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_newval;
+ tmp_newval = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVUCBR) : /* movu.b ${uconst8},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_newval;
+ tmp_newval = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVUCWR) : /* movu.w ${uconst16},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_newval;
+ tmp_newval = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDQ) : /* addq $j,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = FLD (f_u6);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBQ) : /* subq $j,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = FLD (f_u6);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_R_B_R) : /* cmp-r.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_R_W_R) : /* cmp-r.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_R_D_R) : /* cmp-r.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_M_B_M) : /* cmp-m.b [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_M_W_M) : /* cmp-m.w [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMP_M_D_M) : /* cmp-m.d [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPCBR) : /* cmp.b $sconst8,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = TRUNCSIQI (FLD (f_indir_pc__byte));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPCWR) : /* cmp.w $sconst16,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = TRUNCSIHI (FLD (f_indir_pc__word));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPCDR) : /* cmp.d $const32,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = FLD (f_indir_pc__dword);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPQ) : /* cmpq $i,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_andq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = FLD (f_s6);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPS_M_B_M) : /* cmps-m.b [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPS_M_W_M) : /* cmps-m.w [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPSCBR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPSCWR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPU_M_B_M) : /* cmpu-m.b [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPU_M_W_M) : /* cmpu-m.w [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPUCBR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPUCWR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_M_B_M) : /* move-m.b [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = ({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmp, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmp, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_M_W_M) : /* move-m.w [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = ({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmp, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmp, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_M_D_M) : /* move-m.d [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmp, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVS_M_B_M) : /* movs-m.b [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = EXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (FLD (f_operand2), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTSI (tmp_tmp, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVS_M_W_M) : /* movs-m.w [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = EXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (FLD (f_operand2), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTSI (tmp_tmp, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVU_M_B_M) : /* movu-m.b [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = ZEXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (FLD (f_operand2), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTSI (tmp_tmp, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVU_M_W_M) : /* movu-m.w [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = ZEXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) {
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+} else {
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (FLD (f_operand2), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTSI (tmp_tmp, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_R_SPRV32) : /* move ${Rs},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ SI tmp_rno;
+ tmp_tmp = GET_H_GR (FLD (f_operand1));
+ tmp_rno = FLD (f_operand2);
+if (ORIF (ORIF (EQSI (tmp_rno, 0), EQSI (tmp_rno, 1)), ORIF (EQSI (tmp_rno, 4), EQSI (tmp_rno, 8)))) {
+cgen_rtx_error (current_cpu, "move-r-spr: trying to set a read-only special register");
+}
+ else {
+ {
+ SI opval = tmp_tmp;
+ SET_H_SR (FLD (f_operand2), opval);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_SPR_RV32) : /* move ${Ps},${Rd-sfield} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_grno;
+ SI tmp_prno;
+ SI tmp_newval;
+ tmp_prno = FLD (f_operand2);
+ tmp_newval = GET_H_SR (FLD (f_operand2));
+if (EQSI (tmp_prno, 0)) {
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+ else if (EQSI (tmp_prno, 1)) {
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+ else if (EQSI (tmp_prno, 2)) {
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+ else if (EQSI (tmp_prno, 3)) {
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+ else if (EQSI (tmp_prno, 4)) {
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+ else if (EQSI (tmp_prno, 5)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 6)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 7)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 8)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 9)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 10)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 11)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 12)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 13)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 14)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else if (EQSI (tmp_prno, 15)) {
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+ else {
+cgen_rtx_error (current_cpu, "move-spr-r from unimplemented register");
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_M_SPRV32) : /* move [${Rs}${inc}],${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_rno;
+ SI tmp_newval;
+ tmp_rno = FLD (f_operand2);
+if (EQSI (tmp_rno, 0)) {
+ tmp_newval = EXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+}
+ else if (EQSI (tmp_rno, 1)) {
+ tmp_newval = EXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+}
+ else if (EQSI (tmp_rno, 2)) {
+ tmp_newval = EXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+}
+ else if (EQSI (tmp_rno, 3)) {
+ tmp_newval = EXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+}
+ else if (EQSI (tmp_rno, 4)) {
+ tmp_newval = EXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+}
+ else if (EQSI (tmp_rno, 5)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 6)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 7)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 8)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 9)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 10)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 11)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 12)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 13)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 14)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else if (EQSI (tmp_rno, 15)) {
+ tmp_newval = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+}
+ else {
+cgen_rtx_error (current_cpu, "Trying to set unimplemented special register");
+}
+ {
+ SI opval = tmp_newval;
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P0) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P1) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P2) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P3) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P4) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P5) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P6) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P7) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P8) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P9) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P10) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P11) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P12) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P13) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P14) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_C_SPRV32_P15) : /* move ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (f_indir_pc__dword);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_SPR_MV32) : /* move ${Ps},[${Rd-sfield}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_rno;
+ tmp_rno = FLD (f_operand2);
+if (EQSI (tmp_rno, 0)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ QI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ QI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 1)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ QI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ QI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 2)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ QI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ QI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 3)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ QI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ QI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 4)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ HI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMHI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ HI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMHI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 5)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 6)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 7)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 8)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 9)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 10)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 11)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 12)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 13)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 14)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else if (EQSI (tmp_rno, 15)) {
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = GET_H_SR (FLD (f_operand2));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+}
+ else {
+cgen_rtx_error (current_cpu, "write from unimplemented special register");
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_SS_R) : /* move ${Ss},${Rd-sfield} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = GET_H_SUPR (FLD (f_operand2));
+ SET_H_GR (FLD (f_operand1), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_R_SS) : /* move ${Rs},${Sd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = GET_H_GR (FLD (f_operand1));
+ SET_H_SUPR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "supr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVEM_R_M_V32) : /* movem ${Rs-dfield},[${Rd-sfield}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movem_r_m_v32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+{
+ SI tmp_dummy;
+ tmp_dummy = GET_H_GR (FLD (f_operand2));
+}
+ tmp_addr = GET_H_GR (FLD (f_operand1));
+{
+if (GESI (FLD (f_operand2), 0)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 0));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 1)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 1));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 2)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 2));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 3)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 3));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 4)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 4));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 5)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 5));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 6)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 6));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 7)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 7));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 8)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 8));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 9)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 9));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 10)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 10));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 11)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 11));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 12)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 12));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 13)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 13));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 14)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 14));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 15)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (((UINT) 15));
+ {
+ SI opval = tmp_tmp;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+}
+if (NEBI (tmp_postinc, 0)) {
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVEM_M_R_V32) : /* movem [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movem_m_r_v32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = GET_H_GR (FLD (f_operand1));
+{
+ SI tmp_dummy;
+ tmp_dummy = GET_H_GR (FLD (f_operand2));
+}
+{
+if (GESI (FLD (f_operand2), 0)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 0), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 1)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 1), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 2)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 2), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 3)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 3), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 4)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 4), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 5)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 5), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 6)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 6), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 7)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 7), opval);
+ written |= (1 << 19);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 8)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 8), opval);
+ written |= (1 << 20);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 9)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 9), opval);
+ written |= (1 << 21);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 10)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 10), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 11)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 11), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 12)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 12), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 13)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 13), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 14)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 14), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+if (GESI (FLD (f_operand2), 15)) {
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr);
+ {
+ SI opval = tmp_tmp;
+ SET_H_GR (((UINT) 15), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+}
+}
+if (NEBI (tmp_postinc, 0)) {
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 5);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_B_R) : /* add.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_W_R) : /* add.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_D_R) : /* add.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_M_B_M) : /* add-m.b [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_M_W_M) : /* add-m.w [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_M_D_M) : /* add-m.d [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDCBR) : /* add.b ${sconst8}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = FLD (f_indir_pc__byte);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDCWR) : /* add.w ${sconst16}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = FLD (f_indir_pc__word);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDCDR) : /* add.d ${const32}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = FLD (f_indir_pc__dword);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_B_R) : /* adds.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_W_R) : /* adds.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_M_B_M) : /* adds-m.b [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDS_M_W_M) : /* adds-m.w [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDSCBR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDSCWR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDU_B_R) : /* addu.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDU_W_R) : /* addu.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDU_M_B_M) : /* addu-m.b [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDU_M_W_M) : /* addu-m.w [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDUCBR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDUCWR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_B_R) : /* sub.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_W_R) : /* sub.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_D_R) : /* sub.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_M_B_M) : /* sub-m.b [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_M_W_M) : /* sub-m.w [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_M_D_M) : /* sub-m.d [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBCBR) : /* sub.b ${sconst8}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = FLD (f_indir_pc__byte);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBCWR) : /* sub.w ${sconst16}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = FLD (f_indir_pc__word);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBCDR) : /* sub.d ${const32}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = FLD (f_indir_pc__dword);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_B_R) : /* subs.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_W_R) : /* subs.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_M_B_M) : /* subs-m.b [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBS_M_W_M) : /* subs-m.w [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBSCBR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBSCWR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBU_B_R) : /* subu.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBU_W_R) : /* subu.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBU_M_B_M) : /* subu-m.b [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBU_M_W_M) : /* subu-m.w [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBUCBR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBUCWR) : /* [${Rs}${inc}],$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDC_R) : /* addc $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+CPU (h_xbit) = 1;
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDC_M) : /* addc [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+CPU (h_xbit) = 1;
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDC_C) : /* addc ${const32},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+CPU (h_xbit) = 1;
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = FLD (f_indir_pc__dword);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LAPC_D) : /* lapc.d ${const32-pcrel},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lapc_d.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = FLD (i_const32_pcrel);
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LAPCQ) : /* lapcq ${qo},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lapcq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = FLD (i_qo);
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDI_B_R) : /* addi.b ${Rs-dfield}.m,${Rd-sfield} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 1));
+ SET_H_GR (FLD (f_operand1), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDI_W_R) : /* addi.w ${Rs-dfield}.m,${Rd-sfield} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 2));
+ SET_H_GR (FLD (f_operand1), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDI_D_R) : /* addi.d ${Rs-dfield}.m,${Rd-sfield} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 4));
+ SET_H_GR (FLD (f_operand1), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NEG_B_R) : /* neg.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = 0;
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NEG_W_R) : /* neg.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = 0;
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NEG_D_R) : /* neg.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = GET_H_GR (FLD (f_operand1));
+ tmp_tmpopd = 0;
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TEST_M_B_M) : /* test-m.b [${Rs}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpd;
+ tmp_tmpd = ({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+{
+ QI tmp_tmpopd;
+ QI tmp_tmpops;
+ BI tmp_carry;
+ QI tmp_newval;
+ tmp_tmpops = 0;
+ tmp_tmpopd = tmp_tmpd;
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTQI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TEST_M_W_M) : /* test-m.w [${Rs}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpd;
+ tmp_tmpd = ({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+{
+ HI tmp_tmpopd;
+ HI tmp_tmpops;
+ BI tmp_carry;
+ HI tmp_newval;
+ tmp_tmpops = 0;
+ tmp_tmpopd = tmp_tmpd;
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTHI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TEST_M_D_M) : /* test-m.d [${Rs}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = 0;
+ tmp_tmpopd = tmp_tmpd;
+ tmp_carry = CPU (h_cbit);
+ tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+((void) 0); /*nop*/
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0))));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_R_M_B_M) : /* move-r-m.b ${Rs-dfield},[${Rd-sfield}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpd;
+ tmp_tmpd = GET_H_GR (FLD (f_operand2));
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ QI opval = tmp_tmpd;
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ QI opval = tmp_tmpd;
+ SETMEMQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_R_M_W_M) : /* move-r-m.w ${Rs-dfield},[${Rd-sfield}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpd;
+ tmp_tmpd = GET_H_GR (FLD (f_operand2));
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ HI opval = tmp_tmpd;
+ SETMEMHI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ HI opval = tmp_tmpd;
+ SETMEMHI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVE_R_M_D_M) : /* move-r-m.d ${Rs-dfield},[${Rd-sfield}${inc}] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = GET_H_GR (FLD (f_operand2));
+{
+ SI tmp_addr;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+ tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) {
+if (EQBI (CPU (h_pbit), 0)) {
+{
+ {
+ SI opval = tmp_tmpd;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ BI opval = CPU (h_pbit);
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+} else {
+ {
+ SI opval = tmp_tmpd;
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULS_B) : /* muls.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_src1;
+ DI tmp_src2;
+ DI tmp_tmpr;
+ tmp_src1 = EXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
+ tmp_src2 = EXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand2))));
+ tmp_tmpr = MULDI (tmp_src1, tmp_src2);
+ {
+ SI opval = TRUNCDISI (tmp_tmpr);
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ {
+ SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
+ SET_H_SR (((UINT) 7), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTDI (tmp_tmpr, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULS_W) : /* muls.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_src1;
+ DI tmp_src2;
+ DI tmp_tmpr;
+ tmp_src1 = EXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
+ tmp_src2 = EXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand2))));
+ tmp_tmpr = MULDI (tmp_src1, tmp_src2);
+ {
+ SI opval = TRUNCDISI (tmp_tmpr);
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ {
+ SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
+ SET_H_SR (((UINT) 7), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTDI (tmp_tmpr, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULS_D) : /* muls.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_src1;
+ DI tmp_src2;
+ DI tmp_tmpr;
+ tmp_src1 = EXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand1))));
+ tmp_src2 = EXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand2))));
+ tmp_tmpr = MULDI (tmp_src1, tmp_src2);
+ {
+ SI opval = TRUNCDISI (tmp_tmpr);
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ {
+ SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
+ SET_H_SR (((UINT) 7), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTDI (tmp_tmpr, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULU_B) : /* mulu.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_src1;
+ DI tmp_src2;
+ DI tmp_tmpr;
+ tmp_src1 = ZEXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
+ tmp_src2 = ZEXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand2))));
+ tmp_tmpr = MULDI (tmp_src1, tmp_src2);
+ {
+ SI opval = TRUNCDISI (tmp_tmpr);
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ {
+ SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
+ SET_H_SR (((UINT) 7), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTDI (tmp_tmpr, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULU_W) : /* mulu.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_src1;
+ DI tmp_src2;
+ DI tmp_tmpr;
+ tmp_src1 = ZEXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
+ tmp_src2 = ZEXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand2))));
+ tmp_tmpr = MULDI (tmp_src1, tmp_src2);
+ {
+ SI opval = TRUNCDISI (tmp_tmpr);
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ {
+ SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
+ SET_H_SR (((UINT) 7), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTDI (tmp_tmpr, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULU_D) : /* mulu.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_src1;
+ DI tmp_src2;
+ DI tmp_tmpr;
+ tmp_src1 = ZEXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand1))));
+ tmp_src2 = ZEXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand2))));
+ tmp_tmpr = MULDI (tmp_src1, tmp_src2);
+ {
+ SI opval = TRUNCDISI (tmp_tmpr);
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+ {
+ SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32));
+ SET_H_SR (((UINT) 7), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+{
+ {
+ BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit));
+ CPU (h_cbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+ {
+ BI opval = LTDI (tmp_tmpr, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MCP) : /* mcp $Ps,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+CPU (h_xbit) = 1;
+CPU (h_zbit) = 1;
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ BI tmp_carry;
+ SI tmp_newval;
+ tmp_tmpops = GET_H_SR (FLD (f_operand2));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand1));
+ tmp_carry = CPU (h_rbit);
+ tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry)));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand1), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0))));
+ CPU (h_rbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "rbit", 'x', opval);
+ }
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit))));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+ {
+ BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0)));
+ CPU (h_vbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DSTEP) : /* dstep $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ SI tmp_tmps;
+ SI tmp_tmpd;
+ tmp_tmps = GET_H_GR (FLD (f_operand1));
+ tmp_tmp = SLLSI (GET_H_GR (FLD (f_operand2)), 1);
+ tmp_tmpd = ((GEUSI (tmp_tmp, tmp_tmps)) ? (SUBSI (tmp_tmp, tmp_tmps)) : (tmp_tmp));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ABS) : /* abs $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ABSSI (GET_H_GR (FLD (f_operand1)));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_B_R) : /* and.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpd;
+ tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_W_R) : /* and.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpd;
+ tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_D_R) : /* and.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_M_B_M) : /* and-m.b [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpd;
+ tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), ({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_M_W_M) : /* and-m.w [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpd;
+ tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), ({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_M_D_M) : /* and-m.d [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ANDCBR) : /* and.b ${sconst8}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_tmpd;
+ tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__byte));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ANDCWR) : /* and.w ${sconst16}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_tmpd;
+ tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__word));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ANDCDR) : /* and.d ${const32}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ANDQ) : /* andq $i,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_andq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), FLD (f_s6));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORR_B_R) : /* orr.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpd;
+ tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORR_W_R) : /* orr.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpd;
+ tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORR_D_R) : /* orr.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR_M_B_M) : /* or-m.b [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpd;
+ tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), ({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR_M_W_M) : /* or-m.w [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpd;
+ tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), ({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR_M_D_M) : /* or-m.d [${Rs}${inc}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; }));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORCBR) : /* or.b ${sconst8}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcbr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_tmpd;
+ tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__byte));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORCWR) : /* or.w ${sconst16}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcwr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_tmpd;
+ tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__word));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORCDR) : /* or.d ${const32}],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addcdr.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORQ) : /* orq $i,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_andq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), FLD (f_s6));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XOR) : /* xor $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = XORSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1)));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SWAP) : /* swap${swapoption} ${Rs} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmps;
+ SI tmp_tmpd;
+ tmp_tmps = GET_H_GR (FLD (f_operand1));
+ tmp_tmpd = ({ SI tmp_tmpcode;
+ SI tmp_tmpval;
+ SI tmp_tmpres;
+ tmp_tmpcode = FLD (f_operand2);
+; tmp_tmpval = tmp_tmps;
+; if (EQSI (tmp_tmpcode, 0)) {
+ tmp_tmpres = (cgen_rtx_error (current_cpu, "SWAP without swap modifier isn't implemented"), 0);
+}
+ else if (EQSI (tmp_tmpcode, 1)) {
+ tmp_tmpres = ({ SI tmp_tmpr;
+ tmp_tmpr = tmp_tmpval;
+; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
+}
+ else if (EQSI (tmp_tmpcode, 2)) {
+ tmp_tmpres = ({ SI tmp_tmpb;
+ tmp_tmpb = tmp_tmpval;
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
+}
+ else if (EQSI (tmp_tmpcode, 3)) {
+ tmp_tmpres = ({ SI tmp_tmpr;
+ tmp_tmpr = ({ SI tmp_tmpb;
+ tmp_tmpb = tmp_tmpval;
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
+; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
+}
+ else if (EQSI (tmp_tmpcode, 4)) {
+ tmp_tmpres = ({ SI tmp_tmpb;
+ tmp_tmpb = tmp_tmpval;
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
+}
+ else if (EQSI (tmp_tmpcode, 5)) {
+ tmp_tmpres = ({ SI tmp_tmpr;
+ tmp_tmpr = ({ SI tmp_tmpb;
+ tmp_tmpb = tmp_tmpval;
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
+; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
+}
+ else if (EQSI (tmp_tmpcode, 6)) {
+ tmp_tmpres = ({ SI tmp_tmpb;
+ tmp_tmpb = ({ SI tmp_tmpb;
+ tmp_tmpb = tmp_tmpval;
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
+}
+ else if (EQSI (tmp_tmpcode, 7)) {
+ tmp_tmpres = ({ SI tmp_tmpr;
+ tmp_tmpr = ({ SI tmp_tmpb;
+ tmp_tmpb = ({ SI tmp_tmpb;
+ tmp_tmpb = tmp_tmpval;
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
+; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
+}
+ else if (EQSI (tmp_tmpcode, 8)) {
+ tmp_tmpres = INVSI (tmp_tmpval);
+}
+ else if (EQSI (tmp_tmpcode, 9)) {
+ tmp_tmpres = ({ SI tmp_tmpr;
+ tmp_tmpr = INVSI (tmp_tmpval);
+; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
+}
+ else if (EQSI (tmp_tmpcode, 10)) {
+ tmp_tmpres = ({ SI tmp_tmpb;
+ tmp_tmpb = INVSI (tmp_tmpval);
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
+}
+ else if (EQSI (tmp_tmpcode, 11)) {
+ tmp_tmpres = ({ SI tmp_tmpr;
+ tmp_tmpr = ({ SI tmp_tmpb;
+ tmp_tmpb = INVSI (tmp_tmpval);
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
+; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
+}
+ else if (EQSI (tmp_tmpcode, 12)) {
+ tmp_tmpres = ({ SI tmp_tmpb;
+ tmp_tmpb = INVSI (tmp_tmpval);
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
+}
+ else if (EQSI (tmp_tmpcode, 13)) {
+ tmp_tmpres = ({ SI tmp_tmpr;
+ tmp_tmpr = ({ SI tmp_tmpb;
+ tmp_tmpb = INVSI (tmp_tmpval);
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
+; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
+}
+ else if (EQSI (tmp_tmpcode, 14)) {
+ tmp_tmpres = ({ SI tmp_tmpb;
+ tmp_tmpb = ({ SI tmp_tmpb;
+ tmp_tmpb = INVSI (tmp_tmpval);
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
+}
+ else if (EQSI (tmp_tmpcode, 15)) {
+ tmp_tmpres = ({ SI tmp_tmpr;
+ tmp_tmpr = ({ SI tmp_tmpb;
+ tmp_tmpb = ({ SI tmp_tmpb;
+ tmp_tmpb = INVSI (tmp_tmpval);
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); });
+; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); });
+; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); });
+}
+; tmp_tmpres; });
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand1), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRR_B_R) : /* asrr.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmpd;
+ SI tmp_cnt1;
+ SI tmp_cnt2;
+ tmp_cnt1 = GET_H_GR (FLD (f_operand1));
+ tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
+ tmp_tmpd = SRASI (EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRR_W_R) : /* asrr.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmpd;
+ SI tmp_cnt1;
+ SI tmp_cnt2;
+ tmp_cnt1 = GET_H_GR (FLD (f_operand1));
+ tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
+ tmp_tmpd = SRASI (EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRR_D_R) : /* asrr.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_cnt1;
+ SI tmp_cnt2;
+ tmp_cnt1 = GET_H_GR (FLD (f_operand1));
+ tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31)));
+ tmp_tmpd = SRASI (EXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2);
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ASRQ) : /* asrq $c,${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_asrq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = SRASI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSRR_B_R) : /* lsrr.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_cnt;
+ tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
+ tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSRR_W_R) : /* lsrr.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_cnt;
+ tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
+ tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSRR_D_R) : /* lsrr.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_cnt;
+ tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
+ tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSRQ) : /* lsrq $c,${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_asrq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = SRLSI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSLR_B_R) : /* lslr.b $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_cnt;
+ tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
+ tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTQI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSLR_W_R) : /* lslr.w $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_cnt;
+ tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
+ tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
+{
+ SI tmp_oldregval;
+ tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2));
+ {
+ SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000));
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = LTHI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSLR_D_R) : /* lslr.d $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_cnt;
+ tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63);
+ tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31))));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LSLQ) : /* lslq $c,${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_asrq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), FLD (f_u5));
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BTST) : /* $Rs,$Rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_cnt;
+ tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), SUBSI (31, ANDSI (GET_H_GR (FLD (f_operand1)), 31)));
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BTSTQ) : /* btstq $c,${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_asrq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), SUBSI (31, FLD (f_u5)));
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SETF) : /* setf ${list-of-flags} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_setf.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = FLD (f_dstsrc);
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 0)), 0)) {
+ {
+ BI opval = 1;
+ CPU (h_cbit) = opval;
+ written |= (1 << 1);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 1)), 0)) {
+ {
+ BI opval = 1;
+ CPU (h_vbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 2)), 0)) {
+ {
+ BI opval = 1;
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 3)), 0)) {
+ {
+ BI opval = 1;
+ CPU (h_nbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
+ {
+ BI opval = 1;
+ CPU (h_xbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 5)), 0)) {
+ {
+ BI opval = 1;
+ SET_H_IBIT (opval);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "ibit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 6)), 0)) {
+ {
+ BI opval = 1;
+ SET_H_UBIT (opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "ubit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) {
+ {
+ BI opval = 1;
+ CPU (h_pbit) = opval;
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "pbit", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+if (EQSI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CLEARF) : /* clearf ${list-of-flags} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_setf.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = FLD (f_dstsrc);
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 0)), 0)) {
+ {
+ BI opval = 0;
+ CPU (h_cbit) = opval;
+ written |= (1 << 1);
+ TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 1)), 0)) {
+ {
+ BI opval = 0;
+ CPU (h_vbit) = opval;
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 2)), 0)) {
+ {
+ BI opval = 0;
+ CPU (h_zbit) = opval;
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 3)), 0)) {
+ {
+ BI opval = 0;
+ CPU (h_nbit) = opval;
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) {
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 5)), 0)) {
+ {
+ BI opval = 0;
+ SET_H_IBIT (opval);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "ibit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 6)), 0)) {
+ {
+ BI opval = 0;
+ SET_H_UBIT (opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "ubit", 'x', opval);
+ }
+}
+if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) {
+ {
+ BI opval = 0;
+ CPU (h_pbit) = opval;
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "pbit", 'x', opval);
+ }
+}
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RFE) : /* rfe */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_rfe.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ USI tmp_oldccs;
+ USI tmp_samebits;
+ USI tmp_shiftbits;
+ USI tmp_keepmask;
+ BI tmp_p1;
+ tmp_oldccs = GET_H_SR (((UINT) 13));
+ tmp_keepmask = 0xc0000000;
+ tmp_samebits = ANDSI (tmp_oldccs, tmp_keepmask);
+ tmp_shiftbits = ANDSI (SRLSI (ANDSI (tmp_oldccs, 1073609728), 10), INVSI (tmp_keepmask));
+ tmp_p1 = NESI (0, ANDSI (tmp_oldccs, 131072));
+ {
+ SI opval = ORSI (ORSI (tmp_samebits, tmp_shiftbits), ((ANDBI (CPU (h_rbit), NOTBI (tmp_p1))) ? (0) : (128)));
+ SET_H_SR (((UINT) 13), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SFE) : /* sfe */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_rfe.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_oldccs;
+ SI tmp_savemask;
+ tmp_savemask = 0xc0000000;
+ tmp_oldccs = GET_H_SR (((UINT) 13));
+ {
+ SI opval = ORSI (ANDSI (tmp_savemask, tmp_oldccs), ANDSI (INVSI (tmp_savemask), SLLSI (tmp_oldccs, 10)));
+ SET_H_SR (((UINT) 13), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RFG) : /* rfg */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+crisv32f_rfg_handler (current_cpu, pc);
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RFN) : /* rfn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_rfe.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+{
+ USI tmp_oldccs;
+ USI tmp_samebits;
+ USI tmp_shiftbits;
+ USI tmp_keepmask;
+ BI tmp_p1;
+ tmp_oldccs = GET_H_SR (((UINT) 13));
+ tmp_keepmask = 0xc0000000;
+ tmp_samebits = ANDSI (tmp_oldccs, tmp_keepmask);
+ tmp_shiftbits = ANDSI (SRLSI (ANDSI (tmp_oldccs, 1073609728), 10), INVSI (tmp_keepmask));
+ tmp_p1 = NESI (0, ANDSI (tmp_oldccs, 131072));
+ {
+ SI opval = ORSI (ORSI (tmp_samebits, tmp_shiftbits), ((ANDBI (CPU (h_rbit), NOTBI (tmp_p1))) ? (0) : (128)));
+ SET_H_SR (((UINT) 13), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+}
+ {
+ BI opval = 1;
+ SET_H_MBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "mbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_HALT) : /* halt */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ USI opval = crisv32f_halt_handler (current_cpu, pc);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCC_B) : /* b${cc} ${o-pcrel} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bcc_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_truthval;
+ tmp_truthval = ({ SI tmp_tmpcond;
+ BI tmp_condres;
+ tmp_tmpcond = FLD (f_operand2);
+; if (EQSI (tmp_tmpcond, 0)) {
+ tmp_condres = NOTBI (CPU (h_cbit));
+}
+ else if (EQSI (tmp_tmpcond, 1)) {
+ tmp_condres = CPU (h_cbit);
+}
+ else if (EQSI (tmp_tmpcond, 2)) {
+ tmp_condres = NOTBI (CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 3)) {
+ tmp_condres = CPU (h_zbit);
+}
+ else if (EQSI (tmp_tmpcond, 4)) {
+ tmp_condres = NOTBI (CPU (h_vbit));
+}
+ else if (EQSI (tmp_tmpcond, 5)) {
+ tmp_condres = CPU (h_vbit);
+}
+ else if (EQSI (tmp_tmpcond, 6)) {
+ tmp_condres = NOTBI (CPU (h_nbit));
+}
+ else if (EQSI (tmp_tmpcond, 7)) {
+ tmp_condres = CPU (h_nbit);
+}
+ else if (EQSI (tmp_tmpcond, 8)) {
+ tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 9)) {
+ tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
+}
+ else if (EQSI (tmp_tmpcond, 10)) {
+ tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
+}
+ else if (EQSI (tmp_tmpcond, 11)) {
+ tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
+}
+ else if (EQSI (tmp_tmpcond, 12)) {
+ tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
+}
+ else if (EQSI (tmp_tmpcond, 13)) {
+ tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 14)) {
+ tmp_condres = 1;
+}
+ else if (EQSI (tmp_tmpcond, 15)) {
+ tmp_condres = CPU (h_pbit);
+}
+; tmp_condres; });
+crisv32f_branch_taken (current_cpu, pc, FLD (i_o_pcrel), tmp_truthval);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+if (tmp_truthval) {
+{
+ {
+ USI opval = FLD (i_o_pcrel);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BA_B) : /* ba ${o-pcrel} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bcc_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_o_pcrel);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BCC_W) : /* b${cc} ${o-word-pcrel} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bcc_w.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ BI tmp_truthval;
+ tmp_truthval = ({ SI tmp_tmpcond;
+ BI tmp_condres;
+ tmp_tmpcond = FLD (f_operand2);
+; if (EQSI (tmp_tmpcond, 0)) {
+ tmp_condres = NOTBI (CPU (h_cbit));
+}
+ else if (EQSI (tmp_tmpcond, 1)) {
+ tmp_condres = CPU (h_cbit);
+}
+ else if (EQSI (tmp_tmpcond, 2)) {
+ tmp_condres = NOTBI (CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 3)) {
+ tmp_condres = CPU (h_zbit);
+}
+ else if (EQSI (tmp_tmpcond, 4)) {
+ tmp_condres = NOTBI (CPU (h_vbit));
+}
+ else if (EQSI (tmp_tmpcond, 5)) {
+ tmp_condres = CPU (h_vbit);
+}
+ else if (EQSI (tmp_tmpcond, 6)) {
+ tmp_condres = NOTBI (CPU (h_nbit));
+}
+ else if (EQSI (tmp_tmpcond, 7)) {
+ tmp_condres = CPU (h_nbit);
+}
+ else if (EQSI (tmp_tmpcond, 8)) {
+ tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 9)) {
+ tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
+}
+ else if (EQSI (tmp_tmpcond, 10)) {
+ tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
+}
+ else if (EQSI (tmp_tmpcond, 11)) {
+ tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
+}
+ else if (EQSI (tmp_tmpcond, 12)) {
+ tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
+}
+ else if (EQSI (tmp_tmpcond, 13)) {
+ tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 14)) {
+ tmp_condres = 1;
+}
+ else if (EQSI (tmp_tmpcond, 15)) {
+ tmp_condres = CPU (h_pbit);
+}
+; tmp_condres; });
+crisv32f_branch_taken (current_cpu, pc, FLD (i_o_word_pcrel), tmp_truthval);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+if (tmp_truthval) {
+{
+ {
+ USI opval = FLD (i_o_word_pcrel);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BA_W) : /* ba ${o-word-pcrel} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bcc_w.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = FLD (i_o_word_pcrel);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JAS_R) : /* jas ${Rs},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+if (ANDIF (EQSI (FLD (f_operand1), 1), EQSI (FLD (f_operand2), 11))) {
+cris_flush_simulator_decode_cache (current_cpu, pc);
+}
+{
+{
+ {
+ SI opval = ADDSI (pc, 4);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+ {
+ USI opval = GET_H_GR (FLD (f_operand1));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JAS_C) : /* jas ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+{
+{
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+ {
+ USI opval = FLD (f_indir_pc__dword);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JUMP_P) : /* jump ${Ps} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+{
+ {
+ USI opval = GET_H_SR (FLD (f_operand2));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BAS_C) : /* bas ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bas_c.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+{
+{
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_const32_pcrel);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JASC_R) : /* jasc ${Rs},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+{
+{
+ {
+ SI opval = ADDSI (pc, 8);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+ {
+ USI opval = GET_H_GR (FLD (f_operand1));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JASC_C) : /* jasc ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p0.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+{
+{
+ {
+ SI opval = ADDSI (pc, 12);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+ {
+ USI opval = FLD (f_indir_pc__dword);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BASC_C) : /* basc ${const32},${Pd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bas_c.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+{
+{
+ {
+ SI opval = ADDSI (pc, 12);
+ SET_H_SR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval);
+ }
+ {
+ USI opval = FLD (i_const32_pcrel);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BREAK) : /* break $n */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_break.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+ {
+ USI opval = crisv32f_break_handler (current_cpu, FLD (f_u4), pc);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BOUND_R_B_R) : /* bound-r.b ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BOUND_R_W_R) : /* bound-r.w ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1))));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BOUND_R_D_R) : /* bound-r.d ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = TRUNCSISI (GET_H_GR (FLD (f_operand1)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BOUND_CB) : /* bound.b [PC+],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BOUND_CW) : /* bound.w [PC+],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = ZEXTSISI (FLD (f_indir_pc__word));
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BOUND_CD) : /* bound.d [PC+],${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ SI tmp_tmpopd;
+ SI tmp_tmpops;
+ SI tmp_newval;
+ tmp_tmpops = FLD (f_indir_pc__dword);
+ tmp_tmpopd = GET_H_GR (FLD (f_operand2));
+ tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd));
+ {
+ SI opval = tmp_newval;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_newval, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SCC) : /* s${cc} ${Rd-sfield} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_truthval;
+ tmp_truthval = ({ SI tmp_tmpcond;
+ BI tmp_condres;
+ tmp_tmpcond = FLD (f_operand2);
+; if (EQSI (tmp_tmpcond, 0)) {
+ tmp_condres = NOTBI (CPU (h_cbit));
+}
+ else if (EQSI (tmp_tmpcond, 1)) {
+ tmp_condres = CPU (h_cbit);
+}
+ else if (EQSI (tmp_tmpcond, 2)) {
+ tmp_condres = NOTBI (CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 3)) {
+ tmp_condres = CPU (h_zbit);
+}
+ else if (EQSI (tmp_tmpcond, 4)) {
+ tmp_condres = NOTBI (CPU (h_vbit));
+}
+ else if (EQSI (tmp_tmpcond, 5)) {
+ tmp_condres = CPU (h_vbit);
+}
+ else if (EQSI (tmp_tmpcond, 6)) {
+ tmp_condres = NOTBI (CPU (h_nbit));
+}
+ else if (EQSI (tmp_tmpcond, 7)) {
+ tmp_condres = CPU (h_nbit);
+}
+ else if (EQSI (tmp_tmpcond, 8)) {
+ tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 9)) {
+ tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)));
+}
+ else if (EQSI (tmp_tmpcond, 10)) {
+ tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)));
+}
+ else if (EQSI (tmp_tmpcond, 11)) {
+ tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit));
+}
+ else if (EQSI (tmp_tmpcond, 12)) {
+ tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)));
+}
+ else if (EQSI (tmp_tmpcond, 13)) {
+ tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit));
+}
+ else if (EQSI (tmp_tmpcond, 14)) {
+ tmp_condres = 1;
+}
+ else if (EQSI (tmp_tmpcond, 15)) {
+ tmp_condres = CPU (h_pbit);
+}
+; tmp_condres; });
+ {
+ SI opval = ZEXTBISI (tmp_truthval);
+ SET_H_GR (FLD (f_operand1), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LZ) : /* lz ${Rs},${Rd} */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpd;
+ SI tmp_tmp;
+ tmp_tmp = GET_H_GR (FLD (f_operand1));
+ tmp_tmpd = 0;
+{
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+if (GESI (tmp_tmp, 0)) {
+{
+ tmp_tmp = SLLSI (tmp_tmp, 1);
+ tmp_tmpd = ADDSI (tmp_tmpd, 1);
+}
+}
+}
+ {
+ SI opval = tmp_tmpd;
+ SET_H_GR (FLD (f_operand2), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+{
+ {
+ BI opval = LTSI (tmp_tmpd, 0);
+ CPU (h_nbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
+ }
+ {
+ BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)));
+ CPU (h_zbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
+ }
+SET_H_CBIT_MOVE (0);
+SET_H_VBIT_MOVE (0);
+{
+ {
+ BI opval = 0;
+ CPU (h_xbit) = opval;
+ TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+}
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDOQ) : /* addoq $o,$Rs,ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addoq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), FLD (f_s8));
+ SET_H_PREFIXREG_V32 (opval);
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDO_M_B_M) : /* addo-m.b [${Rs}${inc}],$Rd,ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_tmps;
+ tmp_tmps = ({ SI tmp_addr;
+ QI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 1);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTQISI (tmp_tmps));
+ SET_H_PREFIXREG_V32 (opval);
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDO_M_W_M) : /* addo-m.w [${Rs}${inc}],$Rd,ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_tmps;
+ tmp_tmps = ({ SI tmp_addr;
+ HI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 2);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTHISI (tmp_tmps));
+ SET_H_PREFIXREG_V32 (opval);
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDO_M_D_M) : /* addo-m.d [${Rs}${inc}],$Rd,ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addc_m.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmps;
+ tmp_tmps = ({ SI tmp_addr;
+ SI tmp_tmp_mem;
+ BI tmp_postinc;
+ tmp_postinc = FLD (f_memmode);
+; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ()));
+; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr);
+; if (NEBI (tmp_postinc, 0)) {
+{
+if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) {
+ tmp_addr = ADDSI (tmp_addr, 4);
+}
+ {
+ SI opval = tmp_addr;
+ SET_H_GR (FLD (f_operand1), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
+ }
+}
+}
+; tmp_tmp_mem; });
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), tmp_tmps);
+ SET_H_PREFIXREG_V32 (opval);
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDO_CB) : /* addo.b [PC+],$Rd,ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cb.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte))));
+ SET_H_PREFIXREG_V32 (opval);
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDO_CW) : /* addo.w [PC+],$Rd,ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word))));
+ SET_H_PREFIXREG_V32 (opval);
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDO_CD) : /* addo.d [PC+],$Rd,ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bound_cd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword));
+ SET_H_PREFIXREG_V32 (opval);
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDI_ACR_B_R) : /* addi-acr.b ${Rs-dfield}.m,${Rd-sfield},ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 1));
+ SET_H_PREFIXREG_V32 (opval);
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDI_ACR_W_R) : /* addi-acr.w ${Rs-dfield}.m,${Rd-sfield},ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 2));
+ SET_H_PREFIXREG_V32 (opval);
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDI_ACR_D_R) : /* addi-acr.d ${Rs-dfield}.m,${Rd-sfield},ACR */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_muls_b.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 4));
+ SET_H_PREFIXREG_V32 (opval);
+ TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ SET_H_INSN_PREFIXED_P (opval);
+ TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FIDXI) : /* fidxi [$Rs] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ USI opval = crisv32f_fidxi_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1)));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FTAGI) : /* fidxi [$Rs] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ USI opval = crisv32f_ftagi_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1)));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FIDXD) : /* fidxd [$Rs] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ USI opval = crisv32f_fidxd_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1)));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FTAGD) : /* ftagd [$Rs] */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_mcp.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ USI opval = crisv32f_ftagd_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1)));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ }
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+
+ }
+ ENDSWITCH (sem) /* End of semantic switch. */
+
+ /* At this point `vpc' contains the next insn to execute. */
+}
+
+#undef DEFINE_SWITCH
+#endif /* DEFINE_SWITCH */
--- /dev/null
+/* Main simulator entry points specific to the CRIS.
+ Copyright (C) 2004, 2005 Free Software Foundation, Inc.
+ Contributed by Axis Communications.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+/* Based on the fr30 file, mixing in bits from the i960 and pruning of
+ dead code. */
+
+#include "libiberty.h"
+#include "bfd.h"
+
+#include "sim-main.h"
+#ifdef HAVE_STDLIB_H
+#include <stdlib.h>
+#endif
+#include "sim-options.h"
+#include "dis-asm.h"
+
+/* Apparently the autoconf bits are missing (though HAVE_ENVIRON is used
+ in other dirs; also lacking there). Patch around it for major systems. */
+#if defined (HAVE_ENVIRON) || defined (__GLIBC__)
+extern char **environ;
+#define GET_ENVIRON() environ
+#else
+char *missing_environ[] = { "SHELL=/bin/sh", "PATH=/bin:/usr/bin", NULL };
+#define GET_ENVIRON() missing_environ
+#endif
+
+/* AUX vector entries. */
+#define TARGET_AT_NULL 0
+#define TARGET_AT_PHDR 3
+#define TARGET_AT_PHENT 4
+#define TARGET_AT_PHNUM 5
+#define TARGET_AT_PAGESZ 6
+#define TARGET_AT_BASE 7
+#define TARGET_AT_FLAGS 8
+#define TARGET_AT_ENTRY 9
+#define TARGET_AT_UID 11
+#define TARGET_AT_EUID 12
+#define TARGET_AT_GID 13
+#define TARGET_AT_EGID 14
+#define TARGET_AT_HWCAP 16
+#define TARGET_AT_CLKTCK 17
+
+/* Used with get_progbounds to find out how much memory is needed for the
+ program. We don't want to allocate more, since that could mask
+ invalid memory accesses program bugs. */
+struct progbounds {
+ USI startmem;
+ USI endmem;
+};
+
+static void free_state (SIM_DESC);
+static void get_progbounds (bfd *, asection *, void *);
+static SIM_RC cris_option_handler (SIM_DESC, sim_cpu *, int, char *, int);
+
+/* Since we don't build the cgen-opcode table, we use the old
+ disassembler. */
+static CGEN_DISASSEMBLER cris_disassemble_insn;
+
+/* By default, we set up stack and environment variables like the Linux
+ kernel. */
+static char cris_bare_iron = 0;
+
+/* Whether 0x9000000xx have simulator-specific meanings. */
+static char cris_have_900000xxif = 0;
+
+/* Records simulator descriptor so utilities like cris_dump_regs can be
+ called from gdb. */
+SIM_DESC current_state;
+
+/* CRIS-specific options. */
+typedef enum {
+ OPTION_CRIS_STATS = OPTION_START,
+ OPTION_CRIS_TRACE,
+ OPTION_CRIS_NAKED,
+ OPTION_CRIS_900000XXIF,
+} CRIS_OPTIONS;
+
+static const OPTION cris_options[] =
+{
+ { {"cris-cycles", required_argument, NULL, OPTION_CRIS_STATS},
+ '\0', "basic|unaligned|schedulable|all",
+ "Dump execution statistics",
+ cris_option_handler, NULL },
+ { {"cris-trace", required_argument, NULL, OPTION_CRIS_TRACE},
+ '\0', "basic",
+ "Emit trace information while running",
+ cris_option_handler, NULL },
+ { {"cris-naked", no_argument, NULL, OPTION_CRIS_NAKED},
+ '\0', NULL, "Don't set up stack and environment",
+ cris_option_handler, NULL },
+ { {"cris-900000xx", no_argument, NULL, OPTION_CRIS_900000XXIF},
+ '\0', NULL, "Define addresses at 0x900000xx with simulator semantics",
+ cris_option_handler, NULL },
+ { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL, NULL }
+};
+\f
+/* Add the CRIS-specific option list to the simulator. */
+
+SIM_RC
+cris_option_install (SIM_DESC sd)
+{
+ SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
+ if (sim_add_option_table (sd, NULL, cris_options) != SIM_RC_OK)
+ return SIM_RC_FAIL;
+ return SIM_RC_OK;
+}
+
+/* Handle CRIS-specific options. */
+
+static SIM_RC
+cris_option_handler (SIM_DESC sd, sim_cpu *cpu ATTRIBUTE_UNUSED, int opt,
+ char *arg, int is_command ATTRIBUTE_UNUSED)
+{
+ /* The options are CRIS-specific, but cpu-specific option-handling is
+ broken; required to being with "--cpu0-". We store the flags in an
+ unused field in the global state structure and move the flags over
+ to the module-specific CPU data when we store things in the
+ cpu-specific structure. */
+ char *tracefp = STATE_TRACE_FLAGS (sd);
+
+ switch ((CRIS_OPTIONS) opt)
+ {
+ case OPTION_CRIS_STATS:
+ if (strcmp (arg, "basic") == 0)
+ *tracefp = FLAG_CRIS_MISC_PROFILE_SIMPLE;
+ else if (strcmp (arg, "unaligned") == 0)
+ *tracefp
+ = (FLAG_CRIS_MISC_PROFILE_UNALIGNED
+ | FLAG_CRIS_MISC_PROFILE_SIMPLE);
+ else if (strcmp (arg, "schedulable") == 0)
+ *tracefp
+ = (FLAG_CRIS_MISC_PROFILE_SCHEDULABLE
+ | FLAG_CRIS_MISC_PROFILE_SIMPLE);
+ else if (strcmp (arg, "all") == 0)
+ *tracefp = FLAG_CRIS_MISC_PROFILE_ALL;
+ else
+ {
+ /* We'll actually never get here; the caller handles the
+ error case. */
+ sim_io_eprintf (sd, "Unknown option `--cris-stats=%s'\n", arg);
+ return SIM_RC_FAIL;
+ }
+ break;
+
+ case OPTION_CRIS_TRACE:
+ if (strcmp (arg, "basic") == 0)
+ *tracefp |= FLAG_CRIS_MISC_PROFILE_XSIM_TRACE;
+ else
+ {
+ sim_io_eprintf (sd, "Unknown option `--cris-trace=%s'\n", arg);
+ return SIM_RC_FAIL;
+ }
+ break;
+
+ case OPTION_CRIS_NAKED:
+ cris_bare_iron = 1;
+ break;
+
+ case OPTION_CRIS_900000XXIF:
+ cris_have_900000xxif = 1;
+ break;
+
+ default:
+ /* We'll actually never get here; the caller handles the error
+ case. */
+ sim_io_eprintf (sd, "Unknown option `%s'\n", arg);
+ return SIM_RC_FAIL;
+ }
+
+ /* Imply --profile-model=on. */
+ return sim_profile_set_option (sd, "-model", PROFILE_MODEL_IDX, "on");
+}
+
+/* Cover function of sim_state_free to free the cpu buffers as well. */
+
+static void
+free_state (SIM_DESC sd)
+{
+ if (STATE_MODULES (sd) != NULL)
+ sim_module_uninstall (sd);
+ sim_cpu_free_all (sd);
+ sim_state_free (sd);
+}
+
+/* BFD section iterator to find the highest allocated section address
+ (plus one). If we could, we should use the program header table
+ instead, but we can't get to that using bfd. */
+
+void
+get_progbounds (bfd *abfd ATTRIBUTE_UNUSED, asection *s, void *vp)
+{
+ struct progbounds *pbp = (struct progbounds *) vp;
+
+ if ((bfd_get_section_flags (abfd, s) & SEC_ALLOC))
+ {
+ bfd_size_type sec_size = bfd_get_section_size (s);
+ bfd_size_type sec_start = bfd_get_section_vma (abfd, s);
+ bfd_size_type sec_end = sec_start + sec_size;
+
+ if (sec_end > pbp->endmem)
+ pbp->endmem = sec_end;
+
+ if (sec_start < pbp->startmem)
+ pbp->startmem = sec_start;
+ }
+}
+
+/* Create an instance of the simulator. */
+
+SIM_DESC
+sim_open (SIM_OPEN_KIND kind, host_callback *callback, struct bfd *abfd,
+ char **argv)
+{
+ char c;
+ int i;
+ USI startmem = 0;
+ USI endmem = CRIS_DEFAULT_MEM_SIZE;
+ USI endbrk = endmem;
+ USI stack_low = 0;
+ SIM_DESC sd = sim_state_alloc (kind, callback);
+
+ /* Can't initialize to "" below. It's either a GCC bug in old
+ releases (up to and including 2.95.3 (.4 in debian) or a bug in the
+ standard ;-) that the rest of the elements won't be initialized. */
+ bfd_byte sp_init[4] = {0, 0, 0, 0};
+
+ /* The cpu data is kept in a separately allocated chunk of memory. */
+ if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK)
+ {
+ free_state (sd);
+ return 0;
+ }
+
+ if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
+ {
+ free_state (sd);
+ return 0;
+ }
+
+ /* getopt will print the error message so we just have to exit if this fails.
+ FIXME: Hmmm... in the case of gdb we need getopt to call
+ print_filtered. */
+ if (sim_parse_args (sd, argv) != SIM_RC_OK)
+ {
+ free_state (sd);
+ return 0;
+ }
+
+ /* If we have a binary program, endianness-setting would not be taken
+ from elsewhere unfortunately, so set it here. At the time of this
+ writing, it isn't used until sim_config, but that might change so
+ set it here before memory is defined or touched. */
+ current_target_byte_order = LITTLE_ENDIAN;
+
+ /* check for/establish the reference program image */
+ if (sim_analyze_program (sd,
+ (STATE_PROG_ARGV (sd) != NULL
+ ? *STATE_PROG_ARGV (sd)
+ : NULL),
+ abfd) != SIM_RC_OK)
+ {
+ free_state (sd);
+ return 0;
+ }
+
+ /* For CRIS simulator-specific use, we need to find out the bounds of
+ the program as well, which is not done by sim_analyze_program
+ above. */
+ if (STATE_PROG_BFD (sd))
+ {
+ struct progbounds pb;
+
+ /* The sections should now be accessible using bfd functions. */
+ pb.startmem = 0x7fffffff;
+ pb.endmem = 0;
+ bfd_map_over_sections (STATE_PROG_BFD (sd), get_progbounds, &pb);
+
+ /* We align the area that the program uses to page boundaries. */
+ startmem = pb.startmem & ~8191;
+ endbrk = pb.endmem;
+ endmem = (endbrk + 8191) & ~8191;
+ }
+
+ /* Find out how much room is needed for the environment and argv, create
+ that memory and fill it. Only do this when there's a program
+ specified. */
+ if (STATE_PROG_BFD (sd) && !cris_bare_iron)
+ {
+ char *name = bfd_get_filename (STATE_PROG_BFD (sd));
+ char **my_environ = GET_ENVIRON ();
+ /* We use these maps to give the same behavior as the old xsim
+ simulator. */
+ USI envtop = 0x40000000;
+ USI stacktop = 0x3e000000;
+ USI envstart;
+ int envc;
+ int len = strlen (name) + 1;
+ USI epp, epp0;
+ USI stacklen;
+ int i;
+ char **prog_argv = STATE_PROG_ARGV (sd);
+ int my_argc = 0;
+ /* All CPU:s have the same memory map, apparently. */
+ SIM_CPU *cpu = STATE_CPU (sd, 0);
+ USI csp;
+ bfd_byte buf[4];
+
+ /* Count in the environment as well. */
+ for (envc = 0; my_environ[envc] != NULL; envc++)
+ len += strlen (my_environ[envc]) + 1;
+
+ for (i = 0; prog_argv[i] != NULL; my_argc++, i++)
+ len += strlen (prog_argv[i]) + 1;
+
+ envstart = (envtop - len) & ~8191;
+
+ /* Create read-only block for the environment strings. */
+ sim_core_attach (sd, NULL, 0, access_read, 0,
+ envstart, (len + 8191) & ~8191,
+ 0, NULL, NULL);
+
+ /* This shouldn't happen. */
+ if (envstart < stacktop)
+ stacktop = envstart - 64 * 8192;
+
+ csp = stacktop;
+
+ /* Note that the linux kernel does not correctly compute the storage
+ needs for the static-exe AUX vector. */
+ csp -= 4 * 4 * 2;
+
+ csp -= (envc + 1) * 4;
+ csp -= (my_argc + 1) * 4;
+ csp -= 4;
+
+ /* Write the target representation of the start-up-value for the
+ stack-pointer suitable for register initialization below. */
+ bfd_putl32 (csp, sp_init);
+
+ /* If we make this 1M higher; say 8192*1024, we have to take
+ special precautions for pthreads, because pthreads assumes that
+ the memory that low isn't mmapped, and that it can mmap it
+ without fallback in case of failure (and we fail ungracefully
+ long before *that*: the memory isn't accounted for in our mmap
+ list). */
+ stack_low = (csp - (7168*1024)) & ~8191;
+
+ stacklen = stacktop - stack_low;
+
+ /* Tee hee, we have an executable stack. Well, it's necessary to
+ test GCC trampolines... */
+ sim_core_attach (sd, NULL, 0, access_read_write_exec, 0,
+ stack_low, stacklen,
+ 0, NULL, NULL);
+
+ epp = epp0 = envstart;
+
+ /* Can't use sim_core_write_unaligned_4 without everything
+ initialized when tracing, and then these writes would get into
+ the trace. */
+#define write_dword(addr, data) \
+ do \
+ { \
+ USI data_ = data; \
+ USI addr_ = addr; \
+ bfd_putl32 (data_, buf); \
+ if (sim_core_write_buffer (sd, cpu, 0, buf, addr_, 4) != 4) \
+ goto abandon_chip; \
+ } \
+ while (0)
+
+ write_dword (csp, my_argc);
+ csp += 4;
+
+ for (i = 0; i < my_argc; i++, csp += 4)
+ {
+ size_t strln = strlen (prog_argv[i]) + 1;
+
+ if (sim_core_write_buffer (sd, cpu, 0, prog_argv[i], epp, strln)
+ != strln)
+ goto abandon_chip;
+
+ write_dword (csp, envstart + epp - epp0);
+ epp += strln;
+ }
+
+ write_dword (csp, 0);
+ csp += 4;
+
+ for (i = 0; i < envc; i++, csp += 4)
+ {
+ unsigned int strln = strlen (my_environ[i]) + 1;
+
+ if (sim_core_write_buffer (sd, cpu, 0, my_environ[i], epp, strln)
+ != strln)
+ goto abandon_chip;
+
+ write_dword (csp, envstart + epp - epp0);
+ epp += strln;
+ }
+
+ write_dword (csp, 0);
+ csp += 4;
+
+#define NEW_AUX_ENT(nr, id, val) \
+ do \
+ { \
+ write_dword (csp + (nr) * 4 * 2, (id)); \
+ write_dword (csp + (nr) * 4 * 2 + 4, (val)); \
+ } \
+ while (0)
+
+ /* Note that there are some extra AUX entries for a dynlinked
+ program loaded image. */
+
+ /* AUX entries always present. */
+ NEW_AUX_ENT (0, TARGET_AT_HWCAP, 0);
+ NEW_AUX_ENT (1, TARGET_AT_PAGESZ, 8192);
+ NEW_AUX_ENT (2, TARGET_AT_CLKTCK, 100);
+
+ csp += 4 * 2 * 3;
+ NEW_AUX_ENT (0, TARGET_AT_NULL, 0);
+#undef NEW_AUX_ENT
+
+ /* Register R10 should hold 0 at static start (no initfunc), but
+ that's the default, so don't bother. */
+ }
+
+ /* Allocate core managed memory if none specified by user. */
+ if (sim_core_read_buffer (sd, NULL, read_map, &c, startmem, 1) == 0)
+ sim_do_commandf (sd, "memory region 0x%lx,0x%lx", startmem,
+ endmem - startmem);
+
+ /* Allocate simulator I/O managed memory if none specified by user. */
+ if (cris_have_900000xxif)
+ {
+ if (sim_core_read_buffer (sd, NULL, read_map, &c, 0x90000000, 1) == 0)
+ sim_core_attach (sd, NULL, 0, access_write, 0, 0x90000000, 0x100,
+ 0, &cris_devices, NULL);
+ else
+ {
+ (*callback->
+ printf_filtered) (callback,
+ "Seeing --cris-900000xx with memory defined there\n");
+ goto abandon_chip;
+ }
+ }
+
+ /* Establish any remaining configuration options. */
+ if (sim_config (sd) != SIM_RC_OK)
+ {
+ abandon_chip:
+ free_state (sd);
+ return 0;
+ }
+
+ if (sim_post_argv_init (sd) != SIM_RC_OK)
+ {
+ free_state (sd);
+ return 0;
+ }
+
+ /* Open a copy of the cpu descriptor table. */
+ {
+ CGEN_CPU_DESC cd = cris_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
+ CGEN_ENDIAN_LITTLE);
+ for (i = 0; i < MAX_NR_PROCESSORS; ++i)
+ {
+ SIM_CPU *cpu = STATE_CPU (sd, i);
+ CPU_CPU_DESC (cpu) = cd;
+ CPU_DISASSEMBLER (cpu) = cris_disassemble_insn;
+
+ /* See cris_option_handler for the reason why this is needed. */
+ CPU_CRIS_MISC_PROFILE (cpu)->flags = STATE_TRACE_FLAGS (sd)[0];
+
+ /* Set SP to the stack we allocated above. */
+ (* CPU_REG_STORE (cpu)) (cpu, H_GR_SP, (char *) sp_init, 4);
+
+ /* Set the simulator environment data. */
+ cpu->highest_mmapped_page = NULL;
+ cpu->endmem = endmem;
+ cpu->endbrk = endbrk;
+ cpu->stack_low = stack_low;
+ cpu->syscalls = 0;
+ cpu->m1threads = 0;
+ cpu->threadno = 0;
+ cpu->max_threadid = 0;
+ cpu->thread_data = NULL;
+ memset (cpu->sighandler, 0, sizeof (cpu->sighandler));
+ cpu->make_thread_cpu_data = NULL;
+ cpu->thread_cpu_data_size = 0;
+ }
+ }
+
+ /* Initialize various cgen things not done by common framework.
+ Must be done after cris_cgen_cpu_open. */
+ cgen_init (sd);
+
+ /* Store in a global so things like cris_dump_regs can be invoked
+ from the gdb command line. */
+ current_state = sd;
+
+ cris_set_callbacks (callback);
+
+ return sd;
+}
+
+void
+sim_close (SIM_DESC sd, int quitting ATTRIBUTE_UNUSED)
+{
+ cris_cgen_cpu_close (CPU_CPU_DESC (STATE_CPU (sd, 0)));
+ sim_module_uninstall (sd);
+}
+\f
+SIM_RC
+sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
+ char **argv ATTRIBUTE_UNUSED,
+ char **envp ATTRIBUTE_UNUSED)
+{
+ SIM_CPU *current_cpu = STATE_CPU (sd, 0);
+ SIM_ADDR addr;
+
+ if (abfd != NULL)
+ addr = bfd_get_start_address (abfd);
+ else
+ addr = 0;
+ sim_pc_set (current_cpu, addr);
+
+ /* Other simulators have #if 0:d code that says
+ STATE_ARGV (sd) = sim_copy_argv (argv);
+ STATE_ENVP (sd) = sim_copy_argv (envp);
+ Enabling that gives you not-found link-errors for sim_copy_argv.
+ FIXME: Do archaeology to find out more. */
+
+ return SIM_RC_OK;
+}
+
+void
+sim_do_command (SIM_DESC sd, char *cmd)
+{
+ if (sim_args_command (sd, cmd) != SIM_RC_OK)
+ sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
+}
+\f
+/* Disassemble an instruction. */
+
+static void
+cris_disassemble_insn (SIM_CPU *cpu,
+ const CGEN_INSN *insn ATTRIBUTE_UNUSED,
+ const ARGBUF *abuf ATTRIBUTE_UNUSED,
+ IADDR pc, char *buf)
+{
+ disassembler_ftype pinsn;
+ struct disassemble_info disasm_info;
+ SFILE sfile;
+ SIM_DESC sd = CPU_STATE (cpu);
+
+ sfile.buffer = sfile.current = buf;
+ INIT_DISASSEMBLE_INFO (disasm_info, (FILE *) &sfile,
+ (fprintf_ftype) sim_disasm_sprintf);
+ disasm_info.endian =
+ (bfd_big_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_BIG
+ : bfd_little_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_LITTLE
+ : BFD_ENDIAN_UNKNOWN);
+ /* We live with the cast until the prototype is fixed, or else we get a
+ warning because the functions differ in the signedness of one parameter. */
+ disasm_info.read_memory_func =
+ sim_disasm_read_memory;
+ disasm_info.memory_error_func = sim_disasm_perror_memory;
+ disasm_info.application_data = (PTR) cpu;
+ pinsn = cris_get_disassembler (STATE_PROG_BFD (sd));
+ (*pinsn) (pc, &disasm_info);
+}
--- /dev/null
+/* Main header for the CRIS simulator, based on the m32r header.
+ Copyright (C) 2004, 2005 Free Software Foundation, Inc.
+ Contributed by Axis Communications.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+/* All FIXME:s present in m32r apply here too; I just refuse to blindly
+ carry them over, as I don't know if they're really things that need
+ fixing. */
+
+#ifndef SIM_MAIN_H
+#define SIM_MAIN_H
+
+#define USING_SIM_BASE_H
+
+struct _sim_cpu;
+typedef struct _sim_cpu SIM_CPU;
+
+#include "symcat.h"
+#include "sim-basics.h"
+#include "cgen-types.h"
+#include "cris-desc.h"
+#include "cris-opc.h"
+#include "arch.h"
+
+/* These must be defined before sim-base.h. */
+typedef USI sim_cia;
+
+#define CIA_GET(cpu) CPU_PC_GET (cpu)
+#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val))
+
+#define SIM_ENGINE_HALT_HOOK(sd, cpu, cia) \
+do { \
+ if (cpu) /* Null if ctrl-c. */ \
+ sim_pc_set ((cpu), (cia)); \
+} while (0)
+#define SIM_ENGINE_RESTART_HOOK(sd, cpu, cia) \
+do { \
+ sim_pc_set ((cpu), (cia)); \
+} while (0)
+
+#include "sim-base.h"
+#include "cgen-sim.h"
+#include "cris-sim.h"
+
+/* For occurrences of ANDIF in decodev32.c. */
+#include "cgen-ops.h"
+\f
+struct cris_sim_mmapped_page {
+ USI addr;
+ struct cris_sim_mmapped_page *prev;
+};
+
+struct cris_thread_info {
+ /* Identifier for this thread. */
+ unsigned int threadid;
+
+ /* Identifier for parent thread. */
+ unsigned int parent_threadid;
+
+ /* Signal to send to parent at exit. */
+ int exitsig;
+
+ /* Exit status. */
+ int exitval;
+
+ /* Only as storage to return the "set" value to the "get" method.
+ I'm not sure whether this is useful per-thread. */
+ USI priority;
+
+ struct
+ {
+ USI altstack;
+ USI options;
+
+ char action;
+ char pending;
+ char blocked;
+ char blocked_suspendsave;
+ /* The handler stub unblocks the signal, so we don't need a separate
+ "temporary save" for that. */
+ } sigdata[64];
+
+ /* Register context, swapped with _sim_cpu.cpu_data. */
+ void *cpu_context;
+
+ /* Similar, temporary copy for the state at a signal call. */
+ void *cpu_context_atsignal;
+
+ /* The number of the reading and writing ends of a pipe if waiting for
+ the reader, else 0. */
+ int pipe_read_fd;
+ int pipe_write_fd;
+
+ /* System time at last context switch when this thread ran. */
+ USI last_execution;
+
+ /* Nonzero if we just executed a syscall. */
+ char at_syscall;
+
+ /* Nonzero if any of sigaction[0..64].pending is true. */
+ char sigpending;
+
+ /* Nonzero if in (rt_)sigsuspend call. Cleared at every sighandler
+ call. */
+ char sigsuspended;
+};
+
+struct _sim_cpu {
+ /* sim/common cpu base. */
+ sim_cpu_base base;
+
+ /* Static parts of cgen. */
+ CGEN_CPU cgen_cpu;
+
+ CRIS_MISC_PROFILE cris_misc_profile;
+#define CPU_CRIS_MISC_PROFILE(cpu) (& (cpu)->cris_misc_profile)
+
+ /* Copy of previous data; only valid when emitting trace-data after
+ each insn. */
+ CRIS_MISC_PROFILE cris_prev_misc_profile;
+#define CPU_CRIS_PREV_MISC_PROFILE(cpu) (& (cpu)->cris_prev_misc_profile)
+
+ /* Simulator environment data. */
+ USI endmem;
+ USI endbrk;
+ USI stack_low;
+ struct cris_sim_mmapped_page *highest_mmapped_page;
+
+ /* Number of syscalls performed or in progress, counting once extra
+ for every time a blocked thread (internally, when threading) polls
+ the (pipe) blockage. By default, this is also a time counter: to
+ minimize performance noise from minor compiler changes,
+ instructions take no time and syscalls always take 1ms. */
+ USI syscalls;
+
+ /* Number of execution contexts minus one. */
+ int m1threads;
+
+ /* Current thread number; index into thread_data when m1threads != 0. */
+ int threadno;
+
+ /* When a new thread is created, it gets a unique number, which we
+ count here. */
+ int max_threadid;
+
+ /* Thread-specific info, for simulator thread support, created at
+ "clone" call. Vector of [threads+1] when m1threads > 0. */
+ struct cris_thread_info *thread_data;
+
+ /* "If CLONE_SIGHAND is set, the calling process and the child pro-
+ cesses share the same table of signal handlers." ... "However, the
+ calling process and child processes still have distinct signal
+ masks and sets of pending signals." See struct cris_thread_info
+ for sigmasks and sigpendings. */
+ USI sighandler[64];
+
+ /* Function for initializing CPU thread context, which varies in size
+ with each CPU model. They should be in some constant parts or
+ initialized in *_init_cpu, but we can't modify that for now. */
+ void* (*make_thread_cpu_data) (SIM_CPU *, void *);
+ size_t thread_cpu_data_size;
+
+ /* CPU-model specific parts go here.
+ Note that in files that don't need to access these pieces WANT_CPU_FOO
+ won't be defined and thus these parts won't appear. This is ok in the
+ sense that things work. It is a source of bugs though.
+ One has to of course be careful to not take the size of this
+ struct and no structure members accessed in non-cpu specific files can
+ go after here. */
+#if defined (WANT_CPU_CRISV0F)
+ CRISV0F_CPU_DATA cpu_data;
+#elif defined (WANT_CPU_CRISV3F)
+ CRISV3F_CPU_DATA cpu_data;
+#elif defined (WANT_CPU_CRISV8F)
+ CRISV8F_CPU_DATA cpu_data;
+#elif defined (WANT_CPU_CRISV10F)
+ CRISV10F_CPU_DATA cpu_data;
+#elif defined (WANT_CPU_CRISV32F)
+ CRISV32F_CPU_DATA cpu_data;
+#else
+ /* Let's assume all cpu_data have the same alignment requirements, so
+ they all are laid out at the same address. Since we can't get the
+ exact definition, we also assume that it has no higher alignment
+ requirements than a vector of, say, 16 pointers. (A single member
+ is often special-cased, and possibly two as well so we don't want
+ that). */
+ union { void *dummy[16]; } cpu_data_placeholder;
+#endif
+};
+\f
+/* The sim_state struct. */
+
+struct sim_state {
+ sim_cpu *cpu;
+#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)
+
+ CGEN_STATE cgen_state;
+
+ sim_state_base base;
+};
+\f
+/* Misc. */
+
+/* Catch address exceptions. */
+extern SIM_CORE_SIGNAL_FN cris_core_signal;
+#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
+cris_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
+ (TRANSFER), (ERROR))
+
+/* Default memory size. */
+#define CRIS_DEFAULT_MEM_SIZE 0x800000 /* 8M */
+
+extern device cris_devices;
+
+#endif /* SIM_MAIN_H */
--- /dev/null
+/* CRIS target configuration file. -*- C -*-
+ Copyright (C) 2004, 2005 Free Software Foundation, Inc.
+ Contributed by Axis Communications.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#ifndef CRIS_TCONFIG_H
+#define CRIS_TCONFIG_H
+
+#include "ansidecl.h"
+#include "gdb/callback.h"
+#include "gdb/remote-sim.h"
+#include "sim-module.h"
+
+/* There's basically a a big ??? FIXME: CHECK THIS on everything in this
+ file. I just copied it from m32r, pruned some stuff and added
+ HAVE_MODEL because it seemed useful. */
+
+/* See sim-hload.c. We properly handle LMA. */
+#define SIM_HANDLES_LMA 1
+
+/* For MSPR support. FIXME: revisit. */
+#define WITH_DEVICES 1
+
+extern MODULE_INSTALL_FN cris_option_install;
+
+/* FIXME: Revisit. */
+#ifdef HAVE_DV_SOCKSER
+extern MODULE_INSTALL_FN dv_sockser_install;
+#define MODULE_LIST dv_sockser_install, cris_option_install,
+#else
+#define MODULE_LIST cris_option_install,
+#endif
+
+#define SIM_HAVE_MODEL
+
+/* This is a global setting. Different cpu families can't mix-n-match -scache
+ and -pbb. However some cpu families may use -simple while others use
+ one of -scache/-pbb. */
+#define WITH_SCACHE_PBB 1
+
+#endif /* CRIS_TCONFIG_H */
--- /dev/null
+/* CRIS exception, interrupt, and trap (EIT) support
+ Copyright (C) 2004, 2005 Free Software Foundation, Inc.
+ Contributed by Axis Communications.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#include "sim-main.h"
+#include "sim-options.h"
+#include "targ-vals.h"
+#include "bfd.h"
+#ifdef HAVE_ERRNO_H
+#include <errno.h>
+#endif
+#ifdef HAVE_UNISTD_H
+#include <unistd.h>
+#endif
+#ifdef HAVE_FCNTL_H
+#include <fcntl.h>
+#endif
+#ifdef HAVE_SYS_PARAM_H
+#include <sys/param.h>
+#endif
+#ifdef HAVE_SYS_STAT_H
+#include <sys/stat.h>
+#endif
+
+/* The verbatim values are from asm-cris/unistd.h. */
+
+#define TARGET_SYS_exit 1
+#define TARGET_SYS_read 3
+#define TARGET_SYS_write 4
+#define TARGET_SYS_open 5
+#define TARGET_SYS_close 6
+#define TARGET_SYS_unlink 10
+#define TARGET_SYS_time 13
+#define TARGET_SYS_lseek 19
+#define TARGET_SYS_getpid 20
+#define TARGET_SYS_kill 37
+#define TARGET_SYS_rename 38
+#define TARGET_SYS_pipe 42
+#define TARGET_SYS_brk 45
+#define TARGET_SYS_ioctl 54
+#define TARGET_SYS_fcntl 55
+#define TARGET_SYS_getppid 64
+#define TARGET_SYS_setrlimit 75
+#define TARGET_SYS_gettimeofday 78
+#define TARGET_SYS_readlink 85
+#define TARGET_SYS_munmap 91
+#define TARGET_SYS_truncate 92
+#define TARGET_SYS_ftruncate 93
+#define TARGET_SYS_socketcall 102
+#define TARGET_SYS_fstat 108
+#define TARGET_SYS_wait4 114
+#define TARGET_SYS_sigreturn 119
+#define TARGET_SYS_clone 120
+#define TARGET_SYS_uname 122
+#define TARGET_SYS_mprotect 125
+#define TARGET_SYS_llseek 140
+#define TARGET_SYS__sysctl 149
+#define TARGET_SYS_sched_setparam 154
+#define TARGET_SYS_sched_getparam 155
+#define TARGET_SYS_sched_setscheduler 156
+#define TARGET_SYS_sched_getscheduler 157
+#define TARGET_SYS_sched_yield 158
+#define TARGET_SYS_sched_get_priority_max 159
+#define TARGET_SYS_sched_get_priority_min 160
+#define TARGET_SYS_mremap 163
+#define TARGET_SYS_poll 168
+#define TARGET_SYS_rt_sigaction 174
+#define TARGET_SYS_rt_sigprocmask 175
+#define TARGET_SYS_rt_sigsuspend 179
+#define TARGET_SYS_getcwd 183
+#define TARGET_SYS_ugetrlimit 191
+#define TARGET_SYS_mmap2 192
+#define TARGET_SYS_stat64 195
+#define TARGET_SYS_lstat64 196
+#define TARGET_SYS_fstat64 197
+#define TARGET_SYS_geteuid32 201
+#define TARGET_SYS_getuid32 199
+#define TARGET_SYS_getegid32 202
+#define TARGET_SYS_getgid32 200
+#define TARGET_SYS_fcntl64 221
+
+#define TARGET_PROT_READ 0x1
+#define TARGET_PROT_WRITE 0x2
+#define TARGET_PROT_EXEC 0x4
+#define TARGET_PROT_NONE 0x0
+
+#define TARGET_MAP_SHARED 0x01
+#define TARGET_MAP_PRIVATE 0x02
+#define TARGET_MAP_TYPE 0x0f
+#define TARGET_MAP_FIXED 0x10
+#define TARGET_MAP_ANONYMOUS 0x20
+
+#define TARGET_CTL_KERN 1
+#define TARGET_CTL_VM 2
+#define TARGET_CTL_NET 3
+#define TARGET_CTL_PROC 4
+#define TARGET_CTL_FS 5
+#define TARGET_CTL_DEBUG 6
+#define TARGET_CTL_DEV 7
+#define TARGET_CTL_BUS 8
+#define TARGET_CTL_ABI 9
+
+#define TARGET_CTL_KERN_VERSION 4
+
+/* linux/mman.h */
+#define TARGET_MREMAP_MAYMOVE 1
+#define TARGET_MREMAP_FIXED 2
+
+#define TARGET_TCGETS 0x5401
+
+#define TARGET_UTSNAME "#38 Sun Apr 1 00:00:00 MET 2001"
+
+/* Seconds since the above date + 10 minutes. */
+#define TARGET_EPOCH 986080200
+
+/* Milliseconds since start of run. We use the number of syscalls to
+ avoid introducing noise in the execution time. */
+#define TARGET_TIME_MS(cpu) ((cpu)->syscalls)
+
+/* Seconds as in time(2). */
+#define TARGET_TIME(cpu) (TARGET_EPOCH + TARGET_TIME_MS (cpu) / 1000)
+
+#define TARGET_SCHED_OTHER 0
+
+#define TARGET_RLIMIT_STACK 3
+#define TARGET_RLIMIT_NOFILE 7
+
+#define SIM_TARGET_MAX_THREADS 64
+#define SIM_MAX_ALLOC_CHUNK (512*1024*1024)
+
+/* From linux/sched.h. */
+#define TARGET_CSIGNAL 0x000000ff
+#define TARGET_CLONE_VM 0x00000100
+#define TARGET_CLONE_FS 0x00000200
+#define TARGET_CLONE_FILES 0x00000400
+#define TARGET_CLONE_SIGHAND 0x00000800
+#define TARGET_CLONE_PID 0x00001000
+#define TARGET_CLONE_PTRACE 0x00002000
+#define TARGET_CLONE_VFORK 0x00004000
+#define TARGET_CLONE_PARENT 0x00008000
+#define TARGET_CLONE_THREAD 0x00010000
+#define TARGET_CLONE_SIGNAL (TARGET_CLONE_SIGHAND | TARGET_CLONE_THREAD)
+
+/* From asm-cris/poll.h. */
+#define TARGET_POLLIN 1
+
+/* From asm-cris/signal.h. */
+#define TARGET_SIG_BLOCK 0
+#define TARGET_SIG_UNBLOCK 1
+#define TARGET_SIG_SETMASK 2
+
+#define TARGET_SIG_DFL 0
+#define TARGET_SIG_IGN 1
+#define TARGET_SIG_ERR ((USI)-1)
+
+#define TARGET_SIGHUP 1
+#define TARGET_SIGINT 2
+#define TARGET_SIGQUIT 3
+#define TARGET_SIGILL 4
+#define TARGET_SIGTRAP 5
+#define TARGET_SIGABRT 6
+#define TARGET_SIGIOT 6
+#define TARGET_SIGBUS 7
+#define TARGET_SIGFPE 8
+#define TARGET_SIGKILL 9
+#define TARGET_SIGUSR1 10
+#define TARGET_SIGSEGV 11
+#define TARGET_SIGUSR2 12
+#define TARGET_SIGPIPE 13
+#define TARGET_SIGALRM 14
+#define TARGET_SIGTERM 15
+#define TARGET_SIGSTKFLT 16
+#define TARGET_SIGCHLD 17
+#define TARGET_SIGCONT 18
+#define TARGET_SIGSTOP 19
+#define TARGET_SIGTSTP 20
+#define TARGET_SIGTTIN 21
+#define TARGET_SIGTTOU 22
+#define TARGET_SIGURG 23
+#define TARGET_SIGXCPU 24
+#define TARGET_SIGXFSZ 25
+#define TARGET_SIGVTALRM 26
+#define TARGET_SIGPROF 27
+#define TARGET_SIGWINCH 28
+#define TARGET_SIGIO 29
+#define TARGET_SIGPOLL SIGIO
+/* Actually commented out in the kernel header. */
+#define TARGET_SIGLOST 29
+#define TARGET_SIGPWR 30
+#define TARGET_SIGSYS 31
+
+/* From include/asm-cris/signal.h. */
+#define TARGET_SA_NOCLDSTOP 0x00000001
+#define TARGET_SA_NOCLDWAIT 0x00000002 /* not supported yet */
+#define TARGET_SA_SIGINFO 0x00000004
+#define TARGET_SA_ONSTACK 0x08000000
+#define TARGET_SA_RESTART 0x10000000
+#define TARGET_SA_NODEFER 0x40000000
+#define TARGET_SA_RESETHAND 0x80000000
+#define TARGET_SA_INTERRUPT 0x20000000 /* dummy -- ignored */
+#define TARGET_SA_RESTORER 0x04000000
+
+/* From linux/wait.h. */
+#define TARGET_WNOHANG 1
+#define TARGET_WUNTRACED 2
+#define TARGET___WNOTHREAD 0x20000000
+#define TARGET___WALL 0x40000000
+#define TARGET___WCLONE 0x80000000
+
+static const char stat_map[] =
+"st_dev,2:space,10:space,4:st_mode,4:st_nlink,4:st_uid,4"
+":st_gid,4:st_rdev,2:space,10:st_size,8:st_blksize,4:st_blocks,4"
+":space,4:st_atime,4:space,4:st_mtime,4:space,4:st_ctime,4:space,4"
+":st_ino,8";
+
+static const CB_TARGET_DEFS_MAP syscall_map[] =
+{
+ { CB_SYS_open, TARGET_SYS_open },
+ { CB_SYS_close, TARGET_SYS_close },
+ { CB_SYS_read, TARGET_SYS_read },
+ { CB_SYS_write, TARGET_SYS_write },
+ { CB_SYS_lseek, TARGET_SYS_lseek },
+ { CB_SYS_unlink, TARGET_SYS_unlink },
+ { CB_SYS_getpid, TARGET_SYS_getpid },
+ { CB_SYS_fstat, TARGET_SYS_fstat64 },
+ { CB_SYS_lstat, TARGET_SYS_lstat64 },
+ { CB_SYS_stat, TARGET_SYS_stat64 },
+ { CB_SYS_pipe, TARGET_SYS_pipe },
+ { CB_SYS_time, TARGET_SYS_time },
+ { CB_SYS_rename, TARGET_SYS_rename },
+ { CB_SYS_truncate, TARGET_SYS_truncate },
+ { CB_SYS_ftruncate, TARGET_SYS_ftruncate },
+ { 0, -1 }
+};
+
+/* An older, 32-bit-only stat mapping. */
+static const char stat32_map[] =
+"st_dev,2:space,2:st_ino,4:st_mode,2:st_nlink,2:st_uid,2"
+":st_gid,2:st_rdev,2:space,2:st_size,4:st_blksize,4:st_blocks,4"
+":st_atime,4:space,4:st_mtime,4:space,4:st_ctime,4:space,12";
+
+/* Map for calls using the 32-bit struct stat. Primarily used by the
+ newlib Linux mapping. */
+static const CB_TARGET_DEFS_MAP syscall_stat32_map[] =
+{
+ { CB_SYS_fstat, TARGET_SYS_fstat },
+ { 0, -1 }
+};
+
+/* Giving the true value for the running sim process will lead to
+ non-time-invariant behavior. */
+#define TARGET_PID 42
+
+/* Unfortunately, we don't get this from cris.cpu at the moment, and if
+ we did, we'd still don't get a register number with the "16" offset. */
+#define TARGET_SRP_REGNUM (16+11)
+
+/* Extracted by applying
+ awk '/^#define/ { printf "#ifdef %s\n { %s, %s },\n#endif\n", $2, $2, $3;}'
+ on .../include/asm/errno.h in a GNU/Linux/CRIS installation and
+ adjusting the synonyms. */
+
+static const CB_TARGET_DEFS_MAP errno_map[] =
+{
+#ifdef EPERM
+ { EPERM, 1 },
+#endif
+#ifdef ENOENT
+ { ENOENT, 2 },
+#endif
+#ifdef ESRCH
+ { ESRCH, 3 },
+#endif
+#ifdef EINTR
+ { EINTR, 4 },
+#endif
+#ifdef EIO
+ { EIO, 5 },
+#endif
+#ifdef ENXIO
+ { ENXIO, 6 },
+#endif
+#ifdef E2BIG
+ { E2BIG, 7 },
+#endif
+#ifdef ENOEXEC
+ { ENOEXEC, 8 },
+#endif
+#ifdef EBADF
+ { EBADF, 9 },
+#endif
+#ifdef ECHILD
+ { ECHILD, 10 },
+#endif
+#ifdef EAGAIN
+ { EAGAIN, 11 },
+#endif
+#ifdef ENOMEM
+ { ENOMEM, 12 },
+#endif
+#ifdef EACCES
+ { EACCES, 13 },
+#endif
+#ifdef EFAULT
+ { EFAULT, 14 },
+#endif
+#ifdef ENOTBLK
+ { ENOTBLK, 15 },
+#endif
+#ifdef EBUSY
+ { EBUSY, 16 },
+#endif
+#ifdef EEXIST
+ { EEXIST, 17 },
+#endif
+#ifdef EXDEV
+ { EXDEV, 18 },
+#endif
+#ifdef ENODEV
+ { ENODEV, 19 },
+#endif
+#ifdef ENOTDIR
+ { ENOTDIR, 20 },
+#endif
+#ifdef EISDIR
+ { EISDIR, 21 },
+#endif
+#ifdef EINVAL
+ { EINVAL, 22 },
+#endif
+#ifdef ENFILE
+ { ENFILE, 23 },
+#endif
+#ifdef EMFILE
+ { EMFILE, 24 },
+#endif
+#ifdef ENOTTY
+ { ENOTTY, 25 },
+#endif
+#ifdef ETXTBSY
+ { ETXTBSY, 26 },
+#endif
+#ifdef EFBIG
+ { EFBIG, 27 },
+#endif
+#ifdef ENOSPC
+ { ENOSPC, 28 },
+#endif
+#ifdef ESPIPE
+ { ESPIPE, 29 },
+#endif
+#ifdef EROFS
+ { EROFS, 30 },
+#endif
+#ifdef EMLINK
+ { EMLINK, 31 },
+#endif
+#ifdef EPIPE
+ { EPIPE, 32 },
+#endif
+#ifdef EDOM
+ { EDOM, 33 },
+#endif
+#ifdef ERANGE
+ { ERANGE, 34 },
+#endif
+#ifdef EDEADLK
+ { EDEADLK, 35 },
+#endif
+#ifdef ENAMETOOLONG
+ { ENAMETOOLONG, 36 },
+#endif
+#ifdef ENOLCK
+ { ENOLCK, 37 },
+#endif
+#ifdef ENOSYS
+ { ENOSYS, 38 },
+#endif
+#ifdef ENOTEMPTY
+ { ENOTEMPTY, 39 },
+#endif
+#ifdef ELOOP
+ { ELOOP, 40 },
+#endif
+#ifdef EWOULDBLOCK
+ { EWOULDBLOCK, 11 },
+#endif
+#ifdef ENOMSG
+ { ENOMSG, 42 },
+#endif
+#ifdef EIDRM
+ { EIDRM, 43 },
+#endif
+#ifdef ECHRNG
+ { ECHRNG, 44 },
+#endif
+#ifdef EL2NSYNC
+ { EL2NSYNC, 45 },
+#endif
+#ifdef EL3HLT
+ { EL3HLT, 46 },
+#endif
+#ifdef EL3RST
+ { EL3RST, 47 },
+#endif
+#ifdef ELNRNG
+ { ELNRNG, 48 },
+#endif
+#ifdef EUNATCH
+ { EUNATCH, 49 },
+#endif
+#ifdef ENOCSI
+ { ENOCSI, 50 },
+#endif
+#ifdef EL2HLT
+ { EL2HLT, 51 },
+#endif
+#ifdef EBADE
+ { EBADE, 52 },
+#endif
+#ifdef EBADR
+ { EBADR, 53 },
+#endif
+#ifdef EXFULL
+ { EXFULL, 54 },
+#endif
+#ifdef ENOANO
+ { ENOANO, 55 },
+#endif
+#ifdef EBADRQC
+ { EBADRQC, 56 },
+#endif
+#ifdef EBADSLT
+ { EBADSLT, 57 },
+#endif
+#ifdef EDEADLOCK
+ { EDEADLOCK, 35 },
+#endif
+#ifdef EBFONT
+ { EBFONT, 59 },
+#endif
+#ifdef ENOSTR
+ { ENOSTR, 60 },
+#endif
+#ifdef ENODATA
+ { ENODATA, 61 },
+#endif
+#ifdef ETIME
+ { ETIME, 62 },
+#endif
+#ifdef ENOSR
+ { ENOSR, 63 },
+#endif
+#ifdef ENONET
+ { ENONET, 64 },
+#endif
+#ifdef ENOPKG
+ { ENOPKG, 65 },
+#endif
+#ifdef EREMOTE
+ { EREMOTE, 66 },
+#endif
+#ifdef ENOLINK
+ { ENOLINK, 67 },
+#endif
+#ifdef EADV
+ { EADV, 68 },
+#endif
+#ifdef ESRMNT
+ { ESRMNT, 69 },
+#endif
+#ifdef ECOMM
+ { ECOMM, 70 },
+#endif
+#ifdef EPROTO
+ { EPROTO, 71 },
+#endif
+#ifdef EMULTIHOP
+ { EMULTIHOP, 72 },
+#endif
+#ifdef EDOTDOT
+ { EDOTDOT, 73 },
+#endif
+#ifdef EBADMSG
+ { EBADMSG, 74 },
+#endif
+#ifdef EOVERFLOW
+ { EOVERFLOW, 75 },
+#endif
+#ifdef ENOTUNIQ
+ { ENOTUNIQ, 76 },
+#endif
+#ifdef EBADFD
+ { EBADFD, 77 },
+#endif
+#ifdef EREMCHG
+ { EREMCHG, 78 },
+#endif
+#ifdef ELIBACC
+ { ELIBACC, 79 },
+#endif
+#ifdef ELIBBAD
+ { ELIBBAD, 80 },
+#endif
+#ifdef ELIBSCN
+ { ELIBSCN, 81 },
+#endif
+#ifdef ELIBMAX
+ { ELIBMAX, 82 },
+#endif
+#ifdef ELIBEXEC
+ { ELIBEXEC, 83 },
+#endif
+#ifdef EILSEQ
+ { EILSEQ, 84 },
+#endif
+#ifdef ERESTART
+ { ERESTART, 85 },
+#endif
+#ifdef ESTRPIPE
+ { ESTRPIPE, 86 },
+#endif
+#ifdef EUSERS
+ { EUSERS, 87 },
+#endif
+#ifdef ENOTSOCK
+ { ENOTSOCK, 88 },
+#endif
+#ifdef EDESTADDRREQ
+ { EDESTADDRREQ, 89 },
+#endif
+#ifdef EMSGSIZE
+ { EMSGSIZE, 90 },
+#endif
+#ifdef EPROTOTYPE
+ { EPROTOTYPE, 91 },
+#endif
+#ifdef ENOPROTOOPT
+ { ENOPROTOOPT, 92 },
+#endif
+#ifdef EPROTONOSUPPORT
+ { EPROTONOSUPPORT, 93 },
+#endif
+#ifdef ESOCKTNOSUPPORT
+ { ESOCKTNOSUPPORT, 94 },
+#endif
+#ifdef EOPNOTSUPP
+ { EOPNOTSUPP, 95 },
+#endif
+#ifdef EPFNOSUPPORT
+ { EPFNOSUPPORT, 96 },
+#endif
+#ifdef EAFNOSUPPORT
+ { EAFNOSUPPORT, 97 },
+#endif
+#ifdef EADDRINUSE
+ { EADDRINUSE, 98 },
+#endif
+#ifdef EADDRNOTAVAIL
+ { EADDRNOTAVAIL, 99 },
+#endif
+#ifdef ENETDOWN
+ { ENETDOWN, 100 },
+#endif
+#ifdef ENETUNREACH
+ { ENETUNREACH, 101 },
+#endif
+#ifdef ENETRESET
+ { ENETRESET, 102 },
+#endif
+#ifdef ECONNABORTED
+ { ECONNABORTED, 103 },
+#endif
+#ifdef ECONNRESET
+ { ECONNRESET, 104 },
+#endif
+#ifdef ENOBUFS
+ { ENOBUFS, 105 },
+#endif
+#ifdef EISCONN
+ { EISCONN, 106 },
+#endif
+#ifdef ENOTCONN
+ { ENOTCONN, 107 },
+#endif
+#ifdef ESHUTDOWN
+ { ESHUTDOWN, 108 },
+#endif
+#ifdef ETOOMANYREFS
+ { ETOOMANYREFS, 109 },
+#endif
+#ifdef ETIMEDOUT
+ { ETIMEDOUT, 110 },
+#endif
+#ifdef ECONNREFUSED
+ { ECONNREFUSED, 111 },
+#endif
+#ifdef EHOSTDOWN
+ { EHOSTDOWN, 112 },
+#endif
+#ifdef EHOSTUNREACH
+ { EHOSTUNREACH, 113 },
+#endif
+#ifdef EALREADY
+ { EALREADY, 114 },
+#endif
+#ifdef EINPROGRESS
+ { EINPROGRESS, 115 },
+#endif
+#ifdef ESTALE
+ { ESTALE, 116 },
+#endif
+#ifdef EUCLEAN
+ { EUCLEAN, 117 },
+#endif
+#ifdef ENOTNAM
+ { ENOTNAM, 118 },
+#endif
+#ifdef ENAVAIL
+ { ENAVAIL, 119 },
+#endif
+#ifdef EISNAM
+ { EISNAM, 120 },
+#endif
+#ifdef EREMOTEIO
+ { EREMOTEIO, 121 },
+#endif
+#ifdef EDQUOT
+ { EDQUOT, 122 },
+#endif
+#ifdef ENOMEDIUM
+ { ENOMEDIUM, 123 },
+#endif
+#ifdef EMEDIUMTYPE
+ { EMEDIUMTYPE, 124 },
+#endif
+ { 0, -1 }
+};
+
+/* Extracted by applying
+ perl -ne 'if ($_ =~ /^#define/) { split;
+ printf "#ifdef $_[1]\n { %s, 0x%x },\n#endif\n",
+ $_[1], $_[2] =~ /^0/ ? oct($_[2]) : $_[2];}'
+ on pertinent parts of .../include/asm/fcntl.h in a GNU/Linux/CRIS
+ installation and removing synonyms and unnecessary items. Don't
+ forget the end-marker. */
+
+static const CB_TARGET_DEFS_MAP open_map[] = {
+#ifdef O_ACCMODE
+ { O_ACCMODE, 0x3 },
+#endif
+#ifdef O_RDONLY
+ { O_RDONLY, 0x0 },
+#endif
+#ifdef O_WRONLY
+ { O_WRONLY, 0x1 },
+#endif
+#ifdef O_RDWR
+ { O_RDWR, 0x2 },
+#endif
+#ifdef O_CREAT
+ { O_CREAT, 0x40 },
+#endif
+#ifdef O_EXCL
+ { O_EXCL, 0x80 },
+#endif
+#ifdef O_NOCTTY
+ { O_NOCTTY, 0x100 },
+#endif
+#ifdef O_TRUNC
+ { O_TRUNC, 0x200 },
+#endif
+#ifdef O_APPEND
+ { O_APPEND, 0x400 },
+#endif
+#ifdef O_NONBLOCK
+ { O_NONBLOCK, 0x800 },
+#endif
+#ifdef O_NDELAY
+ { O_NDELAY, 0x0 },
+#endif
+#ifdef O_SYNC
+ { O_SYNC, 0x1000 },
+#endif
+#ifdef FASYNC
+ { FASYNC, 0x2000 },
+#endif
+#ifdef O_DIRECT
+ { O_DIRECT, 0x4000 },
+#endif
+#ifdef O_LARGEFILE
+ { O_LARGEFILE, 0x8000 },
+#endif
+#ifdef O_DIRECTORY
+ { O_DIRECTORY, 0x10000 },
+#endif
+#ifdef O_NOFOLLOW
+ { O_NOFOLLOW, 0x20000 },
+#endif
+ { -1, -1 }
+};
+
+/* Needed for the cris_pipe_nonempty and cris_pipe_empty syscalls. */
+static SIM_CPU *current_cpu_for_cb_callback;
+
+static int syscall_read_mem (host_callback *, struct cb_syscall *,
+ unsigned long, char *, int);
+static int syscall_write_mem (host_callback *, struct cb_syscall *,
+ unsigned long, const char *, int);
+static USI create_map (SIM_DESC, struct cris_sim_mmapped_page **,
+ USI addr, USI len);
+static USI unmap_pages (SIM_DESC, struct cris_sim_mmapped_page **,
+ USI addr, USI len);
+static USI is_mapped (SIM_DESC, struct cris_sim_mmapped_page **,
+ USI addr, USI len);
+static void dump_statistics (SIM_CPU *current_cpu);
+static void make_first_thread (SIM_CPU *current_cpu);
+
+/* Read/write functions for system call interface. */
+
+static int
+syscall_read_mem (host_callback *cb ATTRIBUTE_UNUSED,
+ struct cb_syscall *sc,
+ unsigned long taddr, char *buf, int bytes)
+{
+ SIM_DESC sd = (SIM_DESC) sc->p1;
+ SIM_CPU *cpu = (SIM_CPU *) sc->p2;
+
+ return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
+}
+
+static int
+syscall_write_mem (host_callback *cb ATTRIBUTE_UNUSED,
+ struct cb_syscall *sc,
+ unsigned long taddr, const char *buf, int bytes)
+{
+ SIM_DESC sd = (SIM_DESC) sc->p1;
+ SIM_CPU *cpu = (SIM_CPU *) sc->p2;
+
+ return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
+}
+
+/* When we risk running self-modified code (as in trampolines), this is
+ called from special-case insns. The silicon CRIS CPU:s have enough
+ cache snooping implemented making this a simulator-only issue. Tests:
+ gcc.c-torture/execute/931002-1.c execution, -O3 -g
+ gcc.c-torture/execute/931002-1.c execution, -O3 -fomit-frame-pointer. */
+
+void
+cris_flush_simulator_decode_cache (SIM_CPU *current_cpu,
+ USI pc ATTRIBUTE_UNUSED)
+{
+ SIM_DESC sd = CPU_STATE (current_cpu);
+
+#if WITH_SCACHE
+ if (USING_SCACHE_P (sd))
+ scache_flush_cpu (current_cpu);
+#endif
+}
+
+/* Output statistics at the end of a run. */
+static void
+dump_statistics (SIM_CPU *current_cpu)
+{
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ CRIS_MISC_PROFILE *profp
+ = CPU_CRIS_MISC_PROFILE (current_cpu);
+ unsigned64 total = profp->basic_cycle_count;
+ const char *textmsg = "Basic clock cycles, total @: %llu\n";
+
+ /* The --cris-stats={basic|unaligned|schedulable|all} counts affect
+ what's included in the "total" count only. */
+ switch (CPU_CRIS_MISC_PROFILE (current_cpu)->flags
+ & FLAG_CRIS_MISC_PROFILE_ALL)
+ {
+ case FLAG_CRIS_MISC_PROFILE_SIMPLE:
+ break;
+
+ case (FLAG_CRIS_MISC_PROFILE_UNALIGNED | FLAG_CRIS_MISC_PROFILE_SIMPLE):
+ textmsg
+ = "Clock cycles including stall cycles for unaligned accesses @: %llu\n";
+ total += profp->unaligned_mem_dword_count;
+ break;
+
+ case (FLAG_CRIS_MISC_PROFILE_SCHEDULABLE | FLAG_CRIS_MISC_PROFILE_SIMPLE):
+ textmsg = "Schedulable clock cycles, total @: %llu\n";
+ total
+ += (profp->memsrc_stall_count
+ + profp->memraw_stall_count
+ + profp->movemsrc_stall_count
+ + profp->movemdst_stall_count
+ + profp->mulsrc_stall_count
+ + profp->jumpsrc_stall_count
+ + profp->unaligned_mem_dword_count);
+ break;
+
+ case FLAG_CRIS_MISC_PROFILE_ALL:
+ textmsg = "All accounted clock cycles, total @: %llu\n";
+ total
+ += (profp->memsrc_stall_count
+ + profp->memraw_stall_count
+ + profp->movemsrc_stall_count
+ + profp->movemdst_stall_count
+ + profp->movemaddr_stall_count
+ + profp->mulsrc_stall_count
+ + profp->jumpsrc_stall_count
+ + profp->branch_stall_count
+ + profp->jumptarget_stall_count
+ + profp->unaligned_mem_dword_count);
+ break;
+
+ default:
+ abort ();
+
+ sim_io_eprintf (sd,
+ "Internal inconsistency at %s:%d",
+ __FILE__, __LINE__);
+ sim_engine_halt (sd, current_cpu, NULL, 0,
+ sim_stopped, SIM_SIGILL);
+ }
+
+ /* Historically, these messages have gone to stderr, so we'll keep it
+ that way. It's also easier to then tell it from normal program
+ output. FIXME: Add redirect option like "run -e file". */
+ sim_io_eprintf (sd, textmsg, total);
+
+ /* For v32, unaligned_mem_dword_count should always be 0. For
+ v10, memsrc_stall_count should always be 0. */
+ sim_io_eprintf (sd, "Memory source stall cycles: %lld\n",
+ profp->memsrc_stall_count
+ + profp->unaligned_mem_dword_count);
+ sim_io_eprintf (sd, "Memory read-after-write stall cycles: %lld\n",
+ profp->memraw_stall_count);
+ sim_io_eprintf (sd, "Movem source stall cycles: %lld\n",
+ profp->movemsrc_stall_count);
+ sim_io_eprintf (sd, "Movem destination stall cycles: %lld\n",
+ profp->movemdst_stall_count);
+ sim_io_eprintf (sd, "Movem address stall cycles: %lld\n",
+ profp->movemaddr_stall_count);
+ sim_io_eprintf (sd, "Multiplication source stall cycles: %lld\n",
+ profp->mulsrc_stall_count);
+ sim_io_eprintf (sd, "Jump source stall cycles: %lld\n",
+ profp->jumpsrc_stall_count);
+ sim_io_eprintf (sd, "Branch misprediction stall cycles: %lld\n",
+ profp->branch_stall_count);
+ sim_io_eprintf (sd, "Jump target stall cycles: %lld\n",
+ profp->jumptarget_stall_count);
+}
+
+/* Check whether any part of [addr .. addr + len - 1] is already mapped.
+ Return 1 if a overlap detected, 0 otherwise. */
+
+static USI
+is_mapped (SIM_DESC sd ATTRIBUTE_UNUSED,
+ struct cris_sim_mmapped_page **rootp,
+ USI addr, USI len)
+{
+ struct cris_sim_mmapped_page *mapp;
+
+ if (len == 0 || (len & 8191))
+ abort ();
+
+ /* Iterate over the reverse-address sorted pages until we find a page in
+ or lower than the checked area. */
+ for (mapp = *rootp; mapp != NULL && mapp->addr >= addr; mapp = mapp->prev)
+ if (mapp->addr < addr + len && mapp->addr >= addr)
+ return 1;
+
+ return 0;
+}
+
+/* Create mmapped memory. */
+
+static USI
+create_map (SIM_DESC sd, struct cris_sim_mmapped_page **rootp, USI addr,
+ USI len)
+{
+ struct cris_sim_mmapped_page *mapp;
+ struct cris_sim_mmapped_page **higher_prevp = rootp;
+ USI new_addr = 0x40000000;
+
+ if (addr != 0)
+ new_addr = addr;
+ else if (*rootp)
+ new_addr = rootp[0]->addr + 8192;
+
+ if (len != 8192)
+ {
+ USI page_addr;
+
+ if (len & 8191)
+ /* Which is better: return an error for this, or just round it up? */
+ abort ();
+
+ /* Do a recursive call for each page in the request. */
+ for (page_addr = new_addr; len != 0; page_addr += 8192, len -= 8192)
+ if (create_map (sd, rootp, page_addr, 8192) >= (USI) -8191)
+ abort ();
+
+ return new_addr;
+ }
+
+ for (mapp = *rootp;
+ mapp != NULL && mapp->addr > new_addr;
+ mapp = mapp->prev)
+ higher_prevp = &mapp->prev;
+
+ /* Allocate the new page, on the next higher page from the last one
+ allocated, and link in the new descriptor before previous ones. */
+ mapp = malloc (sizeof (*mapp));
+
+ if (mapp == NULL)
+ return (USI) -ENOMEM;
+
+ sim_core_attach (sd, NULL, 0, access_read_write_exec, 0,
+ new_addr, len,
+ 0, NULL, NULL);
+
+ mapp->addr = new_addr;
+ mapp->prev = *higher_prevp;
+ *higher_prevp = mapp;
+
+ return new_addr;
+}
+
+/* Unmap one or more pages. */
+
+static USI
+unmap_pages (SIM_DESC sd, struct cris_sim_mmapped_page **rootp, USI addr,
+ USI len)
+{
+ struct cris_sim_mmapped_page *mapp;
+ struct cris_sim_mmapped_page **higher_prevp = rootp;
+
+ if (len != 8192)
+ {
+ USI page_addr;
+
+ if (len & 8191)
+ /* Which is better: return an error for this, or just round it up? */
+ abort ();
+
+ /* Loop backwards to make each call is O(1) over the number of pages
+ allocated, if we're unmapping from the high end of the pages. */
+ for (page_addr = addr + len - 8192;
+ page_addr >= addr;
+ page_addr -= 8192)
+ if (unmap_pages (sd, rootp, page_addr, 8192) != 0)
+ abort ();
+
+ return 0;
+ }
+
+ for (mapp = *rootp; mapp != NULL && mapp->addr > addr; mapp = mapp->prev)
+ higher_prevp = &mapp->prev;
+
+ if (mapp == NULL || mapp->addr != addr)
+ return EINVAL;
+
+ *higher_prevp = mapp->prev;
+ sim_core_detach (sd, NULL, 0, 0, addr);
+ free (mapp);
+ return 0;
+}
+
+/* The semantic code invokes this for illegal (unrecognized) instructions. */
+
+SEM_PC
+sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
+{
+ SIM_DESC sd = CPU_STATE (current_cpu);
+
+ sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
+ return vpc;
+}
+
+/* Handlers from the CGEN description that should not be called. */
+
+USI
+cris_bmod_handler (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
+ UINT srcreg ATTRIBUTE_UNUSED,
+ USI dstreg ATTRIBUTE_UNUSED)
+{
+ abort ();
+}
+
+void
+h_supr_set_handler (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
+ UINT index ATTRIBUTE_UNUSED,
+ USI page ATTRIBUTE_UNUSED,
+ USI newval ATTRIBUTE_UNUSED)
+{
+ abort ();
+}
+
+USI
+h_supr_get_handler (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
+ UINT index ATTRIBUTE_UNUSED,
+ USI page ATTRIBUTE_UNUSED)
+{
+ abort ();
+}
+
+/* Swap one context for another. */
+
+static void
+schedule (SIM_CPU *current_cpu, int next)
+{
+ /* Need to mark context-switches in the trace output. */
+ if ((CPU_CRIS_MISC_PROFILE (current_cpu)->flags
+ & FLAG_CRIS_MISC_PROFILE_XSIM_TRACE))
+ cris_trace_printf (CPU_STATE (current_cpu), current_cpu,
+ "\t#:%d\n", next);
+
+ /* Copy the current context (if there is one) to its slot. */
+ if (current_cpu->thread_data[current_cpu->threadno].cpu_context)
+ memcpy (current_cpu->thread_data[current_cpu->threadno].cpu_context,
+ ¤t_cpu->cpu_data_placeholder,
+ current_cpu->thread_cpu_data_size);
+
+ /* Copy the new context from its slot. */
+ memcpy (¤t_cpu->cpu_data_placeholder,
+ current_cpu->thread_data[next].cpu_context,
+ current_cpu->thread_cpu_data_size);
+
+ /* Update needed stuff to indicate the new context. */
+ current_cpu->threadno = next;
+
+ /* Handle pending signals. */
+ if (current_cpu->thread_data[next].sigpending
+ /* We don't run nested signal handlers. This means that pause(2)
+ and sigsuspend(2) do not work in sighandlers, but that
+ shouldn't be too hard a restriction. It also greatly
+ simplifies the code. */
+ && current_cpu->thread_data[next].cpu_context_atsignal == NULL)
+ {
+ int sig;
+
+ /* See if there's really a pending, non-blocked handler. We don't
+ queue signals, so just use the first one in ascending order. */
+ for (sig = 0; sig < 64; sig++)
+ if (current_cpu->thread_data[next].sigdata[sig].pending
+ && !current_cpu->thread_data[next].sigdata[sig].blocked)
+ {
+ bfd_byte regbuf[4];
+ USI sp;
+ int i;
+ USI blocked;
+ USI pc = sim_pc_get (current_cpu);
+
+ /* It's simpler to save the CPU context inside the simulator
+ than on the stack. */
+ current_cpu->thread_data[next].cpu_context_atsignal
+ = (*current_cpu
+ ->make_thread_cpu_data) (current_cpu,
+ current_cpu->thread_data[next]
+ .cpu_context);
+
+ (*CPU_REG_FETCH (current_cpu)) (current_cpu, H_GR_SP, regbuf, 4);
+ sp = bfd_getl32 (regbuf);
+
+ /* Make sure we have an aligned stack. */
+ sp &= ~3;
+
+ /* Make room for the signal frame, aligned. FIXME: Check that
+ the memory exists, map it in if absent. (BTW, should also
+ implement on-access automatic stack allocation). */
+ sp -= 20;
+
+ /* This isn't the same signal frame as the kernel uses, because
+ we don't want to bother getting all registers on and off the
+ stack. */
+
+ /* First, we store the currently blocked signals. */
+ blocked = 0;
+ for (i = 0; i < 32; i++)
+ blocked
+ |= current_cpu->thread_data[next].sigdata[i + 1].blocked << i;
+ sim_core_write_aligned_4 (current_cpu, pc, 0, sp, blocked);
+ blocked = 0;
+ for (i = 0; i < 31; i++)
+ blocked
+ |= current_cpu->thread_data[next].sigdata[i + 33].blocked << i;
+ sim_core_write_aligned_4 (current_cpu, pc, 0, sp + 4, blocked);
+
+ /* Then, the actual instructions. This is CPU-specific, but we
+ use instructions from the common subset for v10 and v32 which
+ should be safe for the time being but could be parametrized
+ if need be. */
+ /* MOVU.W [PC+],R9. */
+ sim_core_write_aligned_2 (current_cpu, pc, 0, sp + 8, 0x9c5f);
+ /* .WORD TARGET_SYS_sigreturn. */
+ sim_core_write_aligned_2 (current_cpu, pc, 0, sp + 10,
+ TARGET_SYS_sigreturn);
+ /* BREAK 13. */
+ sim_core_write_aligned_2 (current_cpu, pc, 0, sp + 12, 0xe93d);
+
+ /* NOP (on v32; it's SETF on v10, but is the correct compatible
+ instruction. Still, it doesn't matter because v10 has no
+ delay slot for BREAK so it will not be executed). */
+ sim_core_write_aligned_2 (current_cpu, pc, 0, sp + 16, 0x05b0);
+
+ /* Modify registers to hold the right values for the sighandler
+ context: updated stackpointer and return address pointing to
+ the sigreturn stub. */
+ bfd_putl32 (sp, regbuf);
+ (*CPU_REG_STORE (current_cpu)) (current_cpu, H_GR_SP, regbuf, 4);
+ bfd_putl32 (sp + 8, regbuf);
+ (*CPU_REG_STORE (current_cpu)) (current_cpu, TARGET_SRP_REGNUM,
+ regbuf, 4);
+
+ current_cpu->thread_data[next].sigdata[sig].pending = 0;
+
+ /* Block this signal (for the duration of the sighandler). */
+ current_cpu->thread_data[next].sigdata[sig].blocked = 1;
+
+ sim_pc_set (current_cpu, current_cpu->sighandler[sig]);
+ bfd_putl32 (sig, regbuf);
+ (*CPU_REG_STORE (current_cpu)) (current_cpu, H_GR_R10,
+ regbuf, 4);
+
+ /* We ignore a SA_SIGINFO flag in the sigaction call; the code I
+ needed all this for, specifies a SA_SIGINFO call but treats it
+ like an ordinary sighandler; only the signal number argument is
+ inspected. To make future need to implement SA_SIGINFO
+ correctly possible, we set the siginfo argument register to a
+ magic (hopefully non-address) number. (NB: then, you should
+ just need to pass the siginfo argument; it seems you probably
+ don't need to implement the specific rt_sigreturn.) */
+ bfd_putl32 (0xbad5161f, regbuf);
+ (*CPU_REG_STORE (current_cpu)) (current_cpu, H_GR_R11,
+ regbuf, 4);
+
+ /* The third argument is unused and the kernel sets it to 0. */
+ bfd_putl32 (0, regbuf);
+ (*CPU_REG_STORE (current_cpu)) (current_cpu, H_GR_R12,
+ regbuf, 4);
+ return;
+ }
+
+ /* No, there actually was no pending signal for this thread. Reset
+ this flag. */
+ current_cpu->thread_data[next].sigpending = 0;
+ }
+}
+
+/* Reschedule the simplest possible way until something else is absolutely
+ necessary:
+ - A. Find the next process (round-robin) that doesn't have at_syscall
+ set, schedule it.
+ - B. If there is none, just run the next process, round-robin.
+ - Clear at_syscall for the current process. */
+
+static void
+reschedule (SIM_CPU *current_cpu)
+{
+ int i;
+
+ /* Iterate over all thread slots, because after a few thread creations
+ and exits, we don't know where the live ones are. */
+ for (i = (current_cpu->threadno + 1) % SIM_TARGET_MAX_THREADS;
+ i != current_cpu->threadno;
+ i = (i + 1) % SIM_TARGET_MAX_THREADS)
+ if (current_cpu->thread_data[i].cpu_context
+ && current_cpu->thread_data[i].at_syscall == 0)
+ {
+ schedule (current_cpu, i);
+ return;
+ }
+
+ /* Pick any next live thread. */
+ for (i = (current_cpu->threadno + 1) % SIM_TARGET_MAX_THREADS;
+ i != current_cpu->threadno;
+ i = (i + 1) % SIM_TARGET_MAX_THREADS)
+ if (current_cpu->thread_data[i].cpu_context)
+ {
+ schedule (current_cpu, i);
+ return;
+ }
+
+ /* More than one live thread, but we couldn't find the next one? */
+ abort ();
+}
+
+/* Set up everything to receive (or IGN) an incoming signal to the
+ current context. */
+
+static int
+deliver_signal (SIM_CPU *current_cpu, int sig, unsigned int pid)
+{
+ int i;
+ USI pc = sim_pc_get (current_cpu);
+
+ /* Find the thread index of the pid. */
+ for (i = 0; i < SIM_TARGET_MAX_THREADS; i++)
+ /* Apparently it's ok to send signals to zombies (so a check for
+ current_cpu->thread_data[i].cpu_context != NULL would be
+ wrong). */
+ if (current_cpu->thread_data[i].threadid == pid - TARGET_PID)
+ {
+ if (sig < 64)
+ switch (current_cpu->sighandler[sig])
+ {
+ case TARGET_SIG_DFL:
+ switch (sig)
+ {
+ /* The following according to the glibc
+ documentation. (The kernel code has non-obvious
+ execution paths.) */
+ case TARGET_SIGFPE:
+ case TARGET_SIGILL:
+ case TARGET_SIGSEGV:
+ case TARGET_SIGBUS:
+ case TARGET_SIGABRT:
+ case TARGET_SIGTRAP:
+ case TARGET_SIGSYS:
+
+ case TARGET_SIGTERM:
+ case TARGET_SIGINT:
+ case TARGET_SIGQUIT:
+ case TARGET_SIGKILL:
+ case TARGET_SIGHUP:
+
+ case TARGET_SIGALRM:
+ case TARGET_SIGVTALRM:
+ case TARGET_SIGPROF:
+ case TARGET_SIGSTOP:
+
+ case TARGET_SIGPIPE:
+ case TARGET_SIGLOST:
+ case TARGET_SIGXCPU:
+ case TARGET_SIGXFSZ:
+ case TARGET_SIGUSR1:
+ case TARGET_SIGUSR2:
+ sim_io_eprintf (CPU_STATE (current_cpu),
+ "Exiting pid %d due to signal %d\n",
+ pid, sig);
+ sim_engine_halt (CPU_STATE (current_cpu), current_cpu,
+ NULL, pc, sim_stopped,
+ sig == TARGET_SIGABRT
+ ? SIM_SIGABRT : SIM_SIGILL);
+ return 0;
+
+ /* The default for all other signals is to be ignored. */
+ default:
+ return 0;
+ }
+
+ case TARGET_SIG_IGN:
+ switch (sig)
+ {
+ case TARGET_SIGKILL:
+ case TARGET_SIGSTOP:
+ /* Can't ignore these signals. */
+ sim_io_eprintf (CPU_STATE (current_cpu),
+ "Exiting pid %d due to signal %d\n",
+ pid, sig);
+ sim_engine_halt (CPU_STATE (current_cpu), current_cpu,
+ NULL, pc, sim_stopped, SIM_SIGILL);
+ return 0;
+
+ default:
+ return 0;
+ }
+ break;
+
+ default:
+ /* Mark the signal as pending, making schedule () check
+ closer. The signal will be handled when the thread is
+ scheduled and the signal is unblocked. */
+ current_cpu->thread_data[i].sigdata[sig].pending = 1;
+ current_cpu->thread_data[i].sigpending = 1;
+ return 0;
+ }
+ else
+ {
+ sim_io_eprintf (CPU_STATE (current_cpu),
+ "Unimplemented signal: %d\n", sig);
+ sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc,
+ sim_stopped, SIM_SIGILL);
+ }
+ }
+
+ return
+ -cb_host_to_target_errno (STATE_CALLBACK (CPU_STATE (current_cpu)),
+ ESRCH);
+}
+
+/* Make the vector and the first item, the main thread. */
+
+static void
+make_first_thread (SIM_CPU *current_cpu)
+{
+ current_cpu->thread_data
+ = xcalloc (1,
+ SIM_TARGET_MAX_THREADS
+ * sizeof (current_cpu->thread_data[0]));
+ current_cpu->thread_data[0].cpu_context
+ = (*current_cpu->make_thread_cpu_data) (current_cpu,
+ ¤t_cpu
+ ->cpu_data_placeholder);
+ current_cpu->thread_data[0].parent_threadid = -1;
+
+ /* For good measure. */
+ if (TARGET_SIG_DFL != 0)
+ abort ();
+}
+
+/* Main function: the handler of the "break 13" syscall insn. */
+
+USI
+cris_break_13_handler (SIM_CPU *current_cpu, USI callnum, USI arg1,
+ USI arg2, USI arg3, USI arg4, USI arg5, USI arg6,
+ USI pc)
+{
+ CB_SYSCALL s;
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ host_callback *cb = STATE_CALLBACK (sd);
+ int retval;
+ int threadno = current_cpu->threadno;
+
+ current_cpu->syscalls++;
+
+ CB_SYSCALL_INIT (&s);
+ s.func = callnum;
+ s.arg1 = arg1;
+ s.arg2 = arg2;
+ s.arg3 = arg3;
+
+ if (callnum == TARGET_SYS_exit && current_cpu->m1threads == 0)
+ {
+ if (CPU_CRIS_MISC_PROFILE (current_cpu)->flags
+ & FLAG_CRIS_MISC_PROFILE_ALL)
+ dump_statistics (current_cpu);
+ sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, arg1);
+ }
+
+ s.p1 = (PTR) sd;
+ s.p2 = (PTR) current_cpu;
+ s.read_mem = syscall_read_mem;
+ s.write_mem = syscall_write_mem;
+
+ current_cpu_for_cb_callback = current_cpu;
+
+ if (cb_syscall (cb, &s) != CB_RC_OK)
+ {
+ abort ();
+ sim_io_eprintf (sd, "Break 13: invalid %d? Returned %ld\n", callnum,
+ s.result);
+ sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGILL);
+ }
+
+ retval = s.result == -1 ? -s.errcode : s.result;
+
+ if (s.errcode != 0 && s.errcode == cb_host_to_target_errno (cb, ENOSYS))
+ {
+ /* If the generic simulator call said ENOSYS, then let's try the
+ ones we know ourselves.
+
+ The convention is to provide *very limited* functionality on an
+ as-needed basis, only what's covered by the test-suite, tests
+ added when functionality changes and abort with a descriptive
+ message for *everything* else. Where there's no test-case, we
+ just abort. */
+ switch (callnum)
+ {
+ case 0:
+ /* It's a pretty safe bet that the "old setup() system call"
+ number will not be re-used; we can't say the same for higher
+ numbers. We treat this simulator-generated call as "wait
+ forever"; we re-run this insn. The wait is ended by a
+ callback. Sanity check that this is the reason we got
+ here. */
+ if (current_cpu->thread_data == NULL
+ || (current_cpu->thread_data[threadno].pipe_write_fd == 0))
+ goto unimplemented_syscall;
+
+ sim_pc_set (current_cpu, pc);
+ retval = arg1;
+ break;
+
+ case TARGET_SYS_fcntl64:
+ case TARGET_SYS_fcntl:
+ if (arg2 == 1)
+ {
+ /* F_GETFD.
+ Glibc checks stdin, stdout and stderr fd:s for
+ close-on-exec security sanity. We just need to provide a
+ OK return value. If we really need to have a
+ close-on-exec flag true, we could just do a real fcntl
+ here. */
+ retval = 0;
+ }
+ else if (arg2 == 2)
+ {
+ /* F_SETFD. Just ignore attempts to set the close-on-exec
+ flag. */
+ retval = 0;
+ }
+ break;
+
+ case TARGET_SYS_uname:
+ {
+ /* Fill in a few constants to appease glibc. */
+ static const char sim_utsname[6][65] =
+ {
+ "Linux",
+ "sim-target",
+ "2.4.5",
+ TARGET_UTSNAME,
+ "cris",
+ "localdomain"
+ };
+
+ if ((s.write_mem) (cb, &s, arg1, (const char *) sim_utsname,
+ sizeof (sim_utsname))
+ != sizeof (sim_utsname))
+ retval = -cb_host_to_target_errno (cb, EFAULT);
+ else
+ retval = 0;
+ break;
+ }
+
+ case TARGET_SYS_geteuid32:
+ /* We tell the truth with these. Maybe we shouldn't, but it
+ should match the "stat" information. */
+ retval = geteuid ();
+ break;
+
+ case TARGET_SYS_getuid32:
+ retval = getuid ();
+ break;
+
+ case TARGET_SYS_getegid32:
+ retval = getegid ();
+ break;
+
+ case TARGET_SYS_getgid32:
+ retval = getgid ();
+ break;
+
+ case TARGET_SYS_brk:
+ /* Most often, we just return the argument, like the Linux
+ kernel. */
+ retval = arg1;
+
+ if (arg1 == 0)
+ retval = current_cpu->endbrk;
+ else if (arg1 <= current_cpu->endmem)
+ current_cpu->endbrk = arg1;
+ else
+ {
+ USI new_end = (arg1 + 8191) & ~8191;
+
+ /* If the simulator wants to brk more than a certain very
+ large amount, something is wrong. FIXME: Return an error
+ or abort? Have command-line selectable? */
+ if (new_end - current_cpu->endmem > SIM_MAX_ALLOC_CHUNK)
+ {
+ current_cpu->endbrk = current_cpu->endmem;
+ retval = current_cpu->endmem;
+ break;
+ }
+
+ sim_core_attach (sd, NULL, 0, access_read_write_exec, 0,
+ current_cpu->endmem,
+ new_end - current_cpu->endmem,
+ 0, NULL, NULL);
+ current_cpu->endbrk = arg1;
+ current_cpu->endmem = new_end;
+ }
+ break;
+
+ case TARGET_SYS_getpid:
+ /* Correct until CLONE_THREAD is implemented. */
+ retval = current_cpu->thread_data == NULL
+ ? TARGET_PID
+ : TARGET_PID + current_cpu->thread_data[threadno].threadid;
+ break;
+
+ case TARGET_SYS_getppid:
+ /* Correct until CLONE_THREAD is implemented. */
+ retval = current_cpu->thread_data == NULL
+ ? TARGET_PID - 1
+ : (TARGET_PID
+ + current_cpu->thread_data[threadno].parent_threadid);
+ break;
+
+ case TARGET_SYS_mmap2:
+ {
+ USI addr = arg1;
+ USI len = arg2;
+ USI prot = arg3;
+ USI flags = arg4;
+ USI fd = arg5;
+ USI pgoff = arg6;
+
+ /* If the simulator wants to mmap more than the very large
+ limit, something is wrong. FIXME: Return an error or
+ abort? Have command-line selectable? */
+ if (len > SIM_MAX_ALLOC_CHUNK)
+ {
+ retval = -cb_host_to_target_errno (cb, ENOMEM);
+ break;
+ }
+
+ if ((prot != (TARGET_PROT_READ | TARGET_PROT_WRITE)
+ && (prot
+ != (TARGET_PROT_READ
+ | TARGET_PROT_WRITE
+ | TARGET_PROT_EXEC))
+ && prot != TARGET_PROT_READ)
+ || (flags != (TARGET_MAP_ANONYMOUS | TARGET_MAP_PRIVATE)
+ && flags != TARGET_MAP_PRIVATE
+ && flags != TARGET_MAP_SHARED)
+ || (fd != (USI) -1 && prot != TARGET_PROT_READ)
+ || pgoff != 0
+ || ((len & 8191) != 0 && fd == (USI) -1))
+ {
+ sim_io_eprintf (sd, "Unimplemented mmap2 call "
+ "(0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx)\n",
+ (unsigned long) arg1,
+ (unsigned long) arg2,
+ (unsigned long) arg3,
+ (unsigned long) arg4,
+ (unsigned long) arg5,
+ (unsigned long) arg6);
+ sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped,
+ SIM_SIGILL);
+ break;
+ }
+ else if (fd != (USI) -1)
+ {
+ /* Map a file. */
+
+ USI newaddr;
+ USI pos;
+
+ /* A non-aligned argument is allowed for files. */
+ USI newlen = (len + 8191) & ~8191;
+
+ /* We only support read, which we should already have
+ checked. Check again anyway. */
+ if (prot != TARGET_PROT_READ)
+ abort ();
+
+ newaddr
+ = create_map (sd, ¤t_cpu->highest_mmapped_page, addr,
+ newlen);
+
+ if (newaddr >= (USI) -8191)
+ {
+ abort ();
+ retval = -cb_host_to_target_errno (cb, -(SI) newaddr);
+ break;
+ }
+
+ /* Find the current position in the file. */
+ s.func = TARGET_SYS_lseek;
+ s.arg1 = fd;
+ s.arg2 = 0;
+ s.arg3 = SEEK_CUR;
+ if (cb_syscall (cb, &s) != CB_RC_OK)
+ abort ();
+ pos = s.result;
+
+ if (s.result < 0)
+ abort ();
+
+ /* Use the standard read callback to read in "len"
+ bytes. */
+ s.func = TARGET_SYS_read;
+ s.arg1 = fd;
+ s.arg2 = newaddr;
+ s.arg3 = len;
+ if (cb_syscall (cb, &s) != CB_RC_OK)
+ abort ();
+
+ if ((USI) s.result != len)
+ abort ();
+
+ /* After reading, we need to go back to the previous
+ position in the file. */
+ s.func = TARGET_SYS_lseek;
+ s.arg1 = fd;
+ s.arg2 = pos;
+ s.arg3 = SEEK_SET;
+ if (cb_syscall (cb, &s) != CB_RC_OK)
+ abort ();
+ if (pos != (USI) s.result)
+ abort ();
+
+ retval = newaddr;
+ }
+ else
+ {
+ USI newaddr
+ = create_map (sd, ¤t_cpu->highest_mmapped_page, addr, len);
+
+ if (newaddr >= (USI) -8191)
+ retval = -cb_host_to_target_errno (cb, -(SI) newaddr);
+ else
+ retval = newaddr;
+ }
+ break;
+ }
+
+ case TARGET_SYS_mprotect:
+ {
+ /* We only cover the case of linuxthreads mprotecting out its
+ stack guard page. */
+ USI addr = arg1;
+ USI len = arg2;
+ USI prot = arg3;
+
+ if ((addr & 8191) != 0
+ || len != 8192
+ || prot != TARGET_PROT_NONE
+ || !is_mapped (sd, ¤t_cpu->highest_mmapped_page, addr,
+ len))
+ {
+ sim_io_eprintf (sd, "Unimplemented mprotect call "
+ "(0x%lx, 0x%lx, 0x%lx)\n",
+ (unsigned long) arg1,
+ (unsigned long) arg2,
+ (unsigned long) arg3);
+ sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped,
+ SIM_SIGILL);
+ break;
+ }
+
+ /* FIXME: We should account for pages like this that are
+ "mprotected out". For now, we just tell the simulator
+ core to remove that page from its map. */
+ sim_core_detach (sd, NULL, 0, 0, addr);
+ retval = 0;
+ break;
+ }
+
+ case TARGET_SYS_ioctl:
+ {
+ /* We support only a very limited functionality: checking
+ stdout with TCGETS to perform the isatty function. The
+ TCGETS ioctl isn't actually performed or the result used by
+ an isatty () caller in a "hello, world" program; only the
+ return value is then used. Maybe we shouldn't care about
+ the environment of the simulator regarding isatty, but
+ that's been working before, in the xsim simulator. */
+ if (arg2 == TARGET_TCGETS && arg1 == 1)
+ retval = isatty (1) ? 0 : cb_host_to_target_errno (cb, EINVAL);
+ else
+ retval = -cb_host_to_target_errno (cb, EINVAL);
+ break;
+ }
+
+ case TARGET_SYS_munmap:
+ {
+ USI addr = arg1;
+ USI len = arg2;
+ USI result
+ = unmap_pages (sd, ¤t_cpu->highest_mmapped_page, addr,
+ len);
+ retval = result != 0 ? -cb_host_to_target_errno (cb, result) : 0;
+ break;
+ }
+
+ case TARGET_SYS_wait4:
+ {
+ int i;
+ USI pid = arg1;
+ USI saddr = arg2;
+ USI options = arg3;
+ USI rusagep = arg4;
+
+ /* FIXME: We're not properly implementing __WCLONE, and we
+ don't really need the special casing so we might as well
+ make this general. */
+ if ((!(pid == (USI) -1
+ && options == (TARGET___WCLONE | TARGET_WNOHANG)
+ && saddr != 0)
+ && !(pid > 0
+ && (options == TARGET___WCLONE
+ || options == TARGET___WALL)))
+ || rusagep != 0
+ || current_cpu->thread_data == NULL)
+ {
+ sim_io_eprintf (sd, "Unimplemented wait4 call "
+ "(0x%lx, 0x%lx, 0x%lx, 0x%lx)\n",
+ (unsigned long) arg1,
+ (unsigned long) arg2,
+ (unsigned long) arg3,
+ (unsigned long) arg4);
+ sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped,
+ SIM_SIGILL);
+ break;
+ }
+
+ if (pid == (USI) -1)
+ for (i = 1; i < SIM_TARGET_MAX_THREADS; i++)
+ {
+ if (current_cpu->thread_data[threadno].threadid
+ == current_cpu->thread_data[i].parent_threadid
+ && current_cpu->thread_data[i].threadid != 0
+ && current_cpu->thread_data[i].cpu_context == NULL)
+ {
+ /* A zombied child. Get the exit value and clear the
+ zombied entry so it will be reused. */
+ sim_core_write_unaligned_4 (current_cpu, pc, 0, saddr,
+ current_cpu
+ ->thread_data[i].exitval);
+ retval
+ = current_cpu->thread_data[i].threadid + TARGET_PID;
+ memset (¤t_cpu->thread_data[i], 0,
+ sizeof (current_cpu->thread_data[i]));
+ goto outer_break;
+ }
+ }
+ else
+ {
+ /* We're waiting for a specific PID. If we don't find
+ it zombied on this run, rerun the syscall. */
+ for (i = 1; i < SIM_TARGET_MAX_THREADS; i++)
+ if (pid == current_cpu->thread_data[i].threadid + TARGET_PID
+ && current_cpu->thread_data[i].cpu_context == NULL)
+ {
+ if (saddr != 0)
+ /* Get the exit value if the caller wants it. */
+ sim_core_write_unaligned_4 (current_cpu, pc, 0,
+ saddr,
+ current_cpu
+ ->thread_data[i]
+ .exitval);
+
+ retval
+ = current_cpu->thread_data[i].threadid + TARGET_PID;
+ memset (¤t_cpu->thread_data[i], 0,
+ sizeof (current_cpu->thread_data[i]));
+
+ goto outer_break;
+ }
+
+ sim_pc_set (current_cpu, pc);
+ }
+
+ retval = -cb_host_to_target_errno (cb, ECHILD);
+ outer_break:
+ break;
+ }
+
+ case TARGET_SYS_rt_sigaction:
+ {
+ USI signum = arg1;
+ USI old_sa = arg3;
+ USI new_sa = arg2;
+
+ /* The kernel says:
+ struct sigaction {
+ __sighandler_t sa_handler;
+ unsigned long sa_flags;
+ void (*sa_restorer)(void);
+ sigset_t sa_mask;
+ }; */
+
+ if (old_sa != 0)
+ {
+ sim_core_write_unaligned_4 (current_cpu, pc, 0, old_sa + 0,
+ current_cpu->sighandler[signum]);
+ sim_core_write_unaligned_4 (current_cpu, pc, 0, arg3 + 4, 0);
+ sim_core_write_unaligned_4 (current_cpu, pc, 0, arg3 + 8, 0);
+
+ /* We'll assume _NSIG_WORDS is 2 for the kernel. */
+ sim_core_write_unaligned_4 (current_cpu, pc, 0, arg3 + 12, 0);
+ sim_core_write_unaligned_4 (current_cpu, pc, 0, arg3 + 16, 0);
+ }
+ if (new_sa != 0)
+ {
+ USI sa_handler
+ = sim_core_read_unaligned_4 (current_cpu, pc, 0, new_sa);
+ USI sa_flags
+ = sim_core_read_unaligned_4 (current_cpu, pc, 0, new_sa + 4);
+ USI sa_restorer
+ = sim_core_read_unaligned_4 (current_cpu, pc, 0, new_sa + 8);
+ USI sa_mask_low
+ = sim_core_read_unaligned_4 (current_cpu, pc, 0, new_sa + 12);
+ USI sa_mask_high
+ = sim_core_read_unaligned_4 (current_cpu, pc, 0, new_sa + 16);
+
+ /* We won't interrupt a syscall so we won't restart it,
+ but a signal(2) call ends up syscalling rt_sigaction
+ with this flag, so we have to handle it. The
+ sa_restorer field contains garbage when not
+ TARGET_SA_RESTORER, so don't look at it. For the
+ time being, we don't nest sighandlers, so we
+ ignore the sa_mask, which simplifies things. */
+ if ((sa_flags != 0
+ && sa_flags != TARGET_SA_RESTART
+ && sa_flags != (TARGET_SA_RESTART|TARGET_SA_SIGINFO))
+ || sa_handler == 0)
+ {
+ sim_io_eprintf (sd, "Unimplemented rt_sigaction "
+ "syscall (0x%lx, "
+ "0x%lx: [0x%x, 0x%x, 0x%x, "
+ "{0x%x, 0x%x}], "
+ "0x%lx)\n",
+ (unsigned long) arg1,
+ (unsigned long) arg2,
+ sa_handler, sa_flags, sa_restorer,
+ sa_mask_low, sa_mask_high,
+ (unsigned long) arg3);
+ sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped,
+ SIM_SIGILL);
+ }
+
+ current_cpu->sighandler[signum] = sa_handler;
+
+ /* Because we may have unblocked signals, one may now be
+ pending, if there are threads, that is. */
+ if (current_cpu->thread_data)
+ current_cpu->thread_data[threadno].sigpending = 1;
+ }
+ retval = 0;
+ break;
+ }
+
+ case TARGET_SYS_mremap:
+ {
+ USI addr = arg1;
+ USI old_len = arg2;
+ USI new_len = arg3;
+ USI flags = arg4;
+ USI new_addr = arg5;
+ USI mapped_addr;
+
+ if (new_len == old_len)
+ /* The program and/or library is possibly confused but
+ this is a valid call. Happens with ipps-1.40 on file
+ svs_all. */
+ retval = addr;
+ else if (new_len < old_len)
+ {
+ /* Shrinking is easy. */
+ if (unmap_pages (sd, ¤t_cpu->highest_mmapped_page,
+ addr + new_len, old_len - new_len) != 0)
+ retval = -cb_host_to_target_errno (cb, EINVAL);
+ else
+ retval = addr;
+ }
+ else if (! is_mapped (sd, ¤t_cpu->highest_mmapped_page,
+ addr + old_len, new_len - old_len))
+ {
+ /* If the extension isn't mapped, we can just add it. */
+ mapped_addr
+ = create_map (sd, ¤t_cpu->highest_mmapped_page,
+ addr + old_len, new_len - old_len);
+
+ if (mapped_addr > (USI) -8192)
+ retval = -cb_host_to_target_errno (cb, -(SI) mapped_addr);
+ else
+ retval = addr;
+ }
+ else if (flags & TARGET_MREMAP_MAYMOVE)
+ {
+ /* Create a whole new map and copy the contents
+ block-by-block there. We ignore the new_addr argument
+ for now. */
+ char buf[8192];
+ USI prev_addr = addr;
+ USI prev_len = old_len;
+
+ mapped_addr
+ = create_map (sd, ¤t_cpu->highest_mmapped_page,
+ 0, new_len);
+
+ if (mapped_addr > (USI) -8192)
+ {
+ retval = -cb_host_to_target_errno (cb, -(SI) new_addr);
+ break;
+ }
+
+ retval = mapped_addr;
+
+ for (; old_len > 0;
+ old_len -= 8192, mapped_addr += 8192, addr += 8192)
+ {
+ if (sim_core_read_buffer (sd, current_cpu, read_map, buf,
+ addr, 8192) != 8192
+ || sim_core_write_buffer (sd, current_cpu, 0, buf,
+ mapped_addr, 8192) != 8192)
+ abort ();
+ }
+
+ if (unmap_pages (sd, ¤t_cpu->highest_mmapped_page,
+ prev_addr, prev_len) != 0)
+ abort ();
+ }
+ else
+ retval = -cb_host_to_target_errno (cb, -ENOMEM);
+ break;
+ }
+
+ case TARGET_SYS_poll:
+ {
+ int npollfds = arg2;
+ int timeout = arg3;
+ SI ufds = arg1;
+ SI fd = -1;
+ HI events = -1;
+ HI revents = 0;
+ struct stat buf;
+ int i;
+
+ /* The kernel says:
+ struct pollfd {
+ int fd;
+ short events;
+ short revents;
+ }; */
+
+ /* Check that this is the expected poll call from
+ linuxthreads/manager.c; we don't support anything else.
+ Remember, fd == 0 isn't supported. */
+ if (npollfds != 1
+ || ((fd = sim_core_read_unaligned_4 (current_cpu, pc,
+ 0, ufds)) <= 0)
+ || ((events = sim_core_read_unaligned_2 (current_cpu, pc,
+ 0, ufds + 4))
+ != TARGET_POLLIN)
+ || ((cb->fstat) (cb, fd, &buf) != 0
+ || (buf.st_mode & S_IFIFO) == 0)
+ || current_cpu->thread_data == NULL)
+ {
+ sim_io_eprintf (sd, "Unimplemented poll syscall "
+ "(0x%lx: [0x%x, 0x%x, x], 0x%lx, 0x%lx)\n",
+ (unsigned long) arg1, fd, events,
+ (unsigned long) arg2, (unsigned long) arg3);
+ sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGILL);
+ break;
+ }
+
+ retval = 0;
+
+ /* Iterate over threads; find a marker that a writer is
+ sleeping, waiting for a reader. */
+ for (i = 0; i < SIM_TARGET_MAX_THREADS; i++)
+ if (current_cpu->thread_data[i].cpu_context != NULL
+ && current_cpu->thread_data[i].pipe_read_fd == fd)
+ {
+ revents = TARGET_POLLIN;
+ retval = 1;
+ break;
+ }
+
+ /* Timeout decreases with whatever time passed between the
+ last syscall and this. That's not exactly right for the
+ first call, but it's close enough that it isn't
+ worthwhile to complicate matters by making that a special
+ case. */
+ timeout
+ -= (TARGET_TIME_MS (current_cpu)
+ - (current_cpu->thread_data[threadno].last_execution));
+
+ /* Arrange to repeat this syscall until timeout or event,
+ decreasing timeout at each iteration. */
+ if (timeout > 0 && revents == 0)
+ {
+ bfd_byte timeout_buf[4];
+
+ bfd_putl32 (timeout, timeout_buf);
+ (*CPU_REG_STORE (current_cpu)) (current_cpu,
+ H_GR_R12, timeout_buf, 4);
+ sim_pc_set (current_cpu, pc);
+ retval = arg1;
+ break;
+ }
+
+ sim_core_write_unaligned_2 (current_cpu, pc, 0, ufds + 4 + 2,
+ revents);
+ break;
+ }
+
+ case TARGET_SYS_gettimeofday:
+ if (arg1 != 0)
+ {
+ USI ts = TARGET_TIME (current_cpu);
+ USI tms = TARGET_TIME_MS (current_cpu);
+
+ /* First dword is seconds since TARGET_EPOCH. */
+ sim_core_write_unaligned_4 (current_cpu, pc, 0, arg1, ts);
+
+ /* Second dword is microseconds. */
+ sim_core_write_unaligned_4 (current_cpu, pc, 0, arg1 + 4,
+ (tms % 1000) * 1000);
+ }
+ if (arg2 != 0)
+ {
+ /* Time-zone info is always cleared. */
+ sim_core_write_unaligned_4 (current_cpu, pc, 0, arg2, 0);
+ sim_core_write_unaligned_4 (current_cpu, pc, 0, arg2 + 4, 0);
+ }
+ retval = 0;
+ break;
+
+ case TARGET_SYS_llseek:
+ {
+ /* If it fits, tweak parameters to fit the "generic" 32-bit
+ lseek and use that. */
+ SI fd = arg1;
+ SI offs_hi = arg2;
+ SI offs_lo = arg3;
+ SI resultp = arg4;
+ SI whence = arg5;
+ retval = 0;
+
+ if (!((offs_hi == 0 && offs_lo >= 0)
+ || (offs_hi == -1 && offs_lo < 0)))
+ {
+ sim_io_eprintf (sd,
+ "Unimplemented llseek offset,"
+ " fd %d: 0x%x:0x%x\n",
+ fd, (unsigned) arg2, (unsigned) arg3);
+ sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped,
+ SIM_SIGILL);
+ }
+
+ s.func = TARGET_SYS_lseek;
+ s.arg2 = offs_lo;
+ s.arg3 = whence;
+ if (cb_syscall (cb, &s) != CB_RC_OK)
+ {
+ sim_io_eprintf (sd, "Break 13: invalid %d? Returned %ld\n", callnum,
+ s.result);
+ sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGILL);
+ }
+ if (s.result < 0)
+ retval = -s.errcode;
+ else
+ {
+ sim_core_write_unaligned_4 (current_cpu, pc, 0, resultp,
+ s.result);
+ sim_core_write_unaligned_4 (current_cpu, pc, 0, resultp + 4,
+ s.result < 0 ? -1 : 0);
+ }
+ break;
+ }
+
+ /* This one does have a generic callback function, but at the time
+ of this writing, cb_syscall does not have code for it, and we
+ need target-specific code for the threads implementation
+ anyway. */
+ case TARGET_SYS_kill:
+ {
+ USI pid = arg1;
+ USI sig = arg2;
+
+ retval = 0;
+
+ /* At kill(2), glibc sets signal masks such that the thread
+ machinery is initialized. Still, there is and was only
+ one thread. */
+ if (current_cpu->max_threadid == 0)
+ {
+ if (pid != TARGET_PID)
+ {
+ retval = -cb_host_to_target_errno (cb, EPERM);
+ break;
+ }
+
+ /* FIXME: Signal infrastructure (target-to-sim mapping). */
+ if (sig == TARGET_SIGABRT)
+ /* A call "abort ()", i.e. "kill (getpid(), SIGABRT)" is
+ the end-point for failing GCC test-cases. */
+ sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped,
+ SIM_SIGABRT);
+ else
+ {
+ sim_io_eprintf (sd, "Unimplemented signal: %d\n", sig);
+ sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped,
+ SIM_SIGILL);
+ }
+
+ /* This will not be reached. */
+ abort ();
+ }
+ else
+ retval = deliver_signal (current_cpu, sig, pid);
+ break;
+ }
+
+ case TARGET_SYS_rt_sigprocmask:
+ {
+ int i;
+ USI how = arg1;
+ USI newsetp = arg2;
+ USI oldsetp = arg3;
+
+ if (how != TARGET_SIG_BLOCK
+ && how != TARGET_SIG_SETMASK
+ && how != TARGET_SIG_UNBLOCK)
+ {
+ sim_io_eprintf (sd, "Unimplemented rt_sigprocmask syscall "
+ "(0x%x, 0x%x, 0x%x)\n", arg1, arg2, arg3);
+ sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped,
+ SIM_SIGILL);
+ retval = 0;
+ break;
+ }
+
+ if (newsetp)
+ {
+ USI set_low
+ = sim_core_read_unaligned_4 (current_cpu, pc, 0,
+ newsetp);
+ USI set_high
+ = sim_core_read_unaligned_4 (current_cpu, pc, 0,
+ newsetp + 4);
+
+ /* The sigmask is kept in the per-thread data, so we may
+ need to create the first one. */
+ if (current_cpu->thread_data == NULL)
+ make_first_thread (current_cpu);
+
+ if (how == TARGET_SIG_SETMASK)
+ for (i = 0; i < 64; i++)
+ current_cpu->thread_data[threadno].sigdata[i].blocked = 0;
+
+ for (i = 0; i < 32; i++)
+ if ((set_low & (1 << i)))
+ current_cpu->thread_data[threadno].sigdata[i + 1].blocked
+ = (how != TARGET_SIG_UNBLOCK);
+
+ for (i = 0; i < 31; i++)
+ if ((set_high & (1 << i)))
+ current_cpu->thread_data[threadno].sigdata[i + 33].blocked
+ = (how != TARGET_SIG_UNBLOCK);
+
+ /* The mask changed, so a signal may be unblocked for
+ execution. */
+ current_cpu->thread_data[threadno].sigpending = 1;
+ }
+
+ if (oldsetp != 0)
+ {
+ USI set_low = 0;
+ USI set_high = 0;
+
+ for (i = 0; i < 32; i++)
+ if (current_cpu->thread_data[threadno]
+ .sigdata[i + 1].blocked)
+ set_low |= 1 << i;
+ for (i = 0; i < 31; i++)
+ if (current_cpu->thread_data[threadno]
+ .sigdata[i + 33].blocked)
+ set_high |= 1 << i;
+
+ sim_core_write_unaligned_4 (current_cpu, pc, 0, oldsetp + 0, set_low);
+ sim_core_write_unaligned_4 (current_cpu, pc, 0, oldsetp + 4, set_high);
+ }
+
+ retval = 0;
+ break;
+ }
+
+ case TARGET_SYS_sigreturn:
+ {
+ int i;
+ bfd_byte regbuf[4];
+ int was_sigsuspended;
+
+ if (current_cpu->thread_data == NULL
+ /* The CPU context is saved with the simulator data, not
+ on the stack as in the real world. */
+ || (current_cpu->thread_data[threadno].cpu_context_atsignal
+ == NULL))
+ {
+ sim_io_eprintf (sd, "Invalid sigreturn syscall: no signal"
+ " handler active "
+ "(0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx)\n",
+ (unsigned long) arg1,
+ (unsigned long) arg2,
+ (unsigned long) arg3,
+ (unsigned long) arg4,
+ (unsigned long) arg5,
+ (unsigned long) arg6);
+ sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped,
+ SIM_SIGILL);
+ }
+
+ was_sigsuspended
+ = current_cpu->thread_data[threadno].sigsuspended;
+
+ /* Restore the sigmask, either from the stack copy made when
+ the sighandler was called, or from the saved state
+ specifically for sigsuspend(2). */
+ if (was_sigsuspended)
+ {
+ current_cpu->thread_data[threadno].sigsuspended = 0;
+ for (i = 0; i < 64; i++)
+ current_cpu->thread_data[threadno].sigdata[i].blocked
+ = current_cpu->thread_data[threadno]
+ .sigdata[i].blocked_suspendsave;
+ }
+ else
+ {
+ USI sp;
+ USI set_low;
+ USI set_high;
+
+ (*CPU_REG_FETCH (current_cpu)) (current_cpu,
+ H_GR_SP, regbuf, 4);
+ sp = bfd_getl32 (regbuf);
+ set_low
+ = sim_core_read_unaligned_4 (current_cpu, pc, 0, sp);
+ set_high
+ = sim_core_read_unaligned_4 (current_cpu, pc, 0, sp + 4);
+
+ for (i = 0; i < 32; i++)
+ current_cpu->thread_data[threadno].sigdata[i + 1].blocked
+ = (set_low & (1 << i)) != 0;
+ for (i = 0; i < 31; i++)
+ current_cpu->thread_data[threadno].sigdata[i + 33].blocked
+ = (set_high & (1 << i)) != 0;
+ }
+
+ /* The mask changed, so a signal may be unblocked for
+ execution. */
+ current_cpu->thread_data[threadno].sigpending = 1;
+
+ memcpy (¤t_cpu->cpu_data_placeholder,
+ current_cpu->thread_data[threadno].cpu_context_atsignal,
+ current_cpu->thread_cpu_data_size);
+ free (current_cpu->thread_data[threadno].cpu_context_atsignal);
+ current_cpu->thread_data[threadno].cpu_context_atsignal = NULL;
+
+ /* The return value must come from the saved R10. */
+ (*CPU_REG_FETCH (current_cpu)) (current_cpu, H_GR_R10, regbuf, 4);
+ retval = bfd_getl32 (regbuf);
+
+ /* We must also break the "sigsuspension loop". */
+ if (was_sigsuspended)
+ sim_pc_set (current_cpu, sim_pc_get (current_cpu) + 2);
+ break;
+ }
+
+ case TARGET_SYS_rt_sigsuspend:
+ {
+ USI newsetp = arg1;
+ USI setsize = arg2;
+
+ if (setsize != 8)
+ {
+ sim_io_eprintf (sd, "Unimplemented rt_sigsuspend syscall"
+ " arguments (0x%lx, 0x%lx)\n",
+ (unsigned long) arg1, (unsigned long) arg2);
+ sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped,
+ SIM_SIGILL);
+ }
+
+ /* Don't change the signal mask if we're already in
+ sigsuspend state (i.e. this syscall is a rerun). */
+ else if (!current_cpu->thread_data[threadno].sigsuspended)
+ {
+ USI set_low
+ = sim_core_read_unaligned_4 (current_cpu, pc, 0,
+ newsetp);
+ USI set_high
+ = sim_core_read_unaligned_4 (current_cpu, pc, 0,
+ newsetp + 4);
+ int i;
+
+ /* Save the current sigmask and insert the user-supplied
+ one. */
+ for (i = 0; i < 32; i++)
+ {
+ current_cpu->thread_data[threadno]
+ .sigdata[i + 1].blocked_suspendsave
+ = current_cpu->thread_data[threadno]
+ .sigdata[i + 1].blocked;
+
+ current_cpu->thread_data[threadno]
+ .sigdata[i + 1].blocked = (set_low & (1 << i)) != 0;
+ }
+ for (i = 0; i < 31; i++)
+ {
+ current_cpu->thread_data[threadno]
+ .sigdata[i + 33].blocked_suspendsave
+ = current_cpu->thread_data[threadno]
+ .sigdata[i + 33].blocked;
+ current_cpu->thread_data[threadno]
+ .sigdata[i + 33].blocked = (set_high & (1 << i)) != 0;
+ }
+
+ current_cpu->thread_data[threadno].sigsuspended = 1;
+
+ /* The mask changed, so a signal may be unblocked for
+ execution. */
+ current_cpu->thread_data[threadno].sigpending = 1;
+ }
+
+ /* Because we don't use arg1 (newsetp) when this syscall is
+ rerun, it doesn't matter that we overwrite it with the
+ (constant) return value. */
+ retval = -cb_host_to_target_errno (cb, EINTR);
+ sim_pc_set (current_cpu, pc);
+ break;
+ }
+
+ /* Add case labels here for other syscalls using the 32-bit
+ "struct stat", provided they have a corresponding simulator
+ function of course. */
+ case TARGET_SYS_fstat:
+ {
+ /* As long as the infrastructure doesn't cache anything
+ related to the stat mapping, this trick gets us a dual
+ "struct stat"-type mapping in the least error-prone way. */
+ const char *saved_map = cb->stat_map;
+ CB_TARGET_DEFS_MAP *saved_syscall_map = cb->syscall_map;
+
+ cb->syscall_map = (CB_TARGET_DEFS_MAP *) syscall_stat32_map;
+ cb->stat_map = stat32_map;
+
+ if (cb_syscall (cb, &s) != CB_RC_OK)
+ {
+ abort ();
+ sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped,
+ SIM_SIGILL);
+ }
+ retval = s.result == -1 ? -s.errcode : s.result;
+
+ cb->stat_map = saved_map;
+ cb->syscall_map = saved_syscall_map;
+ break;
+ }
+
+ case TARGET_SYS_getcwd:
+ {
+ USI buf = arg1;
+ USI size = arg2;
+
+ char *cwd = xmalloc (MAXPATHLEN);
+ if (cwd != getcwd (cwd, MAXPATHLEN))
+ abort ();
+
+ /* FIXME: When and if we support chdir, we need something
+ a bit more elaborate. */
+ if (simulator_sysroot[0] != '\0')
+ strcpy (cwd, "/");
+
+ retval = -cb_host_to_target_errno (cb, ERANGE);
+ if (strlen (cwd) + 1 <= size)
+ {
+ retval = strlen (cwd) + 1;
+ if (sim_core_write_buffer (sd, current_cpu, 0, cwd,
+ buf, retval)
+ != (unsigned int) retval)
+ retval = -cb_host_to_target_errno (cb, EFAULT);
+ }
+ free (cwd);
+ break;
+ }
+
+ case TARGET_SYS_readlink:
+ {
+ SI path = arg1;
+ SI buf = arg2;
+ SI bufsiz = arg3;
+ char *pbuf = xmalloc (MAXPATHLEN);
+ char *lbuf = xmalloc (MAXPATHLEN);
+ char *lbuf_alloc = lbuf;
+ int nchars = -1;
+ int i;
+ int o = 0;
+
+ if (sim_core_read_unaligned_1 (current_cpu, pc, 0, path) == '/')
+ {
+ strcpy (pbuf, simulator_sysroot);
+ o += strlen (simulator_sysroot);
+ }
+
+ for (i = 0; i + o < MAXPATHLEN; i++)
+ {
+ pbuf[i + o]
+ = sim_core_read_unaligned_1 (current_cpu, pc, 0, path + i);
+ if (pbuf[i + o] == 0)
+ break;
+ }
+
+ if (i + o == MAXPATHLEN)
+ {
+ retval = -cb_host_to_target_errno (cb, ENAMETOOLONG);
+ break;
+ }
+
+ /* Intervene calls for certain files expected in the target
+ proc file system. */
+ if (strcmp (pbuf + strlen (simulator_sysroot),
+ "/proc/" XSTRING (TARGET_PID) "/exe") == 0)
+ {
+ char *argv0
+ = (STATE_PROG_ARGV (sd) != NULL
+ ? *STATE_PROG_ARGV (sd) : NULL);
+
+ if (argv0 == NULL || *argv0 == '.')
+ {
+ sim_io_eprintf (sd, "Unimplemented readlink syscall "
+ "(0x%lx: [\"%s\"], 0x%lx)\n",
+ (unsigned long) arg1, pbuf,
+ (unsigned long) arg2);
+ sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped,
+ SIM_SIGILL);
+ break;
+ }
+ else if (*argv0 == '/')
+ {
+ if (strncmp (simulator_sysroot, argv0,
+ strlen (simulator_sysroot)) == 0)
+ argv0 += strlen (simulator_sysroot);
+
+ strcpy (lbuf, argv0);
+ nchars = strlen (argv0) + 1;
+ }
+ else
+ {
+ if (getcwd (lbuf, MAXPATHLEN) != NULL
+ && strlen (lbuf) + 2 + strlen (argv0) < MAXPATHLEN)
+ {
+ if (strncmp (simulator_sysroot, lbuf,
+ strlen (simulator_sysroot)) == 0)
+ lbuf += strlen (simulator_sysroot);
+
+ strcat (lbuf, "/");
+ strcat (lbuf, argv0);
+ nchars = strlen (lbuf) + 1;
+ }
+ else
+ abort ();
+ }
+ }
+ else
+ nchars = readlink (pbuf, lbuf, MAXPATHLEN);
+
+ /* We trust that the readlink result returns a *relative*
+ link, or one already adjusted for the file-path-prefix.
+ (We can't generally tell the difference, so we go with
+ the easiest decision; no adjustment.) */
+
+ if (nchars == -1)
+ {
+ retval = -cb_host_to_target_errno (cb, errno);
+ break;
+ }
+
+ if (bufsiz < nchars)
+ nchars = bufsiz;
+
+ if (sim_core_write_buffer (sd, current_cpu, write_map, lbuf,
+ buf, nchars) != (unsigned int) nchars)
+ retval = -cb_host_to_target_errno (cb, EFAULT);
+ else
+ retval = nchars;
+
+ free (pbuf);
+ free (lbuf_alloc);
+ break;
+ }
+
+ case TARGET_SYS_sched_getscheduler:
+ {
+ USI pid = arg1;
+
+ /* FIXME: Search (other) existing threads. */
+ if (pid != 0 && pid != TARGET_PID)
+ retval = -cb_host_to_target_errno (cb, ESRCH);
+ else
+ retval = TARGET_SCHED_OTHER;
+ break;
+ }
+
+ case TARGET_SYS_sched_getparam:
+ {
+ USI pid = arg1;
+ USI paramp = arg2;
+
+ /* The kernel says:
+ struct sched_param {
+ int sched_priority;
+ }; */
+
+ if (pid != 0 && pid != TARGET_PID)
+ retval = -cb_host_to_target_errno (cb, ESRCH);
+ else
+ {
+ /* FIXME: Save scheduler setting before threads are
+ created too. */
+ sim_core_write_unaligned_4 (current_cpu, pc, 0, paramp,
+ current_cpu->thread_data != NULL
+ ? (current_cpu
+ ->thread_data[threadno]
+ .priority)
+ : 0);
+ retval = 0;
+ }
+ break;
+ }
+
+ case TARGET_SYS_sched_setparam:
+ {
+ USI pid = arg1;
+ USI paramp = arg2;
+
+ if ((pid != 0 && pid != TARGET_PID)
+ || sim_core_read_unaligned_4 (current_cpu, pc, 0,
+ paramp) != 0)
+ retval = -cb_host_to_target_errno (cb, EINVAL);
+ else
+ retval = 0;
+ break;
+ }
+
+ case TARGET_SYS_sched_setscheduler:
+ {
+ USI pid = arg1;
+ USI policy = arg2;
+ USI paramp = arg3;
+
+ if ((pid != 0 && pid != TARGET_PID)
+ || policy != TARGET_SCHED_OTHER
+ || sim_core_read_unaligned_4 (current_cpu, pc, 0,
+ paramp) != 0)
+ retval = -cb_host_to_target_errno (cb, EINVAL);
+ else
+ /* FIXME: Save scheduler setting to be read in later
+ sched_getparam calls. */
+ retval = 0;
+ break;
+ }
+
+ case TARGET_SYS_sched_yield:
+ /* We reschedule to the next thread after a syscall anyway, so
+ we don't have to do anything here than to set the return
+ value. */
+ retval = 0;
+ break;
+
+ case TARGET_SYS_sched_get_priority_min:
+ case TARGET_SYS_sched_get_priority_max:
+ if (arg1 != 0)
+ retval = -cb_host_to_target_errno (cb, EINVAL);
+ else
+ retval = 0;
+ break;
+
+ case TARGET_SYS_ugetrlimit:
+ {
+ unsigned int curlim, maxlim;
+ if (arg1 != TARGET_RLIMIT_STACK && arg1 != TARGET_RLIMIT_NOFILE)
+ {
+ retval = -cb_host_to_target_errno (cb, EINVAL);
+ break;
+ }
+
+ /* The kernel says:
+ struct rlimit {
+ unsigned long rlim_cur;
+ unsigned long rlim_max;
+ }; */
+ if (arg1 == TARGET_RLIMIT_NOFILE)
+ {
+ /* Sadly a very low limit. Better not lie, though. */
+ maxlim = curlim = MAX_CALLBACK_FDS;
+ }
+ else /* arg1 == TARGET_RLIMIT_STACK */
+ {
+ maxlim = 0xffffffff;
+ curlim = 0x800000;
+ }
+ sim_core_write_unaligned_4 (current_cpu, pc, 0, arg2, curlim);
+ sim_core_write_unaligned_4 (current_cpu, pc, 0, arg2 + 4, maxlim);
+ retval = 0;
+ break;
+ }
+
+ case TARGET_SYS_setrlimit:
+ if (arg1 != TARGET_RLIMIT_STACK)
+ {
+ retval = -cb_host_to_target_errno (cb, EINVAL);
+ break;
+ }
+ /* FIXME: Save values for future ugetrlimit calls. */
+ retval = 0;
+ break;
+
+ /* Provide a very limited subset of the sysctl functions, and
+ abort for the rest. */
+ case TARGET_SYS__sysctl:
+ {
+ /* The kernel says:
+ struct __sysctl_args {
+ int *name;
+ int nlen;
+ void *oldval;
+ size_t *oldlenp;
+ void *newval;
+ size_t newlen;
+ unsigned long __unused[4];
+ }; */
+ SI name = sim_core_read_unaligned_4 (current_cpu, pc, 0, arg1);
+ SI name0 = name == 0
+ ? 0 : sim_core_read_unaligned_4 (current_cpu, pc, 0, name);
+ SI name1 = name == 0
+ ? 0 : sim_core_read_unaligned_4 (current_cpu, pc, 0, name + 4);
+ SI nlen
+ = sim_core_read_unaligned_4 (current_cpu, pc, 0, arg1 + 4);
+ SI oldval
+ = sim_core_read_unaligned_4 (current_cpu, pc, 0, arg1 + 8);
+ SI oldlenp
+ = sim_core_read_unaligned_4 (current_cpu, pc, 0, arg1 + 12);
+ SI oldlen = oldlenp == 0
+ ? 0 : sim_core_read_unaligned_4 (current_cpu, pc, 0, oldlenp);
+ SI newval
+ = sim_core_read_unaligned_4 (current_cpu, pc, 0, arg1 + 16);
+ SI newlen
+ = sim_core_read_unaligned_4 (current_cpu, pc, 0, arg1 + 20);
+
+ if (name0 == TARGET_CTL_KERN && name1 == TARGET_CTL_KERN_VERSION)
+ {
+ SI to_write = oldlen < (SI) sizeof (TARGET_UTSNAME)
+ ? oldlen : (SI) sizeof (TARGET_UTSNAME);
+
+ sim_core_write_unaligned_4 (current_cpu, pc, 0, oldlenp,
+ sizeof (TARGET_UTSNAME));
+
+ if (sim_core_write_buffer (sd, current_cpu, write_map,
+ TARGET_UTSNAME, oldval,
+ to_write)
+ != (unsigned int) to_write)
+ retval = -cb_host_to_target_errno (cb, EFAULT);
+ else
+ retval = 0;
+ break;
+ }
+
+ sim_io_eprintf (sd, "Unimplemented _sysctl syscall "
+ "(0x%lx: [0x%lx, 0x%lx],"
+ " 0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx)\n",
+ (unsigned long) name,
+ (unsigned long) name0,
+ (unsigned long) name1,
+ (unsigned long) nlen,
+ (unsigned long) oldval,
+ (unsigned long) oldlenp,
+ (unsigned long) newval,
+ (unsigned long) newlen);
+ sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped,
+ SIM_SIGILL);
+ break;
+ }
+
+ case TARGET_SYS_exit:
+ {
+ /* Here for all but the last thread. */
+ int i;
+ int pid
+ = current_cpu->thread_data[threadno].threadid + TARGET_PID;
+ int ppid
+ = (current_cpu->thread_data[threadno].parent_threadid
+ + TARGET_PID);
+ int exitsig = current_cpu->thread_data[threadno].exitsig;
+
+ /* Any children are now all orphans. */
+ for (i = 0; i < SIM_TARGET_MAX_THREADS; i++)
+ if (current_cpu->thread_data[i].parent_threadid
+ == current_cpu->thread_data[threadno].threadid)
+ /* Make getppid(2) return 1 for them, poor little ones. */
+ current_cpu->thread_data[i].parent_threadid = -TARGET_PID + 1;
+
+ /* Free the cpu context data. When the parent has received
+ the exit status, we'll clear the entry too. */
+ free (current_cpu->thread_data[threadno].cpu_context);
+ current_cpu->thread_data[threadno].cpu_context = NULL;
+ current_cpu->m1threads--;
+ if (arg1 != 0)
+ {
+ sim_io_eprintf (sd, "Thread %d exited with status %d\n",
+ pid, arg1);
+ sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped,
+ SIM_SIGILL);
+ }
+
+ /* Still, we may want to support non-zero exit values. */
+ current_cpu->thread_data[threadno].exitval = arg1 << 8;
+
+ if (exitsig)
+ deliver_signal (current_cpu, exitsig, ppid);
+ break;
+ }
+
+ case TARGET_SYS_clone:
+ {
+ int nthreads = current_cpu->m1threads + 1;
+ void *thread_cpu_data;
+ bfd_byte old_sp_buf[4];
+ bfd_byte sp_buf[4];
+ const bfd_byte zeros[4] = { 0, 0, 0, 0 };
+ int i;
+
+ /* That's right, the syscall clone arguments are reversed
+ compared to sys_clone notes in clone(2) and compared to
+ other Linux ports (i.e. it's the same order as in the
+ clone(2) libcall). */
+ USI flags = arg2;
+ USI newsp = arg1;
+
+ if (nthreads == SIM_TARGET_MAX_THREADS)
+ {
+ retval = -cb_host_to_target_errno (cb, EAGAIN);
+ break;
+ }
+
+ /* FIXME: Implement the low byte. */
+ if ((flags & ~TARGET_CSIGNAL) !=
+ (TARGET_CLONE_VM
+ | TARGET_CLONE_FS
+ | TARGET_CLONE_FILES
+ | TARGET_CLONE_SIGHAND)
+ || newsp == 0)
+ {
+ sim_io_eprintf (sd,
+ "Unimplemented clone syscall (0x%lx, 0x%lx)\n",
+ (unsigned long) arg1, (unsigned long) arg2);
+ sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped,
+ SIM_SIGILL);
+ }
+
+ if (current_cpu->thread_data == NULL)
+ make_first_thread (current_cpu);
+
+ /* The created thread will get the new SP and a cleared R10.
+ Since it's created out of a copy of the old thread and we
+ don't have a set-register-function that just take the
+ cpu_data as a parameter, we set the childs values first,
+ and write back or overwrite them in the parent after the
+ copy. */
+ (*CPU_REG_FETCH (current_cpu)) (current_cpu,
+ H_GR_SP, old_sp_buf, 4);
+ bfd_putl32 (newsp, sp_buf);
+ (*CPU_REG_STORE (current_cpu)) (current_cpu,
+ H_GR_SP, sp_buf, 4);
+ (*CPU_REG_STORE (current_cpu)) (current_cpu,
+ H_GR_R10, (bfd_byte *) zeros, 4);
+ thread_cpu_data
+ = (*current_cpu
+ ->make_thread_cpu_data) (current_cpu,
+ ¤t_cpu->cpu_data_placeholder);
+ (*CPU_REG_STORE (current_cpu)) (current_cpu,
+ H_GR_SP, old_sp_buf, 4);
+
+ retval = ++current_cpu->max_threadid + TARGET_PID;
+
+ /* Find an unused slot. After a few threads have been created
+ and exited, the array is expected to be a bit fragmented.
+ We don't reuse the first entry, though, that of the
+ original thread. */
+ for (i = 1; i < SIM_TARGET_MAX_THREADS; i++)
+ if (current_cpu->thread_data[i].cpu_context == NULL
+ /* Don't reuse a zombied entry. */
+ && current_cpu->thread_data[i].threadid == 0)
+ break;
+
+ memcpy (¤t_cpu->thread_data[i],
+ ¤t_cpu->thread_data[threadno],
+ sizeof (current_cpu->thread_data[i]));
+ current_cpu->thread_data[i].cpu_context = thread_cpu_data;
+ current_cpu->thread_data[i].cpu_context_atsignal = NULL;
+ current_cpu->thread_data[i].threadid = current_cpu->max_threadid;
+ current_cpu->thread_data[i].parent_threadid
+ = current_cpu->thread_data[threadno].threadid;
+ current_cpu->thread_data[i].pipe_read_fd = 0;
+ current_cpu->thread_data[i].pipe_write_fd = 0;
+ current_cpu->thread_data[i].at_syscall = 0;
+ current_cpu->thread_data[i].sigpending = 0;
+ current_cpu->thread_data[i].sigsuspended = 0;
+ current_cpu->thread_data[i].exitsig = flags & TARGET_CSIGNAL;
+ current_cpu->m1threads = nthreads;
+ break;
+ }
+
+ /* Better watch these in case they do something necessary. */
+ case TARGET_SYS_socketcall:
+ retval = -cb_host_to_target_errno (cb, ENOSYS);
+ break;
+
+ unimplemented_syscall:
+ default:
+ sim_io_eprintf (sd, "Unimplemented syscall: %d "
+ "(0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x)\n", callnum,
+ arg1, arg2, arg3, arg4, arg5, arg6);
+ sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped,
+ SIM_SIGILL);
+ }
+ }
+
+ /* A system call is a rescheduling point. For the time being, we don't
+ reschedule anywhere else. */
+ if (current_cpu->m1threads != 0
+ /* We need to schedule off from an exiting thread that is the
+ second-last one. */
+ || (current_cpu->thread_data != NULL
+ && current_cpu->thread_data[threadno].cpu_context == NULL))
+ {
+ bfd_byte retval_buf[4];
+
+ current_cpu->thread_data[threadno].last_execution
+ = TARGET_TIME_MS (current_cpu);
+ bfd_putl32 (retval, retval_buf);
+ (*CPU_REG_STORE (current_cpu)) (current_cpu, H_GR_R10, retval_buf, 4);
+
+ current_cpu->thread_data[threadno].at_syscall = 1;
+ reschedule (current_cpu);
+
+ (*CPU_REG_FETCH (current_cpu)) (current_cpu, H_GR_R10, retval_buf, 4);
+ retval = bfd_getl32 (retval_buf);
+ }
+
+ return retval;
+}
+
+/* Callback from simulator write saying that the pipe at (reader, writer)
+ is now non-empty (so the writer should wait until the pipe is empty, at
+ least not write to this or any other pipe). Simplest is to just wait
+ until the pipe is empty. */
+
+static void
+cris_pipe_nonempty (host_callback *cb ATTRIBUTE_UNUSED,
+ int reader, int writer)
+{
+ SIM_CPU *cpu = current_cpu_for_cb_callback;
+ const bfd_byte zeros[4] = { 0, 0, 0, 0 };
+
+ /* It's the current thread: we just have to re-run the current
+ syscall instruction (presumably "break 13") and change the syscall
+ to the special simulator-wait code. Oh, and set a marker that
+ we're waiting, so we can disambiguate the special call from a
+ program error.
+
+ This function may be called multiple times between cris_pipe_empty,
+ but we must avoid e.g. decreasing PC every time. Check fd markers
+ to tell. */
+ if (cpu->thread_data == NULL)
+ {
+ sim_io_eprintf (CPU_STATE (cpu),
+ "Terminating simulation due to writing pipe rd:wr %d:%d"
+ " from one single thread\n", reader, writer);
+ sim_engine_halt (CPU_STATE (cpu), cpu,
+ NULL, sim_pc_get (cpu), sim_stopped, SIM_SIGILL);
+ }
+ else if (cpu->thread_data[cpu->threadno].pipe_write_fd == 0)
+ {
+ cpu->thread_data[cpu->threadno].pipe_write_fd = writer;
+ cpu->thread_data[cpu->threadno].pipe_read_fd = reader;
+ /* FIXME: We really shouldn't change registers other than R10 in
+ syscalls (like R9), here or elsewhere. */
+ (*CPU_REG_STORE (cpu)) (cpu, H_GR_R9, (bfd_byte *) zeros, 4);
+ sim_pc_set (cpu, sim_pc_get (cpu) - 2);
+ }
+}
+
+/* Callback from simulator close or read call saying that the pipe at
+ (reader, writer) is now empty (so the writer can write again, perhaps
+ leave a waiting state). If there are bytes remaining, they couldn't be
+ consumed (perhaps due to the pipe closing). */
+
+static void
+cris_pipe_empty (host_callback *cb,
+ int reader ATTRIBUTE_UNUSED,
+ int writer)
+{
+ int i;
+ SIM_CPU *cpu = current_cpu_for_cb_callback;
+ bfd_byte r10_buf[4];
+ int remaining = cb->pipe_buffer[writer].size;
+
+ /* We need to find the thread that waits for this pipe. */
+ for (i = 0; i < SIM_TARGET_MAX_THREADS; i++)
+ if (cpu->thread_data[i].cpu_context
+ && cpu->thread_data[i].pipe_write_fd == writer)
+ {
+ int retval;
+ /* Temporarily switch to this cpu context, so we can change the
+ PC by ordinary calls. */
+
+ memcpy (cpu->thread_data[cpu->threadno].cpu_context,
+ &cpu->cpu_data_placeholder,
+ cpu->thread_cpu_data_size);
+ memcpy (&cpu->cpu_data_placeholder,
+ cpu->thread_data[i].cpu_context,
+ cpu->thread_cpu_data_size);
+
+ /* The return value is supposed to contain the number of written
+ bytes, which is the number of bytes requested and returned at
+ the write call. We subtract the remaining bytes from that,
+ but making sure we still get a positive number.
+ The return value may also be a negative number; an error
+ value. We cover this case by comparing against remaining,
+ which is always >= 0. */
+ (*CPU_REG_FETCH (cpu)) (cpu, H_GR_R10, r10_buf, 4);
+ retval = (int) bfd_getl_signed_32 (r10_buf);
+ if (retval >= remaining)
+ bfd_putl32 (retval - remaining, r10_buf);
+ (*CPU_REG_STORE (cpu)) (cpu, H_GR_R10, r10_buf, 4);
+
+ sim_pc_set (cpu, sim_pc_get (cpu) + 2);
+ memcpy (cpu->thread_data[i].cpu_context,
+ &cpu->cpu_data_placeholder,
+ cpu->thread_cpu_data_size);
+ memcpy (&cpu->cpu_data_placeholder,
+ cpu->thread_data[cpu->threadno].cpu_context,
+ cpu->thread_cpu_data_size);
+ cpu->thread_data[i].pipe_read_fd = 0;
+ cpu->thread_data[i].pipe_write_fd = 0;
+ return;
+ }
+
+ abort ();
+}
+
+/* We have a simulator-specific notion of time. See TARGET_TIME. */
+
+static long
+cris_time (host_callback *cb ATTRIBUTE_UNUSED, long *t)
+{
+ long retval = TARGET_TIME (current_cpu_for_cb_callback);
+ if (t)
+ *t = retval;
+ return retval;
+}
+
+/* Set target-specific callback data. */
+
+void
+cris_set_callbacks (host_callback *cb)
+{
+ /* Yeargh, have to cast away constness to avoid warnings. */
+ cb->syscall_map = (CB_TARGET_DEFS_MAP *) syscall_map;
+ cb->errno_map = (CB_TARGET_DEFS_MAP *) errno_map;
+
+ /* The kernel stat64 layout. If we see a file > 2G, the "long"
+ parameter to cb_store_target_endian will make st_size negative.
+ Similarly for st_ino. FIXME: Find a 64-bit type, and use it
+ *unsigned*, and/or add syntax for signed-ness. */
+ cb->stat_map = stat_map;
+ cb->open_map = (CB_TARGET_DEFS_MAP *) open_map;
+ cb->pipe_nonempty = cris_pipe_nonempty;
+ cb->pipe_empty = cris_pipe_empty;
+ cb->time = cris_time;
+}
+
+/* Process an address exception. */
+
+void
+cris_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
+ unsigned int map, int nr_bytes, address_word addr,
+ transfer_type transfer, sim_core_signals sig)
+{
+ sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
+ transfer, sig);
+}
projects / deliverable / binutils-gdb.git / commitdiff
