* vu0.h: New file with cop2/vu0 instructions.

        * mips-opc.c: Include vu0.h.
        * mips-dis.c (print_insn_arg): Handle new args 0-9, +, -, %, K, &,
        J, Q, X, and U.
        (print_insn_mips): Do not emit a tab after an instruction if the
        first arg is an instruction completer (&).  If the next arg is an
        escape character (%), then print the next arg verbatim.
        * Makefile.am (mips-opc.lo): Depend on vu0.h

diff --git a/opcodes/.Sanitize b/opcodes/.Sanitize
index 7ce31d47c85f2b2a9fe2f822e765fecdf944e7fb..102e637611a582e1739dd42df8174a04c9e2958d 100644 (file)
--- a/opcodes/.Sanitize
+++ b/opcodes/.Sanitize
@@ -47,6 +47,14 @@ else
        lose_these_too="${sky_files} ${lose_these_too}"
 fi
 
+r5900_files="vu0.h"
+
+if ( echo $* | grep keep\-r5900 > /dev/null ) ; then
+       keep_these_too="${r5900_files} ${keep_these_too}"
+else
+       lose_these_too="${r5900_files} ${lose_these_too}"
+fi
+
 # All files listed between the "Things-to-keep:" line and the
 # "Files-to-sed:" line will be kept.  All other files will be removed.
 # Directories listed in this section will have their own Sanitize
@@ -210,7 +218,7 @@ else
 fi
 
 
-r5900_files="ChangeLog mips-opc.c mips-dis.c"
+r5900_files="ChangeLog mips-opc.c mips-dis.c Makefile.am Makefile.in"
 if ( echo $* | grep keep\-r5900 > /dev/null ) ; then
        for i in $r5900_files ; do
                if test ! -d $i && (grep sanitize-r5900 $i > /dev/null) ; then

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index cac858c3d7d75ae91d9a61e667f26d918dbed343..319d8b2af896108121536175dad9ebd854bcd160 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,16 @@
+start-sanitize-r5900
+Thu Mar 19 13:53:25 1998  Jeffrey A Law  (law@cygnus.com)
+
+       * vu0.h: New file with cop2/vu0 instructions.
+       * mips-opc.c: Include vu0.h.
+       * mips-dis.c (print_insn_arg): Handle new args 0-9, +, -, %, K, &,
+       J, Q, X, and U.
+       (print_insn_mips): Do not emit a tab after an instruction if the
+       first arg is an instruction completer (&).  If the next arg is an
+       escape character (%), then print the next arg verbatim.
+       * Makefile.am (mips-opc.lo): Depend on vu0.h
+
+end-sanitize-r5900
 start-sanitize-sky
 Thu Mar 19 10:42:51 1998  Doug Evans  <devans@canuck.cygnus.com>
 

diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index 2bdc7160b2ef0e50d721adde951ed7bb24a4f3d1..57d484d69aaf7eff223244971342f0cb3486003a 100644 (file)
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -158,12 +158,14 @@ CGENDIR = $(srcdir)/../cgen
 CGENFLAGS = -v
 
 CGENFILES = $(CGENDIR)/object.scm $(CGENDIR)/utils.scm \
+       $(CGENDIR)/attr.scm $(CGENDIR)/enum.scm $(CGENDIR)/types.scm \
        $(CGENDIR)/utils-cgen.scm $(CGENDIR)/cpu.scm \
        $(CGENDIR)/mode.scm $(CGENDIR)/mach.scm \
+       $(CGENDIR)/model.scm $(CGENDIR)/hardware.scm \
        $(CGENDIR)/ifield.scm $(CGENDIR)/iformat.scm \
        $(CGENDIR)/operand.scm $(CGENDIR)/insn.scm \
-       $(CGENDIR)/opcodes.scm $(CGENDIR)/cgen-opc.scm \
-       cgen-opc.in cgen-asm.in cgen-dis.in
+       $(CGENDIR)/opcodes.scm $(CGENDIR)/cdl-c.scm \
+       $(CGENDIR)/cgen-opc.scm cgen-opc.in cgen-asm.in cgen-dis.in
 # The end marker is written this way to pass through automake unscathed.
 ENDSAN = end-sanitize-cygnus
 
@@ -289,6 +291,7 @@ mips-dis.lo: mips-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \
   $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
   $(INCDIR)/bfdlink.h $(INCDIR)/elf/mips.h
 mips-opc.lo: mips-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/mips.h
+mips-opc.lo: vu0.h
 mips16-opc.lo: mips16-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/mips.h
 m10200-dis.lo: m10200-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/mn10200.h \
   $(INCDIR)/dis-asm.h $(BFD_H)

diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index 3bb986a17ac388e93651769cb9f630f298578bc6..bcd2008fd761dd59a08ded51b21bb11caf7e859a 100644 (file)
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -225,12 +225,14 @@ CGENDIR = $(srcdir)/../cgen
 CGENFLAGS = -v
 
 CGENFILES = $(CGENDIR)/object.scm $(CGENDIR)/utils.scm \
+       $(CGENDIR)/attr.scm $(CGENDIR)/enum.scm $(CGENDIR)/types.scm \
        $(CGENDIR)/utils-cgen.scm $(CGENDIR)/cpu.scm \
        $(CGENDIR)/mode.scm $(CGENDIR)/mach.scm \
+       $(CGENDIR)/model.scm $(CGENDIR)/hardware.scm \
        $(CGENDIR)/ifield.scm $(CGENDIR)/iformat.scm \
        $(CGENDIR)/operand.scm $(CGENDIR)/insn.scm \
-       $(CGENDIR)/opcodes.scm $(CGENDIR)/cgen-opc.scm \
-       cgen-opc.in cgen-asm.in cgen-dis.in
+       $(CGENDIR)/opcodes.scm $(CGENDIR)/cdl-c.scm \
+       $(CGENDIR)/cgen-opc.scm cgen-opc.in cgen-asm.in cgen-dis.in
 # The end marker is written this way to pass through automake unscathed.
 ENDSAN = end-sanitize-cygnus
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
@@ -656,6 +658,7 @@ mips-dis.lo: mips-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \
   $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
   $(INCDIR)/bfdlink.h $(INCDIR)/elf/mips.h
 mips-opc.lo: mips-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/mips.h
+mips-opc.lo: vu0.h
 mips16-opc.lo: mips16-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/mips.h
 m10200-dis.lo: m10200-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/mn10200.h \
   $(INCDIR)/dis-asm.h $(BFD_H)

diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 673dbfe6971fcdf8476a5cb571e0210834fcd9fc..f2b18478ccee1d7844e1c8d2b12fd4e4cd7fa75e 100644 (file)
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -84,6 +84,10 @@ print_insn_arg (d, l, pc, info)
     case '[':
     case ']':
       /* end-sanitize-vr5400 */
+      /* start-sanitize-r5900 */
+    case '+':
+    case '-':
+      /* end-santiize-r5900 */
       (*info->fprintf_func) (info->stream, "%c", *d);
       break;
 
@@ -179,6 +183,113 @@ print_insn_arg (d, l, pc, info)
                             (l >> OP_SH_FS) & OP_MASK_FS);
       break;
 
+    /* start-sanitize-r5900
+    case '0':
+      (*info->fprintf_func) (info->stream, "0x%x",
+                             (l >> 6) & 0x1f);
+      break;
+
+    case '9':
+      (*info->fprintf_func) (info->stream, "vi19");
+      break;
+
+    case '1':
+      (*info->fprintf_func) (info->stream, "vf%d",
+                            (l >> OP_SH_FT) & OP_MASK_FT);
+      break;
+    case '2':
+      (*info->fprintf_func) (info->stream, "vf%d",
+                            (l >> OP_SH_FS) & OP_MASK_FS);
+      break;
+    case '3':
+      (*info->fprintf_func) (info->stream, "vf%d",
+                            (l >> OP_SH_FD) & OP_MASK_FD);
+      break;
+
+    case '4':
+      (*info->fprintf_func) (info->stream, "vi%d",
+                            (l >> OP_SH_FT) & OP_MASK_FT);
+      break;
+    case '5':
+      (*info->fprintf_func) (info->stream, "vi%d",
+                            (l >> OP_SH_FS) & OP_MASK_FS);
+      break;
+    case '6':
+      (*info->fprintf_func) (info->stream, "vi%d",
+                            (l >> OP_SH_FD) & OP_MASK_FD);
+      break;
+
+    case '7':
+      (*info->fprintf_func) (info->stream, "vf%d",
+                            (l >> OP_SH_FT) & OP_MASK_FT);
+      switch ((l >> 23) & 0x3)
+       {
+         case 0:
+           (*info->fprintf_func) (info->stream, "x");
+           break;
+         case 1:
+           (*info->fprintf_func) (info->stream, "y");
+           break;
+         case 2:
+           (*info->fprintf_func) (info->stream, "z");
+           break;
+         case 3:
+           (*info->fprintf_func) (info->stream, "w");
+           break;
+       }
+      break;
+    case 'K':
+      break;
+
+    case '&':
+      (*info->fprintf_func) (info->stream, ".");
+      if (l & (1 << 21))
+       (*info->fprintf_func) (info->stream, "w");
+      if (l & (1 << 24))
+       (*info->fprintf_func) (info->stream, "x");
+      if (l & (1 << 23))
+       (*info->fprintf_func) (info->stream, "y");
+      if (l & (1 << 22))
+       (*info->fprintf_func) (info->stream, "z");
+      (*info->fprintf_func) (info->stream, "\t");
+      break;
+       
+    case '8':
+      (*info->fprintf_func) (info->stream, "vf%d",
+                            (l >> OP_SH_FS) & OP_MASK_FS);
+      switch ((l >> 21) & 0x3)
+       {
+         case 0:
+           (*info->fprintf_func) (info->stream, "x");
+           break;
+         case 1:
+           (*info->fprintf_func) (info->stream, "y");
+           break;
+         case 2:
+           (*info->fprintf_func) (info->stream, "z");
+           break;
+         case 3:
+           (*info->fprintf_func) (info->stream, "w");
+           break;
+       }
+      break;
+    case 'J':
+      (*info->fprintf_func) (info->stream, "I");
+      break;
+
+    case 'Q':
+      (*info->fprintf_func) (info->stream, "Q");
+      break;
+
+    case 'X':
+      (*info->fprintf_func) (info->stream, "R");
+      break;
+
+    case 'U':
+      (*info->fprintf_func) (info->stream, "ACC");
+      break;
+    /* end-sanitize-r5900 */
+
     case 'T':
     case 'W':
       (*info->fprintf_func) (info->stream, "$f%d",
@@ -309,6 +420,12 @@ _print_insn_mips (memaddr, word, info)
        target_processor = 4300;
        mips_isa = 3;
        break;
+       /* start-sanitize-vr4320 */
+      case bfd_mach_mips4320:
+       target_processor = 4320;
+       mips_isa = 3;
+       break;
+       /* end-sanitize-vr4320 */
       case bfd_mach_mips4400:
        target_processor = 4400;
        mips_isa = 3;
@@ -397,6 +514,10 @@ _print_insn_mips (memaddr, word, info)
                      && op->membership & INSN_4010) == 0
                  && (target_processor == 4100
                      && op->membership & INSN_4100) == 0
+                 /* start-sanitize-vr4320 */
+                 && (target_processor == 4320
+                     && op->membership & INSN_4320) == 0
+                 /* end-sanitize-vr4320 */
                  /* start-sanitize-vr5400 */
                  && (target_processor == 5400
                      && op->membership & INSN_5400) == 0
@@ -418,9 +539,24 @@ _print_insn_mips (memaddr, word, info)
              d = op->args;
              if (d != NULL && *d != '\0')
                {
-                 (*info->fprintf_func) (info->stream, "\t");
+                 /* start-sanitize-r5900 */
+                 /* If this is an opcode completer, then do not emit
+                    a tab after the opcode.  */
+                 if (*d != '&')
+                 /* end-sanitize-r5900 */
+                   (*info->fprintf_func) (info->stream, "\t");
                  for (; *d != '\0'; d++)
-                   print_insn_arg (d, word, memaddr, info);
+                   /* start-sanitize-r5900 */
+                   /* If this is an escape character, go ahead and print the
+                      next character in the arg string verbatim.  */
+                   if (*d == '%')
+                     {
+                       d++;
+                       (*info->fprintf_func) (info->stream, "%c", *d);
+                     }
+                   else
+                   /* end-sanitize-r5900 */
+                     print_insn_arg (d, word, memaddr, info);
                }
 
              return 4;

diff --git a/opcodes/vu0.h b/opcodes/vu0.h
new file mode 100644 (file)
index 0000000..1ef8ae0
--- /dev/null
+++ b/opcodes/vu0.h
@@ -0,0 +1,153 @@
+/* vu0.h.  Mips cop2/vu0 opcode list for GDB, the GNU debugger.
+   Copyright 1998 Free Software Foundation, Inc.
+
+This file is part of GDB, GAS, and the GNU binutils.
+
+GDB, GAS, and the GNU binutils are free software; you can redistribute
+them and/or modify them under the terms of the GNU General Public
+License as published by the Free Software Foundation; either version
+1, or (at your option) any later version.
+
+GDB, GAS, and the GNU binutils are distributed in the hope that they
+will be useful, but WITHOUT ANY WARRANTY; without even the implied
+warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+the GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this file; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+{"lqc2",     "1,o(b)", 0xd8000000, 0xfc000000, 0,              T5},
+{"qmfc2",    "t,2",    0x48200000, 0xffe007ff, 0,              T5},
+{"qmfc2.ni", "t,2",    0x48200000, 0xffe007ff, 0,              T5},
+{"qmfc2.i",  "t,2",    0x48200001, 0xffe007ff, 0,              T5},
+{"qmtc2",    "t,2",    0x48a00000, 0xffe007ff, 0,              T5},
+{"qmtc2.ni", "t,2",    0x48a00000, 0xffe007ff, 0,              T5},
+{"qmtc2.i", "t,2",     0x48a00001, 0xffe007ff, 0,              T5},
+{"sqc2",     "1,o(b)", 0xe8000000, 0xfc000000, 0,              T5},
+{"vabs",   "&1K,2K",   0x4a0001fd, 0xfe0007ff, 0,              T5},
+{"vadd",   "&3K,2K,1K",        0x4a000028, 0xfe00003f, 0,              T5},
+{"vaddi",  "&3K,2K,J", 0x4a000022, 0xfe1f003f, 0,              T5},
+{"vaddq",  "&3K,2K,Q", 0x4a000020, 0xfe1f003f, 0,              T5},
+{"vaddw",  "&3K,2K,1%w",       0x4a000003, 0xfe00003f, 0,              T5},
+{"vaddx",  "&3K,2K,1%x",       0x4a000000, 0xfe00003f, 0,              T5},
+{"vaddy",  "&3K,2K,1%y",       0x4a000001, 0xfe00003f, 0,              T5},
+{"vaddz",  "&3K,2K,1%z",       0x4a000002, 0xfe00003f, 0,              T5},
+{"vadda",  "&UK,1K,2K",        0x4a0002bc, 0xfe0007ff, 0,              T5},
+{"vaddai", "&UK,2K,J", 0x4a00023e, 0xfe1f07ff, 0,              T5},
+{"vaddaq", "&UK,2K,Q", 0x4a00023c, 0xfe1f07ff, 0,              T5},
+{"vaddaw", "&UK,2K,1%w",       0x4a00003f, 0xfe0007ff, 0,              T5},
+{"vaddax", "&UK,2K,1%x",       0x4a00003c, 0xfe0007ff, 0,              T5},
+{"vadday", "&UK,2K,1%y",       0x4a00003d, 0xfe0007ff, 0,              T5},
+{"vaddaz", "&UK,2K,1%z",       0x4a00003e, 0xfe0007ff, 0,              T5},
+{"vcallms","p",                0x4a000038, 0xffe0003f, 0,              T5},
+{"vcallmsr", "9",              0x4a009839, 0xffffffff, 0,              T5},
+{"vclip","2",          0x4be001ff, 0xffff07ff, 0,              T5},
+{"vdiv","Q,8,7",       0x4a0003bc, 0xfe0007ff, 0,              T5},
+{"vftoi0", "&1K,2K",   0x4a00017c, 0xfe0007ff, 0,              T5},
+{"vftoi4", "&1K,2K",   0x4a00017d, 0xfe0007ff, 0,              T5},
+{"vftoi12", "&1K,2K",  0x4a00017e, 0xfe0007ff, 0,              T5},
+{"vftoi15", "&1K,2K",  0x4a00017f, 0xfe0007ff, 0,              T5},
+{"viadd","6,5,4",      0x4a000030, 0xffe0003f, 0,              T5},
+{"viaddi","4,5,0",     0x4a000032, 0xffe0003f, 0,              T5},
+{"viand","6,5,4",      0x4a000034, 0xffe0003f, 0,              T5},
+{"vilwr.w",  "4,(5)",  0x4a2003fe, 0xffe007ff, 0,              T5},
+{"vilwr.x",  "4,(5)",  0x4b0003fe, 0xffe007ff, 0,              T5},
+{"vilwr.y",  "4,(5)",  0x4a8003fe, 0xffe007ff, 0,              T5},
+{"vilwr.z",  "4,(5)",  0x4a4003fe, 0xffe007ff, 0,              T5},
+{"vior","6,5,4",       0x4a000035, 0xffe0003f, 0,              T5},
+{"viswr.w",  "4,(5)",  0x4a2003ff, 0xffe007ff, 0,              T5},
+{"viswr.x",  "4,(5)",  0x4b0003ff, 0xffe007ff, 0,              T5},
+{"viswr.y",  "4,(5)",  0x4a8003ff, 0xffe007ff, 0,              T5},
+{"viswr.z",  "4,(5)",  0x4a4003ff, 0xffe007ff, 0,              T5},
+{"visub","6,5,4",      0x4a000031, 0xffe0003f, 0,              T5},
+{"vitof0", "&1K,2K",   0x4a00013c, 0xfe0007ff, 0,              T5},
+{"vitof4", "&1K,2K",   0x4a00013d, 0xfe0007ff, 0,              T5},
+{"vitof12", "&1K,2K",  0x4a00013e, 0xfe0007ff, 0,              T5},
+{"vitof15", "&1K,2K",  0x4a00013f, 0xfe0007ff, 0,              T5},
+{"vlqd",  "&2K,(--4)K",        0x4a00037e, 0xfe0007ff, 0,              T5},
+{"vlqi",  "&2K,(4++)K",        0x4a00037c, 0xfe0007ff, 0,              T5},
+{"vmadd", "&3K,2K,1K", 0x4a000029, 0xfe00003f, 0,              T5},
+{"vmaddi", "&3K,2K,J", 0x4a000023, 0xfe1f003f, 0,              T5},
+{"vmaddq", "&3K,2K,Q", 0x4a000021, 0xfe1f003f, 0,              T5},
+{"vmaddw", "&3K,2K,1%w",       0x4a00000b, 0xfe00003f, 0,              T5},
+{"vmaddx", "&3K,2K,1%x",       0x4a000008, 0xfe00003f, 0,              T5},
+{"vmaddy", "&3K,2K,1%y",       0x4a000009, 0xfe00003f, 0,              T5},
+{"vmaddz", "&3K,2K,1%z",       0x4a00000a, 0xfe00003f, 0,              T5},
+{"vmadda", "&UK,2K,1K",        0x4a0002bd, 0xfe0007ff, 0,              T5},
+{"vmaddai", "&UK,2K,J",        0x4a00023f, 0xfe1f07ff, 0,              T5},
+{"vmaddaq", "&UK,2K,Q",        0x4a00023d, 0xfe1f07ff, 0,              T5},
+{"vmaddaw", "&UK,2K,1%w",      0x4a0000bf, 0xfe0007ff, 0,              T5},
+{"vmaddax", "&UK,2K,1%x",      0x4a0000bc, 0xfe0007ff, 0,              T5},
+{"vmadday", "&UK,2K,1%y",      0x4a0000bd, 0xfe0007ff, 0,              T5},
+{"vmaddaz", "&UK,2K,1%z",      0x4a0000be, 0xfe0007ff, 0,              T5},
+{"vmax",    "&3K,2K,1K",       0x4a00002b, 0xfe00003f, 0,              T5},
+{"vmaxi",   "&3K,2K,J",        0x4a00001b, 0xfe1f003f, 0,              T5},
+{"vmaxw",   "&3K,2K,1%w",      0x4a000013, 0xfe00003f, 0,              T5},
+{"vmaxx",   "&3K,2K,1%x",      0x4a000010, 0xfe00003f, 0,              T5},
+{"vmaxy",   "&3K,2K,1%y",      0x4a000011, 0xfe00003f, 0,              T5},
+{"vmaxz",   "&3K,2K,1%z",      0x4a000012, 0xfe00003f, 0,              T5},
+{"vmfir",   "&1K,5",   0x4a0003fd, 0xfe0007ff, 0,              T5},
+{"vmini",   "&3K,2K,1K",       0x4a00002f, 0xfe00003f, 0,              T5},
+{"vminii",  "&3K,2K,J",        0x4a00001f, 0xfe1f003f, 0,              T5},
+{"vminiw",  "&3K,2K,1%w",      0x4a000017, 0xfe00003f, 0,              T5},
+{"vminix",  "&3K,2K,1%x",      0x4a000014, 0xfe00003f, 0,              T5},
+{"vminiy",  "&3K,2K,1%y",      0x4a000015, 0xfe00003f, 0,              T5},
+{"vminiz",  "&3K,2K,1%z",      0x4a000016, 0xfe00003f, 0,              T5},
+{"vmove",   "&1K,2K",  0x4a00033c, 0xfe0007ff, 0,              T5},
+{"vmr32",   "&1K,2K",  0x4a00033d, 0xfe0007ff, 0,              T5},
+{"vmsub",   "&3K,2K,1K",       0x4a00002d, 0xfe00003f, 0,              T5},
+{"vmsubi",  "&3K,2K,J",        0x4a000027, 0xfe1f003f, 0,              T5},
+{"vmsubq",  "&3K,2K,Q",        0x4a000025, 0xfe1f003f, 0,              T5},
+{"vmsubw",  "&3K,2K,1%w",      0x4a00000f, 0xfe00003f, 0,              T5},
+{"vmsubx",  "&3K,2K,1%x",      0x4a00000c, 0xfe00003f, 0,              T5},
+{"vmsuby",  "&3K,2K,1%y",      0x4a00000d, 0xfe00003f, 0,              T5},
+{"vmsubz",  "&3K,2K,1%z",      0x4a00000e, 0xfe00003f, 0,              T5},
+{"vmsuba",  "&UK,1K,2K",       0x4a0002fd, 0xfe0007ff, 0,              T5},
+{"vmsubai", "&UK,2K,J",        0x4a00027f, 0xfe1f07ff, 0,              T5},
+{"vmsubaq", "&UK,2K,Q",        0x4a00027d, 0xfe1f07ff, 0,              T5},
+{"vmsubaw", "&UK,2K,1%w",      0x4a0000ff, 0xfe0007ff, 0,              T5},
+{"vmsubax", "&UK,2K,1%x",      0x4a0000fc, 0xfe0007ff, 0,              T5},
+{"vmsubay", "&UK,2K,1%y",      0x4a0000fd, 0xfe0007ff, 0,              T5},
+{"vmsubaz", "&UK,2K,1%z",      0x4a0000fe, 0xfe0007ff, 0,              T5},
+{"vmtir",   "&4,2K",   0x4a0003fc, 0xfe0007ff, 0,              T5},
+{"vmul",    "&3K,2K,1K",       0x4a00002a, 0xfe00003f, 0,              T5},
+{"vmuli",   "&3K,2K,J",        0x4a00001e, 0xfe1f003f, 0,              T5},
+{"vmulq",   "&3K,2K,Q",        0x4a00001c, 0xfe1f003f, 0,              T5},
+{"vmulw",   "&3K,2K,1%w",      0x4a00001b, 0xfe00003f, 0,              T5},
+{"vmulx",   "&3K,2K,1%x",      0x4a000018, 0xfe00003f, 0,              T5},
+{"vmuly",   "&3K,2K,1%y",      0x4a000019, 0xfe00003f, 0,              T5},
+{"vmulz",   "&3K,2K,1%z",      0x4a00001a, 0xfe00003f, 0,              T5},
+{"vmula",   "&UK,2K,1K",       0x4a0002be, 0xfe0007ff, 0,              T5},
+{"vmulai",  "&UK,2K,J",        0x4a0001fe, 0xfe1f07ff, 0,              T5},
+{"vmulaq",  "&UK,2K,Q",        0x4a0001fc, 0xfe1f07ff, 0,              T5},
+{"vmulaw",  "&UK,2K,1%w",      0x4a0001bf, 0xfe0007ff, 0,              T5},
+{"vmulax",  "&UK,2K,1%x",      0x4a0001bc, 0xfe0007ff, 0,              T5},
+{"vmulay",  "&UK,2K,1%y",      0x4a0001bd, 0xfe0007ff, 0,              T5},
+{"vmulaz",  "&UK,2K,1%z",      0x4a0001be, 0xfe0007ff, 0,              T5},
+{"vnop","",            0x4a0002ff, 0xffffffff, 0,              T5},
+{"vopmula.xyz", "U,2,1", 0x4bc002fe, 0xffe007ff,       0,      T5},
+{"vopmsub.xyz", "3,2,1", 0x4bc0002e, 0xffe0003f,       0,      T5},
+{"vrget",  "1K,X",     0x4a20043d, 0xffe0ffff, 0,              T5},
+{"vrinit", "X,8",      0x4a00043e, 0xff9f07ff, 0,              T5},
+{"vrnext",  "1K,X",    0x4a20043c, 0xffe0ffff, 0,              T5},
+{"vrsqrt","Q,8,7",     0x4a0003be, 0xfe0007ff, 0,              T5},
+{"vrxor", "X,8",       0x4a00043f, 0xff9f07ff, 0,              T5},
+{"vsqd",  "&2K,(--4)K",        0x4a00037f, 0xfe0007ff, 0,              T5},
+{"vsqi",  "&2K,(4++)K",        0x4a00037d, 0xfe0007ff, 0,              T5},
+{"vsqrt", "Q,7",       0x4a2003bd, 0xfe60ffff, 0,              T5},
+{"vsub",  "&3K,2K,1K", 0x4a00002c, 0xfe00003f, 0,              T5},
+{"vsubi", "&3K,2K,J",  0x4a000026, 0xfe1f003f, 0,              T5},
+{"vsubq", "&3K,2K,Q",  0x4a000024, 0xfe1f003f, 0,              T5},
+{"vsubw", "&3K,2K,1%w",        0x4a000007, 0xfe00003f, 0,              T5},
+{"vsubx", "&3K,2K,1%x",        0x4a000004, 0xfe00003f, 0,              T5},
+{"vsuby", "&3K,2K,1%y",        0x4a000005, 0xfe00003f, 0,              T5},
+{"vsubz", "&3K,2K,1%z",        0x4a000006, 0xfe00003f, 0,              T5},
+{"vsuba", "&UK,2K,1K", 0x4a0002fc, 0xfe0007ff, 0,              T5},
+{"vsubai", "&UK,2K,J", 0x4a00027e, 0xfe1f07ff, 0,              T5},
+{"vsubaq", "&UK,2K,Q", 0x4a00027c, 0xfe1f07ff, 0,              T5},
+{"vsubaw", "&UK,2K,1%w",       0x4a00007f, 0xfe0007ff, 0,              T5},
+{"vsubax", "&UK,2K,1%x",       0x4a00007c, 0xfe0007ff, 0,              T5},
+{"vsubay", "&UK,2K,1%y",       0x4a00007d, 0xfe0007ff, 0,              T5},
+{"vsubaz", "&UK,2K,1%z",       0x4a00007e, 0xfe0007ff, 0,              T5},
+{"vwaitq","",          0x4a0003bf, 0xffffffff, 0,              T5},