From: Jan Beulich <jbeulich@suse.com>
Date: Fri, 6 Mar 2020 07:49:45 +0000 (+0100)
Subject: x86: add missing IgnoreSize
X-Git-Url: http://git.efficios.com/?a=commitdiff_plain;h=a04973848dc529f4eeb3bd198251da9faf01e2a2;p=deliverable%2Fbinutils-gdb.git

x86: add missing IgnoreSize

For proper code generation in 16-bit mode (or to avoid the "same type of
prefix used twice" diagnostic there), IgnoreSize is needed on certain
templates allowing for just 32-(and maybe 64-)bit operands.

Beyond adding tests for the previously broken cases, also add ones for
the previously working cases where IgnoreSize is needed for the same
reason (leaving out MPX for now, as that'll require an assembler change
first). Some minor adjustments to tests get done such that re-use of the
same code for 16-bit code generation testing becomes easier.
---

diff --git a/gas/ChangeLog b/gas/ChangeLog
index e82aef3c8d..28af680ce6 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,24 @@
+2020-03-06  Jan Beulich  <jbeulich@suse.com>
+
+	* testsuite/gas/i386/adx.s, testsuite/gas/i386/cet.s,
+	testsuite/gas/i386/ept.s, testsuite/gas/i386/fsgs.s,
+	testsuite/gas/i386/invpcid.s, testsuite/gas/i386/movdir.s,
+	testsuite/gas/i386/ptwrite.s, testsuite/gas/i386/vmx.s,
+	* testsuite/gas/i386/code16.s: Add CR, DR, and TR access cases
+	as well as a BSWAP one.
+	* testsuite/gas/i386/rdpid.s: Add 16-bit case.
+	* testsuite/gas/i386/sse2-16bit.s: Cover more insns.
+	* testsuite/gas/i386/adx-intel.d, testsuite/gas/i386/adx.d,
+	testsuite/gas/i386/cet-intel.d, testsuite/gas/i386/cet.d,
+	testsuite/gas/i386/code16.d, testsuite/gas/i386/ept-intel.d,
+	testsuite/gas/i386/ept.d, testsuite/gas/i386/fsgs-intel.d,
+	testsuite/gas/i386/fsgs.d, testsuite/gas/i386/invpcid-intel.d,
+	testsuite/gas/i386/invpcid.d, testsuite/gas/i386/movdir-intel.d,
+	testsuite/gas/i386/movdir.d, testsuite/gas/i386/ptwrite-intel.d,
+	testsuite/gas/i386/ptwrite.d, testsuite/gas/i386/rdpid-intel.d,
+	testsuite/gas/i386/rdpid.d, testsuite/gas/i386/sse2-16bit.d,
+	testsuite/gas/i386/vmx.d: Adjust expectations.
+
 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 
 	* config/tc-i386.c (md_assemble): Also exclude tpause and umwait
diff --git a/gas/testsuite/gas/i386/adx-intel.d b/gas/testsuite/gas/i386/adx-intel.d
index cf356d5626..1de1e8f763 100644
--- a/gas/testsuite/gas/i386/adx-intel.d
+++ b/gas/testsuite/gas/i386/adx-intel.d
@@ -20,12 +20,22 @@ Disassembly of section .text:
 [       ]*[a-f0-9]+:	f3 0f 38 f6 00       	adox   eax,DWORD PTR \[eax\]
 [       ]*[a-f0-9]+:	f3 0f 38 f6 ca       	adox   ecx,edx
 [       ]*[a-f0-9]+:	f3 0f 38 f6 00       	adox   eax,DWORD PTR \[eax\]
-[       ]*[a-f0-9]+:	66 0f 38 f6 82 8f 01 00 00 	adcx   eax,DWORD PTR \[edx\+0x18f\]
+[       ]*[a-f0-9]+:	66 0f 38 f6 42 24    	adcx   eax,DWORD PTR \[edx\+0x24\]
 [       ]*[a-f0-9]+:	66 0f 38 f6 d1       	adcx   edx,ecx
-[       ]*[a-f0-9]+:	66 0f 38 f6 94 f4 c0 1d fe ff 	adcx   edx,DWORD PTR \[esp\+esi\*8-0x1e240\]
+[       ]*[a-f0-9]+:	66 0f 38 f6 54 f4 f4 	adcx   edx,DWORD PTR \[esp\+esi\*8-0xc\]
 [       ]*[a-f0-9]+:	66 0f 38 f6 00       	adcx   eax,DWORD PTR \[eax\]
-[       ]*[a-f0-9]+:	f3 0f 38 f6 82 8f 01 00 00 	adox   eax,DWORD PTR \[edx\+0x18f\]
+[       ]*[a-f0-9]+:	f3 0f 38 f6 42 24    	adox   eax,DWORD PTR \[edx\+0x24\]
 [       ]*[a-f0-9]+:	f3 0f 38 f6 d1       	adox   edx,ecx
-[       ]*[a-f0-9]+:	f3 0f 38 f6 94 f4 c0 1d fe ff 	adox   edx,DWORD PTR \[esp\+esi\*8-0x1e240\]
+[       ]*[a-f0-9]+:	f3 0f 38 f6 54 f4 f4 	adox   edx,DWORD PTR \[esp\+esi\*8-0xc\]
 [       ]*[a-f0-9]+:	f3 0f 38 f6 00       	adox   eax,DWORD PTR \[eax\]
+[       ]*[a-f0-9]+:	67 66 0f 38 f6 42 24 	adcx   eax,DWORD PTR \[bp\+si\+0x24\]
+[       ]*[a-f0-9]+:	66 0f 38 f6 d1       	adcx   edx,ecx
+[       ]*[a-f0-9]+:	67 66 0f 38 f6 54 f4 	adcx   edx,DWORD PTR \[si-0xc\]
+[       ]*[a-f0-9]+:	f4                   	hlt *
+[       ]*[a-f0-9]+:	67 66 0f 38 f6 00    	adcx   eax,DWORD PTR \[bx\+si\]
+[       ]*[a-f0-9]+:	67 f3 0f 38 f6 42 24 	adox   eax,DWORD PTR \[bp\+si\+0x24\]
+[       ]*[a-f0-9]+:	f3 0f 38 f6 d1       	adox   edx,ecx
+[       ]*[a-f0-9]+:	67 f3 0f 38 f6 54 f4 	adox   edx,DWORD PTR \[si-0xc\]
+[       ]*[a-f0-9]+:	f4                   	hlt *
+[       ]*[a-f0-9]+:	67 f3 0f 38 f6 00    	adox   eax,DWORD PTR \[bx\+si\]
 #pass
diff --git a/gas/testsuite/gas/i386/adx.d b/gas/testsuite/gas/i386/adx.d
index 1269c7cb48..2c54be37d4 100644
--- a/gas/testsuite/gas/i386/adx.d
+++ b/gas/testsuite/gas/i386/adx.d
@@ -19,12 +19,22 @@ Disassembly of section .text:
 [       ]*[a-f0-9]+:	f3 0f 38 f6 00       	adox   \(%eax\),%eax
 [       ]*[a-f0-9]+:	f3 0f 38 f6 ca       	adox   %edx,%ecx
 [       ]*[a-f0-9]+:	f3 0f 38 f6 00       	adox   \(%eax\),%eax
-[       ]*[a-f0-9]+:	66 0f 38 f6 82 8f 01 00 00 	adcx   0x18f\(%edx\),%eax
+[       ]*[a-f0-9]+:	66 0f 38 f6 42 24    	adcx   0x24\(%edx\),%eax
 [       ]*[a-f0-9]+:	66 0f 38 f6 d1       	adcx   %ecx,%edx
-[       ]*[a-f0-9]+:	66 0f 38 f6 94 f4 c0 1d fe ff 	adcx   -0x1e240\(%esp,%esi,8\),%edx
+[       ]*[a-f0-9]+:	66 0f 38 f6 54 f4 f4 	adcx   -0xc\(%esp,%esi,8\),%edx
 [       ]*[a-f0-9]+:	66 0f 38 f6 00       	adcx   \(%eax\),%eax
-[       ]*[a-f0-9]+:	f3 0f 38 f6 82 8f 01 00 00 	adox   0x18f\(%edx\),%eax
+[       ]*[a-f0-9]+:	f3 0f 38 f6 42 24    	adox   0x24\(%edx\),%eax
 [       ]*[a-f0-9]+:	f3 0f 38 f6 d1       	adox   %ecx,%edx
-[       ]*[a-f0-9]+:	f3 0f 38 f6 94 f4 c0 1d fe ff 	adox   -0x1e240\(%esp,%esi,8\),%edx
+[       ]*[a-f0-9]+:	f3 0f 38 f6 54 f4 f4 	adox   -0xc\(%esp,%esi,8\),%edx
 [       ]*[a-f0-9]+:	f3 0f 38 f6 00       	adox   \(%eax\),%eax
+[       ]*[a-f0-9]+:	67 66 0f 38 f6 42 24 	adcx   0x24\(%bp,%si\),%eax
+[       ]*[a-f0-9]+:	66 0f 38 f6 d1       	adcx   %ecx,%edx
+[       ]*[a-f0-9]+:	67 66 0f 38 f6 54 f4 	adcx   -0xc\(%si\),%edx
+[       ]*[a-f0-9]+:	f4                   	hlt *
+[       ]*[a-f0-9]+:	67 66 0f 38 f6 00    	adcx   \(%bx,%si\),%eax
+[       ]*[a-f0-9]+:	67 f3 0f 38 f6 42 24 	adox   0x24\(%bp,%si\),%eax
+[       ]*[a-f0-9]+:	f3 0f 38 f6 d1       	adox   %ecx,%edx
+[       ]*[a-f0-9]+:	67 f3 0f 38 f6 54 f4 	adox   -0xc\(%si\),%edx
+[       ]*[a-f0-9]+:	f4                   	hlt *
+[       ]*[a-f0-9]+:	67 f3 0f 38 f6 00    	adox   \(%bx,%si\),%eax
 #pass
diff --git a/gas/testsuite/gas/i386/adx.s b/gas/testsuite/gas/i386/adx.s
index 18d107c14a..a474d9403f 100644
--- a/gas/testsuite/gas/i386/adx.s
+++ b/gas/testsuite/gas/i386/adx.s
@@ -17,14 +17,17 @@ _start:
         adoxl   (%eax), %eax
 
 	.intel_syntax noprefix
+	.rept 2
 
-        adcx    eax, DWORD PTR [edx+399]
+        adcx    eax, DWORD PTR [edx+36]
         adcx    edx, ecx
-        adcx    edx, DWORD PTR [esp+esi*8-123456]
+        adcx    edx, DWORD PTR [esp+esi*8-12]
         adcx    eax, DWORD PTR [eax]
 
-        adox    eax, DWORD PTR [edx+399]
+        adox    eax, DWORD PTR [edx+36]
         adox    edx, ecx
-        adox    edx, DWORD PTR [esp+esi*8-123456]
+        adox    edx, DWORD PTR [esp+esi*8-12]
         adox    eax, DWORD PTR [eax]
 
+	.code16
+	.endr
diff --git a/gas/testsuite/gas/i386/cet-intel.d b/gas/testsuite/gas/i386/cet-intel.d
index 96ff807f3e..787d6d218b 100644
--- a/gas/testsuite/gas/i386/cet-intel.d
+++ b/gas/testsuite/gas/i386/cet-intel.d
@@ -21,13 +21,29 @@ Disassembly of section .text:
  +[a-f0-9]+:	f3 0f ae e9          	incsspd ecx
  +[a-f0-9]+:	f3 0f 1e c9          	rdsspd ecx
  +[a-f0-9]+:	f3 0f 01 ea          	saveprevssp 
- +[a-f0-9]+:	f3 0f 01 2c 01       	rstorssp QWORD PTR \[ecx\+eax\*1\]
+ +[a-f0-9]+:	f3 0f 01 6c 01 90    	rstorssp QWORD PTR \[ecx\+eax\*1-0x70\]
  +[a-f0-9]+:	0f 38 f6 02          	wrssd  \[edx\],eax
  +[a-f0-9]+:	0f 38 f6 10          	wrssd  \[eax\],edx
  +[a-f0-9]+:	66 0f 38 f5 14 2f    	wrussd \[edi\+ebp\*1\],edx
- +[a-f0-9]+:	66 0f 38 f5 3c 2a    	wrussd \[edx\+ebp\*1\],edi
+ +[a-f0-9]+:	66 0f 38 f5 3c 0e    	wrussd \[esi\+ecx\*1\],edi
  +[a-f0-9]+:	f3 0f 01 e8          	setssbsy 
- +[a-f0-9]+:	f3 0f ae 34 04       	clrssbsy QWORD PTR \[esp\+eax\*1\]
+ +[a-f0-9]+:	f3 0f ae 34 44       	clrssbsy QWORD PTR \[esp\+eax\*2\]
  +[a-f0-9]+:	f3 0f 1e fa          	endbr64 
  +[a-f0-9]+:	f3 0f 1e fb          	endbr32 
+ +[a-f0-9]+:	f3 0f ae e9          	incsspd ecx
+ +[a-f0-9]+:	f3 0f 1e c9          	rdsspd ecx
+ +[a-f0-9]+:	f3 0f 01 ea          	saveprevssp *
+ +[a-f0-9]+:	67 f3 0f 01 6c 01    	rstorssp QWORD PTR \[si\+0x1\]
+ +[a-f0-9]+:	90                   	nop *
+ +[a-f0-9]+:	67 0f 38 f6 02       	wrssd  \[bp\+si\],eax
+ +[a-f0-9]+:	67 0f 38 f6 10       	wrssd  \[bx\+si\],edx
+ +[a-f0-9]+:	67 66 0f 38 f5 14    	wrussd \[si\],edx
+ +[a-f0-9]+:	2f                   	das *
+ +[a-f0-9]+:	67 66 0f 38 f5 3c    	wrussd \[si\],edi
+ +[a-f0-9]+:	0e                   	push   cs
+ +[a-f0-9]+:	f3 0f 01 e8          	setssbsy *
+ +[a-f0-9]+:	67 f3 0f ae 34       	clrssbsy QWORD PTR \[si\]
+ +[a-f0-9]+:	44                   	inc    esp
+ +[a-f0-9]+:	f3 0f 1e fa          	endbr64 *
+ +[a-f0-9]+:	f3 0f 1e fb          	endbr32 *
 #pass
diff --git a/gas/testsuite/gas/i386/cet.d b/gas/testsuite/gas/i386/cet.d
index 0f67716123..b0a23b8028 100644
--- a/gas/testsuite/gas/i386/cet.d
+++ b/gas/testsuite/gas/i386/cet.d
@@ -19,13 +19,29 @@ Disassembly of section .text:
  +[a-f0-9]+:	f3 0f ae e9          	incsspd %ecx
  +[a-f0-9]+:	f3 0f 1e c9          	rdsspd %ecx
  +[a-f0-9]+:	f3 0f 01 ea          	saveprevssp 
- +[a-f0-9]+:	f3 0f 01 2c 01       	rstorssp \(%ecx,%eax,1\)
+ +[a-f0-9]+:	f3 0f 01 6c 01 90    	rstorssp -0x70\(%ecx,%eax,1\)
  +[a-f0-9]+:	0f 38 f6 02          	wrssd  %eax,\(%edx\)
  +[a-f0-9]+:	0f 38 f6 10          	wrssd  %edx,\(%eax\)
  +[a-f0-9]+:	66 0f 38 f5 14 2f    	wrussd %edx,\(%edi,%ebp,1\)
- +[a-f0-9]+:	66 0f 38 f5 3c 2a    	wrussd %edi,\(%edx,%ebp,1\)
+ +[a-f0-9]+:	66 0f 38 f5 3c 0e    	wrussd %edi,\(%esi,%ecx,1\)
  +[a-f0-9]+:	f3 0f 01 e8          	setssbsy 
- +[a-f0-9]+:	f3 0f ae 34 04       	clrssbsy \(%esp,%eax,1\)
+ +[a-f0-9]+:	f3 0f ae 34 44       	clrssbsy \(%esp,%eax,2\)
  +[a-f0-9]+:	f3 0f 1e fa          	endbr64 
  +[a-f0-9]+:	f3 0f 1e fb          	endbr32 
+ +[a-f0-9]+:	f3 0f ae e9          	incsspd %ecx
+ +[a-f0-9]+:	f3 0f 1e c9          	rdsspd %ecx
+ +[a-f0-9]+:	f3 0f 01 ea          	saveprevssp *
+ +[a-f0-9]+:	67 f3 0f 01 6c 01    	rstorssp 0x1\(%si\)
+ +[a-f0-9]+:	90                   	nop *
+ +[a-f0-9]+:	67 0f 38 f6 02       	wrssd  %eax,\(%bp,%si\)
+ +[a-f0-9]+:	67 0f 38 f6 10       	wrssd  %edx,\(%bx,%si\)
+ +[a-f0-9]+:	67 66 0f 38 f5 14    	wrussd %edx,\(%si\)
+ +[a-f0-9]+:	2f                   	das *
+ +[a-f0-9]+:	67 66 0f 38 f5 3c    	wrussd %edi,\(%si\)
+ +[a-f0-9]+:	0e                   	push   %cs
+ +[a-f0-9]+:	f3 0f 01 e8          	setssbsy *
+ +[a-f0-9]+:	67 f3 0f ae 34       	clrssbsy \(%si\)
+ +[a-f0-9]+:	44                   	inc    %esp
+ +[a-f0-9]+:	f3 0f 1e fa          	endbr64 *
+ +[a-f0-9]+:	f3 0f 1e fb          	endbr32 *
 #pass
diff --git a/gas/testsuite/gas/i386/cet.s b/gas/testsuite/gas/i386/cet.s
index 730e7d7fd5..1c3a50fedd 100644
--- a/gas/testsuite/gas/i386/cet.s
+++ b/gas/testsuite/gas/i386/cet.s
@@ -13,15 +13,18 @@ _start:
 	endbr32
 
 	.intel_syntax noprefix
+	.rept 2
 	incsspd ecx
 	rdsspd ecx
 	saveprevssp
-	rstorssp QWORD PTR [ecx + eax]
+	rstorssp QWORD PTR [ecx + eax - 0x70]
 	wrssd [edx],eax
 	wrssd dword ptr [eax],edx
 	wrussd [edi + ebp],edx
-	wrussd dword ptr [edx + ebp],edi
+	wrussd dword ptr [esi + ecx],edi
 	setssbsy
-	clrssbsy QWORD PTR [esp + eax]
+	clrssbsy QWORD PTR [esp + eax * 2]
 	endbr64
 	endbr32
+	.code16
+	.endr
diff --git a/gas/testsuite/gas/i386/code16.d b/gas/testsuite/gas/i386/code16.d
index b860448d6c..246be486ba 100644
--- a/gas/testsuite/gas/i386/code16.d
+++ b/gas/testsuite/gas/i386/code16.d
@@ -10,6 +10,13 @@ Disassembly of section .text:
  +[a-f0-9]+:	f3 66 a7             	repz cmpsl %es:\(%di\),%ds:\(%si\)
  +[a-f0-9]+:	66 f3 a5             	rep movsl %ds:\(%si\),%es:\(%di\)
  +[a-f0-9]+:	66 f3 a7             	repz cmpsl %es:\(%di\),%ds:\(%si\)
+ +[a-f0-9]+:	0f 20 d1             	mov    %cr2,%ecx
+ +[a-f0-9]+:	0f 22 d1             	mov    %ecx,%cr2
+ +[a-f0-9]+:	0f 21 d1             	mov    %d[br]2,%ecx
+ +[a-f0-9]+:	0f 23 d1             	mov    %ecx,%d[br]2
+ +[a-f0-9]+:	0f 24 d1             	mov    %tr2,%ecx
+ +[a-f0-9]+:	0f 26 d1             	mov    %ecx,%tr2
+ +[a-f0-9]+:	66 0f c9             	bswap  %ecx
  +[a-f0-9]+:	66 f3 a5             	rep movsl %ds:\(%si\),%es:\(%di\)
  +[a-f0-9]+:	66 f3 a7             	repz cmpsl %es:\(%di\),%ds:\(%si\)
 #pass
diff --git a/gas/testsuite/gas/i386/code16.s b/gas/testsuite/gas/i386/code16.s
index d18fa5179a..407bb45f9f 100644
--- a/gas/testsuite/gas/i386/code16.s
+++ b/gas/testsuite/gas/i386/code16.s
@@ -4,6 +4,18 @@
 	rep; cmpsd
 	rep movsd %ds:(%si),%es:(%di)
 	rep cmpsd %es:(%di),%ds:(%si)
+
+	mov	%cr2, %ecx
+	mov	%ecx, %cr2
+
+	mov	%dr2, %ecx
+	mov	%ecx, %dr2
+
+	mov	%tr2, %ecx
+	mov	%ecx, %tr2
+
+	bswap	%ecx
+
 	.intel_syntax noprefix
 	rep movsd dword ptr es:[di], dword ptr ds:[si]
 	rep cmpsd dword ptr ds:[si], dword ptr es:[di]
diff --git a/gas/testsuite/gas/i386/ept-intel.d b/gas/testsuite/gas/i386/ept-intel.d
index 7ee26b651d..4057d9663b 100644
--- a/gas/testsuite/gas/i386/ept-intel.d
+++ b/gas/testsuite/gas/i386/ept-intel.d
@@ -11,4 +11,8 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	66 0f 38 81 19       	invvpid ebx,OWORD PTR \[ecx\]
 [ 	]*[a-f0-9]+:	66 0f 38 80 19       	invept ebx,OWORD PTR \[ecx\]
 [ 	]*[a-f0-9]+:	66 0f 38 81 19       	invvpid ebx,OWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	67 66 0f 38 80 19    	invept ebx,OWORD PTR \[bx\+di\]
+[ 	]*[a-f0-9]+:	67 66 0f 38 81 19    	invvpid ebx,OWORD PTR \[bx\+di\]
+[ 	]*[a-f0-9]+:	67 66 0f 38 80 19    	invept ebx,OWORD PTR \[bx\+di\]
+[ 	]*[a-f0-9]+:	67 66 0f 38 81 19    	invvpid ebx,OWORD PTR \[bx\+di\]
 #pass
diff --git a/gas/testsuite/gas/i386/ept.d b/gas/testsuite/gas/i386/ept.d
index 7321a6974e..1889f57089 100644
--- a/gas/testsuite/gas/i386/ept.d
+++ b/gas/testsuite/gas/i386/ept.d
@@ -10,4 +10,8 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	66 0f 38 81 19       	invvpid \(%ecx\),%ebx
 [ 	]*[a-f0-9]+:	66 0f 38 80 19       	invept \(%ecx\),%ebx
 [ 	]*[a-f0-9]+:	66 0f 38 81 19       	invvpid \(%ecx\),%ebx
+[ 	]*[a-f0-9]+:	67 66 0f 38 80 19    	invept \(%bx,%di\),%ebx
+[ 	]*[a-f0-9]+:	67 66 0f 38 81 19    	invvpid \(%bx,%di\),%ebx
+[ 	]*[a-f0-9]+:	67 66 0f 38 80 19    	invept \(%bx,%di\),%ebx
+[ 	]*[a-f0-9]+:	67 66 0f 38 81 19    	invvpid \(%bx,%di\),%ebx
 #pass
diff --git a/gas/testsuite/gas/i386/ept.s b/gas/testsuite/gas/i386/ept.s
index 70ecacd704..e8f0b9a609 100644
--- a/gas/testsuite/gas/i386/ept.s
+++ b/gas/testsuite/gas/i386/ept.s
@@ -1,9 +1,15 @@
 # Check EPT instructions
 	.text
 _start:
+	.rept 2
+
 	invept	(%ecx), %ebx
 	invvpid	(%ecx), %ebx
 
 	.intel_syntax noprefix
 	invept ebx, oword ptr [ecx]
 	invvpid ebx, oword ptr [ecx]
+
+	.att_syntax prefix
+	.code16
+	.endr
diff --git a/gas/testsuite/gas/i386/fsgs-intel.d b/gas/testsuite/gas/i386/fsgs-intel.d
index 1cb1ee3fd0..84e2ff6608 100644
--- a/gas/testsuite/gas/i386/fsgs-intel.d
+++ b/gas/testsuite/gas/i386/fsgs-intel.d
@@ -16,4 +16,12 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	f3 0f ae cb          	rdgsbase ebx
 [ 	]*[a-f0-9]+:	f3 0f ae d3          	wrfsbase ebx
 [ 	]*[a-f0-9]+:	f3 0f ae db          	wrgsbase ebx
+[ 	]*[a-f0-9]+:	f3 0f ae c3          	rdfsbase ebx
+[ 	]*[a-f0-9]+:	f3 0f ae cb          	rdgsbase ebx
+[ 	]*[a-f0-9]+:	f3 0f ae d3          	wrfsbase ebx
+[ 	]*[a-f0-9]+:	f3 0f ae db          	wrgsbase ebx
+[ 	]*[a-f0-9]+:	f3 0f ae c3          	rdfsbase ebx
+[ 	]*[a-f0-9]+:	f3 0f ae cb          	rdgsbase ebx
+[ 	]*[a-f0-9]+:	f3 0f ae d3          	wrfsbase ebx
+[ 	]*[a-f0-9]+:	f3 0f ae db          	wrgsbase ebx
 #pass
diff --git a/gas/testsuite/gas/i386/fsgs.d b/gas/testsuite/gas/i386/fsgs.d
index 234737580d..f7b0d0f89b 100644
--- a/gas/testsuite/gas/i386/fsgs.d
+++ b/gas/testsuite/gas/i386/fsgs.d
@@ -15,4 +15,12 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	f3 0f ae cb          	rdgsbase %ebx
 [ 	]*[a-f0-9]+:	f3 0f ae d3          	wrfsbase %ebx
 [ 	]*[a-f0-9]+:	f3 0f ae db          	wrgsbase %ebx
+[ 	]*[a-f0-9]+:	f3 0f ae c3          	rdfsbase %ebx
+[ 	]*[a-f0-9]+:	f3 0f ae cb          	rdgsbase %ebx
+[ 	]*[a-f0-9]+:	f3 0f ae d3          	wrfsbase %ebx
+[ 	]*[a-f0-9]+:	f3 0f ae db          	wrgsbase %ebx
+[ 	]*[a-f0-9]+:	f3 0f ae c3          	rdfsbase %ebx
+[ 	]*[a-f0-9]+:	f3 0f ae cb          	rdgsbase %ebx
+[ 	]*[a-f0-9]+:	f3 0f ae d3          	wrfsbase %ebx
+[ 	]*[a-f0-9]+:	f3 0f ae db          	wrgsbase %ebx
 #pass
diff --git a/gas/testsuite/gas/i386/fsgs.s b/gas/testsuite/gas/i386/fsgs.s
index 8ad289c716..92473a8479 100644
--- a/gas/testsuite/gas/i386/fsgs.s
+++ b/gas/testsuite/gas/i386/fsgs.s
@@ -2,6 +2,7 @@
 
 	.text
 foo:
+	.rept 2
 	rdfsbase %ebx
 	rdgsbase %ebx
 	wrfsbase %ebx
@@ -12,3 +13,7 @@ foo:
 	rdgsbase ebx
 	wrfsbase ebx
 	wrgsbase ebx
+
+	.att_syntax prefix
+	.code16
+	.endr
diff --git a/gas/testsuite/gas/i386/invpcid-intel.d b/gas/testsuite/gas/i386/invpcid-intel.d
index 8d1b5a97bf..28cee1a2d8 100644
--- a/gas/testsuite/gas/i386/invpcid-intel.d
+++ b/gas/testsuite/gas/i386/invpcid-intel.d
@@ -12,4 +12,7 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	66 0f 38 82 10       	invpcid edx,\[eax\]
 [ 	]*[a-f0-9]+:	66 0f 38 82 10       	invpcid edx,\[eax\]
 [ 	]*[a-f0-9]+:	66 0f 38 82 10       	invpcid edx,\[eax\]
+[ 	]*[a-f0-9]+:	67 66 0f 38 82 10    	invpcid edx,\[bx\+si\]
+[ 	]*[a-f0-9]+:	67 66 0f 38 82 10    	invpcid edx,\[bx\+si\]
+[ 	]*[a-f0-9]+:	67 66 0f 38 82 10    	invpcid edx,\[bx\+si\]
 #pass
diff --git a/gas/testsuite/gas/i386/invpcid.d b/gas/testsuite/gas/i386/invpcid.d
index 3619e59ac4..d40037c25d 100644
--- a/gas/testsuite/gas/i386/invpcid.d
+++ b/gas/testsuite/gas/i386/invpcid.d
@@ -11,4 +11,7 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	66 0f 38 82 10       	invpcid \(%eax\),%edx
 [ 	]*[a-f0-9]+:	66 0f 38 82 10       	invpcid \(%eax\),%edx
 [ 	]*[a-f0-9]+:	66 0f 38 82 10       	invpcid \(%eax\),%edx
+[ 	]*[a-f0-9]+:	67 66 0f 38 82 10    	invpcid \(%bx,%si\),%edx
+[ 	]*[a-f0-9]+:	67 66 0f 38 82 10    	invpcid \(%bx,%si\),%edx
+[ 	]*[a-f0-9]+:	67 66 0f 38 82 10    	invpcid \(%bx,%si\),%edx
 #pass
diff --git a/gas/testsuite/gas/i386/invpcid.s b/gas/testsuite/gas/i386/invpcid.s
index 32067cb839..452c3c2fdd 100644
--- a/gas/testsuite/gas/i386/invpcid.s
+++ b/gas/testsuite/gas/i386/invpcid.s
@@ -2,8 +2,14 @@
 
 	.text
 foo:
+	.rept 2
+
 	invpcid	(%eax), %edx
 
 	.intel_syntax noprefix
 	invpcid	edx,[eax]
 	invpcid	edx,oword ptr [eax]
+
+	.att_syntax prefix
+	.code16
+	.endr
diff --git a/gas/testsuite/gas/i386/movdir-intel.d b/gas/testsuite/gas/i386/movdir-intel.d
index be721ba443..04f58a7892 100644
--- a/gas/testsuite/gas/i386/movdir-intel.d
+++ b/gas/testsuite/gas/i386/movdir-intel.d
@@ -16,4 +16,11 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*0f 38 f9 01[ 	]*movdiri DWORD PTR \[ecx\],eax
 [ 	]*[a-f0-9]+:[ 	]*66 0f 38 f8 01[ 	]*movdir64b eax,\[ecx\]
 [ 	]*[a-f0-9]+:[ 	]*67 66 0f 38 f8 04[ 	]*movdir64b ax,\[si\]
+[ 	]*[a-f0-9]+:[ 	]*67 0f 38 f9 01[ 	]*movdiri DWORD PTR \[bx\+di\],eax
+[ 	]*[a-f0-9]+:[ 	]*67 66 0f 38 f8 01[ 	]*movdir64b ax,\[bx\+di\]
+[ 	]*[a-f0-9]+:[ 	]*66 0f 38 f8 04 67[ 	]*movdir64b eax,\[edi\+eiz\*2\]
+[ 	]*[a-f0-9]+:[ 	]*0f 38 f9 01[ 	]*movdiri DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:[ 	]*67 0f 38 f9 01[ 	]*movdiri DWORD PTR \[bx\+di\],eax
+[ 	]*[a-f0-9]+:[ 	]*67 66 0f 38 f8 01[ 	]*movdir64b ax,\[bx\+di\]
+[ 	]*[a-f0-9]+:[ 	]*66 0f 38 f8 04 90[ 	]*movdir64b eax,\[eax\+edx\*4\]
 #pass
diff --git a/gas/testsuite/gas/i386/movdir.d b/gas/testsuite/gas/i386/movdir.d
index c70b756e37..192dad9920 100644
--- a/gas/testsuite/gas/i386/movdir.d
+++ b/gas/testsuite/gas/i386/movdir.d
@@ -16,4 +16,11 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*0f 38 f9 01[ 	]*movdiri %eax,\(%ecx\)
 [ 	]*[a-f0-9]+:[ 	]*66 0f 38 f8 01[ 	]*movdir64b \(%ecx\),%eax
 [ 	]*[a-f0-9]+:[ 	]*67 66 0f 38 f8 04[ 	]*movdir64b \(%si\),%ax
+[ 	]*[a-f0-9]+:[ 	]*67 0f 38 f9 01[ 	]*movdiri %eax,\(%bx,%di\)
+[ 	]*[a-f0-9]+:[ 	]*67 66 0f 38 f8 01[ 	]*movdir64b \(%bx,%di\),%ax
+[ 	]*[a-f0-9]+:[ 	]*66 0f 38 f8 04 67[ 	]*movdir64b \(%edi,%eiz,2\),%eax
+[ 	]*[a-f0-9]+:[ 	]*0f 38 f9 01[ 	]*movdiri %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:[ 	]*67 0f 38 f9 01[ 	]*movdiri %eax,\(%bx,%di\)
+[ 	]*[a-f0-9]+:[ 	]*67 66 0f 38 f8 01[ 	]*movdir64b \(%bx,%di\),%ax
+[ 	]*[a-f0-9]+:[ 	]*66 0f 38 f8 04 90[ 	]*movdir64b \(%eax,%edx,4\),%eax
 #pass
diff --git a/gas/testsuite/gas/i386/movdir.s b/gas/testsuite/gas/i386/movdir.s
index 5ea4bb5175..29c381ca23 100644
--- a/gas/testsuite/gas/i386/movdir.s
+++ b/gas/testsuite/gas/i386/movdir.s
@@ -3,6 +3,7 @@
 	.allow_index_reg
 	.text
 _start:
+	.rept 2
 	movdiri %eax, (%ecx)
 	movdir64b (%ecx),%eax
 	movdir64b (%si),%ax
@@ -12,3 +13,9 @@ _start:
 	movdiri dword ptr [ecx], eax
 	movdir64b eax,[ecx]
 	movdir64b ax,[si]
+
+	.att_syntax prefix
+	.code16
+	.endr
+
+	nop
diff --git a/gas/testsuite/gas/i386/ptwrite-intel.d b/gas/testsuite/gas/i386/ptwrite-intel.d
index f0f2aad2f9..b534514569 100644
--- a/gas/testsuite/gas/i386/ptwrite-intel.d
+++ b/gas/testsuite/gas/i386/ptwrite-intel.d
@@ -16,4 +16,11 @@ Disassembly of section \.text:
  +[a-f0-9]+:	f3 0f ae e1          	ptwrite ecx
  +[a-f0-9]+:	f3 0f ae 21          	ptwrite DWORD PTR \[ecx\]
  +[a-f0-9]+:	f3 0f ae 21          	ptwrite DWORD PTR \[ecx\]
+ +[a-f0-9]+:	f3 0f ae e1          	ptwrite ecx
+ +[a-f0-9]+:	f3 0f ae e1          	ptwrite ecx
+ +[a-f0-9]+:	67 f3 0f ae 21       	ptwrite DWORD PTR \[bx\+di\]
+ +[a-f0-9]+:	67 f3 0f ae 21       	ptwrite DWORD PTR \[bx\+di\]
+ +[a-f0-9]+:	f3 0f ae e1          	ptwrite ecx
+ +[a-f0-9]+:	67 f3 0f ae 21       	ptwrite DWORD PTR \[bx\+di\]
+ +[a-f0-9]+:	67 f3 0f ae 21       	ptwrite DWORD PTR \[bx\+di\]
 #pass
diff --git a/gas/testsuite/gas/i386/ptwrite.d b/gas/testsuite/gas/i386/ptwrite.d
index 31552bce91..a2349240a0 100644
--- a/gas/testsuite/gas/i386/ptwrite.d
+++ b/gas/testsuite/gas/i386/ptwrite.d
@@ -16,4 +16,11 @@ Disassembly of section \.text:
  +[a-f0-9]+:	f3 0f ae e1          	ptwrite %ecx
  +[a-f0-9]+:	f3 0f ae 21          	ptwritel \(%ecx\)
  +[a-f0-9]+:	f3 0f ae 21          	ptwritel \(%ecx\)
+ +[a-f0-9]+:	f3 0f ae e1          	ptwrite %ecx
+ +[a-f0-9]+:	f3 0f ae e1          	ptwrite %ecx
+ +[a-f0-9]+:	67 f3 0f ae 21       	ptwritel \(%bx,%di\)
+ +[a-f0-9]+:	67 f3 0f ae 21       	ptwritel \(%bx,%di\)
+ +[a-f0-9]+:	f3 0f ae e1          	ptwrite %ecx
+ +[a-f0-9]+:	67 f3 0f ae 21       	ptwritel \(%bx,%di\)
+ +[a-f0-9]+:	67 f3 0f ae 21       	ptwritel \(%bx,%di\)
 #pass
diff --git a/gas/testsuite/gas/i386/ptwrite.s b/gas/testsuite/gas/i386/ptwrite.s
index 61efd7e128..8234d07878 100644
--- a/gas/testsuite/gas/i386/ptwrite.s
+++ b/gas/testsuite/gas/i386/ptwrite.s
@@ -2,6 +2,7 @@
 
 	.text
 _start:
+	.rept 2
 	ptwrite %ecx
 	ptwritel %ecx
 	ptwrite (%ecx)
@@ -11,3 +12,7 @@ _start:
 	ptwrite ecx
 	ptwrite [ecx]
 	ptwrite DWORD PTR [ecx]
+
+	.att_syntax prefix
+	.code16
+	.endr
diff --git a/gas/testsuite/gas/i386/rdpid-intel.d b/gas/testsuite/gas/i386/rdpid-intel.d
index f733b17f52..ff9d9de7a7 100644
--- a/gas/testsuite/gas/i386/rdpid-intel.d
+++ b/gas/testsuite/gas/i386/rdpid-intel.d
@@ -8,4 +8,5 @@ Disassembly of section .text:
 
 0+ <_start>:
 [ 	]*[a-f0-9]+:[ 	]*f3 0f c7 f8[ 	]*rdpid  eax
+[ 	]*[a-f0-9]+:[ 	]*f3 0f c7 f9[ 	]*rdpid  ecx
 #pass
diff --git a/gas/testsuite/gas/i386/rdpid.d b/gas/testsuite/gas/i386/rdpid.d
index ef67c84948..d0d786d6c4 100644
--- a/gas/testsuite/gas/i386/rdpid.d
+++ b/gas/testsuite/gas/i386/rdpid.d
@@ -8,4 +8,5 @@ Disassembly of section .text:
 
 0+ <_start>:
 [ 	]*[a-f0-9]+:[ 	]*f3 0f c7 f8[ 	]*rdpid  %eax
+[ 	]*[a-f0-9]+:[ 	]*f3 0f c7 f9[ 	]*rdpid  %ecx
 #pass
diff --git a/gas/testsuite/gas/i386/rdpid.s b/gas/testsuite/gas/i386/rdpid.s
index fe6e401a98..b82f2e3b8c 100644
--- a/gas/testsuite/gas/i386/rdpid.s
+++ b/gas/testsuite/gas/i386/rdpid.s
@@ -3,3 +3,6 @@
 	.text
 _start:
 	rdpid %eax
+
+	.code16
+	rdpid %ecx
diff --git a/gas/testsuite/gas/i386/sse2-16bit.d b/gas/testsuite/gas/i386/sse2-16bit.d
index 16ea55fa6a..5b9fc2caf2 100644
--- a/gas/testsuite/gas/i386/sse2-16bit.d
+++ b/gas/testsuite/gas/i386/sse2-16bit.d
@@ -164,4 +164,23 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	66 0f fb c1          	psubq  %xmm1,%xmm0
 [ 	]*[a-f0-9]+:	67 66 0f fb 00       	psubq  \(%eax\),%xmm0
 [ 	]*[a-f0-9]+:	0f 58 2f             	addps  \(%bx\),%xmm5
+[ 	]*[a-f0-9]+:	f3 0f 2a d9          	cvtsi2ss %ecx,%xmm3
+[ 	]*[a-f0-9]+:	f3 0f 2d cb          	cvtss2si %xmm3,%ecx
+[ 	]*[a-f0-9]+:	f3 0f 2c cb          	cvttss2si %xmm3,%ecx
+[ 	]*[a-f0-9]+:	66 0f 3a 17 ca 00    	extractps \$0x0,%xmm1,%edx
+[ 	]*[a-f0-9]+:	0f 50 ca             	movmskps %xmm2,%ecx
+[ 	]*[a-f0-9]+:	66 0f 3a 14 ca 00    	pextrb \$0x0,%xmm1,%edx
+[ 	]*[a-f0-9]+:	66 0f 3a 16 ca 00    	pextrd \$0x0,%xmm1,%edx
+[ 	]*[a-f0-9]+:	0f c5 d1 00          	pextrw \$0x0,%mm1,%edx
+[ 	]*[a-f0-9]+:	66 0f c5 d1 00       	pextrw \$0x0,%xmm1,%edx
+[ 	]*[a-f0-9]+:	66 0f 3a 20 d1 00    	pinsrb \$0x0,%ecx,%xmm2
+[ 	]*[a-f0-9]+:	66 0f 3a 22 d1 00    	pinsrd \$0x0,%ecx,%xmm2
+[ 	]*[a-f0-9]+:	0f c4 d1 00          	pinsrw \$0x0,%ecx,%mm2
+[ 	]*[a-f0-9]+:	66 0f c4 d1 00       	pinsrw \$0x0,%ecx,%xmm2
+[ 	]*[a-f0-9]+:	66 0f d7 d3          	pmovmskb %xmm3,%edx
+[ 	]*[a-f0-9]+:	f3 0f 2a 05          	cvtsi2ssl? \(%di\),%xmm0
+[ 	]*[a-f0-9]+:	66 0f 3a 17 0d 00    	extractps \$0x0,%xmm1,\(%di\)
+[ 	]*[a-f0-9]+:	66 0f 3a 21 05 00    	insertps \$0x0,\(%di\),%xmm0
+[ 	]*[a-f0-9]+:	66 0f 3a 16 0d 00    	pextrd \$0x0,%xmm1,\(%di\)
+[ 	]*[a-f0-9]+:	66 0f 3a 22 05 00    	pinsrd \$0x0,\(%di\),%xmm0
 #pass
diff --git a/gas/testsuite/gas/i386/sse2-16bit.s b/gas/testsuite/gas/i386/sse2-16bit.s
index ab9c323220..bf0e2ddbdd 100644
--- a/gas/testsuite/gas/i386/sse2-16bit.s
+++ b/gas/testsuite/gas/i386/sse2-16bit.s
@@ -4,4 +4,26 @@
 	.include "sse2.s"
 	.att_syntax prefix
 
+	# also a few SSE* insns
 	addps (%bx),%xmm5
+	cvtsi2ss %ecx,%xmm3
+	cvtss2si %xmm3,%ecx
+	cvttss2si %xmm3,%ecx
+	extractps $0,%xmm1,%edx
+	movmskps %xmm2,%ecx
+	pextrb $0,%xmm1,%edx
+	pextrd $0,%xmm1,%edx
+	pextrw $0,%mm1,%edx
+	pextrw $0,%xmm1,%edx
+	pinsrb $0,%ecx,%xmm2
+	pinsrd $0,%ecx,%xmm2
+	pinsrw $0,%ecx,%mm2
+	pinsrw $0,%ecx,%xmm2
+	pmovmskb %xmm3,%edx
+
+	.intel_syntax noprefix
+	cvtsi2ss xmm0, dword ptr [di]
+	extractps dword ptr [di], xmm1, 0
+	insertps xmm0, dword ptr [di], 0
+	pextrd dword ptr [di], xmm1, 0
+	pinsrd xmm0, dword ptr [di], 0
diff --git a/gas/testsuite/gas/i386/vmx.d b/gas/testsuite/gas/i386/vmx.d
index 334702d9c2..3905b05608 100644
--- a/gas/testsuite/gas/i386/vmx.d
+++ b/gas/testsuite/gas/i386/vmx.d
@@ -22,4 +22,20 @@ Disassembly of section .text:
   29:	0f 79 d8 [ 	]*vmwrite %eax,%ebx
   2c:	0f 79 18 [ 	]*vmwrite \(%eax\),%ebx
   2f:	0f 79 18 [ 	]*vmwrite \(%eax\),%ebx
-	...
+[ 	]*[a-f0-9]+:	0f 01 c1[ 	]*vmcall *
+[ 	]*[a-f0-9]+:	0f 01 c2[ 	]*vmlaunch *
+[ 	]*[a-f0-9]+:	0f 01 c3[ 	]*vmresume *
+[ 	]*[a-f0-9]+:	0f 01 c4[ 	]*vmxoff *
+[ 	]*[a-f0-9]+:	67 66 0f c7 30[ 	]*vmclear \(%bx,%si\)
+[ 	]*[a-f0-9]+:	67 0f c7 30[ 	]*vmptrld \(%bx,%si\)
+[ 	]*[a-f0-9]+:	67 0f c7 38[ 	]*vmptrst \(%bx,%si\)
+[ 	]*[a-f0-9]+:	67 f3 0f c7 30[ 	]*vmxon  \(%bx,%si\)
+[ 	]*[a-f0-9]+:	0f 78 c3[ 	]*vmread %eax,%ebx
+[ 	]*[a-f0-9]+:	0f 78 c3[ 	]*vmread %eax,%ebx
+[ 	]*[a-f0-9]+:	67 0f 78 03[ 	]*vmread %eax,\(%bp,%di\)
+[ 	]*[a-f0-9]+:	67 0f 78 03[ 	]*vmread %eax,\(%bp,%di\)
+[ 	]*[a-f0-9]+:	0f 79 d8[ 	]*vmwrite %eax,%ebx
+[ 	]*[a-f0-9]+:	0f 79 d8[ 	]*vmwrite %eax,%ebx
+[ 	]*[a-f0-9]+:	67 0f 79 18[ 	]*vmwrite \(%bx,%si\),%ebx
+[ 	]*[a-f0-9]+:	67 0f 79 18[ 	]*vmwrite \(%bx,%si\),%ebx
+#pass
diff --git a/gas/testsuite/gas/i386/vmx.s b/gas/testsuite/gas/i386/vmx.s
index 9f52b3fdea..cea3a0d017 100644
--- a/gas/testsuite/gas/i386/vmx.s
+++ b/gas/testsuite/gas/i386/vmx.s
@@ -2,6 +2,8 @@
 
 	.text
 foo:
+	.rept 2
+
 	vmcall
 	vmlaunch
 	vmresume
@@ -18,4 +20,7 @@ foo:
 	vmwritel %eax,%ebx
 	vmwrite (%eax),%ebx
 	vmwritel (%eax),%ebx
+
+	.code16
+	.endr
 	.p2align	4,0
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 0b0a121063..eaf14b3ce4 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,11 @@
+2020-03-06  Jan Beulich  <jbeulich@suse.com>
+
+	* i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
+	invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
+	adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
+	(ptwrite): Split into non-64-bit and 64-bit forms.
+	* i386-tbl.h: Re-generate.
+
 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 
 	* i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index c79ff5afb8..c6f7f035ec 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -1294,7 +1294,7 @@ movlps, 2, 0x12, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreS
 movlps, 2, 0x13, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex }
 movlps, 2, 0xf12, None, 2, CpuSSE, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM }
 movmskps, 2, 0x50, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { RegXMM, Reg32|Reg64 }
-movmskps, 2, 0xf50, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 }
+movmskps, 2, 0xf50, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 }
 movntps, 2, 0x2b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex }
 movntps, 2, 0xf2b, None, 2, CpuSSE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex }
 movntq, 2, 0xfe7, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegMMX, Qword|Unspecified|BaseIndex }
@@ -1588,7 +1588,7 @@ movsldup, 2, 0xf30f12, None, 2, CpuSSE3, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
 mwait, 0, 0xf01c9, None, 3, CpuSSE3, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { 0 }
 // mwait is very special. AX and CX are always 32 bits.
 // The 64-bit form exists only for compatibility with older gas.
-mwait, 2, 0xf01c9, None, 3, CpuSSE3, CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Acc|Dword|Qword, RegC|Dword|Qword }
+mwait, 2, 0xf01c9, None, 3, CpuSSE3, CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|NoAVX, { Acc|Dword|Qword, RegC|Dword|Qword }
 
 // VMX instructions.
 
@@ -1598,9 +1598,9 @@ vmlaunch, 0, 0xf01c2, None, 3, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N
 vmresume, 0, 0xf01c3, None, 3, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 vmptrld, 1, 0xfc7, 0x6, 2, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex }
 vmptrst, 1, 0xfc7, 0x7, 2, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex }
-vmread, 2, 0xf78, None, 2, CpuVMX|CpuNo64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Reg32|Dword|Unspecified|BaseIndex }
+vmread, 2, 0xf78, None, 2, CpuVMX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Reg32|Unspecified|BaseIndex }
 vmread, 2, 0xf78, None, 2, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg64, Reg64|Qword|Unspecified|BaseIndex }
-vmwrite, 2, 0xf79, None, 2, CpuVMX|CpuNo64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex, Reg32 }
+vmwrite, 2, 0xf79, None, 2, CpuVMX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, Reg32 }
 vmwrite, 2, 0xf79, None, 2, CpuVMX|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg64|Qword|Unspecified|BaseIndex, Reg64 }
 vmxoff, 0, 0xf01c4, None, 3, CpuVMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 vmxon, 1, 0xf30fc7, 0x6, 2, CpuVMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex }
@@ -1615,14 +1615,14 @@ getsec, 0, 0xf37, None, 2, CpuSMX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld
 
 // EPT instructions.
 
-invept, 2, 0x660f3880, None, 3, CpuEPT|CpuNo64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Oword|Unspecified|BaseIndex, Reg32 }
+invept, 2, 0x660f3880, None, 3, CpuEPT|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Oword|Unspecified|BaseIndex, Reg32 }
 invept, 2, 0x660f3880, None, 3, CpuEPT|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 }
-invvpid, 2, 0x660f3881, None, 3, CpuEPT|CpuNo64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Oword|Unspecified|BaseIndex, Reg32 }
+invvpid, 2, 0x660f3881, None, 3, CpuEPT|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Oword|Unspecified|BaseIndex, Reg32 }
 invvpid, 2, 0x660f3881, None, 3, CpuEPT|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 }
 
 // INVPCID instruction
 
-invpcid, 2, 0x660f3882, None, 3, CpuINVPCID|CpuNo64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Oword|Unspecified|BaseIndex, Reg32 }
+invpcid, 2, 0x660f3882, None, 3, CpuINVPCID|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Oword|Unspecified|BaseIndex, Reg32 }
 invpcid, 2, 0x660f3882, None, 3, CpuINVPCID|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 }
 
 // SSSE3 instructions.
@@ -2485,11 +2485,11 @@ vgf2p8mulb, 3, 0x66cf, None, 1, CpuAVX|CpuGFNI, Modrm|Vex|VexOpcode=1|VexVVVV=1|
 
 // FSGSBASE, RDRND and F16C
 
-rdfsbase, 1, 0xf30fae, 0x0, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
-rdgsbase, 1, 0xf30fae, 0x1, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
+rdfsbase, 1, 0xf30fae, 0x0, 2, CpuFSGSBase, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
+rdgsbase, 1, 0xf30fae, 0x1, 2, CpuFSGSBase, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
 rdrand, 1, 0xfc7, 0x6, 2, CpuRdRnd, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64 }
-wrfsbase, 1, 0xf30fae, 0x2, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
-wrgsbase, 1, 0xf30fae, 0x3, 2, CpuFSGSBase, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
+wrfsbase, 1, 0xf30fae, 0x2, 2, CpuFSGSBase, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
+wrgsbase, 1, 0xf30fae, 0x3, 2, CpuFSGSBase, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64 }
 vcvtph2ps, 2, 0x6613, None, 1, CpuF16C, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
 vcvtph2ps, 2, 0x6613, None, 1, CpuF16C, Modrm|Vex=2|VexOpcode=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegYMM }
 vcvtps2ph, 3, 0x661d, None, 1, CpuF16C, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Qword|Unspecified|BaseIndex|RegXMM }
@@ -2880,8 +2880,8 @@ xcryptofb, 0, 0xf30fa7e8, None, 3, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
 xstore, 0, 0xfa7c0, None, 3, CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, { 0 }
 
 // Multy-precision Add Carry, rdseed instructions.
-adcx, 2, 0x660f38f6, None, 3, CpuADX, Modrm|CheckRegSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
-adox, 2, 0xf30f38f6, None, 3, CpuADX, Modrm|CheckRegSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 }
+adcx, 2, 0x660f38f6, None, 3, CpuADX, Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
+adox, 2, 0xf30f38f6, None, 3, CpuADX, Modrm|CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
 rdseed, 1, 0xfc7, 0x7, 2, CpuRdSeed, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64 }
 
 // SMAP instructions.
@@ -4702,7 +4702,7 @@ monitorx, 3, 0xf01fa, None, 3, CpuMWAITX|Cpu64, AddrPrefixOpReg, { Acc|Dword|Qwo
 
 mwaitx, 0, 0xf01fb, None, 3, CpuMWAITX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 // The 64-bit form exists only for compatibility with older gas.
-mwaitx, 3, 0xf01fb, None, 3, CpuMWAITX, CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Qword, RegB|Dword|Qword }
+mwaitx, 3, 0xf01fb, None, 3, CpuMWAITX, CheckRegSize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Acc|Dword|Qword, RegC|Dword|Qword, RegB|Dword|Qword }
 
 // MONITORX/MWAITX instructions end
 
@@ -4715,14 +4715,15 @@ wrpkru, 0, 0xf01ef, None, 3, CpuOSPKE, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|N
 
 // RDPID instructions.
 
-rdpid, 1, 0xf30fc7, 0x7, 2, CpuRDPID|CpuNo64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
+rdpid, 1, 0xf30fc7, 0x7, 2, CpuRDPID|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 }
 rdpid, 1, 0xf30fc7, 0x7, 2, CpuRDPID|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64 }
 
 // RDPID instructions end.
 
 // PTWRITE instructions.
 
-ptwrite, 1, 0xf30fae, 0x4, 2, CpuPTWRITE, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex }
+ptwrite, 1, 0xf30fae, 0x4, 2, CpuPTWRITE|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex }
+ptwrite, 1, 0xf30fae, 0x4, 2, CpuPTWRITE|Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Unspecified|BaseIndex }
 
 // PTWRITE instructions end.
 
@@ -4778,8 +4779,7 @@ cldemote, 1, 0x0f1c, 0x0, 2, CpuCLDEMOTE, Modrm|Anysize|IgnoreSize|No_bSuf|No_wS
 
 // MOVDIR[I,64B] instructions.
 
-movdiri, 2, 0xf38f9, None, 3, CpuMOVDIRI, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
-
+movdiri, 2, 0xf38f9, None, 3, CpuMOVDIRI, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
 movdir64b, 2, 0x660f38f8, None, 3, CpuMOVDIR64B, Modrm|AddrPrefixOpReg, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
 
 // MOVEDIR instructions end.
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index e08f3743ed..49423aae1f 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -12695,7 +12695,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -16645,7 +16645,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
+    { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
@@ -16731,7 +16731,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
@@ -16759,7 +16759,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 1, 0, 0,
@@ -16835,7 +16835,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0,
@@ -16863,7 +16863,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0,
@@ -16891,7 +16891,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0,
@@ -39717,7 +39717,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
@@ -39729,7 +39729,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
@@ -39753,7 +39753,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
@@ -39765,7 +39765,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
@@ -47333,7 +47333,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1,
@@ -47347,7 +47347,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1,
@@ -58051,7 +58051,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
+    { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
@@ -58091,7 +58091,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
@@ -58114,11 +58114,23 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
-        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+    { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 1, 0, 0,
+	  0, 0, 0, 0, 1, 0 } } } },
+  { "ptwrite", 0xf30fae, 0x4, 2, 1,
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
-    { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1,
+    { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 1, 0, 1,
 	  0, 0, 0, 0, 1, 0 } } } },
   { "incsspd", 0xf30fae, 0x5, 2, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -58419,7 +58431,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,