From: H.J. Lu <hjl.tools@gmail.com>
Date: Fri, 5 Oct 2018 18:56:42 +0000 (-0700)
Subject: x86: Add Intel ENCLV to assembler and disassembler
X-Git-Url: http://git.efficios.com/?a=commitdiff_plain;h=a4e78aa5fed5ba2cc343c76b78d062291a6fb659;p=deliverable%2Fbinutils-gdb.git

x86: Add Intel ENCLV to assembler and disassembler

gas/

	* testsuite/gas/i386/se1.s: Add enclv.
	* testsuite/gas/i386/x86-64-se1.s: Likewise.
	* testsuite/gas/i386/se1.d: Updated.
	* testsuite/gas/i386/x86-64-se1.d: Likewise.

opcodes/

	* i386-dis.c (rm_table): Add enclv.
	* i386-opc.tbl: Add enclv.
	* i386-tbl.h: Regenerated.
---

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 9b6afa1b0d..b531980df5 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* testsuite/gas/i386/se1.s: Add enclv.
+	* testsuite/gas/i386/x86-64-se1.s: Likewise.
+	* testsuite/gas/i386/se1.d: Updated.
+	* testsuite/gas/i386/x86-64-se1.d: Likewise.
+
 2018-10-05  Sudakshina Das  <sudi.das@arm.com>
 
 	* config/tc-arm.c (arm_ext_predres): New.
diff --git a/gas/testsuite/gas/i386/se1.d b/gas/testsuite/gas/i386/se1.d
index ff2685c781..d7800ab885 100644
--- a/gas/testsuite/gas/i386/se1.d
+++ b/gas/testsuite/gas/i386/se1.d
@@ -10,4 +10,5 @@ Disassembly of section .text:
 0+ <_start>:
 [ 	]*[a-f0-9]+:	0f 01 cf             	encls  
 [ 	]*[a-f0-9]+:	0f 01 d7             	enclu  
+[ 	]*[a-f0-9]+:	0f 01 c0             	enclv  
 #pass
diff --git a/gas/testsuite/gas/i386/se1.s b/gas/testsuite/gas/i386/se1.s
index 1b57ac87fe..92d57952c0 100644
--- a/gas/testsuite/gas/i386/se1.s
+++ b/gas/testsuite/gas/i386/se1.s
@@ -5,3 +5,4 @@ _start:
 
 	encls
 	enclu
+	enclv
diff --git a/gas/testsuite/gas/i386/x86-64-se1.d b/gas/testsuite/gas/i386/x86-64-se1.d
index 29494f0090..a515219406 100644
--- a/gas/testsuite/gas/i386/x86-64-se1.d
+++ b/gas/testsuite/gas/i386/x86-64-se1.d
@@ -10,4 +10,5 @@ Disassembly of section .text:
 0+ <_start>:
 [ 	]*[a-f0-9]+:	0f 01 cf             	encls  
 [ 	]*[a-f0-9]+:	0f 01 d7             	enclu  
+[ 	]*[a-f0-9]+:	0f 01 c0             	enclv  
 #pass
diff --git a/gas/testsuite/gas/i386/x86-64-se1.s b/gas/testsuite/gas/i386/x86-64-se1.s
index 1b57ac87fe..92d57952c0 100644
--- a/gas/testsuite/gas/i386/x86-64-se1.s
+++ b/gas/testsuite/gas/i386/x86-64-se1.s
@@ -5,3 +5,4 @@ _start:
 
 	encls
 	enclu
+	enclv
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b66a46e704..27ca2da7df 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2018-10-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386-dis.c (rm_table): Add enclv.
+	* i386-opc.tbl: Add enclv.
+	* i386-tbl.h: Regenerated.
+
 2018-10-05  Sudakshina Das  <sudi.das@arm.com>
 
 	* arm-dis.c (arm_opcodes): Add sb.
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index bc4db68a31..a6e0a8ddc8 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -11027,7 +11027,7 @@ static const struct dis386 rm_table[][8] = {
   },
   {
     /* RM_0F01_REG_0 */
-    { Bad_Opcode },
+    { "enclv",		{ Skip_MODRM }, 0 },
     { "vmcall",		{ Skip_MODRM }, 0 },
     { "vmlaunch",	{ Skip_MODRM }, 0 },
     { "vmresume",	{ Skip_MODRM }, 0 },
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 3aec575b0b..409b4cd119 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3992,6 +3992,7 @@ xsavec64, 1, 0xfc7, 0x4, 2, CpuXSAVEC|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sS
 
 encls, 0, 0xf01cf, None, 3, CpuSE1, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 enclu, 0, 0xf01d7, None, 3, CpuSE1, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+enclv, 0, 0xf01c0, None, 3, CpuSE1, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 
 // SGX instructions end.
 
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 3a0959998f..539e5dbd40 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -66539,6 +66539,20 @@ const insn_template i386_optab[] =
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  0, 0 } } } },
+  { "enclv", 0, 0xf01c0, None, 3,
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0 } },
+    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
+      1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0 } } } },
   { "vcvtpd2udqx", 2, 0x79, None, 1,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0,